TTE Router Based on VPX Interface

Abstract

The present invention discloses a TTE router based on a VPX interface, comprising: a CPU system (1), a TTE routing controller system (2) connected to the CPU system (1), a first interface driver (3) connected to the CPU system (1) and the TTE routing controller system (2); a second interface driver (4) connected to the CPU system (1) and the TTE routing controller system (2); an external interface (7) connected to the first interface driver (3); a VPX interface (6) connected to the second interface driver (4); and an on-board power supply (5) connected to the VPX interface (6). The present invention realizes an inter-satellite TTE network router with radiation tolerance, provides a TTE interface, and each TTE interface supports three network interfaces of standard Ethernet, AFDX, and TTE, and can be widely applied to satellite systems in low, medium, and high orbits to realize the function of high-speed inter-satellite data interaction.

Description

Technical Field

[0001] The present invention relates to the technical fields of TTE bus technology, TTE routing control technology, VPX interface technology, and inter-satellite routing technology, and particularly relates to a TTE router based on a VPX interface. Background Art

[0002] TTE: Time Trigger Ethernet, also known as Time-Triggered Network, is a latest international new bus technology based on Ethernet. It has the highest level of security, reliability, and deterministic network. This bus technology combines the advantages of the time-triggered protocol and Ethernet technology, and can be compatible with ordinary network data streams, AFDX data streams, and TTE network data streams on the same network platform, with higher security and a strong fault tolerance mechanism.

[0003] TTE supports data transfer rates of 10M / 100M / 1000Mbps, supports a triple-redundancy architecture, has higher security and a comprehensive fault tolerance mechanism, and achieves a high level of security, reliability, and determinism. It is currently the mainstream technology for aerospace buses. China is applying this technology to various spaceborne electronic systems, and has proposed to use a TTE network to implement the inter-satellite routing function to achieve high-performance and high-bandwidth inter-satellite data interaction. In response to the above requirements, the present invention provides a TTE router based on a VPX interface. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. For this purpose, the present invention provides a TTE router based on a VPX interface, which can achieve high-performance and high-bandwidth inter-satellite data interaction.

[0005] The TTE router based on a VPX interface according to an embodiment of the present invention includes: a CPU system (1), a TTE routing controller system (2) connected to the CPU system (1), a first interface driver (3) connected to the CPU system (1) and the TTE routing controller system (2); a second interface driver (4) connected to the CPU system (1) and the TTE routing controller system (2); an external interface (7) connected to the first interface driver (3); a VPX interface (6) connected to the second interface driver (4); and an on-board power supply (5) connected to the VPX interface (6).

[0006] The TTE router based on a VPX interface according to an embodiment of the present invention has at least the following beneficial effects:

[0007] The embodiment of the present invention realizes high-performance and high-bandwidth inter-satellite data interaction by using a VPX interface.

[0008] According to some embodiments of the present invention, the CPU system (1) includes a program memory (102), a data memory (103), a clock circuit (104), a debug and simulation interface (105), a reset circuit (106), and a CPU (101) connected to the program memory (102), data memory (103), clock circuit (104), debug and simulation interface (105), and reset circuit (106).

[0009] According to some embodiments of the present invention, the TTE routing controller system (2) includes an external memory (202), a debug and simulation interface (203), a configuration interface (204), a clock circuit (205), and a TTE routing controller chip connected to the external memory (202), debug and simulation interface (203), configuration interface (204), and clock circuit (205). The TTE routing controller system (2) is designed based on the radiation-resistant TTE routing chip TT6802-1-SW. After relevant configuration through the configuration interface (204) and the CPU system (1), it can work properly to achieve high-speed switching and scheduling of 6-way 10 / 100 / 1000 Mbps TTE interface signals and 12 10 / 100 Mbps TTE interface data.

[0010] According to some embodiments of the present invention, the first interface driver (3) includes a PHY + transformer module (301) and an RS422 transceiver driver (302), and the second interface driver (4) includes a PHY + transformer module (401) and an RS422 transceiver driver (402). Both the PHY + transformer module (301) and the PHY + transformer module (401) are composed of a PHY and a transformer circuit. The first interface driver (3) and the second interface driver (4) are both designed with an RS422 interface driver circuit and a TTE interface driver circuit supporting a 1000 Mbps communication bandwidth to achieve the transceiver driving function of low-speed and high-speed signals for all interfaces.

[0011] According to some embodiments of the present invention, the on-board power supply (5) includes a 5V to 3.3V DC-DC power supply (501), a 5V to 2.5V DC-DC power supply (502), and a 5V to 1.2V DC-DC power supply (503). The on-board power supply (5) is designed with multiple DC-DC power circuits to convert the externally input +5V power supply into +3.3V, +2.5V, and +1.2V power supplies to provide various power supplies for the TTE router module based on the VPX interface.

[0012] According to some embodiments of the present invention, the VPX interface (6) includes three standard VPX connectors, P0 (603), P1 (602), and P2 (601).

[0013] According to some embodiments of the present invention, the external interface (7) includes a plurality of network interfaces (7000) and a COM interface (6016).

[0014] According to some embodiments of the present invention, the CPU selects an embedded processor chip with radiation tolerance capabilities such as SPARC V8 or other architectures.

[0015] According to some embodiments of the present invention, the CPU selects an embedded processor chip with radiation tolerance capabilities such as SPARC V8 or other architectures.

[0016] According to some embodiments of the present invention, the router includes 16 TTE data interaction interfaces. The 16 TTE data interaction interfaces include 4 VPX interface signals and 14 external interface signals. Each of the TTE data interaction interfaces supports three network interfaces: standard Ethernet, AFDX, and TTE.

[0017] According to some embodiments of the present invention, all components of the router use components with radiation tolerance capabilities.

[0018] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, where:

[0020] Figure 1 is a system block diagram of the TTE router based on the VPX interface according to the embodiment of the present invention.

[0021] Figure 2 is a system block diagram of the CPU system according to the embodiment of the present invention.

[0022] Figure 3 is a system block diagram of the TTE routing controller system according to the embodiment of the present invention.

[0023] Figure 4 is a system block diagram of the first interface driver and the second interface driver according to the embodiment of the present invention.

[0024] Figure 5 is a system block diagram of the on-board power supply according to the embodiment of the present invention.

[0025] Figure 6 is a system block diagram of the VPX interface according to the embodiment of the present invention.

[0026] Figure 7 is a system block diagram of the external interface according to the embodiment of the present invention. Detailed implementation mode

[0027] The following will clearly and completely describe the concept, specific structure and technical effects generated by the present invention in combination with the embodiments and the drawings, so as to fully understand the purpose, solution and effects of the present invention.

[0028] It should be noted that, unless otherwise specified, when a certain feature is referred to as "fixed" or "connected" to another feature, it can be directly fixed or connected to another feature, or indirectly fixed or connected to another feature. The singular forms "a", "the" and "said" used herein are also intended to include the plural forms, unless the context clearly indicates otherwise. In addition, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present invention. The terms used in the description of this specification are only for describing specific embodiments, rather than for limiting the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0029] It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from each other. For example, without departing from the scope of this disclosure, the first element may also be referred to as the second element, and similarly, the second element may also be referred to as the first element. The use of any and all example or exemplary language ("such as", "for example", etc.) provided herein is only intended to better illustrate the embodiments of the present invention, and unless otherwise required, will not impose a limitation on the scope of the present invention.

[0030] Refer to Figure 1 , Figure 1 is the system block diagram of the TTE router based on the VPX interface according to the embodiment of the present invention. As Figure 1 shown, this embodiment includes: a TTE router 100 based on the VPX interface. The TTE router 100 based on the VPX interface includes a CPU system 1, a TTE routing controller system 2, a first interface driver 3, a second interface driver 4, an on-board power supply 5, a VPX interface 6, and an external interface 7.

[0031] Refer to Figure 2 , Figure 2 is the system block diagram of the CPU system according to the embodiment of the present invention. As Figure 2As shown, the CPU system 1 designs the peripheral circuit around the CPU, builds the CPU system, and realizes the control-related functions of the TTE router. The CPU system 1 includes a CPU 101, a program memory 102, a data memory 103, a clock circuit 104, a debug and simulation interface 105, and a reset circuit 106. In some embodiments, the CPU system 1 is designed based on an embedded processor chip with radiation tolerance ability such as SPARC V8 or other architectures to realize the control function of the TTE router.

[0032] Referring to Figure 3 , Figure 3 is the system block diagram of the TTE routing controller system according to the embodiment of the present invention. As Figure 3 shown, the TTE routing controller system 2 includes a TTE routing controller chip 201, an external memory 202, a debug and simulation interface 203, a configuration interface 204, and a clock circuit 205. In some embodiments, the TTE routing controller system is designed based on the TTE routing chip TT6802-1-SW with radiation tolerance ability. After relevant configuration through the configuration interface and the CPU system 1, it can work normally to realize the high-speed switching and scheduling of 6-way 10 / 100 / 1000 Mbps TTE interface signals and 12 10 / 100 Mbps TTE interface data.

[0033] Referring to Figure 4 , Figure 4 is the system block diagram of the first interface driver and the second interface driver according to the embodiment of the present invention. As Figure 4 shown, the first interface driver 3 includes a TTE interface driver and an RS422 interface driver 302, where the TTE interface driver is mainly a PHY + transformer 301. Similarly, the second interface driver 4 includes a TTE interface driver and an RS422 interface driver 402, where the TTE interface driver is mainly a PHY + transformer 401. Among them, the PHY + transformer 301 of the first interface driver 3 and the PHY transformer 401 of the second interface driver 4 are composed of a PHY and a transformer circuit. The PHY selects the Ethernet PHY chip 88E1512 supporting a communication bandwidth of 1000 Mbps, and the transformer selects the network transformer HX5008NL. The RS422 interface drivers 302 of the first interface driver 3 and the RS422 interface drivers 402 of the second interface driver 4 both select the RS422 interface chip MAX3078. In this embodiment, both the first interface driver 3 and the second interface driver 4 are designed with RS422 interface driver circuits and TTE interface driver circuits supporting a communication bandwidth of 1000 Mbps to realize the transceiver driving functions of low-speed and high-speed signals of all interfaces.

[0034] Referring to Figure 5 , Figure 5 is the system block diagram of the on-board power supply according to the embodiment of the present invention. AsFigure 5 As shown, the on-board power supply 5 includes a 5V->3.3V DC-DC power supply 501, a 5V->2.5V DC-DC power supply 502, and a 5V->1.2V DC-DC power supply 503. In this embodiment, the on-board power supply 5 is designed with multiple DC-DC power supply circuits to convert the externally input +5V power supply into +3.3V, +2.5V, and +1.2V power supplies, providing various power supplies for the TTE router module based on the VPX interface.

[0035] Referring to Figure 6 , Figure 6 is the system block diagram of the VPX interface according to an embodiment of the present invention. As Figure 6 shown, the VPX interface 6 includes three standard VPX connectors: a P0 VPX connector 603, a P1 VPX connector 602, and a P2 VPX connector 601. In this embodiment, the VPX interface 6 is designed according to the 6U-size VPX module standard, providing three standard VPX connectors, P0, P1, and P2, and the signal definitions of the connectors can be flexibly defined.

[0036] Referring to Figure 7 , Figure 7 is the system block diagram of the external interface according to an embodiment of the present invention. As Figure 7 shown, the external interface 7 provides an external TTE interaction interface debugging and simulation, and configuration interface for the TTE router based on the VPX interface. The external interface 7 mainly includes 14 TTE interfaces, as well as debugging and simulation and configuration interfaces. Among them, the 14 TTE interfaces use RJ45 interfaces, and the debugging and simulation and configuration interfaces are uniformly connected to the COM interface and use a DB15 connector.

[0037] The embodiment of the present invention realizes an inter-satellite TTE network router with radiation resistance and can be directly installed in a 6U-size VPX chassis, providing 6 10 / 100 / 1000 Mbps and 12 10 / 100 Mbps TTE interfaces. Each TTE interface supports three network interfaces: standard Ethernet, AFDX, and TTE, and can be widely applied to satellite systems in low, medium, and high orbits to achieve the function of high-speed inter-satellite data interaction.

[0038] As described above, it is only a preferred embodiment of the present invention. The present invention is not limited to the above-mentioned embodiments. As long as it achieves the technical effects of the present invention by the same means, any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention. Within the scope of protection of the present invention, its technical solutions and / or implementation manners can have various different modifications and changes.

Claims

1. A TTE router based on the VPX interface, characterized in that Comprising: A CPU system (1), A TTE routing controller system (2) connected to the CPU system (1), A first interface driver (3) connected to the CPU system (1) and the TTE routing controller system (2); A second interface driver (4) connected to the CPU system (1) and the TTE routing controller system (2); An external interface (7) connected to the first interface driver (3); A VPX interface (6) connected to the second interface driver (4); and An on-board power supply (5) connected to the VPX interface (6); The VPX interface (6) includes three standard VPX connectors P0 (603), P1 (602), and P2 (601). The first interface driver (3) includes a PHY + transformer module (301) and an RS422 transceiver driver (302). The second interface driver (4) includes a PHY + transformer module (401) and an RS422 transceiver driver (402). The PHY + transformer module (301) of the first interface driver (3) and the PHY + transformer module (401) of the second interface driver (4) are both composed of a PHY and a transformer circuit.

2. The TTE router based on the VPX interface according to claim 1, wherein The CPU system (1) includes a program memory (102), a data memory (103), a clock circuit (104), a debug and simulation interface (105), a reset circuit (106), and A CPU (101) connected to the program memory (102), data memory (103), clock circuit (104), debug and simulation interface (105), and reset circuit (106).

3. The TTE router based on the VPX interface according to claim 1, characterized in that The TTE routing controller system (2) includes an external memory (202), a debug and simulation interface (203), a configuration interface (204), a clock circuit (205), and A TTE routing controller chip connected to the external memory (202), debug and simulation interface (203), configuration interface (204), and clock circuit (205).

4. The TTE router based on the VPX interface according to claim 1, characterized in that, The on-board power supply (5) includes a 5V to 3.3V DC-DC power supply (501), a 5V to 2.5V DC-DC power supply (502), and a 5V to 1.2V DC-DC power supply (503).

5. The TTE router based on the VPX interface according to claim 1, characterized in that, The external interface (7) includes multiple network interfaces (7000) and a COM interface (6016).

6. The TTE router based on the VPX interface according to claim 1, wherein The CPU selects an embedded processor chip with radiation tolerance capabilities such as SPARCV8 or other architectures.

7. The TTE router based on the VPX interface according to claim 1, characterized in that The router includes 18 TTE data interaction interfaces. The 18 TTE data interaction interfaces include 4 VPX interface signals and 14 external interface signals. Each TTE data interaction interface supports three network interfaces: standard Ethernet, AFDX, and TTE.

8. The TTE router based on the VPX interface according to claim 1, wherein All components of the router adopt components with radiation tolerance capabilities.

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