Memory device and method of operation thereof to avoid multiple turn-on of a memory cell

Abstract

A memory device includes a memory cell coupled to a word line and a bit line, a row driver to drive the word line to a pre-charge level, a column driver to drive the bit line to a first target level, a sense amplifier to sense a first sense level of the word line after the first target level is applied to the memory cell, and a read control circuit to control the column driver to selectively apply a second target level different from the first target level to the memory cell based on the first sense level sensed by the sense amplifier.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0087415, filed with the Korean Intellectual Property Office on July 19, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of the inventive concept disclosed herein relate to a memory device and a method of operating the same, and more specifically, to a memory device and a method of operating the same for preventing memory cells from being turned on multiple times. Background Technology

[0004] Memory in next-generation memory devices may include phase-change memory (PCM) cells. When an electric current is applied, a PCM cell changes between two physical states, each with a different resistance that can be used to represent one of two different logic levels. Electrical signals can be applied to the PCM cell when data is written to and read from it. When writing data, the physical state of the PCM cell can be intentionally altered by the electrical signal. However, when reading data, the physical state of the PCM cell can sometimes be unintentionally altered by the electrical signal. Therefore, the reliability or write endurance of the PCM may be reduced. Summary of the Invention

[0005] At least one embodiment of the present invention provides a memory device and its operation method for avoiding multiple turn-on of memory cells.

[0006] According to an exemplary embodiment of the present invention, a memory device includes: a memory cell connected to a word line and a bit line; a row driver driving the word line to a precharge level; a column driver driving the bit line to a first target level; a sense amplifier sensing a first sense level of the word line after the first target level is applied to the memory cell; and read control circuitry controlling the column driver according to the first sense level sensed by the sense amplifier to selectively apply a second target level different from the first target level to the memory cell.

[0007] According to an exemplary embodiment of the present invention, a memory device includes a plurality of carriages and a plurality of carriage control circuits. Each carriage includes a memory cell connected to a word line and a bit line. Each carriage control circuit is configured to access the memory cell via the word line and the bit line. Each carriage control circuit is configured to perform a first sensing operation on the memory cell based on a first read command by driving the word line to a precharge level and driving the bit line to a first target level; and to perform a second sensing operation on the memory cell based on a first sensing result of the first sensing operation by driving the word line to the precharge level and selectively driving the bit line to a second target level.

[0008] According to an exemplary embodiment of the present invention, an operation method of a memory device includes: driving a word line connected to a memory cell to a precharge level; driving a bit line connected to a memory cell to a first target level; performing a first sensing operation to sense a first sensing level of the word line after the bit line is driven to the first target level; and determining, based on a first sensing result of the first sensing operation, whether to perform a second sensing operation using a second target level different from the first target level. Attached Figure Description

[0009] The inventive concept will become apparent from the accompanying drawings and from a detailed description of exemplary embodiments thereof.

[0010] Figure 1 A block diagram of a memory device according to an exemplary embodiment of the present invention is shown.

[0011] Figure 2 and Figure 3 It shows Figure 1 An exemplary threshold voltage distribution for a storage cell.

[0012] Figure 4 It shows Figure 1 A graph illustrating exemplary IV characteristics of a storage cell.

[0013] Figure 5 and Figure 6 It shows when Figure 2 The read voltage is applied to Figure 1 Exemplary word line voltage, exemplary bit line voltage, and exemplary current flowing through the memory cell.

[0014] Figure 7 An exemplary embodiment of the invention is shown. Figure 1 A flowchart of an operation method for preventing multiple conduction of memory cells in a memory device.

[0015] Figure 8 Exemplary voltages and currents for memory cells with relatively small threshold voltages are shown, which can be determined based on... Figure 7 The flowchart changes accordingly.

[0016] Figure 9 Exemplary voltages and currents for memory cells with relatively large threshold voltages are shown, which can be determined based on... Figure 7 The flowchart changes accordingly.

[0017] Figure 10 Exemplary voltages and currents for memory cells with relatively small threshold voltages are shown, which can be determined based on... Figure 7 The flowchart changes accordingly.

[0018] Figure 11 Exemplary voltages and currents for memory cells with relatively large threshold voltages are shown, which can be determined based on... Figure 7 The flowchart changes accordingly.

[0019] Figures 12 to 15 This is a block diagram illustrating an exemplary memory device according to a concept conceived in the present invention.

[0020] Figure 16 The arrangement in accordance with an exemplary embodiment of the present invention is Figure 15 The storage unit in layer L2.

[0021] Figures 17 to 19 An arrangement illustrating an exemplary embodiment of the concept according to the present invention is shown in Figure 15 The storage cells in layer L2 and the storage cells in layer L3 arranged above layer L2.

[0022] Figure 20 A flowchart illustrating an on-chip valley search operation according to an exemplary embodiment of the present invention is shown.

[0023] Figures 21 to 24 This is a block diagram illustrating an electronic device employing an exemplary embodiment of a memory device according to a concept based on the present invention. Detailed Implementation

[0024] Figure 1 A block diagram of a memory device according to an exemplary embodiment of the present invention is shown. The memory device 100 includes a memory cell 110, a column driver 120 (e.g., a drive circuit), a row driver 130 (e.g., a drive circuit), a sense amplifier 140, and a read control circuit 150.

[0025] A first end of memory cell 110 can be connected to word line WL, and a second end of memory cell 110 can be connected to bit line BL. In an exemplary embodiment of the present invention, memory cell 110 is a resistive memory cell. For example, memory cell 110 can be a non-volatile memory cell, such as a phase-change random access memory (PRAM) cell, a magnetoresistive RAM (MRAM) cell, a resistive RAM (RRAM) cell, or a ferroelectric RAM (FRAM) cell. Hereinafter, it is assumed that memory cell 110 is a PRAM cell, but the present invention is not limited thereto. Memory cell 110 may include a resistive memory (storage) element MD and a select element SD. Memory element MD may include a phase change material. In an exemplary embodiment, when the material is amorphous, the phase change material has a high-resistivity state (e.g., high resistance), and when the material is crystalline, the phase change material has a low-resistivity state (e.g., low resistance), depending on the electrical signal applied to memory cell 110, Joule heating, or temperature. In an exemplary embodiment of the present invention, memory element MD includes a chalcogenide material. Select element SD may be connected in series with memory element MD. For example, the selector element SD can be a diode element with bidirectional characteristics or an oval threshold switch (OTS) element. The selector element SD can have non-linear threshold switching characteristics and an S-shaped IV curve (reference). Figure 4 In an exemplary embodiment of the present invention, the selection element SD comprises a chalcogenide material.

[0026] Column driver 120 can drive bit line BL. Row driver 130 can drive word line WL. Sensing amplifier 140 can sense the voltage level (or current level) of word line WL to determine the sensing result. The sensing result of sensing amplifier 140 can indicate the data stored in memory cell 110. Read control circuit 150 can control column driver 120, row driver 130 and sensing amplifier 140 to read data stored in memory cell 110. For example, under the control of read control circuit 150, a read voltage (see reference) can be applied across memory cell 110 through column driver 120 and row driver 130. Figure 2 (VREAD). After the read voltage is applied, the sense amplifier 140 can sense the data in the memory cell 110 under the control of the read control circuit 150.

[0027] exist Figure 1 An example is shown where a memory element MD is connected to a word line WL and a select element SD is connected to a bit line BL. For example, because memory cell 110 has bidirectional characteristics, the memory element MD can be connected to the bit line BL, and the select element SD can be connected to the word line WL. The word line WL can be referred to as a "bit line", and the bit line BL can be referred to as a "word line".

[0028] Figure 2 and Figure 3 It shows Figure 1 An exemplary threshold voltage distribution of a memory cell. Figure 2 and Figure 3 In the diagram, the horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells 110. Due to various factors such as process, voltage and temperature (PVT) variations, write (or programming) conditions, read conditions, write count, read count, and elapsed time, the threshold voltages of memory cells 110 in the same state can differ and can form a distribution. Figure 2 This pertains to the case where memory cell 110 stores one bit of data. Memory cell 110 may have a threshold voltage corresponding to one of states S1 and S2, which indicate a digital logic value of "0" followed by "1". A read voltage VREAD may be applied to memory cell 110 to identify (read) the state of memory cell 110 (e.g., S1 or S2). Figure 3 This refers to the case where storage cell 110 stores data having one or more bits (e.g., two bits). Storage cell 110 may have a threshold voltage corresponding to one of states S1 to S4, which indicate digital logic values ​​00, 01, 10, and 11. Read voltages VREAD1 to VREAD3 may be applied to storage cell 110 to identify (read) the state of storage cell 110 (e.g., one of S1 to S4). The inventive concept is not limited to the above example of storage cell 110 storing a specific number of bits.

[0029] Figure 4 It shows Figure 1 A graph showing the IV characteristics of a memory cell. Figure 4In the diagram, the horizontal axis represents the voltage across memory cell 110 (i.e., the difference between the voltages applied to opposite ends of memory cell 110), and the vertical axis represents the current flowing through memory cell 110. The current flowing through memory cell 110 can be very small until the voltage across memory cell 110 reaches the threshold voltage VTH. When the voltage across memory cell 110 reaches the threshold voltage VTH, memory cell 110 can be turned on, and a voltage snapback may occur. The threshold voltage VTH can refer to the voltage at which memory cell 110 switches from the RESET state to the SET state. Memory cell 110 is off in the RESET state and on in the SET state. When a voltage snapback occurs, the current flowing through memory cell 110 increases. The voltage across memory cell 110 can change (or decrease) from the threshold voltage VTH to the switching voltage VS. The voltage at the point where the line extending from the IV curve after a voltage snapback intersects the horizontal axis can be the holding voltage VH. One of the read voltages VREAD, VREAD1, VREAD2, or VREAD3 can be applied to the memory cell 110, which has a threshold voltage VTH corresponding to any state, and the data stored in the memory cell 110 can be read according to the on or off state of the memory cell 110.

[0030] Figure 5 and Figure 6 It shows when Figure 2 The read voltage is applied to Figure 1 The exemplary word line voltage, exemplary bit line voltage, and exemplary current flowing through the memory cell are described. From time T1 to time T2, the row driver 130 drives the word line WL from an initial level V2 (or equalization level) to a level V1 (referred to as the "precharge level") that is lower than the initial level V2. When the word line voltage VWL is driven to level V2 (or the word line voltage VWL reaches level V2), the row driver 130 floats (or does not drive) the word line WL, and the word line WL floats from time T2. For example, the word line WL can float from time T2 to time T3.

[0031] After time T2, column driver 120 drives bit line BL from initial level V2 to level V3, which is higher than the initial level V2. For example, level V2 can be the midpoint between levels V1 and V3, or it can correspond to ground voltage GND. The voltage difference (or potential difference) between levels V1 and V3 can be... Figure 2 The read voltage VREAD, and Figure 3 The read voltages VREAD1, VREAD2, and VREAD3 correspond to one of them. The following will... Figure 2 The read voltage VREAD, and Figure 3One of the read voltages VREAD1, VREAD2, and VREAD3 is called the "read voltage VREAD".

[0032] The bit line voltage VBL increases (rises) after time T2. The voltage difference between the bit line voltage VBL and the word line voltage VWL reaches the threshold voltage VTH1 of memory cell 110 at time T3. The voltage across memory cell 110 can be the threshold voltage VTH1 or greater (or exceed the threshold voltage VTH1), and memory cell 110 is turned on. At time T3, the peak current Ipeak flows through memory cell 110. From time T1 to time T3, memory cell 110 is turned off, and the current flowing through memory cell 110 is a very small turn-off current Ioff. Because the word line WL is floating from time T2 to time T3, the word line voltage VWL can gradually increase due to the turn-off current Ioff. However, for ease of illustration, the word line voltage VWL is shown as uniform. As the word line voltage VWL increases from time T3 due to the peak current Ipeak, the amplitude of the voltage across memory cell 110 decreases, and the current flowing through memory cell 110 decreases from the peak current Ipeak. At time T4, the voltage across memory cell 110 reaches the switching voltage VS1, the turn-off current Ioff flows through memory cell 110, and memory cell 110 is turned off. Figure 5 In the diagram, the time interval from time T3 to time T4 is exaggerated to show the decrease in peak current Ipeak. The time interval from time T3 to time T4 may be very short. An example is shown where the magnitude of the voltage across memory cell 110 is greater than the switching voltage VS1 at time T4, and the voltage across memory cell 110 may be referred to as the switching voltage VS1.

[0033] After time T2, column driver 120 increases the bit line voltage VBL. For example, the voltage difference between the bit line voltage VBL and the word line voltage VWL reaches the threshold voltage VTH1 of memory cell 110 again at time T5. The voltage across memory cell 110 can be the threshold voltage VTH1 or greater (or exceed the threshold voltage VTH1), and memory cell 110 is turned on. At time T5, peak current Ipeak flows through memory cell 110 again. As word line voltage VWL increases after time T5, the amplitude of the voltage across memory cell 110 decreases, and the current flowing through memory cell 110 decreases from the peak current Ipeak. At time T6, the voltage across memory cell 110 reaches the switching voltage VS1 again, the turn-off current Ioff flows through memory cell 110, and memory cell 110 is turned off again. Similar to the time interval from time point T3 to time point T4, the time interval from time T5 to time T6 may be very short. The voltage across memory cell 110 at time T6 can be referred to as the switching voltage VS1.

[0034] Figure 6 This relates to a case where the memory cell 110 has a threshold voltage VTH2 that is larger than the threshold voltage VTH1. In an exemplary embodiment, the threshold voltages VTH1 and VTH2 belong to the same physical state indicating the same digital logic value. Figure 6 The word line voltage VWL and bit line voltage VBL applied to memory cell 110 up to time T8 are essentially the same as... Figure 5 Up to time T5, the word line voltage VWL and bit line voltage VBL applied to memory cell 110 are the same. After time T8, the bit line voltage VBL increases (rises), and the voltage difference between VBL and VWL reaches the threshold voltage VTH2 of memory cell 110 at time T9. The voltage across memory cell 110 can be the threshold voltage VTH2 or greater (or exceed VTH2), and memory cell 110 is turned on. At time T9, the peak current Ipeak flows through memory cell 110. As the word line voltage VWL increases after time T9, the amplitude of the voltage across memory cell 110 decreases, and the current flowing through memory cell 110 decreases from the peak current Ipeak. At time T10, the voltage across memory cell 110 reaches the switching voltage VS2, the turn-off current Ioff flows through memory cell 110, and memory cell 110 is turned off. Similar to the time interval from time T3 to time T4, the time interval from time T9 to time T10 can be very short. The voltage across storage cell 110 at time T10 can be called the switching voltage VS2.

[0035] When a read voltage VREAD is applied to memory cell 110, which has a threshold voltage VTH2 higher than the threshold voltage VTH1, memory cell 110 is turned on only at time T9. Conversely, the return... Figure 5When a read voltage VREAD is applied to memory cell 110 with a threshold voltage VTH1, memory cell 110 is turned on at times T3 and T5 (i.e., turned on multiple times). Although the read voltage VREAD is applied to memory cell 110 only once in a single read operation, memory cell 110 can be turned on multiple times, and the peak current Ipeak can flow through memory cell 110 multiple times. The peak current Ipeak can cause localized heating of memory cell 110, resulting in a phase transition of memory cell 110. The accumulation of the peak current Ipeak flowing through memory cell 110 can corrupt the data stored in memory cell 110, and the reliability or durability of memory cell 110 may decrease. For example, if we assume that the physical state of memory cell 110 represents data with logic 0, and then excessive heat causes its physical state to change, so that memory cell 110 now represents data with logic 1, then the data can be considered corrupted and the reliability of the memory is reduced. Furthermore, since this unintentional state change is essentially an additional write, and the memory can only be written to multiple times before a failure occurs, the write durability of the memory is reduced. The peak current Ipeak can correspond to a current spike, and read interference SIRD caused by the spike may occur in the storage cell 110.

[0036] According to an exemplary embodiment of the present invention, during a single read operation of the storage cell 110 (or when a read voltage is applied to the storage cell 110), the storage cell 110 is turned on only once, regardless of the threshold voltage VTH1 or VTH2 of the storage cell 110. Therefore, multiple turns on of the storage cell 110 can be avoided. Since multiple turns on of the storage cell 110 are avoided, the reliability or durability (e.g., write durability) of the storage cell 110 can be improved.

[0037] Figure 7 An exemplary embodiment of the invention is shown. Figure 1 A flowchart of the operation method of the memory device is provided to avoid repeatedly turning on the memory cell. Figure 8 Exemplary voltages and currents for memory cells with relatively small threshold voltages are shown, which can be determined based on... Figure 7 The flowchart changes accordingly. Figure 9 Exemplary voltages and currents for memory cells with relatively large threshold voltages are shown, which can be determined based on... Figure 7 The flowchart varies. In an exemplary embodiment, Figure 8 Threshold voltage VTH1 and Figure 9The threshold voltage VTH2 belongs to the same state indicating the same digital logic value. In operation S105, the read control circuit 150 starts (or initiates) a read operation for the memory cell 110. In an exemplary embodiment, operation S105 and operations S110 to S150 are performed in response to a read command provided to the memory device 100 from an external source (e.g., a memory controller or host).

[0038] In operation S110, the read control circuit 150 sets a target level VTARGET. In an exemplary embodiment of the present invention, the target level VTARGET is set based on the threshold voltage VTH and the switching voltage VS of the memory cell 110. For example, the target level VTARGET can be set to a level lower than level "VTH + (VTH - VS)" (i.e., it can be set to be smaller than level "VTH + (VTH - VS)"). In an exemplary embodiment of the present invention, the target level VTARGET is set to avoid turning on the memory cell 110 multiple times in a single read operation. Assume the memory cell 110 has... Figure 5 The threshold voltage VTH1. As described above, memory cell 110 is turned on at time T3 and at time T5. The level of bit line voltage VBL at time T5 can be "VTH1 + (VTH1 - VS1)". In an exemplary embodiment, the target level VTARGET is set to a level lower than "VTH1 + (VTH1 - VS1)" so that memory cell 110 is not turned on at time T5. Furthermore, memory device 100 may include one or more memory cells 110. In an exemplary embodiment of the inventive concept, the target level VTARGET is set to the sum of the following two values: the minimum threshold voltage Min(VTH) of memory cells 110 having the same digital logic value, and the minimum difference between the threshold voltage and the switching voltage Min(VTH - VS), or the target level VTARGET is set to a level smaller than the sum of the above.

[0039] In operation S115, the row driver 130 drives or precharges the word line WL to the precharge level V1. Figure 8 During the word line precharge period from time T11 to time T12, the line driver 130 drives the word line WL, which has an initial level V2, to the precharge level V1. Figure 9 During the word line precharge period from time T21 to time T22, the row driver 130 drives the word line WL, which has an initial level V2, to a precharge level V1. In operation S115, the row driver 130 drives or precharges the sense data line SDL to a precharge level V4. The sense data line SDL can be connected to the sense amplifier 140, and the word line WL can be connected to the memory cell 110. The sense data line SDL and the word line WL can be connected via... Figure 12The line decoder 270 is electrically connected during the charge-sharing period as described below.

[0040] In operation S120, the row driver 130 is either floated or not driven, driving the word line WL to the precharge level V1. Figure 8 During the word line floating period from time T12 to time T17, word line WL can be floating. Figure 9 During the word line floating period from time T22 to time T25, the word line WL can be floating. (Referring to...) Figure 12 In the described line decoder 270, under the control of the read control circuit 150, the switches SW1 to SW4 connected to the word line WL can disconnect the word line WL from the line driver 130, so the word line WL can be floated by the switch.

[0041] In operation S125, column driver 120 drives or precharges bit line BL from initial level V2 to target level VTARGET. Figure 8 During the bit line precharge period from time T12 to time T15, column driver 120 drives bit line BL, with an initial level V2, to a target level VTARGET1. The voltage difference between the bit line voltage VBL and the word line voltage VWL can reach the threshold voltage VTH1 of memory cell 110 at time T13. The voltage across memory cell 110 can be the threshold voltage VTH1 or greater (or exceed the threshold voltage VTH1), and memory cell 110 is turned on. At time T13, peak current Ipeak flows through memory cell 110. From time T11 to time T13, memory cell 110 is turned off, and the current flowing through memory cell 110 is a very small turn-off current Ioff. Because word line WL floats from time T12 to time T13, word line voltage VWL can gradually increase due to the turn-off current Ioff. However, for ease of illustration, word line voltage VWL is shown as uniform. As the word line voltage VWL increases after time T13, the amplitude of the voltage across memory cell 110 decreases, and the current flowing through memory cell 110 decreases from the peak current Ipeak. At time T14, the voltage across memory cell 110 reaches the switching voltage VS1, the turn-off current Ioff flows through memory cell 110, and memory cell 110 is turned off. The time interval from time T13 to time T14 is exaggerated to show the decrease in peak current Ipeak.

[0042] exist Figure 9 During the bit line precharge period from time T22 to time T23, column driver 120 drives bit line BL from the initial level V2 to the target level VTARGET1. Because Figure 9 The threshold voltage VTH2 of the memory cell 110 is higher than that of the memory cell 110. Figure 8The threshold voltage VTH1 of the memory cell 110 is large, so during the bit line precharge period, Figure 8 The memory cell is turned on, and Figure 9 Storage cell 110 is turned off. From time T21 to time T23, storage cell 110 is turned off, and the current flowing through storage cell 110 is a very small turn-off current Ioff. Because the word line WL floats from time T22 to time T23, the word line voltage VWL can gradually increase due to the turn-off current Ioff. However, for ease of illustration, the word line voltage VWL is shown as uniform.

[0043] For example, the word line precharge period and the bit line precharge period do not overlap, such as Figure 8 and Figure 9 As shown. However, the inventive concept is not limited thereto. In another example, the word line precharge period and the bit line precharge period overlap.

[0044] For example, Figure 1 The capacitor of the word line WL can be compared to Figure 1 The capacitance of bit line BL is small. In an exemplary embodiment, the row driver 130 precharges word line WL at a faster rate during the word line precharge period from time T11 to time T12 than the column driver 120 precharges bit line BL at a faster rate during the bit line precharge period from time T12 to time T15. Similarly, in an exemplary embodiment, the row driver 130 precharges word line WL at a faster rate during the word line precharge period from time T21 to time T22 than the column driver 120 precharges bit line BL at a faster rate during the bit line precharge period from time T22 to time T23.

[0045] In operation S130, column driver 120 either floats the bit line BL driven to the target level VTARGET or decreases the voltage level of the bit line BL driven to the target level VTARGET. Although in Figure 1 Only one storage unit 110 is shown, however, connected to Figure 1 The number of storage cells 110 for bit line BL1 can be one or more. For example, Figure 1 The storage cell 110 shown may be the storage cell selected in the read operation and connected to the remaining storage cells of the bit line BL. Figure 1 (Not shown in the image) can be an unselected storage unit (i.e., another storage unit that is not involved in the read operation). This is because the selected and unselected storage units are connected together. Figure 1The bit line BL allows the initial level V2 of the word line WL and the target level VTARGET of the bit line BL to be applied to the opposite ends of each of the unselected memory cells. The voltage across each unselected memory cell can be lower than the voltage across the selected memory cells, but due to the voltage across each unselected memory cell, a shutdown current Ioff can flow through the unselected memory cells. As the number of unselected memory cells increases, the amount of shutdown current Ioff may also increase. In this case, the bit line voltage VBL can be changed or decreased. Figure 8 During the bit line amplitude period following time T15, column driver 120 either floats the bit line BL or reduces the bit line voltage VBL. Figure 9 During the bit line floating period from time T23 to T26, column driver 120 floats bit line BL or reduces bit line voltage VBL. Figure 8 The storage unit 110 is turned on at time T13, but will not be turned on again at time T15.

[0046] In reference Figure 12 In the described column decoder 260, under the control of the read control circuit 150, the switches SW5 to SW8 connected to the bit line BL can disconnect the bit line BL from the column driver 120, so the bit line BL can be floated by the switches.

[0047] In operation S135, the word line WL and the sensing data line SDL are electrically connected, therefore, charge sharing can occur between the word line WL and the sensing data line SDL. Figure 8 During the charge sharing period from time T15 to time T16, specifically the WL / SDL charge sharing period, charge sharing can occur between the word line WL and the sensing data line SDL. Figure 9 During the charge sharing period WL / SDL from time T23 to time T24, charge sharing can occur between the word line WL and the sensing data line SDL. Because charge sharing occurs, the voltage levels of the word line WL and the sensing data line SDL can be the same or equivalent.

[0048] In operation S135, after applying the target level VTARGET to memory cell 110, sense amplifier 140 can be enabled by read control circuit 150 and can sense the sense level (i.e., word line voltage VWL) of sense data line SDL. For example, read control circuit 150 can provide an enable signal for enabling or triggering sense amplifier 140. Sense amplifier 140 can compare the sense level with a reference level VREFS. For example, the reference level VREFS may exist in... Figure 9 The difference between the sensing levels SL1 and SL2 corresponds to the sensing margin. Figure 8 and Figure 9 An example is shown where the reference level VREFS is equal to the precharge level V4 of the sensing data line SDL, but the reference level VREFS can be different from the precharge level V4 of the sensing data line SDL. The sensing amplifier 140 can sense... Figure 8 The sensing level SL1 during the sensing period from time T16 to time T17. The sensing amplifier 140 can sense... Figure 9 The sensing level SL1 during the sensing period "first sensing" from time T24 to time T25 can be determined (or formed) in storage unit 110 after it is turned on at time T13. Figure 8 The sensing level SL1 can be determined during the bit line precharge period from time T22 to time T23. Figure 9 The sensing level SL1 is such that the memory cell 110 is not turned on during the bit line precharge period. Figure 8 The sensing level SL1 during the sensing period from time T16 to time T17 can be compared with... Figure 9 The sensing level SL1 during the sensing period from time T24 to time T25, which is "first sensing", is different from or higher than that. The sensing amplifier 140 can provide the sensing result of operation S135 to the readout control circuit 150.

[0049] In operation S135, the row driver 130 discharges the word line WL or drives the word line WL to a pre-charge level V1 after the sensing period (or after the sensing amplifier 140 senses the sensing level SL1). The row driver 130 can... Figure 8 During the word line discharge period from time T17 to time T18, the word line WL is discharged to the pre-charge level V1. The line driver 130 can... Figure 9 During the word line discharge period from time T25 to time T26, the word line WL is discharged to the pre-charge level V1. In an exemplary embodiment, the word line WL is... Figure 8 From time T17 to time T18 and Figure 9 The discharge rate during the word line discharge period from time T25 to time T26 is slower than the rate at which the bit line BL decreases during the bit line floating period. Therefore, even if the word line WL is discharged, the voltage amplitude across the memory cell 110 will not increase during the bit line discharge period, thus avoiding multiple turn-on cycles of the memory cell 110.

[0050] For example, the line driver 130 discharges the sensing data line SDL to a pre-charge level V1, such as Figure 8 and Figure 9 As shown. However, the inventive concept is not limited thereto. In another example, with Figure 8 and Figure 9Unlike the example shown, the line driver 130 does not discharge the sensing data line SDL to the precharge level V1.

[0051] Connected to Figure 1 The number of storage units 110 of the word line WL can be one or more. For example, Figure 1 The storage cell 110 shown may be the storage cell selected in a read operation and connected to the remaining storage cells of the word line WL. Figure 1 (Not shown) can be an unselected storage cell. Since both selected and unselected storage cells are connected to the same network... Figure 1 The word line VWL is such that the precharge level V1 of the word line WL and the initial level V2 of the bit line BL can be applied to the opposite ends of each of the unselected memory cells. The voltage across each unselected memory cell can be smaller than the voltage across the selected memory cells, but due to the voltage across each unselected memory cell, a shutdown current Ioff can flow through the unselected memory cells. As the number of unselected memory cells increases, the amount of shutdown current Ioff may also increase. In this case, the word line voltage VWL may be changed or decreased. The change in word line voltage VWL caused by the shutdown current Ioff flowing through the unselected memory cells can be eliminated by discharging the word line voltage VWL to the precharge level V1 in operation S135. By operating S135, the sensing margin of memory cell 110 can be improved.

[0052] In operation S140, the read control circuit 150 determines, based on the sensing result of the sensing amplifier 140, whether the memory cell 110 is in a set state (i.e., the memory cell 110 is turned on by operating the target level VTARGET and the precharge level V1 set in S110), or the memory cell 110 is in a reset state (i.e., the memory cell 110 is turned off by operating the target level VTARGET and the precharge level V1 set in S110). The sensing amplifier 140... Figure 8 The sensing result obtained by sensing the sensing level SLI during the charging sharing period after the time T13 after the memory cell 110 is turned on is compared with the sensing amplifier 140. Figure 9 The sensing results obtained by sensing the sensing level SL1 determined during the charging sharing period from time T22 to time T23 when the storage unit 110 is not turned on are different.

[0053] When the memory cell 110 is turned on by the target level VTARGET set in operation S110 (yes), in operation S145, the read control circuit 150 terminates the read operation on the memory cell 110. Figure 8In such cases, the read control circuit 150 can identify (check) the sensing result of the sensing amplifier 140 indicating that the memory cell 110 is turned on at time T13, or that the sensing level SL1 is higher than the reference level VREFS at time T13, and can terminate the read operation on the memory cell 110. This is illustrated for read operations associated with memory cells 110 having the same threshold voltage VTH1. Figure 5 and Figure 8 Comparison. In Figure 5 In this process, memory cell 110 is turned on twice, at times T3 and T5, while the bit line voltage VBL is increased to level V3 by column driver 120. Conversely, in Figure 8 In this process, memory cell 110 is turned on once at time T13, and simultaneously, the bit line voltage VBL is increased by column driver 120 to the target level VTARGET (lower than level V3). Afterwards, read control circuit 150 can terminate the read operation associated with memory cell 110 based on the sensing result of sensing level SL1 sensed by sense amplifier 140, and can control column driver 120 and row driver 130 so that voltage is no longer applied to memory cell 110. Figure 5 In comparison, Figure 8 In this process, multiple turns of memory cell 110 are avoided by operating S105 to S145.

[0054] When the target level VTARGET set in operation S110 does not turn on memory cell 110 (N), in operation S150, read control circuit 150 adjusts (or changes) the target level VTARGET. In operation S150, read control circuit 150 may increase the target level VTARGET by a value equal to the difference between the threshold voltage VTH and the switching voltage VS of memory cell 110. Memory device 100 may include one or more memory cells 110, and the increment of the target level VTARGET may be the minimum value Min(VTH-VS) of the difference between the threshold voltage and the switching voltage. Read control circuit 150 may control column driver 120 to adjust the target level VTARGET. Read control circuit 150 may control column driver 120, row driver 130, and sense amplifier 140 to re-execute operations S115 to S135. Figure 9In the event that the sensing result of the sensing amplifier 140 indicates that the storage cell 110 is turned off or the sensing level SL1 is lower than the reference level VREFS, the read control circuit 150 can re-execute operations S150 and S115 to S140. In operation S150, the read control circuit 150 can adjust the target level VTARGET1 to the target level VTARGET2. For example, the target level VTARGET2 can be a level lower than the level of "VTH + (VTH - VS) + (VTH - VS)". In an exemplary embodiment, VTARGET2 is higher than the target level VTARGET1.

[0055] In operation S115, the row driver 130 can drive or precharge the sense data line SDL to the precharge level V4 during the sense data line precharge period from time T26 to time T27. In the read operation, when operation S115 is executed for the first time, the word line WL is driven to the precharge level V1, but when operation S115 is executed again, the word line WL has already been discharged in operation S135. In operation S120, the row driver 130 floats the word line WL, which has been discharged to the precharge level V1, during the word line float period from time T26 to time T32.

[0056] In operation S125, column driver 120 can Figure 9During the bit line precharge period from time T26 to time T30, the bit line BL is driven to a target level VTARGET2, which is higher than the target level VTARGET1. At time T28, the voltage difference between the bit line voltage VBL and the word line voltage VWL can reach the threshold voltage VTH2 of the memory cell 110. The voltage across the memory cell 110 can be the threshold voltage VTH2 or greater (or exceed the threshold voltage VTH2), and the memory cell 110 is turned on. At time T28, a peak current Ipeak flows through the memory cell 110. From time T26 to time T28, the memory cell 110 is turned off, and the current flowing through the memory cell 110 is a very small turn-off current Ioff. Because the word line WL is floating from time T26 to time T28, the word line voltage VWL can gradually increase due to the turn-off current Ioff. However, for ease of illustration, the word line voltage VWL is shown as uniform. As the voltage VWL connected to the word line of memory cell 110 increases after time T28, the amplitude of the voltage across memory cell 110 decreases, and the current flowing through memory cell 110 decreases from the peak current Ipeak. At time T29, the voltage across memory cell 110 can reach the switching voltage VS2, the turn-off current Ioff flows through memory cell 110, and memory cell 110 is turned off. The time period from time T28 to time T29 is exaggerated to show the decrease in peak current Ipeak, and peak current Ipeak may be very short.

[0057] In operation S130, during the bit line floating period from time T30 to time T33, column driver 120 either floats the bit line BL that is driven to the target level VTARGET2 or lowers the voltage level of the bit line BL that is driven to the target level VTARGET2. Even if the bit line voltage VBL reaches the target level VTARGET2, the level of the bit line voltage VBL is lower than the target level VTARGET2.

[0058] In operation S135, during the charge sharing period from time T30 to time T31, the word line WL and the sensing data line SDL are electrically connected, thus charge sharing can occur between the word line WL and the sensing data line SDL. In operation S135, the sensing amplifier 140 can sense the sensing level SL2 during the sensing period "second sensing" from time T31 to time T32. The sensing level SL2 for the sensing period "second sensing" can be determined after the memory cell 110 is turned on at time T28, and the sensing level SL1 for the sensing period "first sensing" can be determined after the bit line pre-charge period from time T22 to time T23, during which the memory cell 110 is not turned on. For example, the difference between the sensing level SL1 for the sensing period "first sensing" and the sensing level SL2 for the sensing period "second sensing" can correspond to the sensing margin of the memory cell 110. The sensing amplifier 140 can provide the result of sensing the sensing level SL2 to the read control circuit 150. The process of sensing the data of the storage unit 110 by operating S115 to S135 can be referred to as "Q-sensing".

[0059] In operation S135, the row driver 130 can discharge the word line WL to the pre-charge level V1 during the word line discharge period from time T32 to time T33. For example, the row driver 130 can also discharge the sense data line SDL to the pre-charge level V1, such as... Figure 9 As shown. In another example, with Figure 9 Unlike the example shown, the line driver 130 does not discharge the sensing data line SDL to the precharge level V1.

[0060] In operation S140, the read control circuit 150 can identify whether the sensing result of the sensing amplifier 140 indicates that the memory cell 110 is turned on or the sensing level SL2 is higher than the reference level VREFS. In operation S145, the read control circuit 150 can terminate the read operation associated with the memory cell 110 and control the column driver 120 and row driver 130 so that no more voltage is applied to the memory cell 110. Figure 9 In this process, when operations S150 and S115 through S140 are repeatedly executed, multiple turns on of the memory unit 110 are avoided. (Reference) Figures 7 to 9 This describes an example of repeating operation S150 and operations S115 through S140 once. However, the number of repetitions of operations S150 and S115 through S140 can be one or more. The target level VTARGET can be increased by "rX(VTH-VS)" from the initial level set in operation S110. Here, "r" can indicate the number of times operations S150 and S115 through S140 are repeated, and can be an integer of 1 or greater.

[0061] In an exemplary embodiment, the read control circuit 150 turns on the memory cell 110 only once during a single read operation associated with the memory cell 110. Under the control of the read control circuit 150, a target level VTARGET, initially set to a relatively low value, is applied to bit line BL, which is connected to the memory cell 110. Then, under the control of the read control circuit 150, when the memory cell 110 is turned on, no voltage is applied to the memory cell 110, or when the memory cell 110 is not turned on, the target level VTARGET can be gradually increased by the difference between the threshold voltage VTH and the switching voltage VS of the memory cell 110. Subsequently, under the control of the read control circuit 150, the increased target level VTARGET can be applied to the bit line BL connected to the memory cell 110. The read control circuit 150 can perform a read operation on the memory cell 110 while gradually increasing the target level VTARGET to be applied to the bit line of the memory cell 110 based on whether the memory cell 110 is turned on or off. For example, this gradual increase can be performed by applying a series of step pulses to the bit line. Since the target level VTARGET is increased gradually, multiple turns of the memory cell 110 can be avoided during a single read operation.

[0062] Figure 10 Exemplary voltages and currents for memory cells with relatively small threshold voltages are shown, which can be determined based on... Figure 7 The flowchart changes accordingly. Figure 11 Exemplary voltages and currents for memory cells with relatively large threshold voltages are shown, which can be determined based on... Figure 7 The flowchart will vary. The following description will focus on... Figure 10 and Figure 8 The differences between them, and Figure 11 and Figure 9 The differences between them. Column drive 120 in Figure 10 During the bit line bias period following time T45, bit line BL will be maintained at the target level VTARGET1. Figure 11 During the bit line bias period from time T53 to time T56, column driver 120 holds bit line BL at the target level VTARGET1. Furthermore, column driver 120... Figure 11 During the bit line offset period from time T60 to time T63, the bit line BL will be held at the target level VTARGET2. In addition to the above bit line offset period, Figure 10 and Figure 11 The remaining time periods can be combined with Figure 8 and Figure 9 The corresponding time periods are basically the same.

[0063] Figure 12 A block diagram of a memory device according to an exemplary embodiment of the present invention is shown. The memory device 200 includes a memory cell array 210 having memory cells MC, column drivers 220, row drivers 230, sense amplifiers 240, read / write (read and write) control circuitry 250, column decoders 260, and row decoders 270. Each of the memory cells MC may be substantially the same as memory cell 110. The memory cells MC may be connected to word lines WL1 to WL4 and bit lines BL1 to BL4. The number of memory cells MC, word lines WL1 to WL4, and bit lines BL1 to BL4 are merely examples. The operation of column drivers 220, row drivers 230, sense amplifiers 240, and read / write control circuitry 250 may be substantially the same as the operation of column drivers 120, row drivers 130, sense amplifiers 140, and read control circuitry 150.

[0064] The column driver 220 includes a comparator 221 (e.g., a comparator circuit) and a clamping transistor 222. When the read / write control circuit 250 selects a reference voltage VREF1 in operation S110, the comparator 221 drives the clamping transistor 222 based on the comparison result of the reference voltage VREF1 and the target level VTARGET1. The clamping transistor 222 can output a voltage with the target level VTARGET1 based on the comparison result of the comparator 221 and the supply voltage VPP. When the read / write control circuit 150 selects a reference voltage VREF2 in operation S150, the comparator 221 drives the clamping transistor 222 based on the comparison result of the reference voltage VREF2 and the target level VTARGET2. The clamping transistor 222 can output a voltage with the target level VTARGET2 based on the comparison result of the comparator 221 and the supply voltage VPP. Although the column driver 220 is described as outputting a voltage with one of two target levels, VTARGET1 and VTARGET2, the column driver 220 can output one of the following levels depending on the number of repetitions of operation S150 and operations S115 to S140: the minimum level of the target level VTARGET, the maximum level of the target level VTARGET, and an intermediate level between the minimum and maximum levels. Under the control of the read / write control circuit 250, the column driver 220 can also output the following voltages: an unselected bit line voltage to be applied to the unselected bit lines among bit lines BL1 to BL4, an initial bit line voltage with an initial level (e.g., ... Figure 8 and Figure 9 V2), the programming bit line voltage to be applied to the selected bit line, etc.

[0065] The row driver 230 is connected to the sense data line SDL. The row driver 230 includes switches SW9 and SW10. Under the control of the read / write control circuit 250, the row driver 230 outputs a voltage with a pre-charge level V1, which is used to pre-charge or discharge word lines WL1 to WL4 via switch SW9. Under the control of the read / write control circuit 250, the row driver 230 outputs a voltage with a pre-charge level V4, which is used to pre-charge or discharge the sense data line SDL via switch SW10. Under the control of the read / write control circuit 250, the row driver 230 can also output the following voltages: an unselected word line voltage to be applied to the unselected word lines among word lines WL1 to WL4, and an initial word line voltage with an initial level (e.g., ...). Figure 8 and Figure 9 The voltages include V2), the programming word line voltage to be applied to the selected word line, etc. The line driver 230 can supply the aforementioned voltages to the line decoder 270 via the sensing data line SDL or another line not shown.

[0066] Sensing amplifier 240 can be connected to sensing data line SDL. Sensing amplifier 240 can sense the level of sensing data line SDL to determine the sensing result and can provide the sensing result to read / write control circuit 250. Because charge sharing occurs between the (selected) word line WL and sensing data line SDL in operation S135, the level of sensing data line SDL can be the same as the level of the selected word line WL.

[0067] The read / write control circuit 250 can control the column driver 220, row driver 230, sense amplifier 240, column decoder 260, and row decoder 270. During a read operation, the read / write control circuit 250 can control: the voltage level to be applied to the selected or unselected memory cell MC, the duration of the voltage application, and the order in which the voltage is applied. During a write operation, the read / write control circuit 250 can control: the voltage level to be applied to the selected or unselected memory cell MC, the duration of the voltage application, and the order in which the voltage is applied.

[0068] The column decoder 260 includes switches SW5 to SW8, which are respectively connected to bit lines BL1 to BL4. Figure 12 The number of switches SW5 to SW8 shown is an example. Column decoder 260 can select from switches SW5 to SW8 the following switches: switches connected to the selected bit line indicated by the column address. Read / write control circuitry 250 can send the column address to column decoder 260. Column decoder 260 can apply various voltages output from column driver 220 to the selected or unselected bit line.

[0069] The line decoder 270 includes switches SW1 to SW4, which are respectively connected to word lines WL1 to WL4. Figure 12 The number of switches SW1 to SW4 shown is an example. The row decoder 270 can select from switches SW1 to SW4 the following switches: switches connected to the selected word line indicated by the row address. The read / write control circuitry 250 can send the row address to the row decoder 270. The selected switch can electrically connect the selected word line indicated by the row address and the sense data line SDL. The memory cell MC connected to the selected bit line and the selected word line can be referred to as the "selected memory cell MC". The row decoder 270 can apply various voltages output from the row driver 230 to the selected or unselected word line.

[0070] Figure 13 A block diagram of a memory device according to an exemplary embodiment of the present invention is shown. Memory device 300 includes a memory cell array 310 having memory cells MC, a column decoder 320, a row decoder 330, a sense amplifier 340, read / write control circuitry 350, a column decoder 360, and a row decoder 370. Components 310 and 330 to 370 of memory device 300 may be substantially the same as components 210 and 230 to 270 of memory device 200. Column driver 320 includes switches SW11 and SW12. Column driver 320 can output a voltage with a target level VTARGET1 by (using) switch SW11. Column driver 320 can output a voltage with a target level VTARGET2 by (using) switch SW12. Figure 12 and Figure 13 In both diagrams, column driver 320 can output the following voltages: voltages with target levels VTARGET1, VTARGET2, VTARGET3, etc., voltages with initial levels, non-select bit line voltages, programmable bit line voltages, etc.

[0071] In one embodiment, Figure 12 and Figure 13 The switches SW1 to SW4, SW5 to SW8, SW9 to SW10 and SW11 to SW12 shown can be implemented using transistors (e.g., NMOS transistors, PMOS transistors or combinations thereof).

[0072] Figure 14A block diagram of a memory device according to an exemplary embodiment of the present invention is shown. The memory device 400 includes a tray 410, column drivers 420, row drivers 430, sense amplifiers 440_1 to 440_t, read / write control circuitry 450, column decoder 460, and row decoder 470. Each of the column drivers 420, row drivers 430, sense amplifiers 440_1 to 440_t, read / write control circuitry 450, column decoder 460, and row decoder 470 may be implemented identically to column driver 220 or 320, row driver 230, sense amplifier 240, read / write control circuitry 250, column decoder 260, and row decoder 270.

[0073] Multiple memory cells of memory device 400 (reference) Figure 12 and Figure 13 The MC (memory cell) can form a bracket 410. The bracket 410 can include multiple memory cells and can be divided into one or more tiles 410_1 to 410_t (t is an integer of 2 or greater). Each of the one or more tiles 410_1 to 410_t can include multiple memory cells. For example, in each of the one or more tiles 410_1 to 410_t, the number of word lines connected to the memory cells can be 4K (= 2^32). 12 ) or more (or may exceed 4K), and the number of bit lines connected to the memory cell can be 2K (=2 11 ) or more (or possibly more than 2K). However, the inventive concept is not limited to these values. Unlike memory devices 200 and 300, memory device 400 includes a number of sense amplifiers 410_1 to 410_t equal to the number of tiles 410_1 to 410_t included in a bracket 410. The sense amplifier 440_1 can sense data from memory cells in tile 410_1 via word line WL and sense data line SDL to determine a sensing result, and can provide the sensing result to read / write control circuitry 450. The operation of sense amplifiers 440_2 to 440_t can be similar to the operation of sense amplifier 440_1.

[0074] For example, in a read or write operation, a memory cell MC can be selected for each bay 410. The column driver 420, column decoder 460, and row decoder 470 can apply various voltages required for the read or write operation under the control of the read / write control circuit 450. Sensing amplifiers 440_1 to 440_t, corresponding to the tile where the selected memory cell is located, can sense the data of the selected memory cell and provide the sensing results to the read / write control circuit 450. One or more memory cells MC can be selected for each bay 410 in a read or write operation.

[0075] Figure 15 A block diagram of a memory device according to an exemplary embodiment of the present invention is shown. The memory device 500 includes layers L1 and L2, with layer L2 located, arranged, or stacked on layer L1. The vertical relationship between layers L1 and L2 can be interchanged. References can be used... Figures 1 to 14 The described storage cells MC are arranged in layer L2. The storage cells MC arranged in layer L2 can constitute a storage unit 510. The storage unit 510 can include multiple trays 511. The trays 511 can be connected to... Figure 4 Corresponding to the bracket 410, it may include memory cells MC connected to word lines WL and bit lines BL. The number of memory cells MC, the number of brackets 511, and the number of memory blocks 510 are merely examples.

[0076] A bracket control circuit 520 may be arranged in layer L1. The bracket control circuit 520 controls brackets 511 arranged in layer L2. For example, in a plan view, the bracket control circuit 520 and the brackets 511 controlled by the bracket control circuit 520 overlap each other. The bracket control circuit 520 includes a column driver 522, a row driver 523, a sense amplifier 524, a read / write control circuit 525, a column decoder 526 (e.g., a decoding circuit), and a row decoder 527 (e.g., a decoding circuit). Components 522 to 527 of the bracket control circuit 520 may be integrated with… Figure 14 The various components 420 to 470 of the memory device 400 are basically the same.

[0077] Memory device 500 includes a command decoder 531 (e.g., decoding circuitry), an address buffer 532, data processing circuitry 533, error correction circuitry (ECC) 534, an on-cell counter (OCC) 535 (e.g., counting circuitry), a randomizer 536, a register 537, and a voltage generator 538. Components 531 to 538 may be included in the peripheral circuitry of memory device 500, and the peripheral circuitry may be arranged in layer L1. The following structure may be referred to as a "peripheral cell (COP)": a memory cell MC is arranged in layer L2, and circuitry 520 and 531 to 538 for controlling the memory cell MC are arranged in layer L1.

[0078] Command decoder 531 can receive commands CMD from outside the memory device 500 (e.g., a host or memory controller). Command decoder 531 can decode the commands CMD to produce a decoding result, and can control the remaining components 511, 520, and 532 to 538 of the memory device 500 based on the decoding result. For example, the commands CMD may include a read command or a write command for the memory cell MC. The tray control circuit 520 can perform operations S105 to S150 once under the control of command decoder 531, which decodes the read command.

[0079] Address buffer 532 can receive an address ADD from outside the memory device 500. The address ADD can indicate at least one or more memory cells to be selected from the memory cells of the memory device 500. Address buffer 532 can provide column addresses to column decoder 526 of carriage control circuit 520, which controls carriage 511 including the memory cell MC indicated by address ADD, and can provide row addresses to row decoder 527 of carriage control circuit 520, which also controls carriage 511 including the memory cell MC indicated by address ADD. Command decoder 531 can selectively control carriage control circuit 520 that controls carriage 511 including the memory cell MC indicated by address ADD. For example, command decoder 531 receiving one of a read command and a write command can simultaneously select one or more carriage control circuits 520.

[0080] Data processing circuit 533 can receive data "DATA", including write data, from outside the memory device 500. Data processing circuit 533 can provide the write data to the selected bay control circuit 520. In each of the selected bay control circuits 520, read / write control circuit 525 can control the remaining components 522 to 527 to write the write data into the selected memory cell MC. Data processing circuit 533 can receive read data from the selected bay control circuit 520. Data processing circuit 533 can output data "DATA", including read data. In each of the selected bay control circuits 520, read / write control circuit 525 can control the remaining components 522 to 527 to read read data from the selected memory cell MC.

[0081] Error correction circuit 534 can perform encoding operations on write data to be written to the selected memory cell MC based on error correction codes. Error correction circuit 534 can also perform decoding operations on read data read from the selected memory cell MC based on error correction codes. Error correction circuit 534 can detect errors in the read data, calculate the error count (e.g., the number of erroneous bits) in the read data, and determine whether the errors in the read data are correctable or can be corrected. Error correction circuit 534 can provide the error count of the read data to data processing circuit 533. For example, data processing circuit 533 can provide the write data encoded by error correction circuit 534 to the selected carriage control circuit 520. Data processing circuit 533 can output data "DATA" including the read data decoded by error correction circuit 534.

[0082] The on-cell counter 535 can calculate the number of on-cell OCCs in the selected memory cell MC based on read data output from the selected memory cell MC. The on-cell counter 535 can provide the number of on-cell OCCs to the data processing circuit 533. In an exemplary embodiment, the on-cell counter 535 is not included in the memory device 500. The randomizer 536 can perform a randomization operation on write data to be written to the selected memory cell MC. The randomizer 536 can perform a de-randomization operation on read data read from the selected memory cell MC. For example, when each stored digital logic value in the memory cell MC is one of "0" and "1", the randomizer 536 can adjust the ratio of 1s to 0s in the write data to be written to the selected memory cell MC. The randomizer 536 can calculate the ratio of 1s to 0s in the read data. For example, the randomizer 536 can identify whether the ratio of 1s to 0s in the write data is different from the ratio of 1s to 0s in the read data. The randomizer 536 can provide information about the aforementioned ratio to the data processing circuit 533. In an exemplary embodiment, the randomizer 536 is not included in the memory device 500.

[0083] Register 537 can store various information about memory device 500. For example, register 537 can store: information about the results of operations performed by error correction circuit 534, error counts calculated by error correction circuit 534, the number of active memory cells (OCCs) calculated by active cell counter 535, the ratio calculated by randomizer 536, information about the target level VTARGET set in operation S110 or operation S150, written data, read data, operating conditions, etc.

[0084] Voltage generator 538 can generate various voltages to be used in memory device 500 by using the power supply voltage applied to memory device 500, and can supply the generated voltages to components 510, 520, and 531 to 538 of memory device 500. The power supply voltage applied to memory device 500 may include VDD, VPP, GND, etc. Voltage generator 538 can generate and provide... Figure 12 and Figure 13The voltages shown are VREF1, VREF2, V1, V4, VTARGET1, and VTARGET2. Furthermore, various voltages used in the memory device 500 may include: voltages with various target levels VTARGET1, VTARGET2, VTARGET3, etc.; voltages with an initial level V2; voltages with precharge levels V1 and V4; unselected bit line voltages to be applied to unselected bit lines; unselected word line voltages to be applied to unselected word lines; programming bit line voltages; programming word line voltages; reference voltages VREF1 and VREF2; and a reference voltage VREFS to be used by the sense amplifier 524, etc.

[0085] Figure 16 An arrangement illustrating an exemplary embodiment of the concept according to the present invention is shown in Figure 14 The storage units in layer L2. Layer L2 can be connected with... Figure 15 The memory cell MC corresponds to layer L2. Directions D1 to D3 can be perpendicular to each other. Direction D1 can indicate the direction of bit line BL, direction D2 can indicate the direction of word line WL, and direction D3 can correspond to the stacking direction of layers L1 and L2 and the direction away from layer L2 in the plan view. Each memory cell MC can be placed at or located at the intersection of word line WL and bit line BL. Word line WL can be located above bit line BL along direction D3. Figure 16 As shown, the storage element and select element of each memory cell MC can be connected to the word line WL and the bit line BL, respectively. As mentioned above, because the memory cell MC has bidirectional characteristics, it is compatible with… Figure 16 Unlike the example shown, the storage element and select element of each of the storage cells MC can be connected to the word line WL and the bit line BL, respectively.

[0086] Figures 17 to 19 An arrangement illustrating an exemplary embodiment of the concept according to the present invention is shown in Figure 15 The memory device 500 includes memory cells in layer L2 and memory cells in layer L3 arranged above layer L2. The memory device 500 may also include memory cells MC arranged in layer L3, where layer L3 is located, arranged, or stacked above / on layer L2. The number of layers in which the memory cells MC are arranged can be one or more. (See reference...) Figure 17 The arrangement of the storage cells MC in layer L2 can be consistent with... Figure 16 The arrangement of the memory cells MC in layer L2 is basically the same. The memory cells MC in layer L3 can be arranged similarly to those in layer L2. Each of layers L2 and L3 may include a bit line BL and a word line WL. As mentioned above, because the memory cells MC have bidirectional characteristics, the positions of the storage elements and selection elements in each memory cell MC are not limited to... Figure 17 The examples shown are interchangeable.

[0087] refer to Figure 18 and Figure 19 The arrangement of the storage cells MC in layer L2 can be consistent with... Figure 16 The arrangement of the memory cells (MCs) in layer L2 is similar. The arrangement of the memory cells (MCs) in layer L3 can be similar to... Figure 16 The arrangement of the memory cells (MCs) in layer L2 is similar. (See reference...) Figure 18 Layers L2 and L3 can include a common word line WL, and the word line WL can be shared by layers L2 and L3. Conversely, refer to... Figure 19 Layers L2 and L3 may include a common bit line BL, and the bit line BL can be shared by layers L2 and L3. As mentioned above, because the memory cell MC has bidirectional characteristics, therefore, as referred to Figure 16 The positions of the storage elements and selection elements in each of the storage units MC can be interchanged, and are not limited to... Figure 18 and Figure 19 As shown, the storage element can be connected to one of the word line WL and the bit line BL, and the select element can be connected to one of the bit line BL and the word line WL.

[0088] Figure 18 and Figure 19 An example is shown where, in each of layers L2 and L3, the storage element is located below the selection element relative to direction D3. However, in each of layers L2 and L3, the storage element may be located above the selection element relative to direction D3. The arrangement of storage cells MC in even-numbered layers L2 and in odd-numbered layers L3 is asymmetrical with respect to the plane defined by directions D1 and D2. Conversely, in even-numbered layers L2, the storage element is located below (or above) the selection element; in odd-numbered layers L3, the storage element is located above (or below) the selection element. In this case, the arrangement of storage cells MC in even-numbered layers L2 and in odd-numbered layers L3 is symmetrical with respect to the plane defined by directions D1 and D2.

[0089] In one embodiment, although not in Figure 18 and Figure 19 As shown, however, at least one layer L4 can be stacked on top of... Figure 18 and Figure 19 Above / above layer L3. In this case, as Figure 18 As shown, any two layers can include a common word line WL or can share a word line WL; and as... Figure 19 As shown, the other two layers may include a common bit line BL or may share a bit line BL.

[0090] In one embodiment, the target level VTARGET is Figure 7 The increment "VTH-VS" and target level VTARGET in operation S110 Figure 7 The incremental "VTH-VS" in operation S150 can be determined according to Figure J6 to... Figure 19 The distribution (or characteristics) of the switching voltage VS of the memory cell MC and the distribution (or characteristics) of the threshold voltage VTH of the memory cell MC can vary depending on the layers L2 and L3 in which the memory cell MC is located. Figure 15 The bracket control circuit 520 can be configured to have different target levels VTARGET applied to the memory cell MC in layer L2 and layer L3 in operation S110. For example, as the height of the layer where the memory cell MC is located increases along direction D3, the target level VTARGET of operation S110 can be increased (or decreased). Figure 15 The bracket control circuit 520 can be configured differently for the increment "VTH-VS" of the target level VTARGET to be applied to the memory cell MC in layer L2 during operation S110 and the increment "VTH-VS" of the target level VTARGET to be applied to the memory cell MC in layer L3 during operation S110. For example, as the height of the layer where the memory cell MC is located increases along direction D3, the increment "VTH-VS" of the target level VTARGET in operation S150 can become larger (or smaller). Figures 8 to 11 The target level VTARGET1 shown can vary depending on layers L2 and L3, and Figures 8 to 11 The target level VTARGET2 shown can also vary depending on layers L2 and L3.

[0091] Figure 20 A flowchart illustrating an on-chip valley search operation according to an exemplary embodiment of the present invention is shown. In operation S205, the data processing circuit 533, under the control of the command decoder 531, initiates an on-chip valley search (OVS) operation. The command decoder 531 receives a read command or a command 500 requesting an on-chip search operation from outside the memory device. The data processing circuit 533 can perform the on-chip search operation to search for or track the optimal read voltage of the memory cell MC.

[0092] In operation S210, the data processing circuit 533 receives a first sensing result from the read / write control circuit 525 of the selected bracket control circuit 520. The first sensing result of operation S210 can correspond to the following sensing result: when each of the selected bracket control circuits 520 is first executed... Figure 7During operations S105 to S135, while the target level VTARGET1 is applied to the storage cell 110, the sensing result generated in operation S135 is described. In operation S215, the error correction circuit 534 calculates a first error count based on the first sensing result. The processing circuit 533 can provide the first sensing result to the error correction circuit 534. The error correction circuit 534 can provide the first error count to the data processing circuit 533.

[0093] In operation S220, the data processing circuit 533 receives a second sensing result from the read / write control circuit 525 of the selected bracket control circuit 520. The second sensing result of operation S220 can correspond to the following sensing result: when the selected bracket control circuit 520 executes... Figure 7 When operation S150 is executed and operations S115 to S135 are executed again, the sensing result generated in operation S135 is performed while the target level VTARGET2 is applied to the storage unit 110. In operation S225, the error correction circuit 534 calculates the second error count data based on the second sensing result. The data processing circuit 533 can provide the second sensing result to the error correction circuit 534. The error correction circuit 534_2 can provide the second error count to the data processing circuit 533.

[0094] In operation S230, data processing circuit 533 can adjust the target level VTARGET for the next read operation based on the first and second error counts. Data processing circuit 533 can control the column driver 220 and voltage generator 538 of each of the read / fetch control circuit 525 and the carriage control circuit 520 to adjust the target level VTARGET. For example, under the control of data processing circuit 533, voltage generator 538 can adjust reference voltages VREF1 and VREF2 used to output the target level VTARGET, and can output voltages with adjusted target levels VTARGET1 and VTARGET2. When a first input command is input to memory device 500, data processing circuit 533 can receive the first and second sensing results generated in operations S210 and S220, and output these results to error correction circuit 534 to calculate the first and second error counts in operations S215 and S225. For example, data processing circuit 533 can compare the first and second error counts. When a second read command is input to memory device 500 and a read operation is performed again, data processing circuit 533 can... Figure 7The target level VTARGET set in operation S105 is adjusted to obtain a sensing result showing a relatively low error count. That is, the target level VTARGET set in operation S105 after the first input command input memory device 500 can be different from the target level VTARGET set in operation S150 after the second input command input memory device 500. In one embodiment, in operation S230, the data processing circuit 533 can adjust the target level VTARGET based on a first conduction unit count and a second conduction unit count calculated by the conduction unit counter 535 for the first sensing result and the second sensing result, respectively. In another embodiment, in operation S230, the data processing circuit 533 can adjust the target level VTARGET based on a first ratio information and a second ratio information obtained by the randomizer 536 for the first sensing result and the second sensing result, respectively. In another embodiment, the data processing circuit 533 can adjust the target level VTARGET by combining the error count, the conduction unit count, and the ratio information.

[0095] In operation S235, the data processing circuit 533 terminates the on-chip search operation. (And...) Figure 20 The example shown is different; the number of times the sensing results are received before operation S230 and the number of times information about the sensing results is calculated can each be two or more times.

[0096] Figures 21 to 24 This is a block diagram illustrating an electronic device employing a memory device according to an embodiment of the concept of the present invention. Each of the electronic devices 1000 to 4000 may be referred to as a "computing system," "memory system," "electronic system," or "communication system." For example, each of the electronic devices 1000 to 4000 may be a desktop computer, laptop computer, tablet computer, mobile device, smartphone, personal digital assistant (PDA), portable multimedia player (PMP), wearable device, video game console, workstation, server, data processing device capable of using or supporting the interface protocol proposed by the Mobile Industrial Processor Interface (MIPI) Alliance, home appliance, black box, drone, etc.

[0097] refer to Figure 21The electronic device 1000 includes a host 1100 and a memory module 1200. The host 1100 can exchange data with the memory module 1200. For example, the host 1100 may include one or more cores. The host 1100 may include a memory controller that controls the memory module 1200. The memory controller can send at least one of the following to the memory module 1200 via channel CH: command CMD, address ADD, and data “DATA”, or it can receive data “DATA” from the memory module 1200 via channel CH.

[0098] Memory module 1200 may include memory device 1300. In electronic device 1000, the number of memory modules and the number of memory devices 1300 attached to a memory module 1200 are not limited to... Figure 11 Examples. Memory module 1200 may be a single in-line memory module (SIMM) or a dual in-line memory module (DIMM). Memory device 1300 may include at least one of the following: (Refer to...) Figures 1 to 20 The memory devices described are 100 to 500, including Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Thyristor RAM (TRAM), NAND flash memory, NOR flash memory, Resistive RAM (RRAM), and Ferroelectric RAM (FRAM). The type of memory device 1300 can be one or more. For example, the memory module 1200 can be a SIMM, DIMM, Registered DIMM (RDIMM), Reduced Load DIMM (LRDIMM), Unbuffered DIMM (UDIMM), Fully Buffered DIMM (FB-DIMM), Small DIMM (SO-DIMM), Non-Volatile DIMM (NVDIMM), etc.

[0099] refer to Figure 22 Electronic device 2000 includes host 2100 (e.g., host device) and storage device 2200. Host 2100 can exchange data with storage device 2200. Storage device 2200 includes controller 2210 having on-chip memory 2215, buffer memory 2216, and memory device 2220. Controller 2210 can process requests from host 2100, can execute programs loaded onto on-chip memory 2215 or buffer memory 2216, and can control memory device 2220. On-chip memory 2215, buffer memory 2216, and memory device 2220 may include at least one of the following: [reference needed] Figures 1 to 20The described memory devices 100 and 500 include SRAM devices, DRAM devices, TRAM devices, NAND flash memory devices, NOR flash memory devices, RRAM devices, FRAM devices, and MRAM devices. For example, storage device 2200 may be a solid-state drive (SSD) device, a memory card that can be attached to or removed from electronic device 2000, a secure digital card (SD card), an embedded multimedia card (eMMC), a universal flash memory (UFS) card, etc. Host 2100 or controller 2210 may request data from on-chip memory 2215 or storage device 2220 according to... Figure 7 The flowchart reading operation or based on Figure 20 The OVS operation of the flowchart.

[0100] refer to Figure 23 Electronic device 3000 includes a processor 3100, working memory 3200, storage device 3300, communication block 3400 (e.g., modem or network card), user interface 3500, and bus 3600. The working memory 3200 and storage device 3300 can exchange data with the processor 3100. The working memory 3200 can be used as a buffer or cache for electronic device 3000. The storage device 3300 can store data regardless of whether it is powered on. The working memory 3200 and storage device 3300 may include at least one of the following: [reference] Figures 1 to 20 The described memory devices 100 and 500 include SRAM, DRAM, TRAM, NAND flash memory, NOR flash memory, RRAM, FRAM, and MRAM. Communication block 3400 allows communication with external devices of electronic device 3000. User interface 3500 allows users to communicate with electronic device 3000. Bus 3600 provides communication paths between components of electronic device 3000.

[0101] refer to Figure 24The electronic device 4000 includes an application processor 4100, a display 4220, and an image sensor 4230. The application processor 4100 may include a DigRF master device 4110, a Display Serial Interface (DSI) master 4120, a Camera Serial Interface (CSI) master 4130, and a physical layer 4140. The DSI master 4120 can communicate with the DSI device 4225 of the display 4220 via the DSI. For example, a serializer SER can be implemented in the DSI master 4120, and a deserializer DES can be implemented in the DSI device 4225. The CSI master 4130 can communicate with the CSI device 4235 of the image sensor 4230 via the CSI. For example, the deserializer DES can be implemented in the CSI master 4130, and the serializer SER can be implemented in the CSI device 4235. The electronic device 4000 may also include a radio frequency (RF) chip 4240 for communicating with the application processor 4100. RF chip 4240 may include physical layer 4242, digital radio frequency (DigRF) slave device 4244, and antenna 4246. For example, physical layer 4242 and physical layer 4140 may exchange data with each other according to the digital radio frequency interface proposed by the MIPI Alliance. Electronic device 4000 may also include working memory 4250 and embedded / card storage device 4255. Working memory 4250 and embedded / card storage 4255 may store or output data associated with application processor 4100. Working memory 4250 and embedded / card storage device 4255 may include at least one of the following: Reference Figures 1 to 20 The described memory devices 100 and 500 include SRAM, DRAM, TRAM, NAND flash memory, NOR flash memory, RRAM, FRAM, and MRAM. An embedded storage device 4255 can be embedded in an electronic device 4000, and a card storage device 4255 as a removable device can be installed on the electronic device 4000. The electronic device 4000 can communicate with external devices / systems via communication modules such as WiMAX 4260, WLAN 4262, and UWB 4264. The electronic device 4000 may also include a speaker 4270, a microphone 4275, a GPS device 4280, and a bridge chip 4290.

[0102] According to at least one embodiment of the present invention, the reliability or durability of a memory cell can be improved by avoiding multiple turn-on cycles of the memory cell. Furthermore, the sensing margin of the selected memory cell can be improved by preventing changes in the word line voltage due to the turn-off current of an unselected memory cell. Additionally, multiple sensing results can be obtained in a single read operation, and the optimal read voltage for each memory cell can be determined using these multiple sensing results.

[0103] Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept.

Claims

1. A memory device, comprising: Storage cells are connected to word lines and bit lines; A line driver is configured to drive the word line to a precharge level; A column driver is configured to drive the bit line to a first target level; A sensing amplifier is configured to sense a first sensing level of the word line after the first target level is applied to the memory cell; as well as The read control circuit is configured to control the column driver based on a first sense level sensed by the sense amplifier, such that a second target level different from the first target level is selectively applied to the memory cell. The read control circuit is further configured as follows: When the first sensing level is higher than the reference level, the column driver is controlled so that the second target level is not applied to the memory cell and the read operation on the memory cell is terminated.

2. The memory device of claim 1, wherein, The read control circuit is also configured to: When the first sensing level is lower than the reference level, the column driver is controlled to apply the second target level to the memory cell and perform a read operation on the memory cell.

3. The memory device of claim 1, wherein, The column driver is also configured to drive the bit line to the second target level under the control of the read control circuit, and The sensing amplifier is further configured to sense a second sensing level of the word line after the second target level is applied to the memory cell.

4. The memory device of claim 3, wherein, The read control circuit is further configured to control the column driver based on a second sensing level sensed by the sensing amplifier, such that a third target level, different from the second target level, is applied to the memory cell.

5. The memory device of claim 3, wherein, After driving the bit line to the first target level, the sense amplifier is enabled by the readout control circuit, and after driving the bit line to the second target level, the sense amplifier is enabled by the readout control circuit.

6. The memory device of claim 1, wherein, The row driver is also configured to: After the sensing amplifier senses the first sensing level, the word line is discharged to the pre-charge level.

7. The memory device of claim 6, wherein, The row driver discharges the word line at a slower rate than the level of the bit line driven to the first target level decreases.

8. The memory device of claim 1, wherein, The difference between the second target level and the first target level is based on the difference between the threshold voltage and the switching voltage of the memory cell.

9. The memory device according to claim 1, further comprising: A line decoder, including a switch connected between the word line and the sensing data line, the sensing data line being connected to the sensing amplifier, and... When the bit line is driven to the first target level by the column driver, the switch electrically connects the word line and the sensing data line.

10. A memory device, comprising: Multiple bays, each bay including a storage unit connected to word lines and bit lines; as well as Multiple bay control circuits, each configured to access the memory cell via the word lines and the bit lines. Each of the plurality of bracket control circuits is configured as follows: Based on the first read command, a first sensing operation is performed on the memory cell by driving the word line to a precharge level and the bit line to a first target level; and Based on the first sensing result of the first sensing operation, a second sensing operation is performed on the memory cell by driving the word line to the precharge level and selectively driving the bit line to the second target level. Specifically, when the first sensing result indicates that the storage unit is turned on, each of the plurality of bracket control circuits does not perform the second sensing operation, while when the first sensing result indicates that the storage unit is turned off, each of the plurality of bracket control circuits performs the second sensing operation.

11. The memory device of claim 10, further comprising: The data processing circuit is configured to receive the first sensing result and the second sensing result of the second sensing operation from each of the plurality of bracket control circuits, and to adjust the first target level based on the first sensing result and the second sensing result.

12. The memory device of claim 11, wherein, Each of the plurality of bracket control circuits is further configured to: Based on the second read command, a third sensing operation is performed on the memory cell by driving the word line to the precharge level and driving the bit line to the first target level adjusted by the data processing circuit.

13. The memory device of claim 11, further comprising: The error correction circuit is configured to perform a first error correction operation on the first sensing result and a second error correction operation on the second sensing result. The data processing circuit is further configured to adjust the first target level based on a first error count corresponding to the result of the first error correction operation and a second error count corresponding to the result of the second error correction operation.

14. The memory device of claim 10, wherein, The storage unit includes a memory element and a selection element, wherein the memory element includes a phase change material. The command decoder and the plurality of tray control circuits are disposed in the first layer of the memory device, and The plurality of brackets are disposed in the second layer above the first layer.

15. The memory device of claim 10, wherein, Each of the plurality of bracket control circuits includes: A line driver is configured to drive the word line to the precharge level and stop driving the word line driven to the precharge level or hold the word line at the precharge level; A column driver is configured to drive the bit line to the first target level and stop driving the bit line to the first target level or hold the bit line at the precharge level; A sensing amplifier is configured to sense a first sensing level of the word line after the first target level is applied to the memory cell; and The read control circuit is configured to control the column driver based on the first sensing result, such that the second target level is selectively applied to the memory cell.

16. The memory device of claim 15, wherein, During at least a portion of the period in which the bit line is driven to the first target level, the row driver does not drive the word line to the precharge level or holds the word line at the precharge level.

17. A method of operating a memory device, comprising: Drive the word lines connected to the memory cells to the precharge level; Drive the bit line connected to the memory cell to the first target level; After the bit line is driven to the first target level, a first sensing operation is performed to sense the first sensing level of the word line; as well as Based on the first sensing result of the first sensing operation, determine whether to perform a second sensing operation using a second target level different from the first target level. The determination includes: Determine whether the memory cell is turned on or off by the precharge level and the first target level. Specifically, when it is determined that the storage cell is turned on, the second sensing operation is not performed, and Specifically, when it is determined that the storage unit is turned off, the second sensing operation is performed.

18. The operating method according to claim 17, further comprising: After sensing the first sensing level, the word line is discharged to the pre-charge level.

19. The operating method according to claim 17, further comprising: When it is determined that the second sensing operation is to be performed, a second sensing operation is performed to sense the second sensing level of the word line after the second target level is applied to the memory cell; as well as Based on the second sensing result of the second sensing operation, determine whether to perform a third sensing operation using a third target level different from the second target level.

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