Apparatus and method for providing thermal parameter reporting for multi-chip packages

Abstract

In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and to determine a minimum temperature control margin among a plurality of temperature control margins. Each temperature control margin is to be determined based on a corresponding thermal control temperature associated with the die and also based on the corresponding temperature data associated with the die. The power management logic is also to generate a thermal report, the thermal report being to include the minimum temperature control margin; and store the thermal report. Other embodiments are described and claimed.

Description

Technical Field

[0001] Embodiments relate to power management of systems, and more particularly to power management of multi-chip packages including processors. Background Art

[0002] Developments in semiconductor processing and logic design have permitted growth in the amount of logic that can be present on integrated circuit devices. As a result, computer system configurations have evolved from single integrated circuits to systems that may involve multiple hardware threads, multiple cores, multiple devices, and / or complete systems on separate integrated circuits. In addition, as the density and performance of integrated circuits have grown, the power requirements for computing systems (from embedded systems to servers) have also increased. In addition, software inefficiencies and the requirements of their hardware have also caused an increase in computing device energy consumption. In fact, some studies have shown that computing devices consume a considerable percentage of the entire power supply for a country (such as the United States of America). As a result, there is a vital need for energy efficiency and savings associated with integrated circuits. These needs will increase as servers, desktop computers, notebooks, Ultrabooks™, tablet computers, mobile phones, processors, embedded systems, etc. become even more common (from being included in typical computers, cars, and televisions to biotechnology). BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram of a portion of a system according to an embodiment of the present invention.

[0004] Figure 2 is a block diagram of a processor according to an embodiment of the present invention.

[0005] Figure 3 is a block diagram of a multi-domain processor according to another embodiment of the present invention.

[0006] Figure 4 is an embodiment of a processor comprising multiple cores.

[0007] Figure 5 is a block diagram of a micro-architecture of a processor core according to one embodiment of the present invention.

[0008] Figure 6 is a block diagram of a microarchitecture of a processor core according to another embodiment.

[0009] Figure 7 is a block diagram of a microarchitecture of a processor core according to yet another embodiment.

[0010] Figure 8 is a block diagram of a microarchitecture of a processor core according to yet another embodiment.

[0011] Fig. 9is a block diagram of a processor according to another embodiment of the present invention.

[0012] Fig.10 is a block diagram of a representative SoC according to an embodiment of the present invention.

[0013] Fig.11 is a block diagram of another example SoC according to an embodiment of the present invention.

[0014] Fig.12 is a block diagram of an example system with which embodiments may be used.

[0015] Fig.13 is a block diagram of another example system with which embodiments may be used.

[0016] Fig.14 is a block diagram of a representative computer system.

[0017] Fig.15 is a block diagram of a system according to an embodiment of the present invention.

[0018] Fig.16 is a block diagram of a multi-chip package according to an embodiment of the present invention.

[0019] Fig.17 is a flow chart of a method according to an embodiment of the present invention.

[0020] Fig.18 is a flow chart of a method according to another embodiment of the present invention. DETAILED DESCRIPTION

[0021] Although the following embodiments are described with reference to energy conservation and energy efficiency in a particular integrated circuit (such as a computing platform or processor), other embodiments may be applied to other types of integrated circuits and logic devices. Similar techniques and teachings of the embodiments described herein may be applied to other types of circuits or semiconductor devices, which may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to any particular type of computer system. That is, the disclosed embodiments may be used for many different system types, ranging from server computers (e.g., towers, racks, blades, microservers, etc.), communication systems, storage systems, desktop computers, laptops, notebooks, and tablet computers (including 2:1 tablets, tablet phones, etc.) of any configuration, and may also be used in other devices such as handheld devices, systems on chips (SoCs), and embedded applications. Some examples of handheld devices include cellular phones such as smart phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may typically include microcontrollers, digital signal processors (DSPs), network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, wearable devices, or any other system that can perform the functions and operations taught below. More so, embodiments may be implemented in mobile terminals with standard voice capabilities (such as mobile phones, smart phones, and tablet phones) and / or in non-mobile terminals without standard wireless voice communication capabilities (such as many wearable devices, tablets, notebooks, desktops, micro servers, servers, etc.). In addition, the apparatus, methods, and systems described herein are not limited to physical computing devices, but may also involve software optimization for energy conservation and efficiency. As will be readily apparent in the following description, embodiments of the methods, apparatus, and systems described herein (whether or not with reference to hardware, firmware, software, or a combination thereof) are critical to the future of "green technology", such as power conservation and energy efficiency in products covering a large portion of the U.S. economy.

[0022] Reference now Figure 1 , which shows a block diagram of a part of a system according to an embodiment of the present invention. Figure 1 As shown in , system 100 may include various components including processor 110, which is shown as a multi-core processor. Processor 110 may be coupled to power supply 150 via external voltage regulator 160, which may perform a first voltage conversion to provide a main regulated voltage to processor 110.

[0023] As can be seen, the processor 110 may include a plurality of cores 120 a -120 n In addition, each core can be integrated with an integrated voltage regulator (IVR) 125a -125 n Associated, the integrated voltage regulator 125 a -125 n Receive a master regulated voltage and generate an operating voltage to be provided to one or more agents of a processor associated with the IVR. Likewise, an IVR implementation may be provided to allow fine-grained control of the voltage and, thereby, the power and performance of each individual core. In this way, each core may operate at an independent voltage and frequency, which enables great flexibility and provides a wide range of opportunities for balancing power consumption with performance. In some embodiments, the use of multiple IVRs enables the grouping of components into separate power planes so that power is regulated by the IVR and supplied to only those components in the grouping. During power management, a given power plane of one IVR may be depowered or powered off, when the processor is placed in a certain low-power state, while another power plane of another IVR remains active, or fully powered.

[0024] Also refer to Figure 1 , there may be additional components within the processor, including an input / output interface 132, another interface 134, and an integrated memory controller 136. As can be seen, each of these components may be provided by another integrated voltage regulator 125 x In one embodiment, interface 132 may implement operation for an Intel® Quick Path Interconnect (QPI) interconnect, which provides a point-to-point (PtP) link in a cache coherence protocol that includes multiple layers, including a physical layer, a link layer, and a protocol layer. In turn, interface 134 may communicate via a Peripheral Component Interconnect Express (PCIe™) protocol.

[0025] Also shown is a power control unit (PCU) 138, which may include hardware, software, and / or firmware that performs power management operations with respect to the processor 110. As seen, the PCU 138 provides control information to the external voltage regulator 160 via a digital interface to cause the voltage regulator to generate an appropriate regulated voltage. The PCU 138 also provides control information to the IVR 125 via another digital interface to control the generated operating voltage (or cause the corresponding IVR to be disabled in a low power mode). In various embodiments, the PCU 138 may include a variety of power management logic units to perform hardware-based power management. Such power management may be fully processor controlled (e.g., through various processor hardware, and it may be triggered by workload and / or power, thermal or other processor constraints) and / or power management may be performed in response to an external source (such as a platform or management power management source or system software).

[0026] Although not shown for ease of illustration, it is understood that additional components may be present within processor 110, such as uncore logic and other components such as internal memory (e.g., one or more levels of a cache memory hierarchy, etc.). Figure 1 The implementation of FIG. 5 is shown with an integrated voltage regulator, but the embodiments are not so limited.

[0027] Note that the power management techniques described herein can be independent of and supplement the power management (OSPM) mechanism based on the operating system (OS). According to an example OSPM technique, the processor can operate in various performance states or levels (so-called P states, i.e., from P0 to PN). Typically, the P1 performance state can correspond to the highest guaranteed performance state that can be requested by the OS. In addition to the P1 state, the OS can also request a higher performance state, i.e., the P0 state. The P0 state can be an opportunity or turbo mode state, in which the processor hardware can configure the processor or at least part of it to operate at a frequency higher than the guaranteed frequency when the power and / or thermal budget is available. In many implementations, the processor can include a plurality of so-called bin frequencies higher than the P1 guaranteed maximum frequency, and the bin frequency exceeds the maximum peak frequency of a specific processor such as being fused or otherwise written into the processor during manufacturing. In addition, according to an OSPM mechanism, the processor can operate in various power states or levels. With respect to power states, the OSPM mechanism can specify different power consumption states, commonly referred to as C states, C0, C1 to Cn states. When a core is active, it runs in the C0 state, and when a core is idle, it can be placed into a core low power state, also referred to as a core non-zero C-state (e.g., C1-C6 states), where each C-state is at a lower power consumption level (such that C6 is a deeper low power state than C1, and so on).

[0028] It is to be understood that many different types of power management techniques may be used individually or in combination in different embodiments. As a representative example, a power controller may control a processor to perform power management through some form of dynamic voltage frequency scaling (DVFS), wherein the operating voltage and / or operating frequency of one or more cores or other processor logic may be dynamically controlled to reduce power consumption in certain situations. In an example, DVFS may be performed using Enhanced Intel SpeedStep™ technology available from Intel Corporation of Santa Clara, California to provide optimal performance at the lowest power consumption level. In another example, DVFS may be performed using Intel TurboBoost™ technology to enable one or more cores or other computing engines to operate at a higher frequency than the guaranteed operating frequency based on conditions (e.g., workload and availability).

[0029] Another power management technique that may be used in certain examples is the dynamic swapping of workloads between different computing engines. For example, a processor may include asymmetric cores or other processing engines that operate at different power consumption levels so that in a power-constrained situation, one or more workloads may be dynamically switched to execute on a lower power core or other computing engine. Another exemplary power management technique is hardware duty cycling (HDC), which may cause cores and / or other computing engines to be periodically enabled and disabled according to a duty cycle so that one or more cores may be made inactive during an inactive period of the duty cycle and made active during an active period of the duty cycle. Although described using these specific examples, it is to be understood that many other power management techniques may be used in particular embodiments.

[0030] Embodiments may be implemented in processors targeting a variety of markets including server processors, desktop processors, mobile processors, etc. Referring now to Figure 2 , shows a block diagram of a processor according to an embodiment of the present invention. Figure 2 As shown in FIG. 1 , the processor 200 may include a plurality of cores 210 a -210 n In one embodiment, each such core may have an independent power domain and may be configured to enter and leave an active state and / or a maximum performance state based on workload. The various cores may be coupled to a system agent or uncore 220 comprising various components via interconnect 215. As seen, the uncore 220 may include a shared cache 230, which may be a last level cache. In addition, the uncore may include an integrated memory controller 240 to communicate with system memory (in the example of FIG. 1 ) via a memory bus, for example. Figure 2 The uncore 220 also includes various interfaces 250 and a power control unit 255, which may include logic for performing the power management techniques described herein.

[0031] In addition, through interfaces 250a-250n, connections can be made to various off-chip components (such as peripheral devices, mass storage, etc.). Figure 2 The embodiments of the present invention are shown with this particular implementation, but the scope of the present invention is not limited in this regard.

[0032] Reference now Figure 3 , shows a block diagram of a multi-domain processor according to another embodiment of the present invention. Figure 3 As shown in the embodiment of FIG. 3 , the processor 300 includes multiple domains. Specifically, the core domain 310 may include multiple cores 3100-310 n, graphics domain 320 may include one or more graphics engines, and there may also be a system agent domain 350. In some embodiments, system agent domain 350 may be executed at a frequency independent of the core domain, and may always remain powered on to handle power control events and power management so that domains 310 and 320 can be controlled to dynamically enter and leave high power and low power states. Each of domains 310 and 320 may operate at different voltages and / or powers. Note that although only three domains are shown, it is to be understood that the scope of the present invention is not limited in this regard, and additional domains may be present in other embodiments. For example, there may be multiple core domains, each of which includes at least one core.

[0033] Typically, each core 310 may include a low-level cache in addition to various execution units and additional processing elements. In turn, the various cores may be coupled to each other and to a last-level cache (LLC) 3400-340 n In various embodiments, LLC 340 may be shared between the cores and the graphics engine and various media processing circuits. As can be seen, ring interconnect 330 thus couples the cores together and provides interconnection between the cores, graphics domain 320, and system agent circuitry 350. In one embodiment, interconnect 330 may be part of the core domain. However, in other embodiments, the ring interconnect may have its own domain.

[0034] As further seen, the system agent domain 350 may include a display controller 352 that may provide control of and an interface to an associated display. As further seen, the system agent domain 350 may include a power control unit 355 that may include logic to perform the power management techniques described herein.

[0035] like Figure 3 As further seen in FIG. 3 , processor 300 may also include an integrated memory controller (IMC) 370 that may provide an interface to system memory, such as dynamic random access memory (DRAM). n There may be present to enable interconnection between processors and other circuits. For example, in one embodiment, at least one Direct Media Interface (DMI) interface and one or more PCIe™ interfaces may be provided. Still further, to provide communication between other agents such as additional processors or other circuits, one or more QPI interfaces may also be provided. Although in Figure 3 The embodiments are shown at this high level, but it is understood that the scope of the present invention is not limited in this regard.

[0036] refer to Figure 4, illustrates an embodiment of a processor including multiple cores. Processor 400 includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system on a chip (SoC), or other device that executes code. In one embodiment, processor 400 includes at least two cores, cores 401 and 402, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor 400 may include any number of processing elements that may be symmetric or asymmetric.

[0037] In one embodiment, a processing element refers to hardware or logic that supports a software thread. Examples of hardware processing elements include: thread units, thread slots, threads, processing units, contexts, context units, logical processors, hardware threads, cores, and / or any other element that can maintain a state for a processor, such as an execution state or an architecture state. In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with a code, such as a software thread, an operating system, an application, or other code. A physical processor typically refers to an integrated circuit that potentially includes any number of other processing elements, such as cores or hardware threads.

[0038] A core often refers to logic located on an integrated circuit that is capable of maintaining an independent architectural state, where each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to a core, a hardware thread typically refers to any logic located on an integrated circuit that is capable of maintaining an independent architectural state, where the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and other resources are dedicated to an architectural state, the boundaries between the nomenclature of a hardware thread and a core overlap. Again often, a core and a hardware thread are viewed by an operating system as separate logical processors, where the operating system can schedule operations on each logical processor separately.

[0039] As in Figure 4 As illustrated in , physical processor 400 includes two cores, cores 401 and 402. Here, cores 401 and 402 are considered symmetric cores, i.e., cores with the same configuration, functional units, and / or logic. In another embodiment, core 401 includes an out-of-order processor core, and core 402 includes an in-order processor core. However, cores 401 and 402 can be individually selected from any type of core, such as a native core, a software-managed core, a core adapted to execute a native instruction set architecture (ISA), a core adapted to execute a translated ISA, a co-designed core, or other known cores. As further discussed, the functional units illustrated in core 401 are described in further detail below, because the units in core 402 operate in a similar manner.

[0040] As depicted, core 401 includes two hardware threads 401a and 401b, which may also be referred to as hardware thread slots 401a and 401b. Therefore, in one embodiment, a software entity such as an operating system potentially views processor 400 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads simultaneously. As mentioned above, a first thread is associated with architecture state register 401a, a second thread is associated with architecture state register 401b, a third thread may be associated with architecture state register 402a, and a fourth thread may be associated with architecture state register 402b. Here, each of the architecture state registers (401a, 401b, 402a, and 402b) may be referred to as a processing element, a thread slot, or a thread unit, as described above. As illustrated, architecture state register 401a is replicated in architecture state register 401b, so separate architecture states / contexts can be stored for logical processor 401a and logical processor 401b. In core 401, other smaller resources such as instruction pointers and renaming logic in allocator and renamer block 430 may also be replicated for threads 401a and 401b. Some resources such as reorder buffers, ILTB 420, load / store buffers, and queues in reorder / retirement unit 435 may be shared through partitioning. Other resources such as general internal registers, page table base register(s), low-level data cache and data TLB 415, execution unit(s) 440, and portions of out-of-order unit 435 are potentially fully shared.

[0041] Processor 400 often includes other resources that may be fully shared, shared by partitioning, or dedicated by / to processing elements. Figure 4 , an embodiment of a purely exemplary processor with illustrative logic units / resources of the processor is illustrated. Note that the processor may include or omit any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core 401 includes a simplified representative out-of-order (OOO) processor core. However, in-order processors may be utilized in different embodiments. The OOO core includes a branch target buffer 420 that predicts branches to be executed / taken and an instruction translation buffer (I-TLB) 420 that stores address translation entries for instructions.

[0042] The core 401 also includes a decoding module 425 coupled to the fetch unit 420 to decode the fetched elements. In one embodiment, the fetch logic includes a separate sequencer associated with the thread slots 401a, 401b, respectively. The core 401 is often associated with a first ISA, which defines / specifies instructions executable on the processor 400. Machine code instructions that are part of the first ISA often include a portion of the instruction (called an opcode) that references / specifies the instruction or operation to be performed. The decoding logic 425 includes a circuit that identifies these instructions from their opcodes and passes the decoded instructions to the pipeline for processing as defined by the first ISA. For example, in one embodiment, the decoder 425 includes a specific instruction designed or adapted to identify such as a transaction instruction. As a result of the identification by the decoder 425, the architecture or core 401 takes a specific, predefined action to perform a task associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein can be executed in response to a single or multiple instructions; some of which can be new or old instructions.

[0043] In one example, the allocator and renamer block 430 includes an allocator that reserves resources such as a register file that stores instruction processing results. However, threads 401a and 401b are potentially capable of out-of-order execution, where the allocator and renamer block 430 also reserves other resources, such as a reorder buffer that tracks instruction results. Unit 430 may also include a register renamer to rename program / instruction reference registers to other registers external to processor 400. Reorder / retirement unit 435 includes components such as the reorder buffers, load buffers, and store buffers mentioned above to support out-of-order execution and later in-order retirement of instructions executed out-of-order.

[0044] In one embodiment, the scheduler and (one or more) execution unit block 440 includes a scheduler unit that schedules instructions / operations on the execution units. For example, a floating point instruction is scheduled on a port of an execution unit with an available floating point execution unit. A register file associated with the execution unit is also included to store information instruction processing results. Exemplary execution units include floating point execution units, integer execution units, jump execution units, load execution units, store execution units, and other known execution units.

[0045] A lower level data cache and data translation buffer (D-TLB) 450 is coupled to the execution unit(s) 440. The data cache is to store recently used / operated elements (such as data operands), which are potentially saved in a memory consistency state. The D-TLB is to store recent virtual / linear to physical address translations. As a specific example, the processor may include a page table structure to partition physical memory into multiple virtual pages.

[0046] Here, cores 401 and 402 share access to a higher level or farther cache 410, which is to cache recently fetched elements. Note that higher level or farther refers to cache levels that are farther away or become farther away from (one or more) execution units. In one embodiment, higher level cache 410 is a last level data cache (the last cache in the memory hierarchy on processor 400), such as a second or third level data cache. However, higher level cache 410 is not so limited, as it can be associated with or include an instruction cache. Alternatively, a trace cache (a type of instruction cache) can be coupled after decoder 425 to store recently decoded traces.

[0047] In the depicted configuration, processor 400 also includes a bus interface module 425 and a power controller 460, which can perform power management according to embodiments of the present invention. In this scenario, bus interface 405 communicates with devices external to processor 400, such as system memory and other components.

[0048] The memory controller 470 may interface with other devices such as one or more memories. In an example, the bus interface 405 includes a ring interconnect with a memory controller for interfacing with the memory and a graphics controller for interfacing with the graphics processor. In a SoC environment, even more devices (such as a network interface, a coprocessor, a memory, a graphics processor, and any other known computer device / interface) may be integrated on a single die or integrated circuit to provide a small form factor with high functionality and low power consumption.

[0049] Reference now Figure 5 , shows a block diagram of a micro-architecture of a processor core according to an embodiment of the present invention. Figure 5 As shown in , the processor core 500 may be a multi-stage pipeline out-of-order processor. The core 500 may operate at various voltages based on a received operating voltage, which may be received from an integrated voltage regulator or an external voltage regulator.

[0050] like Figure 5As seen in FIG. 5 , the core 500 includes a front end unit 510 that can be used to fetch instructions to be executed and prepare them for later use in the processor pipeline. For example, the front end unit 510 can include a fetch unit 501, an instruction cache 503, and an instruction decoder 505. In some implementations, the front end unit 510 can also include a trace cache along with a microcode storage and a micro-operation storage. The fetch unit 501 can, for example, fetch macroinstructions from a memory or an instruction cache 503 and feed them to an instruction decoder 505 to decode them into primitives (i.e., micro-operations) for execution by the processor.

[0051] An out-of-order (OOO) engine 515 is coupled between the front end unit 510 and the execution unit 520, and the OOO engine 515 can be used to receive microinstructions and prepare them for execution. More specifically, the OOO engine 515 can include various buffers to reorder the microinstruction stream and allocate various resources required for execution and provide renaming of logical registers to storage locations in various register files (such as register files 530 and extended register files 535). The register file 530 may include separate register files for integer and floating-point operations. For the purpose of configuration, control and additional operations, a set of machine-specific registers (MSRs) 538 may also exist and be accessible to various logics within the core 500 (and outside the core). For example, power limit information can be stored in one or more MSRs and can be dynamically updated, as described herein.

[0052] Various resources may be present in execution unit 520, which may include, for example, various integer, floating point, and single instruction multiple data (SIMD) logic units, among other specialized hardware. For example, such an execution unit may include, among other such execution units, one or more arithmetic logic units (ALUs) 522 and one or more vector execution units 524.

[0053] The results from the execution units may be provided to retirement logic, namely a reorder buffer (ROB) 540. More specifically, ROB 540 may include various arrays and logic that receive information associated with instructions being executed. This information is then reviewed by ROB 540 to determine whether the instruction is validly retired and the result data is committed to the architectural state of the processor, or whether one or more exceptions have occurred that prevent the proper retirement of the instruction. Of course, ROB 540 may handle other operations associated with retirement.

[0054] like Figure 5As shown in FIG. 5 , ROB 540 is coupled to cache 550, which in one embodiment may be a low-level cache (e.g., an L1 cache), although the scope of the invention is not limited in this respect. Execution unit 520 may also be directly coupled to cache 550. Data communication from cache 550 may occur with higher-level caches, system memory, etc. Although in FIG. Figure 5 The embodiments of the present invention are shown at this high level, but it should be understood that the scope of the present invention is not limited in this regard. Figure 5 The implementations are with respect to out-of-order machines, such as those of the Intel® x86 instruction set architecture (ISA), but the scope of the invention is not limited in this regard. That is, other embodiments may be implemented in an in-order processor, a reduced instruction set computing (RISC) processor such as an ARM-based processor, or a processor of another type of ISA that can emulate instructions and operations of a different ISA via an emulation engine and associated logic circuits.

[0055] Reference now Figure 6 , shows a block diagram of a micro-architecture of a processor core according to another embodiment of the present invention. Figure 6 In the embodiment of the present invention, the core 600 may be a low-power core of a different micro-architecture, such as an Intel® Atom-based TM 610 is a processor having a relatively limited pipeline depth designed to reduce power consumption. As seen, core 600 includes an instruction cache 610 coupled to provide instructions to an instruction decoder 615. Branch predictor 605 may be coupled to instruction cache 610. Note that instruction cache 610 may also be coupled to another level of cache memory, such as an L2 cache (in Figure 6 Instruction decoder 615 then provides the decoded instruction to issue queue 620 for storage and delivery to a given execution pipeline. Microcode ROM 618 is coupled to instruction decoder 615.

[0056] The floating point pipeline 630 includes a floating point register file 632, which may include a plurality of architectural registers having given bits, such as 128, 256, or 512 bits. The pipeline 630 includes a floating point scheduler 634 that schedules instructions for execution on one of the plurality of execution units of the pipeline. In the illustrated embodiment, such execution units include an ALU 635, a shuffle unit 636, and a floating point adder 638. The results generated in these execution units may then be provided back to the buffer and / or registers of the register file 632. It is of course to be understood that, although illustrated with these few example execution units, additional or different floating point execution units may be present in another embodiment.

[0057] An integer pipeline 640 may also be provided. In the embodiment shown, the pipeline 640 includes an integer register file 642, which may include a plurality of architectural registers having a given bit, such as 128 or 256 bits. The pipeline 640 includes an integer scheduler 644 that schedules instructions for execution on one of a plurality of execution units of the pipeline. In the embodiment shown, such execution units include an ALU 645, a scramble unit 646, and a jump execution unit 648. In turn, the results generated in these execution units may be provided back to the buffers and / or registers of the register file 642. It is of course to be understood that, although shown with these few example execution units, additional or different integer execution units may be present in another embodiment.

[0058] A memory execution scheduler 650 may schedule memory operations for execution in an address generation unit 652, which is also coupled to a TLB 654. As seen, these structures may be coupled to a data cache 660, which may be an L0 and / or L1 data cache, which in turn may be coupled to additional levels of the cache memory hierarchy, including an L2 cache memory.

[0059] To provide support for out-of-order execution, an allocator / renamer 670 may be provided in addition to a reorder buffer 680, which may be configured to reorder instructions executed out-of-order for in-order retirement. Figure 6 is shown in the diagram of FIG. 1 with this particular pipeline architecture, but it will be understood that many variations and alternatives are possible.

[0060] Note that in a processor with an asymmetric core, such as according to Figure 5 and 6 In a microarchitecture, workloads can be dynamically swapped between cores for power management reasons, since these cores may have the same or related ISAs despite having different pipeline designs and depths. Such dynamic core swapping can be performed in a way that is transparent to user applications (and possibly also to the kernel).

[0061] refer to Figure 7 , shows a block diagram of a micro-architecture of a processor core according to yet another embodiment. Figure 7As illustrated in , the core 700 may include a multi-stage in-order pipeline that executes at a very low power consumption level. As one such example, the processor 700 may have a micro-architecture according to the ARM Cortex A53 that can be obtained from ARM Holdings, Inc. of Sunnyvale, California. In an implementation, an 8-stage pipeline configured to execute both 32-bit and 64-bit codes may be provided. The core 700 includes a fetch unit 710, which is configured to fetch instructions and provide them to a decode unit 715, which may decode instructions (e.g., macroinstructions of a given ISA such as an ARMv8 ISA). It is also noted that a queue 730 may be coupled to the decode unit 715 to store decoded instructions. The decoded instructions are provided to an issue logic 725, where the decoded instructions may be issued to a given one of a plurality of execution units.

[0062] Further references Figure 7 , issue logic 725 may issue instructions to one of a plurality of execution units. In the illustrated embodiment, these execution units include integer unit 735, multiplication unit 740, floating point / vector unit 750, dual issue unit 760, and load / store unit 770. The results of these different execution units may be provided to write-back unit 780. It is to be understood that while a single write-back unit is shown for ease of illustration, in some implementations a different write-back unit may be associated with each execution unit. Furthermore, it is to be understood that while in Figure 7 Each unit and logic shown in FIG. 1 is represented at a high level, but a specific implementation may include more or different structures. Figure 7 A processor designed with one or more cores in a pipeline can be implemented in many different end products ranging from mobile devices to server systems.

[0063] refer to Figure 8 , shows a block diagram of a micro-architecture of a processor core according to yet another embodiment. Figure 8 As illustrated in FIG. 8 , core 800 may include a multi-stage, multi-issue, out-of-order pipeline that executes at very high performance levels (which may be faster than Figure 7700 higher power consumption levels occur). As one such example, processor 800 may have a microarchitecture designed according to the ARM CortexA57. In an implementation, a 15 (or more) stage pipeline configured to execute both 32-bit and 64-bit code may be provided. In addition, the pipeline may provide 3 (or more) wide and 3 (or more) issue operations. Core 800 includes a fetch unit 810, which is configured to fetch instructions and provide them to a decoder / renamer / dispatcher 815, which may decode instructions (e.g., macroinstructions of the ARMv8 instruction set architecture), rename register references within the instructions, and (ultimately) dispatch the instructions to the selected execution unit. The decoded instructions may be stored in a queue 825. Note that although in Figure 8 A single queue structure is shown in for ease of illustration, but it is to be understood that a separate queue may be provided for each of a plurality of different types of execution units.

[0064] exist Figure 8 Also shown in FIG. 8 is issue logic 830 from which decoded instructions stored in queue 825 may be issued to a selected execution unit. Issue logic 830 may also be implemented in certain embodiments with separate issue logic for each of a plurality of different types of execution units to which issue logic 830 is coupled.

[0065] The decoded instructions may be issued to a given one of a plurality of execution units. In the illustrated embodiment, these execution units include one or more integer units 835, multiplication units 840, floating point / vector units 850, branch units 860, and load / store units 870. In an embodiment, the floating point / vector unit 850 may be configured to process 128 or 256 bits of SIMD or vector data. Still further, the floating point / vector execution unit 850 may perform IEEE-754 double precision floating point operations. The results of these different execution units may be provided to a write back unit 880. Note that in some implementations, a different write back unit may be associated with each of the execution units. Furthermore, it is to be understood that although in Figure 8 Each unit and logic shown in the diagram is represented at a high level, but a particular implementation may include more or different structures.

[0066] Note that in a processor with an asymmetric core, such as according to Figure 7 and 8 With a microarchitecture, workloads can be swapped dynamically for power management reasons, since the cores can have the same or related ISA despite having different pipeline designs and depths. Such dynamic core swapping can be performed in a way that is transparent to user applications (and possibly also to the kernel).

[0067] Use with Figure 5-8 The processor of one or more core designs of one or more pipelines in one or more of the pipelines can be implemented in many different end products ranging from mobile devices to server systems. Fig. 9 , shows a block diagram of a processor according to another embodiment of the present invention. Fig. 9 In an embodiment of the present invention, the processor 900 may be a SoC including multiple domains, each of which may be controlled to operate at an independent operating voltage and operating frequency. As a specific illustrative example, the processor 900 may be based on the Intel® Architecture Core i7 processor. TM , such as an i3, i5, i7, or another such processor available from Intel Corporation. However, other low-power processors such as an ARM-based design from ARM Holdings, Inc. or its licensees, or a MIPS-based design from MIPS Technologies, Inc. of Sunnyvale, California, or its licensees or adopters, may instead be present in other embodiments, such as an Apple A7 processor, a Qualcomm Snapdragon processor, or a Texas Instruments OMAP processor. Such a SoC may be used in low-power systems such as smartphones, tablet computers, phablet computers, Ultrabooks, and the like. TM Computer or other portable computing device.

[0068] exist Fig. 9 In the high-level view shown in FIG. 9 , the processor 900 includes a plurality of core units 9100-910 n . Each core unit may include one or more processor cores, one or more cache memories, and other circuits. Each core unit 910 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set; the ARM instruction set (with optional additional extensions such as NEON)) or other instruction sets or combinations thereof. Note that some of the core units may be heterogeneous resources (e.g., of different designs). In addition, each such core may be coupled to a cache memory (not shown), which in an embodiment may be a shared level (L2) cache memory. The non-volatile memory 930 may be used to store various programs and other data. For example, the memory may be used to store at least part of microcode, boot information (such as BIOS), other system software, and the like.

[0069] Each core unit 910 may also include an interface such as a bus interface that enables interconnection to additional circuits of the processor. In an embodiment, each core unit 910 is coupled to a coherence structure, which may serve as a primary cache coherence on-die interconnect, which in turn is coupled to a memory controller 930. In turn, the memory controller 935 controls the connection to a memory such as DRAM (in Fig. 9 For ease of illustration (not shown).

[0070] In addition to the core units, there are additional processing engines within the processor, including at least one graphics unit 920, which may include one or more graphics processing units (GPUs) that perform graphics processing and possibly general-purpose operations on a graphics processor (so-called GPGPU operations). In addition, there may be at least one image signal processor 925. The signal processor 925 may be configured to process incoming image data received from one or more capture devices (internal to the SoC or external to the chip).

[0071] Other accelerators may also be present. Fig. 9 In the illustration of , the video encoder 950 can perform encoding operations, including encoding and decoding for video information, such as providing hardware acceleration support for high-definition video content. A display controller 955 can also be provided to accelerate display operations, including providing support for internal and external displays of the system. In addition, a security processor 945 can exist to perform security operations, such as secure boot operations, various cryptographic operations, etc.

[0072] Each unit may have its power consumption controlled via a power manager 940, which may include control logic that performs the various power management techniques described herein.

[0073] In some embodiments, SoC 900 may also include a non-coherent structure that is coupled to a coherent structure to which various peripheral devices may be coupled. One or more interfaces 960a-960d enable communication with one or more off-chip devices. Such communication may be via a variety of communication protocols, such as PCIe, among other types of communication protocols. TM ,GPIO,USB,I 2 C, UART, MIPI, SDIO, DDR, SPI, HDMI. Fig. 9 The embodiments are shown at this high level, but it is understood that the scope of the present invention is not limited in this regard.

[0074] Reference now Fig.10, a block diagram of a representative SoC is shown. In the illustrated embodiment, SoC 1000 may be a multi-core SoC configured for low-power operation to be optimized for incorporation into a smartphone or other low-power device, such as a tablet or other portable computing device. As an example, SoC 1000 may be implemented using asymmetric or different types of cores, such as a combination of higher power and / or low power cores (e.g., out-of-order cores and in-order cores). In various embodiments, these cores may be based on the Inte® Architecture. TM Core design or ARM architecture design. In yet other embodiments, a mix of Intel and ARM cores can be implemented in a given SoC.

[0075] like Fig.10 As seen in FIG. 1 , SoC 1000 includes a first core domain 1010 having a plurality of first cores 10120-10123. In an embodiment, these cores may be low power cores, such as in-order cores. In an embodiment, these first cores may be implemented as ARM Cortex A53 cores. In turn, these cores are coupled to a cache memory 1015 of the core domain 1010. In addition, SoC 1000 includes a second core domain 1020. In FIG. Fig.10 In the illustration of , the second core domain 1020 has a plurality of second cores 10220-10223. In an example, these cores may be higher power consuming cores compared to the first core 1012. In an embodiment, the second cores may be out-of-order cores, which may be implemented as ARM Cortex A57 cores. In turn, these cores are coupled to the cache memory 1025 of the core domain 1020. Note that although in Fig.10 The example shown in includes 4 cores in each domain, but it is understood that in other embodiments there may be more or fewer cores in a given domain.

[0076] Further references Fig.10 , a graphics domain 1030 is also provided, which may include one or more graphics processing units (GPUs) configured to independently execute, for example, graphics workloads provided by one or more cores of core domains 1010 and 1020. As an example, in addition to providing graphics and display rendering operations, GPU domain 1030 may also be used to provide display support for a variety of screen sizes.

[0077] As seen, the various domains are coupled to a coherent interconnect 1040, which in an embodiment may be a cache coherent interconnect structure, which in turn is coupled to an integrated memory controller 1050. In some examples, coherent interconnect 1040 may include a shared cache memory, such as an L3 cache. In an embodiment, memory controller 1050 may be a processor that provides multiple channels of communication with off-chip memory, such as (in Fig.10 A direct memory controller for multiple channels of DRAM (not shown for ease of illustration).

[0078] In different examples, the number of core domains may vary. For example, for a low-power SoC suitable for incorporation into a mobile computing device, there may be a core domain such as Fig.10 . Still further, in such a low-power SoC, a core domain 1020 including higher power cores may have a smaller number of such cores. For example, in one implementation, two cores 1022 may be provided to enable operation at a reduced power consumption level. In addition, different core domains may also be coupled to an interrupt controller to enable dynamic exchange of workloads between different domains.

[0079] In yet other embodiments, there may be a larger number of core domains and additional optional IP logic, as the SoC may be scaled to higher performance (and power) levels for incorporation into other computing devices, such as desktops, servers, high performance computing systems, base stations, and the like. As one such example, four core domains, each with a given number of out-of-order cores, may be provided. Still further, in addition to optional GPU support (which may take the form of a GPGPU as an example), one or more accelerators may be provided for providing optimized hardware support for specific functions (e.g., web (network) services, network processing, switching, and the like). In addition, there may be an input / output interface to couple such an accelerator to off-chip components.

[0080] Reference now Fig.11 , a block diagram of another example SoC is shown. Fig.11 In an embodiment of the present invention, SoC 1100 may include various circuits that enable high performance for multimedia applications, communications, and other functions. Likewise, SoC 1100 is suitable for incorporation into a variety of portable and other devices, such as smart phones, tablet computers, smart TVs, and the like. In the example shown, SoC 1100 includes a central processor unit (CPU) domain 1110. In an embodiment, multiple separate processor cores may exist in CPU domain 1110. As an example, CPU domain 1110 may be a quad-core processor with 4 multi-threaded cores. Such processors may be homogeneous or heterogeneous processors, for example, a mixture of low-power and high-power processor cores.

[0081] In turn, GPU domain 1120 is provided to perform advanced graphics processing in one or more GPUs to handle graphics and compute APIs. DSP unit 1130 may provide one or more low-power DSPs for processing low-power multimedia applications such as music playback, audio / video, etc. in addition to advanced computations that may occur during execution of multimedia instructions. In turn, communication unit 1140 may include various components that provide connectivity via various wireless protocols, such as cellular communications (including 3G / 4G LTE), wireless local area protocols (such as Bluetooth™, IEEE 802.11), etc.

[0082] Still further, the multimedia processor 1150 may be used to perform capture and playback of high-definition video and audio content, including processing of user gestures. The sensor unit 1160 may include multiple sensors and / or sensor controllers to interface to various off-chip sensors present in a given platform. The image signal processor 1170 may be provided with one or more separate ISPs to perform image processing on content captured from one or more cameras (including still and video cameras) of the platform.

[0083] The display processor 1180 may provide support for connection to a high-definition display of a given pixel density, including the ability to wirelessly transmit content for playback on such a display. Still further, the location unit 1190 may include a GPS receiver with support for multiple GPS constellations to provide applications with highly accurate positioning information obtained using such a GPS receiver. It is to be understood that although in Fig.11 The examples are shown with this particular set of components, but many variations and alternatives are possible.

[0084] Reference now Fig.12 , a block diagram of an example system with which embodiments may be used is shown. As seen, system 1200 may be a smart phone or other wireless communicator. Baseband processor 1205 is configured to perform various signal processing with respect to communication signals to be transmitted from or received by the system. In turn, baseband processor 1205 is coupled to application processor 1210, which may be the main CPU of the system that executes an OS and other system software in addition to user applications such as many well-known social media and multimedia applications. Application processor 1210 may also be configured to perform various other computing operations for the device.

[0085] In turn, the application processor 1210 may be coupled to a user interface / display 1220, such as a touch screen display. In addition, the application processor 1210 may be coupled to a memory system including non-volatile memory (i.e., flash memory 1230) and system memory (i.e., dynamic random access memory (DRAM) 1235). As further seen, the application processor 1210 is also coupled to a capture device 1240, such as one or more image capture devices that can record video and / or still images.

[0086] Also refer to Fig.12 A universal integrated circuit card (UICC) 1240, including a subscriber identity module and possibly secure storage and a cryptographic processor, is also coupled to the application processor 1210. The system 1200 may also include a security processor 1250, which may be coupled to the application processor 1210. A plurality of sensors 1225 may be coupled to the application processor 1210 to enable input of various sensed information, such as accelerometers and other environmental information. An audio output device 1295 may provide an interface to output sound, such as in the form of voice communications, playing or streaming audio data, etc.

[0087] As further illustrated, a near field communication (NFC) contactless interface 1260 is provided that communicates in the NFC near field via an NFC antenna 1265. Fig.12 Separate antennas are shown in FIG, but it is understood that in some implementations, one antenna or a different set of antennas may be provided to enable various wireless functions.

[0088] A power management integrated circuit (PMIC) 1215 is coupled to the application processor 1210 to perform platform-level power management. To this end, the PMIC 1215 can issue power management requests to the application processor 1210 to enter certain low-power states, as desired. In addition, based on platform constraints, the PMIC 1215 can also control the power levels of other components of the system 1200.

[0089] To enable communications to be transmitted and received, various circuits may be coupled between the baseband processor 1205 and the antenna 1290. Specifically, there may be a radio frequency (RF) transceiver 1270 and a wireless local area network (WLAN) transceiver 1275. Typically, the RF transceiver 1270 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as a 3G or 4G wireless communication protocol (such as according to code division multiple access (CDMA), global system for mobile communications (GSM), long term evolution (LTE) or other protocols). In addition, there may be a GPS sensor 1280. Other wireless communications such as the reception or transmission of radio signals (e.g., AM / FM and other signals) may also be provided. In addition, local wireless communications may also be implemented via the WLAN transceiver 1275.

[0090] Reference now Fig.13 , shows a block diagram of another example system with which embodiments may be used. Fig.13 In the illustration of , system 1300 may be a mobile low-power system such as a tablet computer, a 2:1 tablet computer, a tablet phone, or other convertible or standalone tablet system. As illustrated, SoC 1310 is present and may be configured to operate as an application processor for the device.

[0091] Various devices may be coupled to the SoC 1310. In the illustrated illustration, the memory subsystem includes a flash memory 1340 and a DRAM 1345 coupled to the SoC 1310. In addition, a touch panel 1320 is coupled to the SoC 1310 to provide display capabilities and user input via touch, including provisioning a virtual keyboard on the display of the touch panel 1320. To provide wired network connectivity, the SoC 1310 is coupled to an Ethernet interface 1330. A peripheral hub 1325 is coupled to the SoC 1310 to enable interfacing with various peripheral devices, such as may be coupled to the system 1300 through any of a variety of ports or other connectors.

[0092] In addition to the internal power management circuits and functions within the SoC 1310, the PMIC 1380 is coupled to the SoC 1310 to provide platform-based power management, for example, based on whether the system is powered by a battery 1390 or by AC power via an AC adapter 1395. In addition to this power source-based power management, the PMIC 1380 can also perform platform power management activities based on environmental and usage conditions. Still further, the PMIC 1380 can transmit control and status information to the SoC 1310 to cause various power management actions within the SoC 1310.

[0093] Also refer to Fig.13To provide wireless capabilities, the WLAN unit 1350 is coupled to the SoC 1310 and in turn to the antenna 1355. In various implementations, the WLAN unit 1350 may provide communications according to one or more wireless protocols.

[0094] As further illustrated, a plurality of sensors 1360 may be coupled to the SoC 1310. These sensors may include various accelerometers, environmental and other sensors, including user gesture sensors. Finally, an audio codec 1365 is coupled to the SoC 1310 to provide an interface to an audio output device 1370. Of course, it is to be understood that although in Fig.13 Although shown in this particular implementation, many variations and alternatives are possible.

[0095] Reference now Fig.14 , a block diagram of a representative computer system, such as a notebook, Ultrabook™, or other small form factor system, is shown. In one embodiment, processor 1410 includes a microprocessor, a multi-core processor, a multi-threaded processor, an ultra-low voltage processor, an embedded processor, or other known processing element. In the illustrated implementation, processor 1410 acts as a main processing unit and central hub for communicating with many of the various components of system 1400. As an example, processor 1400 is implemented as a SoC.

[0096] In one embodiment, processor 1410 is in communication with system memory 1415. As an illustrative example, system memory 1415 is implemented via multiple memory devices or modules to provide a certain amount of system memory.

[0097] To provide persistent storage of information such as data, applications, one or more operating systems, and the like, mass storage 1420 may also be coupled to processor 1410. In various embodiments, to enable thinner and lighter system designs and to improve system responsiveness, this mass storage may be implemented via an SSD, or the mass storage may be implemented primarily using a hard disk drive (HDD) with a smaller amount of SSD storage acting as an SSD cache to enable non-volatile storage of context state and other such information during a power-off event so that a fast power-up may occur upon reinitialization of system activity. Fig.14 Also shown in FIG. 14 , a flash device 1422 may be coupled to the processor 1410, for example, via a serial peripheral interface (SPI). The flash device may provide non-volatile storage for system software, including basic input / output software (BIOS) and other firmware for the system.

[0098] Various input / output (I / O) devices may be present in system 1400. Specifically, Fig.14 In the embodiment shown in FIG. 1 , a display 1424 is shown, which may be a high definition LCD or LED panel, which may further provide a touch screen 1425. In one embodiment, the display 1424 may be coupled to the processor 1410 via a display interconnect, which may be implemented as a high performance graphics interconnect. The touch screen 1425 may be coupled to the processor 1410 via another interconnect, which may be an I 2 C interconnection. Fig.14 As further shown in FIG. 14 , in addition to the touch screen 1425, user input by way of touch may also occur via a touch pad 1430, which may be configured within the chassis and may also be coupled to the same I 2 C interconnection.

[0099] For sensory computing and other purposes, various sensors may be present within the system and may be coupled to the processor 1410 in different ways. Certain inertial and environmental sensors may be coupled to the processor 1410 through the sensor hub 1440 (e.g., via I 2 C interconnect) is coupled to processor 1410. Fig.14 In the embodiment shown in , these sensors may include an accelerometer 1441, an ambient light sensor (ALS) 1442, a compass 1443, and a gyroscope 1444. Other environmental sensors may include one or more thermal sensors 1446, which in some embodiments are coupled to processor 1410 via a system management bus (SMBus) bus.

[0100] exist Fig.14 1430. As also seen in FIG. 144 , various peripherals can be coupled to the processor 1410 via a low pin count (LPC) interconnect. In the embodiment shown, various components can be coupled through an embedded controller 1435. Such components can include a keyboard 1436 (e.g., coupled via a PS2 interface), a fan 1437, and a thermal sensor 1439. In some embodiments, a touchpad 1430 can also be coupled to the EC 1435 via a PS2 interface. In addition, a security processor such as a trusted platform module (TPM) 1438 can also be coupled to the processor 1410 via the LPC interconnect.

[0101] System 1400 can communicate with external devices in a variety of ways, including wirelessly. Fig.14In the embodiment shown in , there are various wireless modules, each of which can correspond to a radio configured for a specific wireless communication protocol. One way to wirelessly communicate in a short distance (such as a near field) can be via an NFC unit 1445, which in one embodiment can communicate with the processor 1410 via the SMBus. Note that via the NFC unit 1445, devices in close proximity to each other can communicate.

[0102] like Fig.14 As further seen in the figure, the additional wireless unit may include other short-range wireless engines, including a WLAN unit 1450 and a Bluetooth unit 1452. Using the WLAN unit 1450, Wi-Fi™ communication may be achieved, while via the Bluetooth unit 1452, short-range Bluetooth communication may occur. TM Communication. These units can communicate with the processor 1410 via a given link.

[0103] Furthermore, wireless wide area communications, such as according to a cellular or other wireless wide area protocol, may occur via a WWAN unit 1456, which in turn may be coupled to a subscriber identity module (SIM) 1457. Additionally, to enable the receipt and use of location information, a GPS module 1455 may also be present. Note that in Fig.14 In the embodiment shown in , WWAN unit 1456 and an integrated capture device (such as camera module 1454) can communicate via a given link.

[0104] An integrated camera module 1454 may be incorporated into the cover. To provide audio input and output, the audio processor may be implemented via a digital signal processor (DSP) 1460, which may be coupled to the processor 1410 via a high-definition audio (HDA) link. Similarly, the DSP 1460 may communicate with an integrated encoder / decoder (CODEC) and amplifier 1462, which in turn may be coupled to an output speaker 1463, which may be implemented within the chassis. Similarly, the amplifier and codec 1462 may be coupled to receive audio input from a microphone 1465, which in an embodiment may be implemented via a dual array microphone (such as a digital microphone array) to provide high quality audio input to enable voice activated control of various operations within the system. Note also that audio output may be provided from the amplifier / codec 1462 to a headphone jack 1464. Although in Fig.14 Although shown with these specific components in the embodiments described above, it is to be understood that the scope of the present invention is not limited in this regard.

[0105] Embodiments may be implemented in many different system types. Fig.15 , shows a block diagram of a system according to an embodiment of the present invention. Fig.15 As shown in FIG. 1 , the multiprocessor system 1500 is a point-to-point interconnect system and includes a first processor 1570 and a second processor 1580 coupled via a point-to-point interconnect 1550. Fig.15 As shown in , each of processors 1570 and 1580 can be a multi-core processor that includes first and second processor cores (i.e., processor cores 1574a and 1574b and processor cores 1584a and 1584b), although there can potentially be more cores in the processor. Each processor can include a PCU or other power management logic to perform processor-based power management as described herein.

[0106] Also refer to Fig.15 , the first processor 1570 also includes a memory controller hub (MCH) 1572 and point-to-point (PP) interfaces 1576 and 1578. Similarly, the second processor 1580 includes an MCH 1582 and PP interfaces 1586 and 1588. Fig.15 As shown in FIG. 1 , MCHs 1572 and 1582 couple the processors to respective memories, namely memory 1532 and memory 1534, which may be portions of system memory (e.g., DRAM) locally attached to the respective processors. First processor 1570 and second processor 1580 may be coupled to chipset 1590 via PP interconnects 1562 and 1564, respectively. Fig.15 As shown in , chipset 1590 includes PP interfaces 1594 and 1598 .

[0107] In addition, the chipset 1590 includes an interface 1592 that couples the chipset 1590 with the high performance graphics engine 1538 via the PP interconnect 1539. In turn, the chipset 1590 may be coupled to the first bus 1516 via an interface 1596. Fig.15 As shown in FIG. 1 , various input / output (I / O) devices 1514 may be coupled to first bus 1516 along with a bus bridge 1518 that couples first bus 1516 to a second bus 1520. In one embodiment, various devices may be coupled to second bus 1520 including, for example, a keyboard / mouse 1522, communication devices 1526, and a data storage unit 1528 (such as a disk drive or other mass storage device) which may include code 1530. Additionally, an audio I / O 1524 may be coupled to second bus 1520. Embodiments may be incorporated into other types of systems including mobile devices such as smart cell phones, tablet computers, notebooks, Ultrabook™, and the like.

[0108] Multi-chip processor (MCP) packages and other multi-device components (such as dual in-line memory modules (DIMMs)) have the ability to deliver temperature information for each device (e.g., each die or chip) packaged on a common substrate. However, platform thermal management typically does not require high granularity (e.g., density) of sensor data that is available from all temperature sensors. Instead, platform server management firmware (SMFW) can act based on different components within a cooling zone to deliver cooling on demand. One technique to provide the appropriate level of cooling can be based on the minimum thermal margin of all components within a cooling zone.

[0109] To simplify SMFW implementations with MCPs, a mechanism can normalize and aggregate the data received from temperature sensors. For example, SMFW can act on a minimum margin for sensors in an MCP (e.g., a minimum difference in the difference between a determined trigger value associated with a thermal control technique (such as cooling or throttling) and each measured die temperature).

[0110] In an embodiment, the MCP includes a processor die and a platform controller hub (PCH) die. In another embodiment, the MCP includes a processor die, one or more dynamic random access memory (DRAM) dies, and a network interface controller (NIC) die. In another embodiment, the MCP includes a processor die and a NIC die. In other embodiments, the MCP may include other combinations of two or more dies.

[0111] In order to reduce SMFW complexity while ensuring efficiency of operation, the MCP may benefit from a mechanism for reporting a minimum temperature margin to each of one or more preset thresholds (e.g., the difference between the measured temperature and the preset threshold). In an embodiment, the margins provided to the SMFW may include a minimum margin to the temperature control parameters of all die within the MCP (control temperature margin) and a minimum margin to the throttling parameters of all die within the MCP. The minimum margin to the temperature control margin may be used to determine whether to provide cooling to the MCP, while the minimum margin to the throttling margin may be used to anticipate throttling activity in the MCP. In addition, the highest temperature from all die within the MCP may be reported.

[0112] The margin to the temperature control parameters of the die within the MCP (ΔT control ) can be calculated by comparing the measured temperature of the die with the control temperature T controlThe coolant may be a gas (e.g., air) that is circulated by one or more fans, or a liquid coolant that is circulated by, for example, a pump device, or another type of coolant circulation mechanism.

[0113] To the margin of throttling parameters (ΔT throttle ) can be calculated by comparing the measured temperature of one of the dies in the MCP with the throttling temperature T throttle The difference between the preset temperatures at which the die is throttled (e.g., the activity level is reduced) is calculated. The throttling (e.g., reduction) of activity within the die may be implemented by reducing the clock frequency of logic within the die, reducing the operating voltage of the logic, reducing the instruction throughput of the execution logic, reducing the duty cycle of one or more logic within the die, etc., or any combination of the above-mentioned throttling techniques or other throttling techniques.

[0114] Fig.16 1 is a block diagram of a multi-chip package 1600 according to an embodiment of the present invention. The MCP 1600 may include a plurality of dies 16100-1610 N , which includes a processor die 16100 and a platform controller hub (PCH) die 16101 .

[0115] Processor die 16100 may include a core region 1620, which may include a plurality of cores 16240-1624 N , multiple temperature sensors 16260-1626 N and cache memory 1628. The processor die 16100 may include an uncore region 1630, which may include a power management unit (PMU) 1632, interconnect logic 1636, and one or more uncore agents, each of which has one or more temperature sensors 1638. The PMU 1632 may include temperature comparison logic 1634, a temperature data timer 1642, and a package sleep state timer 1644. The PMU 1632 may include hardware (e.g., a controller), software, firmware, or a combination thereof. For example, the PMU 1632 may include a hardware controller that performs a calculation (e.g., determining a difference between a received temperature value and a temperature control parameter, determining a maximum value among multiple values, etc.).

[0116] PCH die 16101 may include temperature sensor 1646 and temperature reporting logic 1640. Additional die 16102-1610 NCan include one or more of dynamic random access memory (DRAM), network interface controller (NIC) die and / or other die. Other die 16102-1610 N Each of may include a temperature sensor and temperature reporting logic (not shown).

[0117] In operation, the temperature reporting logic 1640 may report temperature data associated with the temperature of the PCH die 16101 to the PMU 1632. The temperature data may be generated by the temperature sensor 1646. (Alternatively, the temperature reporting logic 1640 may receive raw temperature data from the temperature sensor 1646 and may convert the received raw temperature data into temperature data before reporting to the PMU 1632). The temperature data may be received by the temperature comparison logic 1634 from the temperature reporting logic 1640 on a periodic basis according to a period to be determined by the temperature data timer 1642. The temperature data timer 1642 may periodically count down over a preset time period (Δt), and when the time period (Δt) is completed, the temperature data received by the temperature reporting logic 1640 from the temperature sensor 1646 may be received by the PMU 1632 and may be input to the temperature comparison logic 1634. In some embodiments, the temperature data may be measured substantially instantaneously, and the instantaneous temperature data may be transmitted from the PCH 16101 to the PMU 1632 when Δt expires. In other embodiments, the temperature data may be measured multiple times during the time period Δt. The measured temperature data may be averaged, and the average of the temperature data measured over Δt may be provided to the temperature comparison logic 1634.

[0118] Based on the temperature data received from each die, the temperature comparison logic 1634 can calculate the maximum temperature (T highest ). The temperature comparison logic 1634 can also calculate ΔT for each die. throttle and ΔT control For example, ΔT for the jth die in the Kth type of die throttle j The measured temperature of the die (determined based on the received temperature data) and the determined throttling temperature T throttleK (e.g., the throttling temperature for die type K, where K is an integer corresponding to the die type). Based on the calculated ΔT throttle j value, the minimum value (“ΔT throttle ”). The temperature comparison logic 1634 can be calculated from ΔT throttleK Select ΔT from the calculated values ​​(for all values ​​of K) throttleK The minimum value ("ΔT throttle ”).

[0119] In a similar manner, the temperature comparison logic 1634 may determine the ΔT for the j-th die (j=1, 2, . . . ) of the K-th type of die. control j , as the measured temperature of the die and the determined control temperature T controlK (eg, the control temperature for die type K, where K is an integer corresponding to the die type). Temperature comparison logic 1634 may determine the ΔT for a die of type K for each value of K. control j The minimum value ("ΔT controlK ”). According to various ΔT for all values ​​of K controlK , the minimum throttling margin ΔT can be selected control . Thermal reports can include T highest , ΔT throttle and ΔT control One or more of. Thermal reports may be stored, for example, in PMU 1632 and may be provided upon request. For example, reports may be provided to software management firmware (SMFW, not shown), which may be external to MCP 1600.

[0120] Based on the thermal report, SMFW can determine a course of action to reduce the operating temperature of MCP 1600. For example, if ΔT control is interpreted by the SMFW as an indication that the MCP 1600 is operating at an excessive temperature, the SMFW may, for example, implement cooling of the MCP 1600 via a coolant such as air or another coolant such as a liquid coolant. For example, if the coolant is air, the cooling may be implemented via engaging one or more fans to circulate the air. For example, if the coolant is liquid, the cooling may be implemented via engaging one or more liquid pumps to circulate the coolant. If according to ΔT contro If subsequent values ​​are used to determine that the MCP 1600 is not operating at an excessive temperature, the coolant circulation mechanism can be reduced, removed, or shut down.

[0121] If according to ΔT throttle , determine one of the tube cores 1610 i is operating at over 1610 die i T throttleK The temperature of ΔT may indicate throttling of one or more dies of MCP 1600. throttle The subsequent value of the tube core temperature is determined to be no more than its corresponding control temperature T throttleK , you can stop throttling.

[0122] Fig.1717 is a flow chart of a method 1700 according to an embodiment of the present invention. At block 1702, a temperature report request is received, for example, at a power management unit (PMU) of the MCP. Continuing to block 1704, temperature data is received from each die of the MCP by the PMU. Proceeding to block 1706, a maximum temperature T of all N dies of the MCP may be determined. max .

[0123] Thermal margins for temperatures collected on different types of dies may be handled differently because each die of type K may have a T specific to die type K. throttleK and / or T controlK Continuing to block 1707, K is initialized to a value of 1. Moving to block 1708, a margin to throttling (ΔT ) may be determined for each die of a particular type K (eg, K=1, 2, 3, etc.) in the MCP. throttle j ). (In some embodiments, the throttling temperature T throttleK is the same for all dies. In other embodiments, the throttling temperature T throttleK K may be different for each die type. ) Continuing to block 1710, the throttle j The value of determines the minimum ΔT for type K die throttleK .

[0124] Continuing to block 1712 , a margin ΔT to control may be determined for each die of type K. control j . (In some embodiments, the temperature T controlK is the same for all dies. In other embodiments, the control temperature T controlK may depend on die type K. ) Proceeding to block 1714, the control j The value of determines the minimum ΔT for a die of type K control j (=ΔT controlK ). Moving to decision diamond 1716, if another type of die is present in the MCP, proceed to block 1718, increment K and return to block 1708 to determine a minimum margin (eg, ΔT) for the other die type. throttleK and ΔT controlK ). Proceeding to block 1720, ΔT throttle and ΔT control is determined as ΔT for all values ​​of K throttleK and ΔT controlK Proceeding to block 1722, the MCP thermal report may be stored in response to the request and may include T max , ΔT throttle and ΔT controlThe report may be provided upon request, for example, to an external requestor (such as a platform including MCP, SMFW) or to another requestor.

[0125] Fig.18 18 is a flow chart of a method 1800 according to another embodiment of the present invention. At block 1802, a temperature timer (e.g., within a power management unit (PMU) of the MCP) may be started, which is used to time a first period, such as a timed interval that occurs before receiving temperature data from one or more dies of the MCP to the PMU. Continuing to decision diamond 1804, if the temperature timer has not completed timing of its first period, the temperature timer may continue to run until the first period is completed. Continuing to decision diamond 1806, if the MCP is in an active state (e.g., the MCP is in a package C0 state), continuing to block 1814, temperature data may be received by the PMU from the dies of the MCP.

[0126] If at decision diamond 1806, the MCP is in a sleep state (e.g., in a sleep state such as a package C3 state, a package C6 state, etc.), proceeding to block 1808, a delay timer may be started to delay the PMU's receipt of temperature data, which may allow the MCP to remain in sleep mode for an additional delay time, which may result in energy savings, such as compared to an earlier "wake-up" (e.g., to collect temperature data) that would be requested by the PMU upon expiration of the first period. Continuing to decision diamond 1810, the delay timer may run to complete the delay period. When the delay period is completed, proceeding to block 1811, the MCP may wake up from its sleep state to collect temperature data from the die of the MCP. Moving to block 1812, the delay timer may be reset. Continuing to block 1814, temperature data may be read from the die of the MCP, and proceeding to block 1816, the temperature data timer may be reset. Continuing to block 1802, the temperature data timer may be started again to time another first period between temperature measurements. Thus, when the MCP is in a sleep state, the timing of the data acquisition instances including the delay timer can provide a longer "down time" (e.g., a second period, which includes the first period and the delay period) compared to the first period. Implementation of the second period when the MCP is in a sleep mode can result in increased power savings due to the extended time interval in which the MCP is in the sleep state.

[0127] Other embodiments are described below.

[0128] A first embodiment is a processor including at least one core and power management logic to receive temperature data from a plurality of dies within a package including the processor, determine a minimum temperature control margin among a plurality of temperature control margins, wherein each temperature control margin is determined based on a respective thermal control temperature associated with the die and based on respective temperature data associated with the die, generate a thermal report, the thermal report being to include the minimum temperature control margin, and store the thermal report.

[0129] The second embodiment includes the elements of the first embodiment. In addition, the power management logic is further to determine a corresponding temperature control margin for each of the plurality of dies, wherein each temperature control margin is determined based on a difference between a corresponding thermal control temperature associated with the die and corresponding temperature data associated with the die.

[0130] The third embodiment includes the elements of the second embodiment. In addition, the power management logic is to select a minimum thermal control margin from among the plurality of temperature control margins.

[0131] A fourth embodiment includes the elements of the second embodiment. In addition, the power management logic is to determine whether the package is in an active state, and in response to determining that the package is in an active state, the power management logic is to periodically receive corresponding temperature data from each die of the package according to a first time period.

[0132] A fifth embodiment includes elements of the fourth embodiment. In addition, in response to determining by the power management logic that the package is in the sleep state, the power management logic is to wake up the package to an active state after a second time period has elapsed, wherein the second time period is longer than the first time period, and when waking up the package to the active state, the power management logic is to receive corresponding temperature data from each of the plurality of dies.

[0133] A sixth embodiment includes the elements of the first embodiment, wherein the power management logic is to provide thermal reporting in response to a request.

[0134] A seventh embodiment includes elements of the first embodiment, wherein the power management logic further determines each of a plurality of throttling margins, and wherein each throttling margin is determined based on a throttling temperature and based on corresponding temperature data received from a corresponding die of the plurality of die.

[0135] An eighth embodiment includes elements of the seventh embodiment. Additionally, the power management logic is further configured to determine a minimum throttling margin among the plurality of throttling margins and include the minimum throttling margin in the thermal report.

[0136] A ninth embodiment includes the elements of any of embodiments 1-9, wherein the power management logic is further to determine a maximum temperature of the plurality of dies based on the received temperature data and include the maximum temperature of the plurality of dies in a thermal report.

[0137] A tenth embodiment is a multi-chip package (MCP) to include a plurality of dies, each die providing corresponding temperature data associated with a die temperature of the die. The MCP is further to include power management logic to receive a plurality of temperature data including the corresponding temperature data from each die, determine a plurality of temperature control margins, each temperature control margin being based on the corresponding temperature data of the die and based on a corresponding thermal control temperature of the die, determine a minimum temperature control margin among the temperature control margins, and store a report including the minimum temperature control margin.

[0138] An eleventh embodiment includes the elements of the tenth embodiment. Additionally, the power management logic is to determine a maximum die temperature from the plurality of temperature data and include information associated with the maximum die temperature of the die in the report.

[0139] A twelfth embodiment includes the elements of the tenth embodiment, wherein the processor is to determine a throttling margin for each die based on a comparison of a corresponding throttling temperature of the die and a die temperature based on temperature data received from the die.

[0140] A thirteenth embodiment includes the elements of the twelfth embodiment, and the processor is further configured to determine a minimum throttle margin from the plurality of throttle margins and include the minimum throttle margin in the report.

[0141] A fourteenth embodiment includes the elements of any one of embodiments 10 to 13. In addition, the power management logic is to periodically collect corresponding temperature data from each die according to a first time period in response to the MCP being in an active state.

[0142] A 15th embodiment includes the elements of the 14th embodiment. In addition, in response to the MCP being in the sleep state, the power management logic is to wake up the MCP after a second time period longer than the first time period and collect corresponding temperature data from each die.

[0143] The 16th embodiment is a machine-readable medium having data stored thereon, which, if used by at least one machine, causes the at least one machine to manufacture at least one integrated circuit to perform a method, the method comprising: receiving corresponding temperature data from each of a plurality of dies of a multi-chip package (MCP) at a power management logic of the multi-chip package (MCP), determining, by the power management logic, a corresponding control temperature margin for each die based on the corresponding temperature data and based on a corresponding control temperature of the die, determining, by the power management logic, a minimum control temperature margin from the control temperature margins, and storing, by the power management logic, a thermal report including the minimum control temperature margin.

[0144] A seventeenth embodiment includes the elements of the sixteenth embodiment. Additionally, the method further includes determining, by the power management logic, a minimum throttling margin for the die based on a comparison of the die temperature to a reduced throttling temperature associated with activity of the MCP, and including the minimum throttling margin in the thermal report.

[0145] An eighteenth embodiment includes elements of any one of embodiments 16-17. In addition, the MCP is in one of an active state and a sleep state, and the method further includes determining, by the power management logic, whether the MCP is in the active state.

[0146] A 19th embodiment includes the elements of the 18th embodiment, and the method further includes, in response to determining that the MCP is in an active state, periodically receiving, by the power management logic, corresponding temperature data from each die according to a first time period.

[0147] A twentieth embodiment includes the elements of the nineteenth embodiment, and the method further includes, in response to determining that the MCP is in a sleep state, causing the MCP to change to an active state after a second time period greater than the first time period has elapsed, and receiving corresponding temperature data when the MCP is in the active state.

[0148] The 21st embodiment is a method, which includes: receiving corresponding temperature data from each of a plurality of dies of a multi-chip package (MCP) at a power management logic of the multi-chip package (MCP), determining, by the power management logic, a corresponding control temperature margin for each die based on the corresponding temperature data and based on the corresponding control temperature of the die, determining, by the power management logic, a minimum control temperature margin from the control temperature margins, and storing, by the power management logic, a thermal report including the minimum control temperature margin.

[0149] A 22nd embodiment includes the elements of the 21st embodiment, and further includes determining, by the power management logic, a minimum throttle margin for the die based on a comparison of the die temperature to a reduced throttle temperature associated with activity of the MCP, and including the minimum throttle margin in the thermal report.

[0150] A 23rd embodiment includes the elements of the 21st embodiment, wherein the MCP is in one of an active state and a sleep state, and the method further comprises determining, by the power management logic, whether the MCP is in the active state.

[0151] A 24th embodiment includes the elements of the 23rd embodiment, and further includes, in response to determining that the MCP is in an active state, periodically receiving, by the power management logic, corresponding temperature data from each die according to a first time period.

[0152] A 25th embodiment includes the elements of the 24th embodiment, and further includes, in response to determining that the MCP is in the sleep state, causing the MCP to change to an active state after a second time period greater than the first time period has elapsed, and receiving corresponding temperature data when the MCP is in the active state.

[0153] The twenty-sixth embodiment includes the elements of the twenty-first embodiment, and further includes providing a thermal report response to the request.

[0154] The 27th embodiment includes an apparatus for performing the method of any one of embodiments 21-26.

[0155] A twenty-eighth embodiment includes an apparatus comprising components for performing the method of any of embodiments 21-26.

[0156] The 29th embodiment is a device, which includes: a component for receiving corresponding temperature data from each of a plurality of dies in a multi-chip package (MCP), a component for determining a corresponding control temperature margin for each die based on the corresponding temperature data and based on the corresponding control temperature of the die, a component for determining a minimum control temperature margin from the control temperature margins, and a component for storing a thermal report including the minimum control temperature margin.

[0157] A 30th embodiment includes the elements of the 29th embodiment and further includes means for determining a minimum throttle margin for the die based on a comparison of the die temperature to a reduced throttle temperature associated with activity of the MCP and for including the minimum throttle margin in a thermal report.

[0158] A 31st embodiment includes the elements of the 29th embodiment. The MCP is in one of an active state and a sleep state, and the apparatus further includes means for determining whether the MCP is in the active state.

[0159] The 32nd embodiment includes the elements of the 31st embodiment, and further includes means for periodically receiving, by the power management logic, corresponding temperature data from each die according to a first time period in response to determining that the MCP is in an active state.

[0160] A 33rd embodiment includes the elements of the 32nd embodiment, further comprising means for causing the MCP to change to an active state after a second time period greater than the first time period has elapsed in response to determining that the MCP is in a sleep state, and receiving corresponding temperature data when the MCP is in the active state.

[0161] A thirty-fourth embodiment includes the elements of any of embodiments 29-33, and further includes means for providing a thermal report response to a request.

[0162] Embodiments may be implemented in code and may be stored on a non-transitory storage medium having instructions stored thereon, which may be used to program a system to perform the instructions. Embodiments may also be implemented in data and may be stored on a non-transitory storage medium, which, if used by at least one machine, causes at least one machine to manufacture at least one integrated circuit to perform one or more operations. The storage medium may include, but is not limited to, any type of disk (including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritable devices (CD-RWs), and magneto-optical disks), semiconductor devices (such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic cards or optical cards), or any other type of medium suitable for storing electronic instructions.

[0163] While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this invention.

Claims

1. A device comprising: Multi-die package substrate; a plurality of dies mounted on a multi-die package substrate, the plurality of dies comprising a first die and a second die; The first die includes: First, multiple cores to execute instructions and process data; a first plurality of integrated voltage regulators associated with respective cores of the first plurality of cores; a shared cache coupled to the first plurality of cores; a first plurality of temperature sensors associated with the first plurality of cores to generate first temperature measurement data; and The second die is coupled to the first die via a bidirectional interconnect, the second die comprising: a second temperature sensor integrated with the second die, for generating second temperature measurement data; A power management unit for executing thermal management firmware to manage the temperature of the plurality of dies, the power management unit being configured to: periodically reading temperature values ​​from the plurality of dies according to a specified time period, including temperature values ​​from the plurality of first temperature sensors, second temperature sensors, and additional temperature values ​​from additional dies of the plurality of dies, and processing the temperature values ​​to determine a thermal management result, wherein processing the temperature values ​​includes determining a maximum temperature value; Wherein a clock frequency of one or more of the plurality of dies is reduced based at least in part on the thermal management result.

2. The device according to claim 1, wherein: The first die also includes a power control unit for reducing a clock frequency of one or more of the first plurality of cores.

3. The device according to claim 1 or 2, wherein: An external voltage regulator will generate a regulated voltage that is applied to one or more of the plurality of dies.

4. The device according to claim 1 or 2, wherein: The first die includes a plurality of power domains including a plurality of core power domains, each power domain including one or more integrated voltage regulators. The apparatus of claim 4 , wherein the plurality of power domains further comprises an uncore power domain.

6. The device according to claim 1 or 2, wherein: The first die is divided into a plurality of clock domains, and each clock domain operates at an independent frequency.

7. The device according to claim 1 or 2, wherein: The first die also includes: An on-chip communication structure for coupling to the first plurality of cores.

8. The apparatus of claim 7, wherein the second die further comprises: A memory controller is provided for coupling the second die to the system memory.

9. The device according to claim 7, further comprising: a data interconnect coupled to an on-chip communication fabric; as well as A data communications link coupled to the data interconnect couples the first die to the second die.

10. The device according to claim 1 or 2, wherein: Processing the temperature values ​​also includes normalizing and aggregating the temperature values ​​received from the plurality of dies.

11. The device according to claim 1 or 2, wherein: The second die includes an input / output (I / O) interface.

12. The device according to claim 1 or 2, wherein: The first die has a first die type and the second die has a second die type.

13. The apparatus of claim 12, wherein the first die type comprises a processor die, and the second die type comprises a platform controller hub (PCH) die, a dynamic random access memory (DRAM) die, and a network interface controller (NIC) die.

14. The device according to claim 1 or 2, wherein: The power management unit is integrated on one of the plurality of dies to execute the thermal management firmware to manage the temperature of the plurality of dies.

15. A system comprising: System memory, used to store program code and data; a graphics processor coupled to the system memory to execute graphics commands; A processor coupled to the system memory to execute the program code and process the data, the processor comprising the apparatus according to any one of claims 1 to 14.

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