A Low Phase Noise Voltage Controlled Oscillator

Abstract

The present invention discloses a low phase noise voltage controlled oscillator, which receives the output voltage of LPF, and includes: a three-stage delay unit, a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a resistor and a capacitor, wherein the gates of the first NMOS tube and the second NMOS tube respectively receive the output voltage of LPF; the sources of the first NMOS tube and the second NMOS tube are respectively grounded; the drain of the first NMOS tube is connected to the drain of the first PMOS tube; the drain of the second NMOS tube is connected to the drain of the third PMOS tube. The present invention effectively compresses the low-frequency flicker noise of VCO.

Description

Technical Field

[0001] The present invention relates to a key module in a phase-locked loop frequency synthesizer (phase lock loop: PLL for short), namely a voltage controlled oscillator (VCO for short). Background Art

[0002] With the improvement of circuit design integration and higher-speed applications, the requirements for low-noise, high-precision clocks are becoming increasingly strong. In order to provide high-quality frequency signals, phase-locked loop frequency synthesizers are being used more and more frequently. Frequency synthesizers are devices that generate multiple frequencies from one or more reference frequencies. The signals generated by frequency synthesizers can be used as local oscillation signals for various transceivers, and can also complete modulation, demodulation, and provide clocks for clock recovery circuits in interface circuits.

[0003] VCO is the core module in the phase-locked loop. Designing a high-precision, low-phase-noise VCO is related to the performance of the entire PLL loop (phase-locked loop).

[0004] The traditional PLL circuit structure is as follows: Figure 2 . It consists of the following main modules: predivider, frequency phase detector (PFD), charge pump (CP), low pass filter (LPF), voltage control oscillator (VCO), feedback divider and lock detector. PFD compares the reference input signal after the predivider with the divided signal of VCO to obtain their frequency difference and phase difference. The frequency phase difference directly controls LPF through CP to generate an average voltage to control the output frequency of VCO, so that the system can be locked automatically. Ring VCO is widely used because of its small circuit area, low power consumption and wide frequency adjustment range. Figure 2 In the figure, Ref represents the reference frequency; Fdiv represents the signal after the VCO oscillation frequency is divided; UP represents the charging signal of the charge pump to the filter; DN represents the discharging signal of the charge pump to the filter; Vlpf represents the output signal of the filter; Fout represents the output signal of the oscillator; PLL Lock represents the signal for judging whether the PLL is locked.

[0005] The traditional ring VCO (ring voltage controlled oscillator) structure is as follows Figure 3The output of LPF is converted into the control current Vc of VCO, which is used to control the oscillation frequency of the delay cell of VCO. When the current increases, the oscillation frequency becomes higher, and vice versa. Figure 4 The simulation results of the ring VCO show that its phase noise index (PN) is about -87dBc@1MHz. PLLs with high signal quality requirements cannot use this structure. In order to overcome the problem of excessive phase noise of the ring VCO, a solution has proposed a structure of LC VCO (voltage-controlled oscillator with inductor and capacitor as adjustment unit) with superior phase noise performance, but LC VCO also has its shortcomings: first, its frequency processing range is too narrow compared to the ring VCO, and its power consumption is higher, and the resonance circuit of the inductor and capacitor will use too much chip area.

[0006] The traditional PLL has the following noise sources: input noise, phase detection noise, control voltage noise, VCO noise... Among them, input noise and phase detection noise can be obtained by reducing the loop bandwidth, but the reduction of loop bandwidth will increase the control voltage noise and VCO noise. The noise reduction of the control voltage can be controlled by reducing the voltage gain Kvco (gain of the voltage-controlled oscillator) of the VCO. The VCO has a stable gain mainly to suppress the external noise of the VCO, and the internal noise of the VCO is mainly divided into two categories: device thermal noise, flicker noise and environmental noise, and the environmental noise includes power supply noise and substrate noise. In terms of overcoming environmental noise, differential is better than single-ended design. Summary of the invention

[0007] The object of the present invention is to overcome the defects of the prior art and provide a low phase noise voltage controlled oscillator, which effectively compresses the low frequency flicker noise of the VCO.

[0008] The technical solution to achieve the above purpose is:

[0009] A low phase noise voltage controlled oscillator receives the output voltage of an LPF, comprising: a three-stage delay unit, a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a resistor and a capacitor, wherein:

[0010] The gates of the first NMOS transistor and the second NMOS transistor receive the output voltage of the LPF respectively;

[0011] The source electrodes of the first NMOS tube and the second NMOS tube are respectively grounded;

[0012] The drain of the first NMOS tube is connected to the drain of the first PMOS tube;

[0013] The drain of the second NMOS tube is connected to the drain of the third PMOS tube;

[0014] The sources of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are connected;

[0015] The gate of the first PMOS tube is connected to the drain of the first PMOS tube;

[0016] The gate of the first PMOS tube is connected to the gate of the second PMOS tube through a resistor;

[0017] The gate of the second PMOS tube is connected to the source of the second PMOS tube through a capacitor;

[0018] The drain of the second PMOS tube is connected to the drain of the fourth PMOS tube;

[0019] The gate of the third PMOS tube is connected to the drain of the third PMOS tube;

[0020] The gate of the third PMOS tube is connected to the gate of the fourth PMOS tube;

[0021] The drain of the fourth PMOS tube is connected to the control end of the three-stage delay unit.

[0022] Preferably, the three-stage delay unit comprises: first to third stage delay units;

[0023] The first to third stage delay units are connected in series, and the output end of the third stage delay unit is connected to the input end of the first stage delay unit;

[0024] The control terminals of the first to third stage delay units are respectively connected to the drain of the fourth PMOS tube.

[0025] The beneficial effects of the present invention are as follows: the present invention adds a path of resistors and capacitors connected in series, and by adding redundant zeros and poles in the v2i (voltage to current) current mirror direction of the ring VCO to compress the low-frequency flicker noise of the VCO, a lower power supply noise rejection ratio (PSRR) can be provided for the power supply noise, thereby compressing the flicker noise of the VCO device to the greatest extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a circuit diagram of a low phase noise voltage controlled oscillator of the present invention;

[0027] Figure 2 It is a circuit diagram of a phase-locked loop frequency synthesizer in the prior art;

[0028] Figure 3 It is a circuit diagram of a ring voltage-controlled oscillator in the prior art;

[0029] Figure 4 It is a schematic diagram of a ring VCO PN characteristic curve in the prior art;

[0030] Figure 5 It is a schematic diagram of the ring VCO PN characteristic curve in the present invention. DETAILED DESCRIPTION

[0031] The present invention will be further described below in conjunction with the accompanying drawings.

[0032] See also Figure 1 The low phase noise voltage controlled oscillator of the present invention receives the output voltage Vlpf of the LPF, and includes: a three-stage delay unit, a first NMOS tube NM1, a second NMOS tube NM2, a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a resistor R and a capacitor C.

[0033] The gates of the first NMOS transistor NM1 and the second NMOS transistor NM2 receive the output voltage Vlpf of the LPF, respectively. The sources of the first NMOS transistor NM1 and the second NMOS transistor NM2 are grounded, respectively.

[0034] The drain of the first NMOS transistor NM1 is connected to the drain of the first PMOS transistor PM1. The drain of the second NMOS transistor NM2 is connected to the drain of the third PMOS transistor PM3. The sources of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are connected. The gate of the first PMOS transistor PM1 is connected to the drain of the first PMOS transistor PM1. The gate of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2 through a resistor R. The gate of the second PMOS transistor PM2 is connected to the source of the second PMOS transistor PM2 through a capacitor C.

[0035] The drain of the second PMOS transistor PM2 is connected to the drain of the fourth PMOS transistor PM4. The gate of the third PMOS transistor PM3 is connected to the drain of the third PMOS transistor PM3; the gate of the third PMOS transistor PM3 is connected to the gate of the fourth PMOS transistor PM4; the drain of the fourth PMOS transistor PM4 is connected to the control end of the three-stage delay unit.

[0036] The three-stage delay unit includes: first-stage to third-stage delay units 1, 2, and 3; the first-stage to third-stage delay units 1, 2, and 3 are connected in series, and the output end of the third-stage delay unit 3 is connected to the input end of the first-stage delay unit 1; and the control ends of the first-stage to third-stage delay units 1, 2, and 3 are respectively connected to the drain of the fourth PMOS tube PM4.

[0037] In the above, the control current of the three-stage delay unit is not simply realized by v2i (voltage to current) controlled by LPF. The output voltage Vlpf of LPF generates two currents v2i through the amplification effect of the input tube (the first NMOS tube NM1 and the second NMOS tube NM2). One current generates a current of gm2*N through the mirror, and the other current generates a current of gm1*M through the added resistor R and capacitor C, which generates low-frequency zero poles. Since the flicker noise of VCO is usually at a very low frequency, the flicker noise can be well suppressed and better isolation is also provided for power supply noise. The calculation method of the newly added zero poles of the circuit is as follows:

[0038]

[0039] Among them, v2i: represents the conversion technology from voltage to current; gm1, gm2: represent the gain of input field effect tube; gm1*M : Indicates M times the input field effect tube gain ； gm2*N: represents N times the input field effect tube gain; Rout: represents the output impedance; S: represents the complex number after Laplace transformation of the transfer function; ω z : represents the zero point of the transfer function; ω p : represents the pole of the transfer function; R: represents the resistance in the circuit; C: represents the capacitance in the circuit; N: represents N times amplification; M: represents M times amplification.

[0040] like Figure 5 As shown, the ring VCO PN characteristic curve of the present invention. VCO PN index is -107dBc@1MHz.

[0041] The above embodiments are only used to illustrate the present invention, rather than to limit the present invention. Those skilled in the relevant technical field may make various changes or modifications without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions should also belong to the scope of the present invention and should be defined by the claims.

Claims

1. A low phase noise voltage controlled oscillator, receiving an output voltage of an LPF, characterized in that: include: A three-stage delay unit, a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a resistor and a capacitor, wherein: The gates of the first NMOS transistor and the second NMOS transistor receive the output voltage of the LPF respectively; The source electrodes of the first NMOS tube and the second NMOS tube are respectively grounded; The drain of the first NMOS tube is connected to the drain of the first PMOS tube; The drain of the second NMOS tube is connected to the drain of the third PMOS tube; The sources of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are connected; The gate of the first PMOS tube is connected to the drain of the first PMOS tube; The gate of the first PMOS tube is connected to the gate of the second PMOS tube through a resistor; The gate of the second PMOS tube is connected to the source of the second PMOS tube through a capacitor; The drain of the second PMOS tube is connected to the drain of the fourth PMOS tube; The gate of the third PMOS tube is connected to the drain of the third PMOS tube; The gate of the third PMOS tube is connected to the gate of the fourth PMOS tube; The drain of the fourth PMOS tube is connected to the control end of the three-stage delay unit; The three-stage delay unit comprises: first to third stage delay units; The first to third stage delay units are connected in series, and the output end of the third stage delay unit is connected to the input end of the first stage delay unit; The control terminals of the first to third stage delay units are respectively connected to the drain of the fourth PMOS tube; The control current of the three-stage delay unit is not simply realized by v2i controlled by LPF. The output voltage Vlpf of LPF generates two currents v2i through the amplification effect of the first NMOS tube and the second NMOS tube. One current generates a current of gm2*N through the mirror, and the other current generates a current of gm1*M through the added resistor R and capacitor C, thereby generating low-frequency zero poles. Among them, v2i: represents the conversion technology from voltage to current; gm1, gm2: represent the gain of the input field effect tube; gm1*M: represents M times the gain of the input field effect tube; gm2*N: represents N times the gain of the input field effect tube.

Images