Display Devices

Abstract

The display device includes: a display area and a non-display area; a plurality of signal lines in the display area; and a plurality of connecting lines in the display area and respectively connected to the plurality of signal lines, wherein the plurality of connecting lines include a plurality of first connecting lines respectively connected to the plurality of signal lines, a plurality of third connecting lines on the same layer as the plurality of first connecting lines, and a plurality of second connecting lines respectively connecting the plurality of first connecting lines to the plurality of third connecting lines.

Description

Technical Field

[0001] Aspects of some example embodiments of the present disclosure relate to a display device. Background Art

[0002] With the development of multimedia, the importance of display devices has increased. In this regard, various types of display devices such as liquid crystal displays (LCDs) and organic light emitting displays (OLEDs) are used. Among the above display devices, organic light emitting displays have a relatively wide viewing angle and may include self-emissive elements.

[0003] The organic light emitting display includes a pixel circuit and a driving unit for driving the pixel circuit. The driving unit may include a scan driver for providing a scan signal to the pixel circuit and a data driver for providing a data signal to the pixel circuit. The driving circuits of the scan driver and the data driver may be arranged in a non-display area adjacent to the display area, and the non-display area may be used as an invalid space in terms of the function of the display device.

[0004] The above information disclosed in this Background section is only for enhancement of background understanding and therefore, the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0005] Aspects of the present disclosure provide a display device that minimizes or reduces a non-display area of ​​the display device and prevents or reduces degradation of display quality.

[0006] The technical problems of the present disclosure are not limited to the above-mentioned technical problems, and a person of ordinary skill in the art can obviously understand other technical problems not mentioned herein based on the following description.

[0007] According to some example embodiments of the present disclosure, a display device includes a display area and a non-display area, a plurality of signal lines in the display area, and a plurality of connection lines in the display area and respectively connected to the plurality of signal lines, wherein the plurality of connection lines include a plurality of first connection lines respectively connected to the plurality of signal lines, a plurality of third connection lines on the same layer as the plurality of first connection lines, and a plurality of second connection lines configured to respectively connect the plurality of first connection lines to the plurality of third connection lines.

[0008] According to some example embodiments, wherein the first connection line and the third connection line extend in a first direction, and the second connection line extends in a second direction crossing the first direction.

[0009] According to some example embodiments, the display device further includes a plurality of first dummy patterns and a plurality of second dummy patterns, wherein the first dummy patterns are on the same layer as the first connection lines, and the second dummy patterns are on the same layer as the second connection lines.

[0010] According to some example embodiments, wherein the first dummy patterns extend in a first direction, and the second dummy patterns extend in a second direction crossing the first direction, and wherein intervals between the plurality of first dummy patterns in the second direction are substantially equal to intervals between the plurality of first connecting lines in the second direction.

[0011] According to some example embodiments, the signal line is formed of a first conductive layer, the first connection line or the third connection line is formed of a second conductive layer, the second connection line is formed of a third conductive layer, and the second conductive layer is between the first conductive layer and the third conductive layer.

[0012] According to some example embodiments, wherein the second connection line is electrically connected to the first connection line through a first contact hole exposing one end of the first connection line, and wherein the second connection line is electrically connected to the third connection line through a second contact hole exposing one end of the third connection line.

[0013] According to some example embodiments, wherein the first dummy pattern is formed of the second conductive layer, and the second dummy pattern is formed of the third conductive layer.

[0014] According to some example embodiments, the display device further includes a power supply voltage line formed of the first conductive layer, wherein the power supply voltage line is electrically connected to the second dummy pattern.

[0015] According to some example embodiments of the present disclosure, a display device includes: a substrate including a display area and a non-display area, a plurality of signal lines in the display area of ​​the substrate, a plurality of connecting lines in the display area and respectively connected to the plurality of signal lines, a first electrode on the plurality of connecting lines, a light-emitting layer on the first electrode, and a second electrode on the light-emitting layer, wherein the plurality of connecting lines include a plurality of first connecting lines respectively connected to the plurality of signal lines and a plurality of second connecting lines respectively connected to the plurality of first connecting lines, and the first connecting lines and the second connecting lines are on different layers from each other.

[0016] According to some example embodiments, the signal line is formed of a first conductive layer, the first connection line is formed of a second conductive layer, the second connection line is formed of a third conductive layer, and the second conductive layer is between the first conductive layer and the third conductive layer.

[0017] According to some example embodiments, the display device further includes a semiconductor layer on the substrate and a first gate conductive layer on the semiconductor layer, wherein the first gate conductive layer is between the semiconductor layer and the first conductive layer, and wherein the first electrode is between the third conductive layer and the second electrode.

[0018] According to some example embodiments, wherein the first connection lines extend in a first direction, and the second connection lines extend in a second direction crossing the first direction.

[0019] According to some example embodiments, wherein the connection lines further include a plurality of third connection lines respectively connected to the plurality of second connection lines, and the third connection lines extend in the first direction and are on the same layer as the first connection lines.

[0020] According to some example embodiments, the display device further includes a plurality of first dummy patterns and a plurality of second dummy patterns in the display area, wherein the first dummy patterns are on the same layer as the first connection lines, and the second dummy patterns are on the same layer as the second connection lines.

[0021] According to some example embodiments, wherein the display area includes a front display area, a first side display area extending from a first side of the front display area, and a second side display area extending from a second side of the front display area.

[0022] According to some example embodiments, wherein the plurality of connection lines extend from the non-display area and extend to the non-display area via the first side display area, the front display area or the second side display area.

[0023] According to some example embodiments, the display device further includes a corner region between the first side display region and the second side display region, wherein the first connection line is connected to the signal line through a contact hole in the corner region. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other aspects and features of the present disclosure will become more apparent by describing in more detail aspects of some example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0025] Figure 1 is a plan view of a display device according to some example embodiments;

[0026] Figure 2 is a plan view illustrating signal lines, connection lines, and dummy lines of a display device according to some example embodiments;

[0027] Figure 3 yes Figure 2 An enlarged plan view of area A;

[0028] Figure 4 is along Figure 3 A cross-sectional view taken along line IV-IV';

[0029] Figure 5 yes Figure 2 an enlarged plan view of area B;

[0030] Figure 6 is along Figure 5 A cross-sectional view taken along line VI-VI';

[0031] Figure 7 is along Figure 5A cross-sectional view taken along line VII-VII';

[0032] Figure 8 yes Figure 2 An enlarged plan view of region C;

[0033] Fig. 9 is along Figure 8 A cross-sectional view taken along line IX-IX';

[0034] Fig.10 is a plan view showing an arrangement of pixels according to some example embodiments;

[0035] Fig.11 It is shown Fig.10 A cross-sectional view of an example of a pixel;

[0036] Fig.12 is an enlarged plan view of region B according to some example embodiments;

[0037] Fig.13 is along Fig.12 A cross-sectional view taken along line XIII-XIII';

[0038] Fig.14 is an enlarged plan view of region A according to some example embodiments;

[0039] Fig.15 is along Fig.14 A cross-sectional view taken along line XV-XV';

[0040] Fig.16 is an enlarged plan view of region B according to some example embodiments;

[0041] Fig.17 is along Fig.16 A cross-sectional view taken along line XVII-XVII';

[0042] Fig.18 is along Fig.16 A cross-sectional view taken along line XVIII-XVIII';

[0043] Fig.19 is a perspective view of a display device according to some example embodiments;

[0044] Fig. 20 yes Fig.19 An expanded view of a display device;

[0045] Fig.21 It is shown Fig.19 An expanded diagram of the signal lines and connecting lines of the display device;

[0046] Fig. 22 yes Fig.21an enlarged plan view of area D; and

[0047] Fig.23 is along Fig. 22 A cross-sectional view taken along line XXIII-XXIII'. DETAILED DESCRIPTION

[0048] Aspects of some example embodiments of the present invention will now be more fully described below with reference to the accompanying drawings in which example embodiments of the present invention are shown. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these example embodiments are provided so that this disclosure will be thorough and complete, and will more fully convey the scope of the present invention to those skilled in the art.

[0049] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0050] Like reference numerals refer to like parts throughout the specification.

[0051] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0052] In the disclosure herein, the first direction DR1 indicates a Y-axis direction, the second direction DR2 indicates an X-axis direction, and the third direction DR3 indicates a Z-axis direction.

[0053] Figure 1 is a plan view of a display device according to some example embodiments. Figure 2 is a plan view illustrating signal lines, connection lines, and dummy lines of a display device according to some example embodiments. Figure 3 yes Figure 2 An enlarged plan view of area A. Figure 4 is along Figure 3 A cross-sectional view taken along line IV-IV'. Figure 5 yes Figure 2 An enlarged plan view of area B. Figure 6 is along Figure 5 A cross-sectional view taken along line VI-VI'. Figure 7 is along Figure 5 A cross-sectional view taken along line VII-VII'. Figure 8 yes Figure 2 An enlarged plan view of area C. Fig. 9 is along Figure 8 A cross-sectional view taken along line IX-IX'.

[0054] refer to Figures 1 to 9The display device 1 is a device configured to display a moving image or a still image. The display device 1 can be used as a display screen for various products such as portable electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation or ultra-portable mobile PCs (UMPCs)), as well as televisions, notebook computers, monitors, billboards, or IoT devices.

[0055] The display device 1 may include a display panel 10. The display panel 10 may be a flexible substrate including a flexible polymer material such as polyimide. Therefore, the display panel 10 may be bent, curved, folded, or rolled.

[0056] The display panel 10 may include a main region MR and a bending region BR connected to one side of the main region MR. The display panel 10 may further include a sub region SR connected to the bending region BR and overlapping the main region MR in a thickness direction.

[0057] The display panel 10 may include a display area DA as a portion in which an image is displayed and a non-display area NDA other than the display area DA. The display area DA may include a plurality of pixels. Each pixel may include a light-emitting layer and a circuit layer for controlling the amount of light emitted by the light-emitting layer. The circuit layer may include a display line, a display electrode, and at least one transistor. The light-emitting layer may include an organic light-emitting material. The light-emitting layer may be sealed by an encapsulation layer. The detailed configuration of the pixel will be described later.

[0058] The display area DA is located in the main region MR. The peripheral edge portion of the display area DA in the main region MR, the bending area BR, and the sub-region SR may be a non-display area NDA. However, the embodiment according to the present disclosure is not limited thereto, and the bending area BR and the sub-region SR may also include the display area DA.

[0059] When viewed from the top, the main region MR may have a shape similar to the appearance of the display device 1. The main region MR may be a flat region located on one surface of the display device 1. However, embodiments according to the present disclosure are not limited thereto, and at least one of the edges in the main region MR except for the edge (side) connected to the bending region BR may be formed as a curved surface or bent in a vertical direction.

[0060] When at least one of the edges in the main region MR except the edge (side) connected to the bending region BR is formed as a curved surface or is bent, the display area DA may also be located at the corresponding edge. However, the embodiments according to the present disclosure are not limited thereto, and the non-display area NDA that does not display an image may be located at the bent or curved edge, or the display area DA and the non-display area NDA may be arranged together at the bent or curved edge.

[0061] The non-display area NDA may be located around the display area DA of the main region MR. The non-display area NDA of the main region MR may be located in a region from the outer boundary of the display area DA to the edge of the display panel 10. A signal line DL, a connection line DM, or a driving circuit configured to apply a signal to the display area DA may be located in the non-display area NDA of the main region MR. In addition, the outermost black matrix may be located in the non-display area NDA of the main region MR, but embodiments according to the present disclosure are not limited thereto.

[0062] The bending region BR is connected to the main region MR. For example, the bending region BR may be connected through one short side of the main region MR. In the bending region BR, the display panel 10 may be bent with a curvature in a direction opposite to the third direction DR3 (i.e., in a direction opposite to the display surface). When the display panel 10 is bent in the bending region BR, the surface of the display panel 10 may be reversed. In other words, the surface may be changed so that one surface of the display panel 10 facing upward faces outward through the bending region BR and then faces downward.

[0063] The sub-region SR extends from the bending region BR. The sub-region SR may start from the portion where the bending is completed and extend in a direction parallel to the main region MR. The sub-region SR may overlap with the main region MR in the third direction DR3 of the display panel 10 (i.e., in the thickness direction). The sub-region SR may overlap with the non-display area NDA at the edge of the main region MR, and may further overlap with the display area DA of the main region MR.

[0064] The width of the sub-region SR in the second direction DR2 may be equal to the width of the bending region BR in the second direction DR2, but is not limited thereto.

[0065] The driving chip 20 may be located on the sub-region SR of the display panel 10. The driving chip 20 may generate a driving signal required to drive the pixel and supply the driving signal to the pixel defined in the display area DA. For example, the driving chip 20 may generate a data signal to determine the emission brightness of the pixel. In this case, the driving chip 20 may provide the data signal to the pixel through the connection line DM and the signal line DL.

[0066] The driving chip 20 may be attached to the display panel 10 through an anisotropic conductive film, or may be attached to the display panel 10 through ultrasonic bonding. The width of the driving chip 20 in the second direction DR2 may be smaller than the width of the display panel 10 in the second direction DR2.

[0067] The driving substrate 30 may be connected to one end of the sub-region SR of the display panel 10. A pad portion may be provided at the end of the sub-region SR, and the driving substrate 30 may be connected to the pad portion. The driving substrate 30 may be a flexible printed circuit board or a film.

[0068] A plurality of signal lines DL, connection lines DM or dummy lines DP may be located in the subregion SR, the bending region BR and the main region MR. The signal lines DL and connection lines DM may extend from the subregion SR through the bending region BR to the main region MR. The dummy lines DP may be located in the main region MR.

[0069] Reference Figures 2 to 9 The signal lines DL, the connection lines DM, and the dummy lines DP are described in more detail.

[0070] refer to Figures 2 to 9 , the display device 1 may include a plurality of signal lines DL, a plurality of connection lines DM, and a plurality of dummy lines DP. Meanwhile, the signal lines DL, the connection lines DM, and the dummy lines DP are configured to extend in the first direction DR1 or the second direction DR2, and may be symmetrical about a reference axis (not shown) formed through the center of the area of ​​the display device 1. Hereinafter, the description will focus on the signal lines DL, the connection lines DM, and the dummy lines DP located on the left side of the display device 1.

[0071] The signal lines DL may extend from the non-display area NDA and be located in the display area DA. The signal lines DL may extend in a first direction DR1 and may be sequentially arranged at certain intervals along a second direction DR2. The second direction DR2 refers to a direction crossing the first direction DR1 and may be perpendicular to the first direction DR1.

[0072] One end of the signal line DL may be electrically connected to the connection line DM. One end of the signal line DL connected to the connection line DM may be located in the non-display area NDA under the main region MR. The signal line DL may be, for example, a data line that transmits a data signal.

[0073] The plurality of connection lines DM may extend from the non-display area NDA and extend to the non-display area NDA through the display area DA. The connection lines DM may include first connection lines DM1 respectively connected to the signal lines DL, second connection lines DM2 respectively connected to the first connection lines DM1, and third connection lines DM3 respectively connected to the second connection lines DM2.

[0074] A plurality of first connection lines DM1 may extend from the non-display area NDA and be located in the display area DA. The first connection lines DM1 may extend in a first direction DR1 and may be sequentially arranged at certain intervals along a second direction DR2. An interval WD1 between the plurality of first connection lines DM1 may be substantially the same as an interval between the signal lines DL.

[0075] One end of the first connection line DM1 may be located in the non-display area NDA, and the other end of the first connection line DM1 may be located in the display area DA. The one end of the first connection line DM1 may extend to one end of the signal line DL located in the non-display area NDA below the main area MR. The one end of the first connection line DM1 may be electrically connected to each signal line DL in the non-display area NDA below the main area MR.

[0076] The first connection line DM1 may be located on a layer different from the layer on which the signal line DL is located, and may be insulated from the signal line DL by an insulating layer. Figure 4 As shown in FIG. 1 , the signal line DL may be formed of the first conductive layer 130, the first connection line DM1 may be formed of the second conductive layer 140, and the signal line DL may be insulated from the first connection line DM1 by the fourth insulating layer IL4. The one end of the first connection line DM1 may pass through the fourth insulating layer IL4 and be electrically connected to the signal line DL through the first contact hole CNT1 exposing one end of the signal line DL.

[0077] at the same time, Figure 4 and Figure 6 The first connection line DM1 is illustrated as overlapping the signal line DL in the thickness direction, but the embodiments according to the present disclosure are not limited thereto. In other words, when viewed from the top, the first connection line DM1 may be arranged so as not to overlap with the signal line DL. In this case, the first connection line DM1 may be located in a space where a plurality of signal lines DL are spaced apart from each other.

[0078] A plurality of second connection lines DM2 may be located in the display area DA. The second connection lines DM2 may extend in the second direction DR2 and may be sequentially arranged at specific intervals along the first direction DR1. One end of the second connection line DM2 may extend to the other end of the first connection line DM1 located in the display area DA. The one end of the second connection line DM2 may be electrically connected to the other end of each first connection line DM1 in the display area DA.

[0079] The second connection wire DM2 may be located on a layer different from the layer on which the first connection wire DM1 is located, and may be insulated from the first connection wire DM1 by an insulating layer. Figure 6As shown in , the first connection line DM1 may be formed by the second conductive layer 140, the second connection line DM2 may be formed by the third conductive layer 150, and the first connection line DM1 may be insulated from the second connection line DM2 by the fifth insulating layer IL5. The one end of the second connection line DM2 may pass through the fifth insulating layer IL5 and be electrically connected to the first connection line DM1 through the second contact hole CNT2 exposing the other end of the first connection line DM1.

[0080] A plurality of third connection lines DM3 may extend from the non-display area NDA and be located in the display area DA. The third connection lines DM3 may extend in the first direction DR1 and may be sequentially arranged at certain intervals along the second direction DR2. An interval WD3 between the third connection lines DM3 may be substantially the same as an interval WD1 between the first connection lines DM1.

[0081] One end of the third connection line DM3 may be located in the display area DA, and the other end of the third connection line DM3 may be located in the non-display area NDA. The one end of the third connection line DM3 may extend to the other end of the second connection line DM2. The one end of the third connection line DM3 may be electrically connected to the other end of the second connection line DM2 in the display area DA.

[0082] The third connection line DM3 may be located on a layer different from the layer on which the second connection line DM2 is located, and may be insulated from the second connection line DM2 by an insulating layer. In addition, the third connection line DM3 may be located on the same layer as the layer on which the first connection line DM1 is located. Figure 6 As shown in , the second connection line DM2 may be formed by the third conductive layer 150, the third connection line DM3 may be formed by the second conductive layer 140, and the second connection line DM2 may be insulated from the third connection line DM3 by the fifth insulating layer IL5. The other end of the second connection line DM2 may pass through the fifth insulating layer IL5 and be electrically connected to the third connection line DM3 through the third contact hole CNT3 exposing the one end of the third connection line DM3.

[0083] at the same time, Figure 6 The third connection line DM3 is illustrated as overlapping the signal line DL in the thickness direction, but the embodiments of the present disclosure are not limited thereto. In other words, when viewed from the top, the third connection line DM3 may be arranged so as not to overlap with the signal line DL. In this case, the third connection line DM3 may be located in a space where a plurality of signal lines DL are spaced apart from each other.

[0084] As described above, the display device 1 may include first to third connection lines DM1, DM2, and DM3 disposed via the display area DA, and provide image signals to the signal lines DL through the first to third connection lines DM1, DM2, and DM3. Therefore, an additional dead space required to connect the signal lines DL to the driving chip 20 may be unnecessary. In other words, the dead space may be minimized or reduced.

[0085] The plurality of dummy lines DP may be located on the display area DA of the main region MR. The dummy lines DP may include a plurality of first dummy lines (or first dummy patterns) DP1 and a plurality of second dummy lines (or second dummy patterns) DP2.

[0086] A plurality of first dummy lines DP1 may extend in the first direction DR1 and may be sequentially arranged at specific intervals along the second direction DR2. An interval WP1 between the first dummy lines DP1 may be substantially the same as an interval WD1 between the first connection lines DM1. In addition, an interval WP1 between the first dummy lines DP1 may be substantially the same as an interval WD3 between the third connection lines DM3.

[0087] The first dummy line DP1 may be aligned with the first connection line DM1 and / or the third connection line DM3 in the first direction DR1. The first dummy line DP1 may partially overlap with the second connection line DM2.

[0088] One end of the first dummy line DP1 may be spaced apart from one end or the other end of the first connection line DM1 and / or the third connection line DM3. The one end of the first dummy line DP1 may face the one end or the other end of the first connection line DM1 and / or the third connection line DM3. The first gap G1 may be defined at a space where the one end of the first dummy line DP1 is spaced apart from the one end or the other end of the first connection line DM1 and / or the third connection line DM3 and faces the one end or the other end of the first connection line DM1 and / or the third connection line DM3.

[0089] The first dummy line DP1 may be located on the same layer as the layer on which the first connection line DM1 and / or the third connection line DM3 are located. In addition, the first dummy line DP1 may be located on a layer different from the layer on which the second connection line DM2 is located. Figure 7 and Fig. 9 As shown in , the first dummy line DP1 may be formed of the second conductive layer 140 .

[0090] at the same time, Figure 7 and Fig. 9The first dummy line DP1 is illustrated as overlapping the signal line DL in the thickness direction, but the embodiments according to the present disclosure are not limited thereto. In other words, when viewed from the top, the first dummy line DP1 may be arranged so as not to overlap with the signal line DL. In this case, the first dummy line DP1 may be located in a space where a plurality of signal lines DL are spaced apart from each other.

[0091] The plurality of second dummy lines DP2 may extend in the second direction DR2 and may be sequentially arranged at certain intervals along the first direction DR1. An interval WP2 between the second dummy lines DP2 may be substantially the same as an interval WD2 between the second connection lines DM2.

[0092] When viewed from the top, the plurality of second dummy lines DP2 may be located at one side and the other side of the second connection line DM2. In other words, when viewed from the top, the second connection line DM2 may be located between the plurality of second dummy lines DP2. The second dummy line DP2 may be aligned with the second connection line DM2 in the second direction DR2. The second dummy line DP2 may partially overlap the first connection line DM1 and / or the third connection line DM3.

[0093] One end or the other end of the second dummy line DP2 may be spaced apart from one end or the other end of the second connection line DM2. A second gap G2 may be defined at a space where the one end or the other end of the second dummy line DP2 is spaced apart from the one end or the other end of the second connection line DM2.

[0094] The second dummy line DP2 may be located on a layer different from the layer on which the first dummy line DP1 is located. In addition, the second dummy line DP2 may be located on a layer different from the layer on which the first connection line DM1 and / or the third connection line DM3 are located. In addition, the second dummy line DP2 may be located on the same layer as the layer on which the second connection line DM2 is located. For example, Figure 7 and Fig. 9 As shown in , the second dummy line DP2 may be formed of the third conductive layer 150 .

[0095] As described above, when the dummy lines DP1 and DP2 include a plurality of conductive layers, and when the first dummy line DP1 extends in the first direction DR1 and the second dummy line DP2 extends in the second direction DR2, the dummy lines DP1 and DP2 may implement a grid pattern shape together with the connection lines DM1, DM2, and DM3. Therefore, different patterns are minimized or reduced, so that visual recognition of the patterns may be prevented or reduced.

[0096] Hereinafter, the pixel P of the display device 1 will be described in more detail.

[0097] Fig.10 is a plan view showing the arrangement of pixels according to the embodiment. Fig.11It is shown Fig.10 A cross-sectional view of an example of a pixel.

[0098] refer to Fig.10 and Fig.11 , each pixel P may include sub-pixels R, G, and B. The sub-pixels R, G, and B may include a first sub-pixel R emitting light of a first color, a second sub-pixel G emitting light of a second color, and a third sub-pixel B emitting light of a third color. One first sub-pixel R, two second sub-pixels G, and one third sub-pixel B may be defined as one pixel P. A pixel P refers to a group of sub-pixels capable of representing grayscale. Fig.10 It is illustrated that the second subpixel G, the first subpixel R, the second subpixel G, and the third subpixel B are sequentially arranged in the second direction DR2 . However, the arrangement of the subpixels R, G, and B is not limited thereto.

[0099] Each sub-pixel R, G, and B may have different shapes and sizes. Fig.10 It is illustrated that the third sub-pixel B has the largest size, and the second sub-pixel G has the smallest size. However, the sizes of the sub-pixels R, G, and B are not limited thereto.

[0100] The anode electrode ANO may be arranged to correspond to each of the sub-pixels R, G, and B. The anode electrode ANO may include first to third anode electrodes ANO1, ANO2, and ANO3 corresponding to each of the sub-pixels R, G, and B. The first anode electrode ANO1 may be arranged to correspond to the first sub-pixel R, the second anode electrode ANO2 may be arranged to correspond to the second sub-pixel G, and the third anode electrode ANO3 may be arranged to correspond to the third sub-pixel B.

[0101] Reference Fig.11 The cross-sectional structure of each sub-pixel R, G, and B is described in more detail. Fig.11 , new reference numerals are additionally given and occasionally written together with some components to clarify inter-layer configurations of the same configurations as previously mentioned components.

[0102] refer to Fig.11 , each sub-pixel R, G and B may include a substrate 101, a buffer layer BF, a semiconductor layer ACT, a first insulating layer IL1, a first gate conductive layer 110, a second insulating layer IL2, a second gate conductive layer 120, a third insulating layer IL3, a first conductive layer 130, a fourth insulating layer IL4, a second conductive layer 140, a fifth insulating layer IL5, a third conductive layer 150, a sixth insulating layer IL6, a first electrode 171, a pixel defining layer 180 including an opening exposing the first electrode 171, a light emitting layer 172 located in the opening of the pixel defining layer 180, a second electrode 173 located on the light emitting layer 172 and the pixel defining layer 180, and a passivation layer 190.

[0103] Each of the layers described above may be composed of a single layer, or may be composed of a laminated layer including a plurality of layers. Another layer may be further located between the layers.

[0104] The substrate 101 may support layers thereon. The substrate 101 may be formed of an insulating material. The substrate 101 may be formed of an inorganic material such as glass or quartz, or may be formed of an organic material such as polyimide. The substrate 101 may be a rigid substrate or a flexible substrate.

[0105] The buffer layer BF is located on the substrate 101. The buffer layer BF can prevent or reduce the diffusion of impurity ions, prevent or reduce the penetration of moisture, and serve as a surface planarization. The buffer layer BF may include silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0106] The semiconductor layer ACT is located on the buffer layer BF. The semiconductor layer ACT may form channels of a plurality of transistors of each sub-pixel R, G, and B. The semiconductor layer ACT may include polycrystalline silicon. The polycrystalline silicon may be formed by crystallizing amorphous silicon.

[0107] When the semiconductor layer ACT is formed of polysilicon and ions are doped into the semiconductor layer ACT, the semiconductor layer ACT doped with ions may have conductivity. Therefore, the semiconductor layer ACT may include not only the channel regions of the plurality of transistors but also the source region and the drain region. The source region and the drain region may be connected to both sides of each channel region.

[0108] In another embodiment, the semiconductor layer ACT may include single crystal silicon, low temperature polycrystalline silicon, amorphous silicon or an oxide semiconductor. The oxide semiconductor may include, for example, a binary compound (AB) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr) or magnesium (Mg). x ), ternary compounds (AB x C y ) and quaternary compounds (AB x C y D z In one embodiment, the semiconductor layer ACT may include an oxide including indium, tin, and zinc (ITZO) or an oxide including indium, gallium, and zinc (IGZO).

[0109] The first insulating layer IL1 is located on the semiconductor layer ACT. The first insulating layer IL1 may be arranged substantially over the entire surface of the substrate 101. The first insulating layer IL1 may be a gate insulating layer having a gate insulating function. The first insulating layer IL1 may include a silicon compound and a metal oxide, etc. For example, the first insulating layer IL1 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. The first insulating layer IL1 may be a single layer or a multilayer consisting of laminated layers formed of different materials.

[0110] The first gate conductive layer 110 is located on the first insulating layer IL1. The first gate conductive layer 110 may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu). The first gate conductive layer 110 may be a single layer or a multilayer. The first gate conductive layer 110 may include a gate electrode of a transistor and a first electrode of a storage capacitor.

[0111] The second insulating layer IL2 is located on the first gate conductive layer 110. The second insulating layer IL2 may be located substantially over the entire surface of the substrate 101. The second insulating layer IL2 is used to insulate the first gate conductive layer 110 from the second gate conductive layer 120.

[0112] The second insulating layer IL2 may be an interlayer insulating layer. The second insulating layer IL2 may include the same material as the first insulating layer IL1 described above, or may include at least one material selected from the materials listed as example constituent materials of the first insulating layer IL1.

[0113] The second gate conductive layer 120 is located on the second insulating layer IL2. The second gate conductive layer 120 may include a second electrode of a storage capacitor. The second gate conductive layer 120 may overlap the first gate conductive layer 110 and the second insulating layer IL2 is placed between the second gate conductive layer 120 and the first gate conductive layer 110 to form a storage capacitor. The second gate conductive layer 120 may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu). The second gate conductive layer 120 may be formed of the same material as the first gate conductive layer 110, but is not limited thereto. The second gate conductive layer 120 may be a single layer or a multilayer.

[0114] The third insulating layer IL3 covers the second gate conductive layer 120. The third insulating layer IL3 insulates the second gate conductive layer 120 and the first conductive layer 130. The third insulating layer IL3 may include the same material as the first insulating layer IL1 described above, or may include at least one material selected from the materials listed as example constituent materials of the first insulating layer IL1.

[0115] The first conductive layer 130 is located on the third insulating layer IL3. The first conductive layer 130 may include at least one metal selected from the group consisting of aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu). The first conductive layer 130 may be a single layer or a multilayer. For example, the first conductive layer 130 may be formed by a laminated structure such as Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo or Ti / Cu. The first conductive layer 130 may include the signal line DL and the source electrode SE described above. The source electrode SE may be connected to the source region of the semiconductor layer ACT through a contact hole formed via the third insulating layer IL3, the second insulating layer IL2 and the first insulating layer IL1.

[0116] The fourth insulating layer IL4 covers the first conductive layer 130. The fourth insulating layer IL4 may be a via layer. The fourth insulating layer IL4 may include an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0117] The second conductive layer 140 is located on the fourth insulating layer IL4. The second conductive layer 140 may include the same material as the first conductive layer 130 described above, or may include at least one material selected from the materials listed as example constituent materials of the first conductive layer 130. The second conductive layer 140 may include a first conductive pattern CP1 and the first connection wire DM1, the third connection wire DM3, and the first dummy wire DP1 described above. The first conductive pattern CP1 may be connected to the source electrode SE through a contact hole formed through the fourth insulating layer IL4.

[0118] The fifth insulating layer IL5 covers the second conductive layer 140. The fifth insulating layer IL5 may be a via layer. The fifth insulating layer IL5 may include the same material as the fourth insulating layer IL4 described above, or may include at least one material selected from the materials listed as example constituent materials of the fourth insulating layer IL4.

[0119] The third conductive layer 150 is located on the fifth insulating layer IL5. The third conductive layer 150 may include the same material as the first conductive layer 130 described above, or may include at least one material selected from the materials listed as example constituent materials of the first conductive layer 130. The third conductive layer 150 may include a second conductive pattern CP2 and the second connection line DM2 and the second dummy line DP2 described above. The second conductive pattern CP2 may be connected to the first conductive pattern CP1 by forming a contact hole through the fifth insulating layer IL5.

[0120] The sixth insulating layer IL6 covers the third conductive layer 150. The sixth insulating layer IL6 may be a via layer. The sixth insulating layer IL6 may include the same material as the fourth insulating layer IL4 described above, or may include at least one material selected from the materials listed as example constituent materials of the fourth insulating layer IL4.

[0121] The first electrode 171 is located on the sixth insulating layer IL6. Although not limited to the following, the first electrode 171 may have a laminated layer structure formed by forming a material layer having a high work function (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 )) and a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof are laminated to form. A layer with a higher work function may be located above the reflective material layer so as to be closer to the light emitting layer 172. The first electrode 171 may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag or ITO / Ag / ITO, but is not limited thereto. Anode electrodes ANO1, ANO2 and ANO3 of each sub-pixel R, G and B may be formed by the first electrode 171. The anode electrodes ANO1, ANO2 and ANO3 may be connected to the second conductive pattern CP2 through contact holes formed via the sixth insulating layer IL6.

[0122] The pixel defining layer 180 may be located on the first electrode 171. The pixel defining layer 180 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide, or an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or BCB. The pixel defining layer 180 may be a single layer or a multilayer consisting of laminated layers formed of different materials.

[0123] The pixel defining layer 180 may include an opening exposing the first electrode 171. The opening may define the light emitting region of each sub-pixel R, G, and B. The second conductive layer 140 and the third conductive layer 150 located below the light emitting region of each sub-pixel R, G, and B may be designed in an equivalent pattern. In other words, the position and width of the overlap between the light emitting region of each sub-pixel R, G, and B and the second conductive layer 140 may be substantially the same. In addition, the position and width of the overlap between the light emitting region of each sub-pixel R, G, and B and the third conductive layer 150 may be substantially the same. In this case, the step difference in the light emitting region of the plurality of sub-pixels R, G, and B may be minimized or reduced. Therefore, the color deviation of the plurality of sub-pixels R, G, and B may be improved. The second conductive layer 140 located below the light emitting region of each sub-pixel R, G, and B may be one of the first connection line DM1, the third connection line DM3, and the first dummy line DP1 described above. In addition, the third conductive layer 150 located below the light emitting region of each sub-pixel R, G, and B may be one of the second connection line DM2 and the second dummy line DP2 described above.

[0124] The light emitting layer 172 is located in the opening of the pixel defining layer 180. The light emitting layer 172 may include an organic light emitting layer, a hole injection / transport layer, and an electron injection / transport layer.

[0125] The second electrode 173 is located on the light emitting layer 172 and the pixel defining layer 180. The cathode electrode may be formed by the second electrode 173. The cathode electrode may be located over the entire display area DA. The second electrode 173 may include a material layer having a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). The second electrode 173 may further include a transparent metal oxide layer located on the material layer having a low work function.

[0126] The passivation layer 190 may be located on the second electrode 173. The passivation layer 190 may prevent or reduce the penetration of moisture or oxygen into the light emitting layer 172. The passivation layer 190 may include at least one inorganic layer and / or organic layer. The inorganic layer may include, for example, Al x O y 、TiO x 、ZrO x 、SiO x 、AlO x N y 、Al x N y 、SiO x N y 、Si x N y 、ZnOx and Ta x O y The organic layer may be formed by polymerizing at least one monomer selected from the group consisting of, for example, pentabromophenyl acrylate, [2-(9H-carbazole-9-yl)ethyl methacrylate, N-vinyl carbazole, bis(methacryloylthiophenyl) sulfide, and zirconium acrylate. The organic layer may be a planarization layer.

[0127] As described above, the second conductive layer 140 and the third conductive layer 150 located under the light emitting region of each sub-pixel R, G, and B can be designed in an equivalent pattern. Therefore, the step difference in the light emitting region of the plurality of sub-pixels R, G, and B can be minimized or reduced, and the color deviation of the plurality of sub-pixels R, G, and B can be improved.

[0128] Hereinafter, another embodiment will be described. Hereinafter, the same reference numerals will be referred to as the same components as those described above, and repeated descriptions will be omitted or simplified.

[0129] Fig.12 is an enlarged plan view of region B according to another embodiment. Fig.13 is along Fig.12 A cross-sectional view taken along line XIII-XIII'.

[0130] refer to Fig.12 and Fig.13 , this embodiment and Figures 1 to 11 The embodiment of the present invention is different in that it further includes a first power supply voltage line VDL.

[0131] The first power voltage lines VDL may transmit a driving voltage and may be located at one side of the signal line DL. The first power voltage lines VDL may extend in the first direction DR1 and may be sequentially arranged at certain intervals along the second direction DR2.

[0132] The first power supply voltage line VDL may be located on the same layer as the layer on which the signal line DL is located. In addition, the first power supply voltage line VDL may be located on a layer different from the layer on which the second dummy line DP2 is located, and may be insulated from the second dummy line DP2 by an insulating layer. Fig.13As shown in , the first power supply voltage line VDL may be formed by the first conductive layer 130, the second dummy line DP2 may be formed by the third conductive layer 150, and the first power supply voltage line VDL and the second dummy line DP2 may be insulated by the fourth insulating layer IL4 and the fifth insulating layer IL5. The second dummy line DP2 may be electrically connected to the first power supply voltage line VDL by forming a fourth contact hole CNT4 through the fourth insulating layer IL4 and the fifth insulating layer IL5 to partially expose the first power supply voltage line VDL. In this case, the resistance of the first power supply voltage line VDL may be minimized or reduced, so that the power supply voltage drop (IR drop) may be mitigated. Therefore, the brightness uniformity of the display device 1 may be improved.

[0133] Fig.14 is an enlarged plan view of region A according to still another embodiment. Fig.15 is along Fig.14 A cross-sectional view taken along line XV-XV'. Fig.16 is an enlarged plan view of region B according to still another embodiment. Fig.17 is along Fig.16 A cross-sectional view taken along line XVII-XVII'. Fig.18 is along Fig.16 A cross-sectional view taken along line XVIII-XVIII'.

[0134] refer to Figures 14 to 18 Considering the arrangement of the conductive layer constituting the connection line DM' and the dummy line DP', the present embodiment is different from Figures 1 to 11 The embodiments are different.

[0135] For example, the first connection line DM1′ may be located on a layer different from the layer on which the signal line DL is located, and may be insulated from the signal line DL by an insulating layer. Fig.15 As shown in , the signal line DL may be formed by the first conductive layer 130, the first connection line DM1' may be formed by the third conductive layer 150, and the signal line DL and the first connection line DM1' may be insulated by the fourth insulating layer IL4 and the fifth insulating layer IL5. One end of the first connection line DM1' may be electrically connected to the signal line DL through a fifth contact hole CNT5 formed through the fourth insulating layer IL4 and the fifth insulating layer IL5 to expose one end of the signal line DL. The intervals between the plurality of first connection lines DM1' may be substantially the same as the intervals between the signal lines DL.

[0136] at the same time, Fig.15 and Fig.17The first connection line DM1' is illustrated as overlapping the signal line DL in the thickness direction, but the embodiments according to the present disclosure are not limited thereto. In other words, when viewed from the top, the first connection line DM1' may be arranged so as not to overlap with the signal line DL. In this case, the first connection line DM1' may be located in a space where a plurality of signal lines DL are spaced apart from each other.

[0137] The second connection wire DM2' may be located on a layer different from the layer on which the first connection wire DM1' is located, and may be insulated from the first connection wire DM1' by an insulating layer. Fig.17 As shown in FIG, the first connection line DM1' may be formed by the third conductive layer 150, the second connection line DM2' may be formed by the second conductive layer 140, and the first connection line DM1' may be insulated from the second connection line DM2' by the fifth insulating layer IL5. The other end of the first connection line DM1' may be electrically connected to the second connection line DM2' through a sixth contact hole CNT6 formed through the fifth insulating layer IL5 to expose one end of the second connection line DM2'.

[0138] The third connection line DM3' may be located on a layer different from the layer on which the second connection line DM2' is located, and may be insulated from the second connection line DM2' by an insulating layer. In addition, the third connection line DM3' may be located on the same layer as the layer on which the first connection line DM1' is located. Fig.17 As shown in , the second connection line DM2' may be formed by the second conductive layer 140, the third connection line DM3' may be formed by the third conductive layer 150, and the second connection line DM2' may be insulated from the third connection line DM3' by the fifth insulating layer IL5. One end of the third connection line DM3' may be electrically connected to the second connection line DM2' through a seventh contact hole CNT7 formed through the fifth insulating layer IL5 to expose the other end of the second connection line DM2'.

[0139] at the same time, Fig.17 The third connection line DM3' is illustrated as overlapping the signal line DL in the thickness direction, but the embodiments according to the present disclosure are not limited thereto. In other words, when viewed from the top, the third connection line DM3' may be arranged so as not to overlap with the signal line DL. In this case, the third connection line DM3' may be located in a space where a plurality of signal lines DL are spaced apart from each other.

[0140] As described above, the display device 1 may include first to third connection lines DM1', DM2', and DM3' disposed via the display area DA, and provide image signals to the signal lines DL through the first to third connection lines DM1', DM2', and DM3'. Therefore, as described above, since an additional dead space required to connect the signal lines DL to the driving chip 20 may be unnecessary, the dead space may be minimized or reduced.

[0141] The first dummy line DP1' may be located on the same layer as the layer on which the first connection line DM1' and / or the third connection line DM3' are located. In addition, the first dummy line DP1' may be located on a layer different from the layer on which the second connection line DM2' is located. Fig.18 As shown in , the first dummy line DP1 ′ may be formed of the third conductive layer 150 .

[0142] at the same time, Fig.18 The first dummy line DP1' is illustrated as overlapping the signal line DL in the thickness direction, but the embodiments according to the present disclosure are not limited thereto. In other words, when viewed from the top, the first dummy line DP1' may be arranged so as not to overlap with the signal line DL. In this case, the first dummy line DP1' may be located in a space where a plurality of signal lines DL are spaced apart from each other.

[0143] The second dummy line DP2' may be located on a layer different from the layer on which the first dummy line DP1' is located. In addition, the second dummy line DP2' may be located on a layer different from the layer on which the first connection line DM1' and / or the third connection line DM3' are located. In addition, the second dummy line DP2' may be located on the same layer as the layer on which the second connection line DM2' is located. For example, Fig.18 As shown in , the second dummy line DP2 ′ may be formed of the second conductive layer 140 .

[0144] As described above, when the dummy lines DP1' and DP2' include a plurality of conductive layers, and when the first dummy line DP1' extends in the first direction DR1 and the second dummy line DP2' extends in the second direction, the dummy lines DP1' and DP2' may implement a mesh pattern shape together with the connection lines DM1', DM2', and DM3'. Therefore, as described above, different patterns are minimized or reduced, so that visual recognition of the patterns may be prevented or reduced.

[0145] Fig.19 is a perspective view of a display device according to still another embodiment. Fig. 20 yes Fig.19 An expanded view of the display device. Fig.21 It is shown Fig.19 An expanded diagram of the signal lines, connecting lines, and imaginary lines of a display device. Fig. 22 yes Fig.21 An enlarged plan view of area D. Fig.23 is along Fig. 22 A cross-sectional view taken along line XXIII-XXIII'.

[0146] refer to Figures 19 to 23 According to the display device 1_1 of this embodiment, Figures 1 to 11The embodiment of the present invention is different in that the main region MR of the display panel 10_1 includes a front display area DA0, side display areas DA1, DA2, DA3 and DA4, and corner areas C1, C2, C3 and C4.

[0147] The front display area DA0 and the side display areas DA1, DA2, DA3 and DA4 may be display areas DA configured to display images. The corner areas C1, C2, C3 and C4 are non-display areas NDA that do not display images and may provide spaces through which signal lines DL and connection lines DM pass.

[0148] The front display area DA0 may have a rectangular shape including two long sides extending in the first direction DR1 and two short sides extending in the second direction DR2. However, the embodiment of the present disclosure is not limited thereto, and the front display area DA0 may be formed in a polygonal shape having rounded corners at the intersection of the short sides and the long sides.

[0149] The side display areas DA1, DA2, DA3, and DA4 may include a first side display area DA1, a second side display area DA2, a third side display area DA3, and a fourth side display area DA4.

[0150] The first side display area DA1 may be an area extending in a direction opposite to the first direction DR1 at an edge of the front display area DA0, the second side display area DA2 may be an area extending in a direction opposite to the second direction DR2 at an edge of the front display area DA0, the third side display area DA3 may be an area extending in the first direction DR1 at an edge of the front display area DA0, and the fourth side display area DA4 may be an area extending in the second direction DR2 at an edge of the front display area DA0.

[0151] The first to fourth side display areas DA1, DA2, DA3 and DA4 may have substantially the same function or configuration as each other except for the position. Hereinafter, common features of the first to fourth side display areas DA1, DA2, DA3 and DA4 will be described based on the first side display area DA1, and repeated descriptions will be omitted.

[0152] The first side display area DA1 may extend outward from the edge of the front display area DA0 and bend at an angle (eg, a set angle or a predetermined angle). For example, the first side display area DA1 may be bent at an angle of 90° to 150° relative to the front display area DA0.

[0153] The first side display area DA1 may be connected to the bending area BR. Fig.19As shown in , when the first side display area DA1 is bent or curved vertically relative to the front display area DA0, the bending area BR is bent or curved vertically again relative to the first side display area DA1 (in other words, bent or curved at an angle of 180° relative to the front display area DA0), and thus the sub-area SR located at one side of the bending area BR may be located below the front display area DA0 in the thickness direction of the front display area DA0. The sub-area SR may overlap with the front display area DA0 and may be disposed parallel to the front display area DA0.

[0154] Corner areas C1, C2, C3 and C4 may be located between side display areas DA1, DA2, DA3 and DA4. Corner areas C1, C2, C3 and C4 may include first to fourth corner areas C1, C2, C3 and C4 located between first to fourth side display areas DA1, DA2, DA3 and DA4. The first to fourth corner areas C1, C2, C3 and C4 may be arranged to be adjacent to four corners where long sides and short sides intersect each other. The first to fourth corner areas C1, C2, C3 and C4 may have functions or configurations substantially the same as each other except for the positions. Hereinafter, the common features of the first to fourth corner areas C1, C2, C3 and C4 will be described based on the first corner area C1, and repeated descriptions will be omitted.

[0155] The first corner area C1 may be located between the first side display area DA1 and the second side display area DA2. One end of the first corner area C1 may contact the first side display area DA1, and the other end of the first corner area C1 may contact the second side display area DA2.

[0156] The first corner area C1 may extend from the front display area DA0 and may be rounded to have a curvature (e.g., a set curvature or a predetermined curvature). The curvature of the first corner area C1 relative to the front display area DA0 may be greater than the curvatures of the first side display area DA1 and the second side display area DA2 relative to the front display area DA0.

[0157] The first corner region C1 may provide a space in which the signal line DL may be connected to the connection line DM. Figure 21 to Figure 23 The signal lines DL and the connection lines DM are described in detail.

[0158] refer to Figure 21 to Figure 23, the display device 1_1 may include a plurality of signal lines DL, a plurality of connection lines DM, and a plurality of dummy lines DP. Meanwhile, the signal lines DL, the connection lines DM, and the dummy lines DP are configured to extend in the first direction DR1 or the second direction DR2, and may be symmetrical about a reference axis (not shown) formed through the center of the area of ​​the display device 1_1. Hereinafter, the description will focus on the signal lines DL, the connection lines DM, and the dummy lines DP located on the left side of the display device 1_1.

[0159] A plurality of signal lines DL may extend from the non-display area NDA and be located in the side display areas DA1, DA2, DA3, and DA4 and the front display area DA0. The signal lines DL may extend in the first direction DR1 and may be sequentially arranged at specific intervals along the second direction DR2. One end of the signal line DL may be electrically connected to the connection line DM, and the one end of the signal line DL connected to the connection line DM may be located in the non-display area NDA below the main area MR, for example, the first corner area C1. The one end of the signal line DL may be electrically connected to the connection line DM through the eighth contact hole CNT8 located in the first corner area C1. A detailed description thereof will be provided later.

[0160] A plurality of connection lines DM may extend from the non-display area NDA and extend to the non-display area NDA (e.g., the first corner area C1) via the first side display area DA1, the second side display area DA2, or the front display area DA0. Each of the connection lines DM may include first connection lines DM1 respectively connected to the signal lines DL, second connection lines DM2 respectively connected to the first connection lines DM1, and third connection lines DM3 respectively connected to the second connection lines DM2.

[0161] A plurality of first connection lines DM1 may extend from a non-display area NDA (e.g., a first corner area C1) and be located in a first side display area DA1, a second side display area DA2, or a front display area DA0. The first connection lines DM1 may extend in a first direction DR1 and may be sequentially arranged at specific intervals along a second direction DR2. One end of the first connection line DM1 may be located in the first corner area C1, and the other end of the first connection line DM1 may be located in the second side display area DA2, the first side display area DA1, or the front display area DA0. The one end of the first connection line DM1 may extend to an end of the signal line DL located in the first corner area C1. The one end of the first connection line DM1 may be electrically connected to the signal line DL in the first corner area C1. The first connection line DM1 may be located on a layer different from a layer on which the signal line DL is located and may be insulated from the signal line DL by an insulating layer. For example, as Fig.23As shown in FIG. 1 , the signal line DL may be formed of the first conductive layer 130, the first connection line DM1 may be formed of the second conductive layer 140, and the signal line DL may be insulated from the first connection line DM1 by the fourth insulating layer IL4. The one end of the first connection line DM1 may pass through the fourth insulating layer IL4 and be electrically connected to the signal line DL through the eighth contact hole CNT8 exposing one end of the signal line DL.

[0162] at the same time, Fig. 22 and Fig.23 The eighth contact hole CNT8 is shown to be located in the first corner region C1, but the embodiments of the present disclosure are not limited thereto. Fig.21 As shown in FIG. 8 , the eighth contact hole CNT8 may be located in the non-display area NDA disposed between the first side display area DA1 and the bending area BR.

[0163] In addition, since reference has been made Figures 1 to 11 The second connection line DM2 , the third connection line DM3 , the first dummy line DP1 , and the second dummy line DP2 are described, and thus a repeated description will be omitted.

[0164] As described above, the display device 1_1 may include first to third connection lines DM1, DM2, and DM3 disposed via the front display area DA0 and the side display areas DA1, DA2, DA3, and DA4, and provide image signals to the signal lines DL through the first to third connection lines DM1, DM2, and DM3. Therefore, an additional dead space required to connect the signal lines DL to the driving chip 20 may be unnecessary. In other words, as described above, the dead space may be minimized or reduced.

[0165] According to the display device of the embodiment, the connection line is located in the display area, so that the dead space of the display device can be reduced.

[0166] In addition, the connection lines and the dummy lines are formed of a plurality of conductive layers to minimize or reduce different patterns, so that visual recognition of the patterns can be prevented or reduced.

[0167] In addition, the lines located under the sub-pixels are uniformly designed so that the step difference in the light emitting area can be minimized or reduced. In other words, the degradation of the display quality of the display device can be prevented or reduced.

[0168] The effects according to the embodiments of the present disclosure are not limited by the contents of the description of the above exemplary embodiments, and various effects are included in the description herein.

[0169] In the concluding part of the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the exemplary embodiments without departing substantially from the principles of the present invention. Therefore, the exemplary embodiments of the present invention disclosed are only used in a general and descriptive sense and not for limiting purposes.

Claims

1. A display device, comprising: Display area and non-display area; a plurality of signal lines in the display area; a plurality of connection lines, in the display area and respectively connected to the plurality of signal lines; as well as a plurality of first dummy patterns and a plurality of second dummy patterns, wherein the plurality of connection lines include a plurality of first connection lines respectively connected to the plurality of signal lines, a plurality of third connection lines on the same layer as the plurality of first connection lines, and a plurality of second connection lines respectively connecting the plurality of first connection lines to the plurality of third connection lines, wherein the first connection line and the third connection line extend in a first direction, and the second connection line extends in a second direction intersecting the first direction, wherein the first dummy pattern extends in the first direction, and the second dummy pattern extends in the second direction, and The length of the first dummy pattern overlapping the second connection line is different from the length of the first dummy pattern not overlapping the second connection line.

2. The display device according to claim 1, wherein The first dummy pattern is on a same layer as the first connection line, and the second dummy pattern is on a same layer as the second connection line.

3. The display device according to claim 2, wherein An interval between the plurality of first dummy patterns in the second direction is equal to an interval between the plurality of first connection lines in the second direction.

4. The display device according to claim 2, wherein: The signal line is formed of a first conductive layer, the first connection line or the third connection line is formed of a second conductive layer, the second connection line is formed of a third conductive layer, and the second conductive layer is between the first conductive layer and the third conductive layer.

5. The display device according to claim 4, wherein: A second connection line among the plurality of second connection lines is electrically connected to the first connection line through a first contact hole exposing one end of a first connection line among the plurality of first connection lines, and The second connection line is electrically connected to the third connection line through a second contact hole exposing one end of the third connection line among the plurality of third connection lines.

6. The display device according to claim 4, wherein: The first dummy pattern is formed from the second conductive layer, and the second dummy pattern is formed from the third conductive layer.

7. The display device according to claim 4, further comprising: a power supply voltage line formed by the first conductive layer, wherein the power supply voltage line is electrically connected to a second dummy pattern among the plurality of second dummy patterns.

8. A display device, comprising: A substrate including a display area and a non-display area; a plurality of signal lines in the display area of ​​the substrate; a plurality of connection lines, in the display area and respectively connected to the plurality of signal lines; A first electrode, on the plurality of connecting lines; a light-emitting layer, on the first electrode; a second electrode, on the light-emitting layer; as well as a plurality of first dummy patterns and a plurality of second dummy patterns in the display area, wherein the plurality of connection lines include a plurality of first connection lines respectively connected to the plurality of signal lines and a plurality of second connection lines respectively connected to the plurality of first connection lines, and the first connection lines and the second connection lines are on different layers from each other, wherein the first connecting line extends in a first direction, and the second connecting line extends in a second direction intersecting the first direction, wherein the first dummy pattern extends in the first direction, and the second dummy pattern extends in the second direction, and The length of the first dummy pattern overlapping the second connection line is different from the length of the first dummy pattern not overlapping the second connection line.

9. The display device according to claim 8, wherein: The signal line is formed of a first conductive layer, the first connection line is formed of a second conductive layer, the second connection line is formed of a third conductive layer, and the second conductive layer is between the first conductive layer and the third conductive layer.

10. The display device according to claim 9, further comprising: a semiconductor layer on the substrate; as well as a first gate conductive layer, on the semiconductor layer, wherein the first gate conductive layer is between the semiconductor layer and the first conductive layer, and The first electrode is between the third conductive layer and the second electrode.

11. The display device according to claim 8, wherein: The connection lines further include a plurality of third connection lines respectively connected to the plurality of second connection lines, and the third connection lines extend in the first direction and are on the same layer as the first connection lines. 12 . The display device of claim 11 , wherein the first dummy pattern is on a same layer as the first connection line, and the second dummy pattern is on a same layer as the second connection line.

13. The display device according to claim 8, wherein: The display area includes a front display area, a first side display area extending from a first side of the front display area, and a second side display area extending from a second side of the front display area.

14. The display device according to claim 13, wherein: The plurality of connection lines extend from the non-display area and extend to the non-display area via the first side display area, the front display area, or the second side display area.

15. The display device according to claim 13, further comprising: In a corner area between the first side display area and the second side display area, A first connection line among the plurality of first connection lines is connected to a signal line among the plurality of signal lines through a contact hole in the corner region.

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