Amplifier

Abstract

An amplifier includes: a first input transistor connected to a first input, a first output, and a power supply or ground; a second input transistor connected to a second input, a second output, and the power supply or ground; a first replica transistor connected to the first input, a detection node, and the power supply or ground; a second replica transistor connected to the second input, the detection node, and the power supply or ground; and a bias transistor connected to a bias voltage, the detection node, and the power supply or ground.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2019 - 0092654, filed on Jul. 30, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to an amplifier. Background art

[0004] An amplifier is mounted on an electronic device to amplify voice signals, biological signals, etc. Depending on the application to which the amplifier is applied, the required noise level and bandwidth may vary. For example, amplifying a signal from a piezoelectric microphone array for voice recognition from a speaker requires a noise of 1 μV or less and a bandwidth of 20 kHz or more.

[0005] In the prior art, current - reuse amplifiers that can effectively reuse current have been used. However, since a current - reuse amplifier stacks multiple transistors to form an amplifier, a high power needs to be applied to the amplifier. As higher power is applied to the amplifier, the power consumption of the amplifier increases.

[0006] Therefore, it is necessary to study an amplifier that operates at low noise and low power. Summary of the invention

[0007] An amplifier is provided. Additional aspects will be set forth in part in the following description, and in part will become apparent from the following description, or may be learned by practice of the presented embodiments.

[0008] According to an aspect of the present disclosure, there is provided an amplifier including: a first input transistor having a first gate connected to a first input, a first connection line connected to a first output, and a second connection line connected to a power supply or ground; a second input transistor having a second gate connected to a second input, a third connection line connected to a second output, and a fourth connection line connected to a power supply or ground; a first copy transistor having a third gate connected to the first input, a fifth connection line connected to a detection node, and a sixth connection line connected to a power supply or ground; a second copy transistor having a fourth gate connected to the second input, a seventh connection line connected to the detection node, and an eighth connection line connected to a power supply or ground; and a bias transistor having a fifth gate connected to a bias voltage, a ninth connection line connected to the detection node, and a tenth connection line connected to a power supply or ground.

[0009] The first copy transistor may be configured to copy the configuration of the first input transistor, and the second copy transistor is configured to copy the configuration of the second input transistor.

[0010] The amplifier may further include: a bias control circuit connected to the detection node, the first input, and the second input, wherein the bias control circuit may be configured to adjust the input values of the first input and the second input based on the detection voltage of the detection node.

[0011] The bias control circuit may further be configured to feedback the input values of the first input and the second input such that the detection voltage of the detection node corresponds to a target voltage.

[0012] The amplifier may further include: an active load connected to the bias control circuit, wherein the detection voltage is corrected by changing the resistance value of the active load until the detection voltage of the detection node corresponds to the target voltage.

[0013] The resistance value of the active load may be determined based on the voltage applied to the active load from the bias control circuit.

[0014] The first input transistor may include n individual transistors, the second input transistor may include m individual transistors, the first copy transistor and the second copy transistor may include n and m individual transistors respectively, and n and m are natural numbers.

[0015] The amplifier may further include: an external input; a first capacitor connecting the external input to the first input; and a second capacitor connecting the external input to the second input; wherein the first input and the second input may be separated from the external input by the first capacitor and the second capacitor.

[0016] The amplifier may have a noise of 1 μV or less and a bandwidth of 20 kHz or more.

[0017] The first input and the second input may be inside the amplifier.

[0018] The first copy transistor and the first input transistor have the same channel width to channel length ratio, and the second copy transistor and the second input transistor have the same channel width to channel length ratio.

[0019] The first copy transistor may be configured to copy the current flowing through the first input transistor at a specific ratio, and the second copy transistor may be configured to copy the current flowing through the second input transistor at a specific ratio.

[0020] According to another aspect of the present disclosure, an amplifier is provided, including: a first input transistor having a first gate connected to a first input, a first drain connected to a first output, and a first source connected to a power supply; a second input transistor having a second gate connected to a second input, a second drain connected to a second output, and a second source connected to the power supply; a first copy transistor having a third gate connected to the first input, a third drain connected to a detection node, and a third source connected to the power supply; a second copy transistor having a fourth gate connected to the second input, a fourth drain connected to the detection node, and a fourth source connected to the power supply; and a bias transistor having a fifth gate connected to a bias voltage, a fifth drain connected to the detection node, and a fifth source connected to ground.

[0021] The first input and the second input may be inside the amplifier.

[0022] The first copy transistor and the first input transistor have the same channel width to channel length ratio, and the second copy transistor and the second input transistor have the same channel width to channel length ratio.

[0023] The first copy transistor may be configured to copy the current flowing through the first input transistor at a specific ratio, and the second copy transistor may be configured to copy the current flowing through the second input transistor at a specific ratio.

[0024] According to another aspect of the present disclosure, an amplifier is provided, including: a first input transistor having a first gate connected to a first input, a first drain connected to a first output, and a first source connected to ground; a second input transistor having a second gate connected to a second input, a second drain connected to a second output, and a second source connected to ground; a first copy transistor having a third gate connected to the first input, a third drain connected to a detection node, and a third source connected to ground; a second copy transistor having a fourth gate connected to the second input, a fourth drain connected to the detection node, and a fourth source connected to ground; and a bias transistor having a fifth gate connected to a bias voltage, a fifth source connected to the detection node, and a fifth drain connected to the power supply.

[0025] The first input and the second input may be inside the amplifier.

[0026] The first copy transistor and the first input transistor have the same channel width to channel length ratio, and the second copy transistor and the second input transistor have the same channel width to channel length ratio.

[0027] The first copy transistor can be configured to copy the current flowing through the first input transistor at a specific ratio, and the second copy transistor can be configured to copy the current flowing through the second input transistor at a specific ratio.

[0028] According to another aspect of the present disclosure, there is provided an amplification of an operational amplifier, including: obtaining a detection voltage or a detection current at a detection node of the amplifier; adjusting input values of a first internal input and a second internal input of the amplifier based on the obtained detection voltage or the obtained detection current; and feeding back the adjusted input values of the first internal input and the second internal input as input values of the amplifier such that the obtained detection voltage or detection current corresponds to a target voltage or a target current, wherein the detection voltage or detection current at the detection node is determined by drain currents of a first copy transistor and a second copy transistor of the amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings, in which:

[0030] Figure 1A and Figure 1B is a schematic diagram of an amplifier according to an exemplary embodiment;

[0031] Figure 2 is a schematic diagram of an amplifier including copy transistors according to an exemplary embodiment;

[0032] Figure 3 is a schematic diagram of an amplifier including copy transistors according to an exemplary embodiment;

[0033] Figure 4 is a schematic diagram of an amplifier including an active load according to an exemplary embodiment;

[0034] Figure 5 is a diagram showing an example of a circuit diagram of an amplifier including an amplifier and a bias control circuit according to an exemplary embodiment;

[0035] Figure 6 is a schematic diagram of an example of an amplifier connected to an external power supply according to an exemplary embodiment; and

[0036] Figure 7 is a flowchart of an operation of an amplifier according to an exemplary embodiment. DETAILED DESCRIPTION

[0037] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the example embodiments are described below only by referring to the drawings, to explain the various aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of... " modify the entire list of elements following the expression, rather than modifying individual elements in the list.

[0038] General and widely used terms have been employed herein, and these terms may vary according to the intention of those of ordinary skill in the art, precedent, or the emergence of new technologies. Additionally, in some cases, the present disclosure may arbitrarily select specific terms, in which case the present disclosure will provide the meaning of the terms in the description of the embodiments. Therefore, it should be understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted as having an ideal or overly formal meaning, unless expressly so defined herein.

[0039] Throughout the present disclosure, when a part "includes" an element, unless otherwise stated, it may also include another element without excluding the presence of the other element. In addition, terms such as "... unit", "... module" represent units for performing at least one function or operation, and these units may be implemented as hardware or software or a combination of hardware and software.

[0040] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings.

[0041] Figure 1A and Figure 1B are schematic diagrams of an amplifier according to an example embodiment.

[0042] Referring to Figure 1A , the basic amplifier 10a includes five transistors M 1a , M 1b , M 2a , M 2b and M 3 . In Figure 1A , the transistors M 1a , M 1b and M 3 are NMOS transistors, and the transistors M 2a and M 2b are PMOS transistors.

[0043] The transistor M 1a includes a gate connected to the input voltage V in , a connection to the transistor M3 the source of the drain, and connected to the output voltage V out the drain of transistor M 1a includes a gate connected to the voltage V ip the source of the drain of transistor M 3 and connected to the output voltage V out the drain of

[0044] Transistor M 2a includes a gate connected to the bias voltage V b2 the source connected to the voltage V DD and the drain connected to the output voltage V out the drain of transistor M 2a includes a gate connected to the bias voltage V b2 the source connected to the voltage V DD and the drain connected to the output voltage V out the drain of

[0045] Transistor M 3 is a bias transistor and includes a gate connected to the bias voltage V b1 the drain connected to M 1a and M 1b the source of the drain of, and the grounded source. The basic amplifier 10a is biased by the tail current flowing through transistor M 3

[0046] Figure 1B is a schematic diagram of a current reuse amplifier 10b, which includes six transistors M 1a 、M 1b 、M 2a 、M 2b 、M 3 and M 4 。The current reuse amplifier 10b reuses the current used by transistors M 2a and M 2b at transistors M 1a and M 1b 。

[0047] The gain that the current reuse amplifier 10b can obtain is approximately twice the gain of the basic amplifier 10a. This is because the basic amplifier 10a uses two transistors M 1a and M 1b as input transistors, while the current reuse amplifier 10b uses four transistors M 1a 、M 1b 、M 2a 、and M 2b as input transistors.

[0048] ​The current reuse amplifier 10b is a stack of more transistors while maintaining the basic structure of the amplifier. The current reuse amplifier 10b can effectively reuse current, but since many transistors are stacked to form the amplifier, a relatively high voltage V DD needs to be applied to the amplifier. The higher the voltage V DD used in the amplifier, the higher the power consumption.

[0049] Figure 2 is a schematic diagram of an amplifier including replica transistors according to an embodiment.

[0050] Refer to Figure 2 , the amplifier 200 includes internal inputs 201 and 202, input transistors 211 and 212, replica transistors 221 and 222, a bias transistor 230, outputs 241 and 242, and a power supply 250.

[0051] Figure 2 Each of the input transistors 211 and 212, replica transistors 221 and 222, and bias transistor 230 of

[0052] can include NMOS or PMOS transistors. According to another embodiment, those of ordinary skill in the art should understand that various combinations of NMOS or PMOS transistors forming the input transistors 211 and 212, replica transistors 221 and 222, and bias transistor 230 can be configured.

[0052] The first input transistor 211 can have a gate connected to the first internal input 201, a first connection line L1 connected to the first output 241, and a second connection line L2 connected to the power supply 250. According to an embodiment, the power supply 250 can be 2*V DS .

[0053] The second input transistor 212 can have a gate connected to the second internal input 202, a third connection line L3 connected to the second output 242, and a fourth connection line L4 connected to the power supply 250.

[0054] The first replica transistor 221 can have a gate connected to the first internal input 201, a fifth connection line L5 connected to the detection node 260, and a sixth connection line L6 connected to the power supply 250.

[0055] The second replica transistor 222 can have a gate connected to the second internal input 202, a seventh connection line L7 connected to the detection node 260, and an eighth connection line L8 connected to the power supply 250.

[0056] The bias transistor 230 may have a gate connected to a bias voltage 270, a ninth connection line L9 connected to a detection node 260, and a tenth connection line L10 connected to ground. According to an exemplary embodiment, a load may be connected to the first connection line L1, the third connection line L3, and the tenth connection line L10. According to another exemplary embodiment, the load may not be provided.

[0057] The circuit diagram of the amplifier 200 may vary depending on whether each of the first input transistor 211, the second input transistor 212, the first replica transistor 221, the second replica transistor 222, and the bias transistor 230 includes an NMOS transistor or a PMOS transistor as a MOSFET transistor.

[0058] Figure 2 An amplifier 200 is shown, in which the first input transistor 211, the second input transistor 212, the first replica transistor 221, and the second replica transistor 222 include PMOS transistors, and the bias transistor 230 includes an NMOS transistor. Hereinafter, the amplifier 200 will be described based on Figure 2 the type of each transistor shown in 1.

[0059] The first input transistor 211 may have a gate connected to a first internal input 201, a drain connected to a first output 241, and a source connected to a power supply 250.

[0060] The second input transistor 212 may have a gate connected to a second internal input 202, a drain connected to a second output 242, and a source connected to a power supply 250.

[0061] The first replica transistor 211 may have a gate connected to a first internal input 201, a drain connected to a detection node 260, and a source connected to a power supply 250.

[0062] The second replica transistor 222 may have a gate connected to a second internal input 202, a drain connected to a detection node 260, and a source connected to a power supply 250.

[0063] The bias transistor 230 may have a gate connected to a bias voltage 270, a drain connected to a detection node 260, and a grounded source.

[0064] The first copy transistor 221 is a transistor that replicates the configuration of the first input transistor 211. In an exemplary embodiment, the first copy transistor 221 may include a MOSFET transistor (NMOS or PMOS) of the same type as the first input transistor 211. Additionally, the first copy transistor 221 may have the same channel width to channel length ratio as the first input transistor 211. The first copy transistor 221 may replicate the current flowing through the first input transistor 211 at a specific ratio.

[0065] The second copy transistor 222 is a transistor that replicates the configuration of the second input transistor 212. In one embodiment, the second copy transistor 222 may include a MOSFET transistor (NMOS or PMOS) of the same type as the second input transistor 212. Additionally, the second copy transistor 222 may have the same channel width to channel length ratio as the second input transistor 212. The second copy transistor 222 may replicate the current flowing through the second input transistor 212 at a specific ratio.

[0066] The detection node 260 may be connected to the drain of the first copy transistor 221 and the drain of the second copy transistor 222. Additionally, the detection node 260 may be connected to the bias transistor 230.

[0067] That is, the detection voltage of the detection node 260 may be determined by the drain currents of the first copy transistor 221 and the second copy transistor 222. According to another embodiment, the detection current of the detection node 260 may be determined by the drain currents of the first copy transistor 221 and the second copy transistor 222. Additionally, the common component of the drain currents of the first copy transistor 221 and the second copy transistor 222 may be used as a bias.

[0068] The bias transistor 230 operates the amplifier 200 in a stable state and may determine the stability of the amplifier 200 through the bias transistor 230 based on the detection voltage of the detection node 260. For example, when the detection voltage of the detection node 260 corresponds to a target voltage, the amplifier 200 may operate in a stable state. According to another embodiment, the bias transistor 230 operates the amplifier 200 in a stable state and may determine the stability of the amplifier 200 through the bias transistor 230 based on the detection current of the detection node 260. For example, when the detection current of the detection node 260 corresponds to a target current, the amplifier 200 may operate in a stable state.

[0069] Meanwhile, the drain currents of the first replica transistor 221 and the second replica transistor 222 can be determined by a first internal input 201 connected to the gate of the first replica transistor 221 and a second internal input 202 connected to the gate of the second replica transistor 222, respectively. That is, since the detection voltage of the detection node 260 is determined by the drain currents of the first replica transistor 221 and the second replica transistor 222, the detection voltage of the detection node 260 can be changed by adjusting the input values of the first internal input 201 and the second internal input 202. That is, since the detection current of the detection node 260 is determined by the drain currents of the first replica transistor 221 and the second replica transistor 222, the detection current of the detection node 260 can be changed by adjusting the input values of the first internal input 201 and the second internal input 202.

[0070] As described above, since the amplifier 200 operates in a stable state when the detection voltage of the detection node 260 corresponds to the target voltage, the input values of the first internal input 201 and the second internal input 202 need to be adjusted when the detection voltage of the detection node 260 is different from the target voltage. As described above, since the amplifier 200 operates in a stable state when the detection current of the detection node 260 corresponds to the target current, the input values of the first internal input 201 and the second internal input 202 need to be adjusted when the detection current of the detection node 260 is different from the target current.

[0071] The detection node 260 can be connected to a bias control circuit. In addition, the bias control circuit can be connected to the first internal input 201 and the second internal input 202.

[0072] The bias control circuit can adjust the input values of the first internal input 201 and the second internal input 202 based on the detection voltage of the detection node 260. In an embodiment, the bias control circuit can feedback the input values of the first internal input 201 and the second internal input 202 such that the detection voltage of the detection node 260 corresponds to the target voltage. According to another embodiment, the bias control circuit can adjust the input values of the first internal input 201 and the second internal input 202 based on the detection current of the detection node 260. In an embodiment, the bias control circuit can feedback the input values of the first internal input 201 and the second internal input 202 such that the detection current of the detection node 260 corresponds to the target current.

[0073] For example, when the target voltage of the detection node 260 is 0.5V and the detection voltage is 0.3V, the bias control circuit can reduce the input values of the first internal input 201 and the second internal input 202.

[0074] Figure 2The amplifier 200 includes a first input transistor 211, a second input transistor 212, a first replica transistor 221, and a second replica transistor 222. However, in another embodiment, each of the first input transistor 211, the second input transistor 212, the first replica transistor 221, and the second replica transistor 222 may include a plurality of individual transistors.

[0075] For example, when the first input transistor 211 includes n individual transistors (n is a natural number) and the second input transistor 212 includes m individual transistors (m is a natural number), the first replica transistor 221 and the second replica transistor 222 may include n and m individual transistors, respectively.

[0076] Figure 3 is a schematic diagram of an amplifier including replica transistors according to an exemplary embodiment.

[0077] Figure 3 An amplifier 300 is shown, where the first input transistor 311, the second input transistor 312, the first replica transistor 321, and the second replica transistor 322 include NMOS transistors, and the bias transistor 330 includes a PMOS transistor. Hereinafter, the amplifier 300 will be described based on Figure 3 the type of each transistor shown in.

[0078] The first input transistor 311 may have a gate connected to the first internal input 301, a drain connected to the first output 341, and a source grounded.

[0079] The second input transistor 312 may have a gate connected to the second internal input 302, a drain connected to the second output 342, and a source grounded.

[0080] The first replica transistor 211 may have a gate connected to the first internal input 301, a drain connected to the detection node 360, and a source grounded.

[0081] The second replica transistor 322 may have a gate connected to the second internal input 302, a drain connected to the detection node 360, and a source grounded.

[0082] The bias transistor 330 may have a gate connected to the bias voltage 370, a drain connected to the detection node 360, and a drain connected to the power supply 350. According to an exemplary embodiment, this drain is connected to the power supply through a load. According to another exemplary embodiment, the load may not be provided.

[0083] The first copy transistor 321 is a transistor that replicates the configuration of the first input transistor 311. In one embodiment, the first copy transistor 321 may include a MOSFET transistor (NMOS or PMOS) of the same type as the first input transistor 311. Additionally, the first copy transistor 321 may have the same channel width-to-channel length ratio as the first input transistor 311. The first copy transistor 321 may replicate the current flowing through the first input transistor 311 at a specific ratio.

[0084] The second copy transistor 322 is a transistor that replicates the configuration of the second input transistor 312. In one embodiment, the second copy transistor 322 may include a MOSFET transistor (NMOS or PMOS) of the same type as the second input transistor 312. Additionally, the second copy transistor 322 may have the same channel width-to-channel length ratio as the second input transistor 312. The second copy transistor 322 may replicate the current flowing through the second input transistor 312 at a specific ratio.

[0085] The detection node 360 may be connected to the drain of the first copy transistor 321 and the drain of the second copy transistor 322. Additionally, the detection node 360 may be connected to the bias transistor 330.

[0086] That is, the detection voltage of the detection node 360 may be determined by the drain currents of the first copy transistor 321 and the second copy transistor 322. According to another exemplary embodiment, the detection current of the detection node 360 may be determined by the drain currents of the first copy transistor 321 and the second copy transistor 322. Additionally, the common component of the drain currents of the first copy transistor 321 and the second copy transistor 322 may be used as a bias.

[0087] The bias transistor 330 operates the amplifier 300 in a stable state and may determine the stability of the amplifier 300 through the bias transistor 330 based on the detection voltage of the detection node 360. For example, when the detection voltage of the detection node 360 corresponds to a target voltage, the amplifier 300 may operate in a stable state. According to another exemplary embodiment, the bias transistor 330 operates the amplifier 300 in a stable state and may determine the stability of the amplifier 300 through the bias transistor 330 based on the detection current of the detection node 360. For example, when the detection current of the detection node 360 corresponds to a target current, the amplifier 300 may operate in a stable state.

[0088] Meanwhile, the drain currents of the first replica transistor 321 and the second replica transistor 322 can be determined by a first internal input 301 connected to the gate of the first replica transistor 321 and a second internal input 302 connected to the gate of the second replica transistor 322, respectively. That is, since the detection voltage of the detection node 360 is determined by the drain currents of the first replica transistor 321 and the second replica transistor 322, the detection voltage of the detection node 360 can be changed by adjusting the input values of the first internal input 301 and the second internal input 302. According to another exemplary embodiment, that is, since the detection current of the detection node 360 is determined by the drain currents of the first replica transistor 321 and the second replica transistor 322, the detection current of the detection node 360 can be changed by adjusting the input values of the first internal input 301 and the second internal input 302.

[0089] The detection node 360 can be connected to a bias control circuit. In addition, the bias control circuit can be connected to the first internal input 301 and the second internal input 302.

[0090] The bias control circuit can adjust the input values of the first internal input 301 and the second internal input 302 based on the detection voltage (or detection current) of the detection node 360. In an exemplary embodiment, the bias control circuit can feedback the input values of the first internal input 301 and the second internal input 302 such that the detection voltage of the detection node 360 corresponds to a target voltage. According to another exemplary embodiment, the bias control circuit can feedback the input values of the first internal input 301 and the second internal input 302 such that the detection current of the detection node 360 corresponds to a target current.

[0091] For example, when the target voltage of the detection node 360 is 0.5V and the detection voltage is 0.3V, the bias control circuit can reduce the input values of the first internal input 301 and the second internal input 302.

[0092] Figure 4 is a schematic diagram of an amplifier including an active load according to an exemplary embodiment.

[0093] Figure 4 An amplifier 400 is shown, where the first input transistor 211, the second input transistor 212, the first replica transistor 221, and the second replica transistor 222 include PMOS transistors, and the bias transistor 230 includes an NMOS transistor.

[0094] The first input transistor 211 can have a gate connected to the first internal input 201, a drain connected to the first output 241, and a source connected to the power supply 250.

[0095] The second input transistor 212 may have a gate connected to the second internal input 202, a drain connected to the second output 242, and a source connected to the power supply 250.

[0096] The first copy transistor 211 may have a gate connected to the first internal input 201, a drain connected to the first output 260, and a source connected to the power supply 250.

[0097] The second copy transistor 222 may have a gate connected to the second internal input 202, a drain connected to the detection node 260, and a source connected to the power supply 250.

[0098] The bias transistor 230 may have a gate connected to the bias voltage 270, a drain connected to the detection node 260, and a source grounded.

[0099] The detection node 260 may be connected to the bias control circuit. In addition, the bias control circuit may be connected to the first internal input 201 and the second internal input 202.

[0100] The bias control circuit may adjust the input values of the first internal input 201 and the second internal input 202 based on the detected voltage (or detected current) of the detection node 260. In an embodiment, the bias control circuit may feedback the input values of the first internal input 201 and the second internal input 202 such that the detected voltage (or detected current) of the detection node 260 corresponds to a target voltage (or target current).

[0101] For example, when the target voltage of the detection node 260 is 0.5V and the detected voltage is 0.3V, the bias control circuit may reduce the input values of the first internal input 201 and the second internal input 202.

[0102] In an example embodiment, the amplifier 400 may include an active load 410. The resistance value of the active load 410 may be changed by the current applied to the active load 410. According to another example embodiment, the resistance value of the active load 410 may be changed by the voltage applied to the active load 410.

[0103] The active load 410 may be connected to the bias control circuit through a central connection line 420. The resistance value of the active load 410 may be determined based on the voltage (or current) applied from the bias control circuit to the active load 410. According to another example embodiment, the resistance value of the active load 410 may be determined based on the current applied from the bias control circuit to the active load 410.

[0104] More specifically, the transistor 411 of the active load 410 can be connected to the bias control circuit through a central connection line 420. The transistor 411 can have a gate connected to a bias voltage, a drain connected to the bias control circuit, and a source grounded. In Figure 4 , the transistor 411 includes an NMOS transistor, but it can also include a PMOS transistor.

[0105] As described above in Figure 2 , since the amplifier 400 operates in a steady state when the detection voltage of the detection node 260 corresponds to the target voltage, the bias control circuit can adjust the input values of the first internal input 201 and the second internal input 202 such that the detection voltage of the detection node 260 corresponds to the target voltage. According to another embodiment, since the amplifier 400 operates in a steady state when the detection current of the detection node 260 corresponds to the target current, the bias control circuit can adjust the input values of the first internal input 201 and the second internal input 202 such that the detection current of the detection node 260 corresponds to the target current.

[0106] In addition, when the active load 410 is included in the amplifier 400, the bias control circuit adjusts the input values of the first internal input 201 and the second internal input 202 and changes the resistance value of the active load 410 such that the voltages from the outputs 241 and 242 can be corrected.

[0107] That is, since the active load 410 is included in the amplifier 400, in order to make the detection voltage of the detection node 260 correspond to the target voltage, even if the input values of the first internal input 201 and the second internal input 202 are fed back, a voltage close to the desired voltage can be output from the outputs 241 and 242. According to another embodiment, since the active load 410 is included in the amplifier 400, in order to make the detection current of the detection node 260 correspond to the target current, even if the input values of the first internal input 201 and the second internal input 202 are fed back, a voltage close to the desired voltage can be output from the outputs 241 and 242.

[0108] The circuit configuration of the active load 410 is not limited to the circuit configuration shown in Figure 4 . Those of ordinary skill in the art should understand that any structure (i.e., a structure in which gain occurs) can be used as the active load 410 as long as the resistance value can be changed according to the applied voltage (or current).

[0109] Figure 5 is a diagram showing an example of a circuit diagram including an amplifier and a bias control circuit according to an exemplary embodiment.

[0110] Refer to Figure 5, Circuit diagram 510 includes amplifier 520 and bias control circuit 530. According to an embodiment, bias control circuit 530 may refer to the circuit in circuit diagram 510 other than amplifier 520.

[0111] Amplifier 520 may include an internal input V in , two input transistors, two replica transistors, and one bias transistor. The number of transistors included in amplifier 520 is not limited to the above example. In another embodiment, the input transistors and replica transistors may include three or more individual transistors.

[0112] In Figure 5 , the input transistors (TR INPUT) and replica transistors (REPLICA TR) include PMOS transistors, and the bias transistor (BIAS TR) and the transistors of the active load include NMOS transistors. However, those of ordinary skill in the art should understand that various combinations of NMOS transistors or PMOS transistors forming each transistor can be configured according to variations of the embodiments.

[0113] The replica transistor is a transistor that replicates the configuration of the input transistor. In an embodiment, the replica transistor may include the same type of MOSFET transistor (NMOS or PMOS) as the input transistor. Additionally, the replica transistor may have the same "channel width to channel length ratio" as the input transistor. The replica transistor can replicate the current flowing through the input transistor at a specific ratio.

[0114] The detection node 521 of amplifier 520 may be connected to the drains of the replica transistor and bias control circuit 530.

[0115] Bias control circuit 530 may adjust the input value of the internal input based on the detected voltage of detection node 521. In an embodiment, bias control circuit 530 may feedback the input value of the internal input such that the detected voltage of detection node 521 corresponds to a target voltage. According to another exemplary embodiment, bias control circuit 530 may adjust the input value of the internal input based on the detected current of detection node 521. In an embodiment, bias control circuit 530 may feedback the input value of the internal input such that the detected current of detection node 521 corresponds to a target current.

[0116] The amplifier according to the present disclosure can generate a lower level of noise and provide sufficient bandwidth by using replica transistors and bias transistors instead of using a tail current. For example, the amplifier according to the present disclosure can generate noise of 1 μV or less and can have a bandwidth of 20 kHz or greater.

[0117] Additionally, since the amplifier does not have such as Figure 1Ba stacked structure of multiple transistors as in the current-reuse amplifier shown, so that the amplifier can reduce the voltage of the power supply applied to the amplifier. Thus, the power consumption of the amplifier can be reduced. In addition, the amplifier according to the present disclosure generates a lower level of signal distortion.

[0118] In addition, the amplifier 520 may further include an active load. When an active load is included in the amplifier 520, in addition to adjusting the input value of the internal input, the bias control circuit may also correct the voltage output from the output terminal by changing the resistance value of the active load.

[0119] That is, since an active load is included in the amplifier 520, in order to make the detection voltage of the detection node 521 correspond to the target voltage, even if the input value of the internal input is fed back, a voltage close to the desired voltage can be output from the output terminal. According to another exemplary embodiment, since an active load is included in the amplifier 520, in order to make the detection current of the detection node 521 correspond to the target current, even if the input value of the internal input is fed back, a voltage close to the desired voltage can be output from the output terminal.

[0120] Figure 6 is a schematic diagram of an example of an amplifier connected to an external power supply according to an exemplary embodiment.

[0121] Reference Figure 6 , the amplifier 600 has a first internal input 611 and a second internal input 612. The amplifier 600 also has a first external input 621 and a second external input 622. The first internal input 611 and the first external input 621 may be connected to each other through a first capacitor 631, and the second internal input 612 and the second external input 622 may be connected to each other through a second capacitor 632.

[0122] Due to the first capacitor 631 and the second capacitor 632, the internal inputs 611 and 612 can be independent of the external inputs 621 and 622.

[0123] As described above in Figure 2 , since the amplifier 600 operates in a stable state when the detection voltage (or detection current) of the detection node corresponds to the target voltage (or target current), the bias control circuit can adjust the input values of the internal inputs 611 and 612 so that the detection voltage (or detection current) of the detection node corresponds to the target voltage (or target current).

[0124] Since it is difficult to directly control the external inputs 621 and 622, according to the exemplary embodiments of the present disclosure, the internal inputs 611 and 612 can be separated from the external inputs 621 and 622 by providing capacitors 631 and 632 between the external inputs 621 and 622 and the internal inputs 611 and 612.

[0125] Figure 7 is a flowchart of the operation of an amplifier according to an embodiment.

[0126] Since the information about Figure 7 the operation of the amplifier shown in is related to the embodiment described in the above figures, the description in the above figures can be applied to Figure 7 the method of.

[0127] The amplifier may include a first input transistor, a second input transistor, a first replica transistor, a second replica transistor, and a bias transistor.

[0128] The first input transistor may have a gate connected to a first internal input, a first connection line connected to a first output, and a second connection line connected to a power supply or ground. The second input transistor may have a gate connected to a second internal input, a first connection line connected to a second output, and a second connection line connected to a power supply or ground. The first replica transistor may have a gate connected to a first internal input, a first connection line connected to a detection node, and a second connection line connected to a power supply or ground. The second replica transistor may have a gate connected to a second internal input, a first connection line connected to a detection node, and a second connection line connected to a power supply or ground. The bias transistor may have a gate connected to a bias voltage, a first connection line connected to a detection node, and a second connection line connected to a power supply or ground.

[0129] The circuit diagram of amplifier 2 may vary depending on whether each of the first input transistor, the second input transistor, the first replica transistor, the second replica transistor, and the bias transistor includes a MOSFET transistor of an NMOS transistor or a PMOS transistor.

[0130] Hereinafter, it is assumed that the first input transistor, the second input transistor, the first replica transistor, and the second replica transistor include PMOS transistors, and the bias transistor includes an NMOS transistor.

[0131] The amplifier may include a bias control circuit. The bias control circuit may be connected to the detection node. In addition, the bias control circuit may be connected to the first internal input and the second internal input.

[0132] Referring to Figure 7 , in operation 710, the bias control circuit may obtain the detection voltage of the detection node. According to another embodiment, the bias control circuit may obtain the detection current of the detection node.

[0133] The detection node may be connected to the drain of the first replica transistor and the drain of the second replica transistor. Additionally, the detection node may be connected to the bias transistor.

[0134] That is, the sense voltage of the sense node can be determined by the drain currents of the first replica transistor and the second replica transistor. According to another embodiment, the sense current of the sense node can be determined by the drain currents of the first replica transistor and the second replica transistor. Additionally, a common component of the drains of the first replica transistor and the second replica transistor can be used as a bias.

[0135] In operation 720, the bias control circuit can adjust the input values of the first internal input and the second internal input based on the obtained sense current. According to another embodiment, the bias control circuit can adjust the input values of the first internal input and the second internal input based on the obtained sense voltage.

[0136] The drain currents of the first replica transistor and the second replica transistor can be determined by the first internal input connected to the gate of the first replica transistor and the second internal input connected to the gate of the second replica transistor, respectively.

[0137] That is, since the sense voltage of the sense node is determined by the drain currents of the first replica transistor and the second replica transistor, the sense voltage of the sense node can be changed by adjusting the input values of the first internal input and the second internal input based on the obtained sense voltage. According to another embodiment, since the sense current of the sense node is determined by the drain currents of the first replica transistor and the second replica transistor, the sense current of the sense node can be changed by adjusting the input values of the first internal input and the second internal input based on the obtained sense current.

[0138] In operation 730, the bias control circuit can feedback the input values of the first internal input and the second internal input such that the obtained sense voltage or sense current corresponds to a target voltage or a target current.

[0139] For example, when the target voltage of the sense node is 0.5V and the sense voltage is 0.3V, the bias control circuit can feedback the input values of the first internal input and the second internal input until the sense voltage of the sense node is 0.5V.

[0140] The amplifier according to the present disclosure can be used in low-power, high-resolution, and low-noise sensor applications. For example, the amplifier according to the present disclosure can be used to amplify a voice signal output from a piezoelectric microphone.

[0141] Additionally, the amplifier according to the present disclosure can be used in high-resolution sensing multi-channel applications. For example, the amplifier according to the present disclosure can be used in small biomedical devices or implantable devices.

[0142] In addition, the amplifier according to the present disclosure can be mounted on wearable devices, mobile phones, Internet of Things (IoT) devices, etc., and can help reduce power consumption.

[0143] The amplifier according to the present disclosure can generate a lower level of noise and provide sufficient bandwidth by using replica transistors and bias transistors instead of using a tail current.

[0144] In addition, the amplifier according to the present disclosure can operate at a low-level power supply, thereby reducing power consumption.

[0145] It should be understood that the example embodiments described herein should be considered only illustrative and not for purposes of limitation. The description of features or aspects in each embodiment should generally be regarded as available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art should understand that various changes in form and detail may be made without departing from the spirit and scope defined by the appended claims.

Claims

1. An amplifier, comprising: A first input transistor having a first gate connected to a first input, a first connection line connected to a first output, and a second connection line connected to a power supply or ground; A second input transistor having a second gate connected to a second input, a third connection line connected to a second output, and a fourth connection line connected to the power supply or ground; A first copy transistor having a third gate connected to the first input, a fifth connection line connected to a detection node, and a sixth connection line connected to the power supply or ground; A second copy transistor having a fourth gate connected to the second input, a seventh connection line connected to the detection node, and an eighth connection line connected to the power supply or ground; and A bias transistor having a fifth gate connected to a bias voltage, a ninth connection line connected to the detection node, and a tenth connection line connected to the power supply or ground.

2. The amplifier according to claim 1, wherein the first copy transistor is configured to copy the configuration of the first input transistor, and the second copy transistor is configured to copy the configuration of the second input transistor.

3. The amplifier according to claim 1, further comprising: A bias control circuit connected to the detection node, the first input, and the second input, wherein the bias control circuit is configured to adjust the input values of the first input and the second input based on the detection voltage of the detection node.

4. The amplifier according to claim 3, wherein the bias control circuit is further configured to feedback the input values of the first input and the second input such that the detection voltage of the detection node corresponds to a target voltage.

5. The amplifier according to claim 4, further comprising: An active load connected to the bias control circuit, wherein the detection voltage is corrected by changing the resistance value of the active load until the detection voltage of the detection node corresponds to the target voltage.

6. The amplifier according to claim 5, wherein the resistance value of the active load is determined based on the voltage applied from the bias control circuit to the active load.

7. The amplifier according to claim 1, wherein the first input transistor includes n individual transistors, the second input transistor includes m individual transistors, the first copy transistor and the second copy transistor respectively include n and m individual transistors, and n and m are natural numbers.

8. The amplifier according to claim 1, further comprising: An external input; A first capacitor connecting the external input to the first input; and A second capacitor connecting the external input to the second input, wherein the first input and the second input are separated from the external input by the first capacitor and the second capacitor.

9. The amplifier according to claim 1, wherein the amplifier has a noise of 1 μV or less and a bandwidth of 20 kHz or more.

10. The amplifier according to claim 1, wherein the first input and the second input are inside the amplifier.

11. The amplifier according to claim 1, wherein the first replica transistor and the first input transistor have the same channel width-to-channel length ratio, and the second replica transistor and the second input transistor have the same channel width-to-channel length ratio.

12. The amplifier according to claim 1, wherein the first replica transistor is configured to replicate the current flowing through the first input transistor at a specific ratio, and the second replica transistor is configured to replicate the current flowing through the second input transistor at a specific ratio.

13. An amplifier, comprising: a first input transistor having a first gate connected to a first input, a first drain connected to a first output, and a first source connected to a power supply; a second input transistor having a second gate connected to a second input, a second drain connected to a second output, and a second source connected to the power supply; a first replica transistor having a third gate connected to the first input, a third drain connected to a detection node, and a third source connected to the power supply; a second replica transistor having a fourth gate connected to the second input, a fourth drain connected to the detection node, and a fourth source connected to the power supply; and a bias transistor having a fifth gate connected to a bias voltage, a fifth drain connected to the detection node, and a fifth source connected to ground.

14. The amplifier according to claim 13, wherein the first input and the second input are inside the amplifier.

15. The amplifier according to claim 13, wherein the first replica transistor and the first input transistor have the same channel width-to-channel length ratio, and the second replica transistor and the second input transistor have the same channel width-to-channel length ratio.

16. The amplifier according to claim 13, wherein the first replica transistor is configured to replicate the current flowing through the first input transistor at a specific ratio, and the second replica transistor is configured to replicate the current flowing through the second input transistor at a specific ratio.

17. An amplifier, comprising: a first input transistor having a first gate connected to a first input, a first drain connected to a first output, and a first source connected to ground; a second input transistor having a second gate connected to a second input, a second drain connected to a second output, and a second source connected to ground; a first replica transistor having a third gate connected to the first input, a third drain connected to a detection node, and a third source connected to ground; a second replica transistor having a fourth gate connected to the second input, a fourth drain connected to the detection node, and a fourth source connected to ground; and a bias transistor having a fifth gate connected to a bias voltage, a fifth source connected to the detection node, and a fifth drain connected to a power supply.

18. The amplifier according to claim 17, wherein the first input and the second input are inside the amplifier.

19. The amplifier according to claim 17, wherein the first replica transistor and the first input transistor have the same channel width to channel length ratio, and the second replica transistor and the second input transistor have the same channel width to channel length ratio.

20. The amplifier according to claim 17, wherein the first replica transistor is configured to replicate the current flowing through the first input transistor at a specific ratio, and the second replica transistor is configured to replicate the current flowing through the second input transistor at a specific ratio.

21. A method of operating an amplifier according to any one of claims 1 to 20, comprising: obtaining a detection voltage or a detection current at a detection node of the amplifier; adjusting input values of a first internal input and a second internal input of the amplifier based on the obtained detection current or the obtained detection voltage; and feeding back the adjusted input values of the first internal input and the second internal input as input values of the amplifier such that the obtained detection voltage or detection current corresponds to a target voltage or a target current, wherein the detection voltage or detection current at the detection node is determined by drain currents of a first replica transistor and a second replica transistor of the amplifier.

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