Display device including a scan driver

Abstract

The inventive concept relates to a display device, the display device including: a substrate including a display area for displaying an image and a non-display area surrounding the display area; a plurality of pixels disposed in the display area and each including an organic light emitting diode and a pixel circuit portion configured to operate the organic light emitting diode; and a scan driver disposed in the non-display area and including a plurality of stages configured to output scan signals to the plurality of pixels. The plurality of stages may be arranged in n columns, the height of one stage may correspond to the height of n pixels, and n may be an integer of 2 or greater.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0101156, filed with the Korean Intellectual Property Office on August 19, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the inventive concept relate to a display device, and more particularly, to a display device including a scan driver. Background Art

[0004] An organic light emitting diode display device is a device for displaying an image. Different from a liquid crystal display device, since an organic light emitting diode display device has a self-emission characteristic and does not require an additional light source, it is possible to reduce its thickness and weight. In addition, the organic light emitting diode display device has high-quality characteristics such as low power consumption, high brightness, and high response speed.

[0005] Generally, an organic light emitting diode display device includes a substrate, a plurality of thin film transistors disposed on the substrate, a plurality of insulating layers disposed between lines for configuring the thin film transistors, and an organic light emitting diode (OLED) connected to the thin film transistors. Specifically, additional thin film transistors are used to allow the OLED to operate to emit light.

[0006] As the demand for high-resolution display devices increases, the area occupied by pixels including a plurality of thin film transistors and OLEDs decreases. Summary of the Invention

[0007] According to an exemplary embodiment of the inventive concept, a display device includes: a substrate including a display area for displaying an image and a non-display area surrounding the display area; a plurality of pixels disposed in the display area, each including an organic light emitting diode and a pixel circuit portion configured to operate the organic light emitting diode; and a scan driver disposed in the non-display area and including a plurality of stages configured to output scan signals to the plurality of pixels. The plurality of stages may be arranged in n columns, the height of one stage may correspond to the height of n pixels, and n may be an integer of 2 or greater.

[0008] The substrate may further include lines disposed in the non-display area and configured to apply control signals including a clock signal, and lines configured to apply voltages used in the scan driver, and one of the lines configured to apply the control signals including the clock signal or one of the lines configured to apply the voltages used in the scan driver may intersect at least one of the plurality of stages.

[0009] The line configured to apply the control signal including the clock signal may include four clock lines and a global clock signal line, and the line configured to apply the voltage used in the scan driver may include a low voltage line.

[0010] The global clock signal line or the low voltage line may intersect at least one of the plurality of stages.

[0011] The four clock lines, the global clock signal line, and the low voltage line may be formed in each of the plurality of stages.

[0012] The four clock lines may be arranged to be farthest from the display area at the outer edge of the non-display area or between adjacent columns of the n columns.

[0013] The display device may further include a signal controller configured to supply a clock signal, a global clock signal, and a low voltage to the four clock lines, the global clock signal line, and the low voltage line, respectively.

[0014] The display device may further include: a test line configured to test the display device and disposed on the substrate, and a driving low voltage line configured to apply a driving low voltage to the plurality of pixels. The test line and the driving low voltage line may be arranged to be farther from the display area than the four clock lines.

[0015] Each of the plurality of stages may include three clock input terminals, a global clock signal input terminal, a low voltage input terminal, a start signal input terminal, and an output terminal.

[0016] Each of the plurality of stages may be connected to three of the four clock lines. The first stage in the first column of the first row may be connected to the first clock line, the second clock line, and the third clock line. The second stage in the second column of the first row may be connected to the second clock line, the third clock line, and the fourth clock line. The third stage in the third column of the first row may be connected to the third clock line, the fourth clock line, and the first clock line. The fourth stage in the first column of the second row may be connected to the fourth clock line, the first clock line, and the second clock line.

[0017] Each of the plurality of stages may further include: two buffer transistors connected to the output terminal configured to output one of the scan signals. A unit transistor may be connected to each of the two buffer transistors.

[0018] The start signal input terminal of the stage may receive the output of the previous stage.

[0019] The plurality of stages may further include a dummy stage configured to receive the output of the last stage.

[0020] Among the plurality of pixels, a red pixel configured to display red, a blue pixel configured to display blue, and two green pixels configured to display green may be repeatedly formed as a unit.

[0021] The plurality of pixels may include a red pixel configured to display red, a blue pixel configured to display blue, and a green pixel configured to display green, and the red pixel, the blue pixel, and the green pixel may be formed in a ratio of 1:1:1.

[0022] The plurality of stages may be disposed on opposite sides of the display area. Two of the plurality of stages may be connected to one scan line, and the two stages may apply the same scan signal to the one scan line.

[0023] According to an exemplary embodiment of the inventive concept, a display device includes: a substrate including a display area for displaying an image and a non-display area surrounding the display area; a plurality of pixels disposed in the display area and each including an organic light emitting diode and a pixel circuit portion configured to operate the organic light emitting diode; a scan driver disposed in the non-display area and including a plurality of stages configured to output scan signals to the plurality of pixels; and a signal controller configured to apply a control signal including a clock signal and a voltage used in the scan driver to the scan driver. A line for applying the control signal or the voltage used in the scan driver may intersect at least one of the plurality of stages.

[0024] In the non-display area of the substrate, four clock lines, a global clock signal line, and a low voltage line may connect the signal controller and the plurality of stages, and the line intersecting at least one of the plurality of stages may be the global clock signal line or the low voltage line.

[0025] Each of the plurality of stages may include: an output terminal connected to a scan line configured to transmit a scan signal to the pixel circuit portion; and two buffer transistors connected to the output terminal. The line intersecting at least one of the plurality of stages may pass between the two buffer transistors.

[0026] The plurality of stages included in the scan driver may be arranged in n columns, and n may be an integer of 2 or greater.

[0027] According to an exemplary embodiment of the inventive concept, a display device includes: a substrate including a display area for displaying an image and a non-display area surrounding the display area; a plurality of pixels disposed in the display area; a scan driver disposed in the non-display area and including a plurality of stages configured to output scan signals to the plurality of pixels; four clock lines disposed adjacent to the plurality of stages; a global clock signal line intersecting the plurality of stages; and a low voltage line intersecting the plurality of stages. Each of the plurality of stages may be connected to only three of the four clock lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

[0029] Figure 2 Block diagram illustrating a scan driver according to an exemplary embodiment of the inventive concept.

[0030] Figure 3 Circuit diagram illustrating one stage of a scan driver according to an exemplary embodiment of the inventive concept.

[0031] Figure 4 Illustration of signals applied to a stage of Figure 3 and signals output from a stage of Figure 3 waveform diagram.

[0032] Figure 5 Schematic layout diagram illustrating a scan driver according to an exemplary embodiment of the inventive concept.

[0033] Figures 6 to 10 Illustration of a scan driver according to an exemplary embodiment of the inventive concept Figure 5 detailed layout diagram of the divided.

[0034] Figure 11 and Figure 12 Illustration of a scan driver according to an exemplary embodiment of the inventive concept Figure 5 cross-sectional view of a part of.

[0035] Figure 13 Schematic diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

[0036] Figure 14 Schematic diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

[0037] Figure 15 Schematic diagram illustrating a display device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0038] Exemplary embodiments of the inventive concept provide a high-resolution display device that can be suitably integrated even when the size of a stage of a scan driver formed together with the high-resolution display device is larger than the size of a small pixel of the high-resolution display device.

[0039] Hereinafter, exemplary embodiments of the inventive concept will be described more fully with reference to the accompanying drawings. Throughout this application, like reference numerals may refer to like elements.

[0040] In the drawings, the size and thickness of each element are arbitrarily shown for ease of description, and the inventive concept is not necessarily limited to the size and thickness shown in the drawings. For clarity, the thickness of layers, films, panels, regions, etc. may be exaggerated.

[0041] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it may be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, no intervening elements are present. Further, in the specification, the words “on... ” or “above... ” mean being disposed on or under an object part and do not necessarily mean being disposed on the upper side of the object part based on the direction of gravity.

[0042] In addition, throughout the specification, the phrase “cross-sectional view” refers to a cross-section viewed by vertically cutting a target part from the side.

[0043] Hereinafter, reference will be made to Figure 1 describe a display device according to an exemplary embodiment of the inventive concept.

[0044] Figure 1 A schematic diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

[0045] The display device according to the present exemplary embodiment is an organic light-emitting diode display device and displays a high resolution such as 4K or 8K.

[0046] The organic light-emitting diode display device includes: a display area 110 in which pixels 111 are formed on a substrate 100 to display an image; and a non-display area, which is an area other than the display area 110.

[0047] Pixel 111 includes a pixel circuit portion, and the pixel circuit portion includes transistors, capacitors, etc. that operate an organic light-emitting diode. In the present exemplary embodiment, the pixels 111 in the display area 110 are repeatedly formed by a red pixel 111R, a blue pixel 111B, and two green pixels 111G1 and 111G2 as one unit. Accordingly, the ratio of the red pixel 111R, the blue pixel 111B, and the green pixels 111G1 and 111G2 is 1:1:2. However, the number and arrangement of the pixels are not limited thereto. When two green pixels 111G1 and 111G2 are used as in the present exemplary embodiment, a smaller number of pixels can be used to display a higher resolution.

[0048] In Figure 1 the pixel 111 shown as a quadrilateral in does not show the area where the organic light-emitting diode emits light, but schematically shows the area occupied by the pixel circuit portion that supplies current to the organic light-emitting diode. The transistors included in the pixel circuit portion of the pixel 111 include one driving transistor and at least one switching transistor. The at least one switching transistor may include a switching transistor connected to a scan line to transmit a data voltage to the pixel 111 according to a scan signal. Additionally, a switching transistor for initialization or compensation may be further included, and when only one switching transistor is included, it is possible to divide the period during which the one switching transistor operates to perform different operations for each period. The pixel circuit portion further includes a capacitor that maintains the voltage of the gate electrode of the driving transistor. In addition, additional capacitors may be included as needed. For a display device with high resolution, the area occupied by the pixel circuit portion may not be large, and thus, a large number of transistors and capacitors may not be formed, and two or three transistors and one or two capacitors may be included. Additionally, all the pixels 111 can emit light at substantially the same time.

[0049] The scan driver is formed in the non-display area, and the scan driver includes a plurality of stages 150 that respectively output one scan signal, and signal lines FLM, CLK1, CLK2, CLK3, CLK4, GCK, and VGL that are input to and output from each of the stages 150. The scan signal output for each stage 150 is transmitted to the scan lines S1, S2, S3, S4,..., Sn-1, and Sn.

[0050] In Figure 1In [the figure], a plurality of stages 150 are arranged in two columns, and the height Y of one stage 150 corresponds to approximately twice the height P of the pixel 111. This is because there are limitations regarding reducing the area occupied by the stage 150, while the area occupied by the pixel 111 decreases as the resolution of the display device increases. Therefore, since it is inevitable to occupy a height higher than the height of the pixel 111, when forming one stage, the stage 150 is arranged in two columns according to the height of two pixels 111. In other words, the stages 150 arranged in two columns are set at substantially equal distances from one side of the substrate 100 and are arranged in a first direction, for example, in the direction in which the scan lines extend. However, the inventive concept is not limited thereto, and the stage 150 can be modified to have a different arrangement.

[0051] Based on one stage 150, the lines CLK1, CLK2, CLK3, and CLK4 for applying clock signals are arranged far from the display area 110, and the line GCK for applying a global clock signal and the line VGL for applying a low voltage intersect the stage 150. The lines CLK1, CLK2, CLK3, and CLK4 for applying clock signals are arranged as far from the display area 110 as possible so that the pixels 111 in the display area 110 can be less affected whenever the clock signal changes.

[0052] The reason why the line GCK for applying a global clock signal and the line VGL for applying a low voltage are arranged to intersect the central portion of the stage 150 is that when forming the connection lines from the line GCK and the line VGL to a part in the stage 150, the area occupied by the stage 150 can be increased. The line GCK and the line VGL can be set adjacent to the part of the stage 150 that needs to be connected. The lines CLK1, CLK2, CLK3, and CLK4 for applying clock signals to the stage 150 arranged near the display area 110 are arranged between the stages 150 arranged in two columns.

[0053] The line FLM for transmitting a start signal is arranged outside the lines CLK1, CLK2, CLK3, and CLK4 for applying clock signals to the stage 150, which are arranged far from the display area 110. Additional lines can be arranged outside the line FLM for transmitting a start signal, and in an exemplary embodiment of the inventive concept, a driving low voltage line or a test line for testing the display device can be arranged (see Figure 5 ).

[0054] In FIG. 1, scan drivers including a plurality of stages 150 are arranged on the left and right sides of the display area 110. In the figure, the stages 150 arranged on the left side of the display area 110 are denoted by SL, and the stages 150 arranged on the right side of the display area 110 are denoted by SR. The attached numbers indicate that a given stage 150 applies a scan signal to the corresponding numbered scan line, for example, inFigure 1 The stages SL1, SL2, SL3, SL4, …, SLn-1, SLn and stages SR1, SR2, SR3, SR4, …, SRn-1, SRn shown in the figure. In addition, both stage SL1 and stage SR1 transmit the scan signal to the first scan line S1, and the signals output from stage SL1 and stage SR1 are the same scan signal. In this way, the reason for forming the scan driver for outputting the same scan signal on the opposite sides of the display area 110 is that as the resolution of the display area 110 increases, the display area 110 has a large number of pixels 111. Therefore, when the scan signal is applied only from one side, since the other side receives the delayed scan signal, the display may be abnormal. When there is no such problem, the scan driver can be formed only on one side.

[0055] The stages 150 arranged in two columns may have a structure for receiving a carry signal.

[0056] The non-display area may further include various lines, such as lines for applying a data voltage, test lines for testing, lines for applying a driving voltage, and lines for applying a pixel initialization voltage.

[0057] The signal controller 200 is formed on one side of the non-display area, and provides a control signal including a clock signal and a voltage used in the scan driver through the signal controller 200. The signal controller 200 also provides a data voltage used in the pixel 111.

[0058] The signal controller 200 may be mounted on the substrate 100, or may be connected to the substrate 100 through a flexible substrate.

[0059] Hereinafter, reference will be made to Figures 2 to 4 Describe the structure and connection relationship of the stage 150 in more detail.

[0060] First, reference will be made to Figure 2 Describe the stage 150.

[0061] Figure 2 Explain a block diagram of a scan driver according to an exemplary embodiment of the inventive concept.

[0062] One stage 150 has six input terminals STV, INCLK1, INCLK2, INCLK3, INGCK and INVGL, and one output terminal OUT.

[0063] The start signal input terminal STV receives a start signal through a line FLM for transmitting the start signal or receives a scan signal from a previous stage 150. In other words, stages SR1 and SL1 receive the start signal from the line FLM for transmitting the start signal, and subsequent stages 150 receive the scan signal from the previous stage 150. In an exemplary embodiment of the inventive concept, a carry signal of the previous stage 150 may be applied, and the carry signal may be a signal having substantially the same timing as the timing of the scan signal.

[0064] Three clock input terminals INCLK1, INCLK2, and INCLK3 are connected to three of the lines CLK1, CLK2, CLK3, and CLK4 for applying four clock signals. For example, in stages SR1 and SL1, the first clock line CLK1, the second clock line CLK2, and the third clock line CLK3 are connected to the three clock input terminals INCLK1, INCLK2, and INCLK3, respectively. In stages SR2 and SL2, the second clock line CLK2, the third clock line CLK3, and the fourth clock line CLK4 are connected to the three clock input terminals INCLK1, INCLK2, and INCLK3, respectively, and in stages SR3 and SL3, the third clock line CLK3, the fourth clock line CLK4, and the first clock line CLK1 are connected to the three clock input terminals INCLK1, INCLK2, and INCLK3, respectively. In this way, it is determined which three clock lines are to be connected to the next stage.

[0065] The global clock signal input terminal INGCK and the low voltage input terminal INVGL are connected to a line GCK for applying a global clock signal and a line VGL for applying a low voltage, respectively, to receive the global clock signal and the low voltage.

[0066] The output terminal OUT of stage 150 outputs the scan signal to the scan line connected thereto and transmits the scan signal to the start signal input terminal STV of the next stage 150 to be used as a start signal. In an exemplary embodiment of the inventive concept, a carry signal having substantially the same timing as the scan signal may be transmitted to the start signal input terminal STV of the next stage 150.

[0067] Meanwhile, in an exemplary embodiment of the inventive concept, stage 150 may further include an input terminal configured to receive the scan signal or the carry signal of the next stage 150, and in this case, the output of the next stage 150 is also transmitted to stage 150 provided at its front end, such as the previous stage 150. In an exemplary embodiment of the inventive concept, it may be transmitted to stage 150 before the current stage 150, or transmitted to stage 150 two or more stages before the current stage 150.

[0068] Figure 2Also shown is a structure in which a global clock signal line GCK and a low voltage line VGL are also formed to intersect the stage 150 and are disposed to intersect the central portion of the stage 150.

[0069] The detailed structure and operation of the stage 150 having such a connection relationship will be described with reference to Figure 3 and Figure 4 will be described.

[0070] Figure 3 Illustrate a circuit diagram of one stage of a scan driver according to an exemplary embodiment of the inventive concept, and Figure 4 Illustrate a waveform diagram of signals applied to the Figure 3 stage and signals output therefrom according to an exemplary embodiment of the inventive concept.

[0071] One stage 150 has nine transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9, and two capacitors C Q and C QB .

[0072] First, the first transistor T1 has a structure in which two transistors T1_1 and T1_2 are connected as one transistor. In other words, the gate electrodes of the two transistors T1_1 and T1_2 receive the same signal, and the output electrode of one transistor T1_1 and the input electrode of the other transistor T1_2 are connected.

[0073] The gate electrode of the first transistor T1 is connected to the second clock input terminal INCLK2, its input electrode is connected to the start signal input terminal STV, and its output electrode is connected to the Q node. Accordingly, the first transistor T1 is controlled by the clock signal input to the second clock input terminal INCLK2, and receives a start signal or an output signal of the previous stage 150 through the start signal input terminal STV, and outputs it to the Q node or blocks it from reaching the Q node.

[0074] The gate electrode of the second transistor T2 is connected to the start signal input terminal STV, the input electrode is connected to the first clock input terminal INCLK1, and the output electrode is connected to the input electrode of the third transistor T3. Accordingly, the second transistor T2 is controlled by the start signal or the output signal of the previous stage 150 input through the start signal input terminal STV to output the clock signal input from the first clock input terminal INCLK1 to the third transistor T3 or block it from reaching the third transistor T3.

[0075] The gate electrode of the third transistor T3 is connected to the second clock input terminal INCLK2, its input electrode is connected to the output electrode of the second transistor T2, and its output electrode is connected to the QB node. Therefore, the third transistor T3 is controlled by the clock signal input from the second clock input terminal INCLK2 to transfer the output of the second transistor T2 to the QB node or block it from reaching the QB node.

[0076] The gate electrode and the input electrode of the fourth transistor T4 are connected to the first clock input terminal INCLK1, and its output electrode is connected to the QB node. Therefore, when the clock signal input to the first clock input terminal INCLK1 is a voltage for turning on the fourth transistor T4, the fourth transistor T4 transfers the corresponding voltage to the QB node. In the present exemplary embodiment, since the fourth transistor T4 is an n-type transistor, when a high voltage of the clock signal is applied thereto, the fourth transistor transfers the corresponding high voltage to the QB node, and when a low voltage of the clock signal is applied thereto, the fourth transistor T4 blocks the corresponding low voltage.

[0077] The gate electrode of the fifth transistor T5 is connected to the global clock signal input terminal INGCK, its input electrode is connected to the low voltage input terminal INVGL, and its output electrode is connected to the Q node. Therefore, the fifth transistor T5 is controlled by the global clock signal input from the global clock signal input terminal INGCK to transfer a low voltage to the Q node or block the low voltage from reaching the Q node.

[0078] The gate electrode of the sixth transistor T6 is connected to the third clock input terminal INCLK3, its input electrode is connected to the Q node, and its output electrode is connected to the input electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the QB node, its input electrode is connected to the output electrode of the sixth transistor T6, and its output electrode is connected to the output terminal OUT of stage 150.

[0079] When the clock signal input to the third clock input terminal INCLK3 has a high voltage and the QB node has a high voltage, the sixth transistor T6 and the seventh transistor T7 are used to connect the Q node and the output terminal OUT of stage 150. Since the QB node has a low voltage for a predetermined period based on the period of outputting a high voltage (gate conduction voltage) as the scan signal, the Q node and the output terminal OUT of stage 150 are not connected during the predetermined period. However, when the clock signal input to the third clock input terminal INCLK3 has a high voltage during a period other than the predetermined period (for example, during a period when the QB node has a high voltage), the voltage of the Q node is output to the output terminal OUT of stage 150. Since the Q node has a high voltage for a predetermined period based on the period of outputting a high voltage (gate conduction voltage) as the scan signal and has a low voltage during the remaining period, the low voltage of the Q node is output to the output terminal OUT of stage 150, so that the scan signal is maintained at a low voltage.

[0080] The gate electrode of the eighth transistor T8 is connected to the Q node, its input electrode is connected to the third clock input terminal INCLK3, and its output electrode is connected to the output terminal OUT of stage 150. Although the eighth transistor T8 conducts according to the voltage of the Q node and outputs the clock signal input to the third clock input terminal INCLK3, when the clock signal input to the third clock input terminal INCLK3 has a high voltage, as the voltage of the Q node rises, the eighth transistor T8 is operated to output a high voltage to the output terminal OUT of stage 150.

[0081] The gate electrode of the ninth transistor T9 is connected to the QB node, its input electrode is connected to the global clock signal input terminal INGCK, and its output electrode is connected to the output terminal OUT of stage 150. The ninth transistor T9 conducts according to the voltage of the QB node and outputs the global clock signal input to the global clock signal input terminal INGCK.

[0082] Meanwhile, a Q node capacitor C for storing and maintaining the voltage of the Q node is formed between the gate electrode of the eighth transistor T8 and the output terminal OUT of stage 150 Q . In addition, a QB node capacitor C for storing and maintaining the voltage of the QB node is formed between the gate electrode of the ninth transistor T9 and the global clock signal input terminal INGCK QB .

[0083] The eighth transistor T8 and the ninth transistor T9 are connected to the output terminal OUT and are responsible for output, and the eighth transistor T8 and the ninth transistor T9 are collectively referred to as buffer transistors. Refer to Figures 5 to 10, the global clock signal line GCK and the low voltage line VGL are formed while intersecting with stage 150 and are disposed between two buffer transistors of stage 150. Therefore, it is possible to prevent an increase in the height of stage 150 while forming a line connecting the global clock signal line GCK and the low voltage line VGL.

[0084] In Figure 4 is shown the operation according to the signal applied to stage 150 having the above structure. Figure 4 Shown is a waveform diagram in which the first clock line CLK1, the second clock line CLK2, and the third clock line CLK3 are respectively applied to three clock input terminals INCLK1, INCLK2, and INCLK3 of stage 150.

[0085] Hereinafter, reference will be made to Figure 3 the structure to describe Figure 4 the waveform diagram.

[0086] Figure 4 The waveform diagram of TH is divided into three time periods (emission period (emission), initialization and compensation period (initial & V

[0087] compensation), and data addressing period (data addressing)). First described is the data addressing period which is the most basic period. Figure 4 The clock signals applied through four clock lines CLK1, CLK2, CLK3, and CLK4 are clock voltages that have a high voltage only during 1H of the 4H period and have a low voltage during the remaining periods, as shown in

[0088] The start signal or the scan signal of the previous stage 150 has a high voltage only within 1H of one frame and has a low voltage during other periods.

[0089] First, the 1H period (first data addressing period) during which the clock signal applied to the first clock line CLK1 has a high voltage will be described.

[0090] In the first data addressing period, the fourth transistor T4 is turned on to transmit the high voltage of the clock signal to the QB node, such that the voltage of the QB node is maintained at the high voltage VGH.

[0091] Thereafter, during the 1H period (second data addressing period) in which the clock signal applied to the second clock line CLK2 has a high voltage, a high voltage is applied to the start signal or the scan signal of the previous stage 150. Therefore, during the second data addressing period, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on. A high voltage is applied to the Q node through the first transistor T1, causing the voltage of the Q node to become the high voltage VGH, and the high voltage VGH is stored in the Q node capacitor C Q therein. In addition, the second transistor T2 and the third transistor T3 are turned on, and thus the clock signal applied to the first clock line CLK1, for example, the low voltage VGL, is applied to the QB node to convert the voltage of the QB node from the high voltage VGH to the low voltage VGL. In this case, the low voltage VGL is stored in the QB node capacitor C QB therein.

[0092] Thereafter, during the 1H period (third data addressing period) in which the clock signal applied to the third clock line CLK3 has a high voltage, a high voltage is output as the scan signal through the eighth transistor T8. (See S1) Here, as the clock signal input to the input electrode of the eighth transistor T8 changes from a low voltage to a high voltage, the voltage of the gate electrode of the eighth transistor T8 also increases, and thus the high voltage VGH is doubled to the high voltage 2*VGH. As a result, the eighth transistor T8 is turned on, and the clock signal input to its input electrode is output as the scan signal. In this case, the output scan signal can also be enhanced and output.

[0093] Thereafter, during the 1H period (fourth data addressing period) in which the clock signal applied to the fourth clock line CLK4 has a high voltage, the voltage of the gate electrode of the eighth transistor T8 can become the high voltage VGH again, while the clock signal applied to the third clock line CLK3 becomes a low voltage, and the eighth transistor T8 can be turned off.

[0094] Thereafter, when the clock signal applied to the first clock line CLK1 is in the 1H period (fifth data addressing period) in which the clock signal again has a high voltage, the fourth transistor T4 is turned on to change the voltage of the QB node to the high voltage VGH, and the high voltage VGH is stored in the QB node capacitor C QB therein. When the voltage of the QB node becomes the high voltage VGH, the ninth transistor T9 is turned on, and thus the global clock signal is output as the scan signal, and in this case, since the global clock signal has a low voltage, a low voltage is output.

[0095] Thereafter, when the clock signal applied to the second clock line CLK2 is in the 1H period (sixth data addressing period) in which the clock signal again has a high voltage, different from the second data addressing period, a low voltage is applied to the start signal or the scan signal of the previous stage 150. Therefore, in the sixth data addressing period, the third transistor T3 is turned on, but the second transistor T2 remains in the off state, and thus the voltage of the QB node remains unchanged. In addition, although the first transistor T1 is turned on, since the input start signal or the scan signal of the previous stage 150 is a low voltage, the voltage of the Q node changes from the high voltage VGH to the low voltage VGL.

[0096] Thereafter, when the clock signal applied to the third clock line CLK3 is in the 1H period (seventh data addressing period) in which the clock signal again has a high voltage, the sixth transistor T6 is turned on. In this case, since the seventh transistor T7 remains in the on state from the fifth data addressing period in which the voltage of the QB node changes to a high voltage, the Q node and the output terminal OUT of the stage 150 are connected. In other words, the voltage of the Q node is output as the scan signal, and in this case, since the Q node has a low voltage VGL, a low voltage is output as the scan signal.

[0097] After that, even if the clock signal flowing through the clock line changes, the voltage of the Q node remains at the low voltage VGL, and the voltage of the QB node remains at the high voltage VGH. This state is maintained not only during the data addressing period but also during the light emission period (e.g., emission period). In other words, during the light emission period, even if the clock signal changes, the voltage of the Q node remains at the low voltage VGL, and the voltage of the QB node remains at the high voltage VGH, so that a low voltage is output as the scan signal.

[0098] Thereafter, when the light emission period ends and the initialization and compensation period starts, all clock signals become low voltages, and thus only the global clock signal becomes high voltage.

[0099] When the global clock signal becomes high voltage, the fifth transistor T5 is turned on to change the voltage of the Q node to a low voltage applied from the low voltage line VGL to initialize it. In this case, since the ninth transistor T9 is turned on, the input global clock signal having a high voltage is also output to the output terminal OUT of the stage 150.

[0100] Since the global clock signal is equally connected to all stages 150, the initialization and compensation operations are performed on all pixels 111 while applying the same high voltage to all scan lines.

[0101] In contrast, during the data addressing period, three clock lines out of the four clock lines CLK1, CLK2, CLK3, and CLK4 are selected to be connected to all levels 150, and for each 1H period, a high voltage is sequentially applied to one scan line due to a change in the time point of the transmission start signal or the high voltage of the scan signal of the previous level 150.

[0102] Figure 3 and Figure 4 An exemplary embodiment is shown in which the nine transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9 included in level 150 are n-type transistors. However, according to an exemplary embodiment of the inventive concept, they may be p-type transistors, and in this case, when a low voltage is applied thereto, since they are turned on, the high voltage and the low voltage should be switched in Figure 4 . Additionally, the low voltage input terminal INVGL in Figure 3 can be changed to a high voltage input terminal for inputting a high voltage.

[0103] Since level 150 is formed on substrate 100 by the same process as pixel 111, when the transistors included in pixel 111 are n-type transistors, level 150 can be formed of n-type transistors, and when the transistors included in pixel 111 are p-type transistors, level 150 can be formed of p-type transistors.

[0104] Level 150 having the circuit shown in Figure 3 is formed in two columns as shown in Figure 1 , and the level 150 arranged in the two columns will be described in detail with reference to Figures 5 to 12 .

[0105] First, its overall structure will be described with reference to Figure 5 .

[0106] Figure 5 A schematic layout diagram of a scan driver according to an exemplary embodiment of the inventive concept is shown.

[0107] Figure 5 Level 150 is described. Level 150 is arranged in two columns provided on the left side of display area 110 and is included in the scan driver provided in the Figure 1 non-display area. In Figure 5 , a test line or a driving low voltage ELVSS line is provided on the leftmost side, the first four clock lines CLK1, CLK2, CLK3, CLK4 are provided on its right side, and the level 150 of the first column is provided on its right side. The area occupied by the level 150 ODD of the first column is occupied until the formation of Figure 5The second four clock lines CLK1, CLK2, CLK3, and CLK4 shown at the center of Figure 5 are provided on its right side, the stage 150EVEN of the second column is provided on its right side, and the display area 110 (not shown in

[0108] Figure 5 is provided on its right side. Here, the test line is a line for applying a signal for testing the display device, and the driving low voltage ELVSS line is a line for applying a driving low voltage during the operation of the pixel 111. Figure 1 In

[0109] two signal lines GCK and VGL pass through the central portions of the stage 150ODD of the first column and the stage 150EVEN of the second column. Two stages 150 and two signal lines GCK and VGL are provided such that the area (or height) occupied by the stage 150 due to the connection lines connecting them does not increase. In other words, since the width of the connection lines would increase the height Y occupied by the stage 150, the connection lines are minimized to minimize the height Y. Additionally, referring to Figure 5 Figure 5 the structure of Figures 6 to 10 is divided and enlarged to Figure 5 the VI part of Figure 6 is shown in detail in Figure 5 the VII part of Figure 7 is shown in detail in Figure 5 the VIII part of Figure 8 is shown in detail in Figure 5 the IX part of Figure 9 is shown in detail in Figure 5 the X part of Figure 10 is shown in detail in

[0110] Figures 6 to 10 A detailed layout diagram of the divided Figure 5 scan driver according to an exemplary embodiment of the inventive concept is described, and Figure 11 Figure 12 a cross-sectional view of a part of the Figure 5 scan driver according to an exemplary embodiment of the inventive concept is described.

[0111] In Figures 6 to 10 ​​​In the figure, the part surrounded by the thick solid line represents the semiconductor layer, and the part surrounded by the hatched line represents the first conductive layer. The semiconductor layer may be a polycrystalline semiconductor layer, and the part of the hatched line portion shown as the semiconductor layer that does not overlap with the first conductive layer may be doped, while the part that overlaps with the first conductive layer may not be doped. The second conductive layer used in forming a part of the capacitor and the third conductive layer formed by the remaining lines are shown by ordinary solid lines.

[0112] Reference Figure 6 , from the part where the four clock lines CLK1, CLK2, CLK3, and CLK4 are connected to stage 150, the first transistor T1, second transistor T2, third transistor T3, first four-transistor T4, sixth transistor T6, and seventh transistor T7 of stage 150 are shown.

[0113] Among the four clock lines CLK1, CLK2, CLK3, and CLK4, the first clock line CLK1, second clock line CLK2, and third clock line CLK3 are respectively connected to the inside of stage 150 through line I1, line I2, and line I3.

[0114] Line I1 extends to form the gate electrode G4 of the fourth transistor T4, and further extends to be connected to the input electrode of the second transistor T2 through line EC2. Line I1 is also connected to the input electrode of the fourth transistor T4 through line EC1, such that the fourth transistor T4 has a diode-connected structure.

[0115] The fourth transistor T4 is provided with a structure having two gate electrodes G4, and the other transistors T1, T2, T3, T5, T6, and T7 have similar structures. The cross-sectional structure of such transistors is shown in detail in Figure 11 . The structure of the transistors will be described below.

[0116] Line I2 extends to form the gate electrode G3 of the third transistor T3, and further extends to form the gate electrode G1 of the first transistor T1. The first transistor T1 has a structure in which two transistors are formed continuously.

[0117] Line I3 extends to form the gate electrode G6 of the sixth transistor T6, and reference Figure 7 , it further extends to be connected to the input electrode of the eighth transistor T8 through line EC5.

[0118] Line EC3 is connected to the output electrode of the third transistor T3, is also connected to the output electrode of the fourth transistor T4, and further extends to be connected to the gate electrode G7 of the seventh transistor T7. Reference Figure 7 , the gate electrode G7 of the seventh transistor T7 extends to form the QB node line, and further extends to form the first electrode of the QB node capacitor C QB .

[0119] The gate electrode G2 of the second transistor T2 extends to connect to the carry signal CR line.

[0120] In addition to the gate electrode G2 of the second transistor T2, the CR line is connected to the input electrode of the first transistor T1. Additionally, referring Figure 7 , Figure 8 and Figure 9 , the CR line further extends to connect to the output electrode of the eighth transistor T8 of the previous stage. In the case of the first stage, a start signal can be applied thereto.

[0121] The Q node line is electrically connected to the semiconductor layer in the middle part between the first transistor T1 and the sixth transistor T6, and is connected to the output electrode of the first transistor T1 and the input electrode of the sixth transistor T6. The Q node line extends, and referring Figure 7 , it is connected to the second electrode of the Q node capacitor C Q .

[0122] The EC4 line is connected to the output electrode of the seventh transistor T7, and referring Figure 7 , it extends to be electrically connected to the first electrode of the Q node capacitor C Q , and further extends to form the output electrode of the eighth transistor T8.

[0123] In Figure 6 , the semiconductor layers of some transistors are connected to each other, and since the portions not overlapping with the gate electrodes are doped to have conductive characteristics, two transistors are electrically connected to each other through the doped regions that are the doped portions of the semiconductor layers. In Figure 6 are also shown contacts for electrically connecting components such as lines, electrodes, and semiconductor layers.

[0124] Hereinafter, the structure of Figure 7 will be described, and the content described above with reference Figure 6 will be omitted.

[0125] In Figure 7 , the gate electrode G8 of the eighth transistor T8 extends left and right, and it extends and expands to the left to form the Q node capacitor C QThe first electrode. Additionally, it extends to the right to be connected to the output electrode of the fifth transistor T5 via the EC6 line. The gate electrode G8 of the eighth transistor T8 has an opening in its central portion and overlaps with the semiconductor layer, and a part of the semiconductor layer is electrically connected to the EC4 line and the remaining part thereof is electrically connected to the EC5 line. Accordingly, the EC5 line is configured as an input electrode, the EC4 line is configured as an output electrode, and each of them is electrically connected to the doped region of the semiconductor layer. The eighth transistor T8 is configured as a unit eighth transistor T8 based on one semiconductor layer, and since a large number of unit eighth transistors T8 are included, only some of them are shown in Figure 7 Only some of them are shown. The unit eighth transistors T8 are electrically connected to each other via the EC4 line and the EC5 line.

[0126] The EC4 line further extends to be connected to the I4 line, the I4 line is connected to the EC7 line, and the EC7 line forms the output electrode of the ninth transistor T9. Refer to Figure 8 , the EC7 line further extends to be connected to the input electrode of the first transistor T1 and the gate electrode G2 of the second transistor T2 provided in stage 150 in the second column via the I5 line, and additionally further extends to the scan line S1, as shown in Figure 9 and Figure 10 shown.

[0127] The gate electrode G5 of the fifth transistor T5 extends to form the GCK-1 line and is electrically connected to the GCK line. The GCK line extends in the longitudinal direction but has the EC8 line extending to the right. The EC8 line is electrically connected to the second electrode of the QB node capacitor C QB and further extends to form the input electrode of the ninth transistor T9.

[0128] The VGL line extends to the left and is electrically connected to the input electrode of the fifth transistor T5.

[0129] As shown in Figure 7 , the height Y occupied by stage 150 is reduced by reducing the space connecting the fifth transistor T5 with the GCK line and the VGL line. In other words, when the GCK-1 line passes through the eighth transistor T8 and further extends, space must be provided such that the GCK-1 line can pass through the eighth transistor T8, and for this purpose the vertical height of stage 150 is further increased. However, in Figure 7 , the GCK line is arranged adjacent to the fifth transistor T5 to minimize the height occupied by stage 150. This configuration also applies to the VGL line.

[0130] The structure of the ninth transistor T9 is substantially the same as that of the eighth transistor T8, and the structure of the unit ninth transistor T9 is substantially the same as that of the unit eighth transistor T8. However, instead of the EC4 line and the EC5 line of the eighth transistor T8, the EC7 line and the EC8 line are used in the ninth transistor T9. The EC7 line forms the output electrode of the ninth transistor T9, and the EC8 line forms the input electrode of the ninth transistor T9.

[0131] In the planar structure of the eighth transistor T8 and the ninth transistor T9, a doped region is formed only between the two gate electrodes G8 and G9 to reduce the height occupied by the transistor. This is because if an electrode is formed, its height will increase. According to the double-gate structure, in addition to the area (height reduction), it is also used to reduce the leakage current. Hereinafter, the structure having the lines EC4, EC5, EC7, and EC8 connecting the unit transistors (such as the eighth transistor T8 and the ninth transistor T9) is also referred to as a finger transistor.

[0132] Although the planar structures of the eighth transistor T8 and the ninth transistor T9 are different from those of the other transistors T1, T2, T3, T4, T5, T6, and T7, their cross-sectional structures are similar to Figure 11 the cross-sectional structure of Figure 11 which will be described in detail below.

[0133] Meanwhile, in Figure 7 the Q-node capacitor C Q and the QB-node capacitor C QB are shown. These two capacitors include a first electrode formed of a first conductive layer and a second electrode formed of a second conductive layer, and their cross-sectional structures are substantially the same and are shown in Figure 12 which will be described below. Figure 12 the structures of the two capacitors in

[0134] Figure 8 is a view similar to Figure 6 however, different from Figure 6 it details the stage 150 provided in the second column. The stages provided in the first column and the stages provided in the second column have substantially the same internal structure, and only the line structures to be connected thereto are different. In other words, the I1' line of Figure 6 corresponding to the I1 line of Figure 8 is connected to the second clock line CLK2, the I2' line of Figure 6 corresponding to the I2 line of Figure 8 is connected to the third clock line CLK3, and the I3' line of Figure 6 corresponding to the I3 line of Figure 8 is connected to the fourth clock line CLK4.

[0135] In addition, Figure 9 has a structure similar to Figure 7 and there is no difference between them except for the lines to be connected.

[0136] Figure 10 shows the scan lines from the end of stage 150EVEN provided in the second column to the scan lines connected thereto. In Figure 6 and Figure 7 the output of stage 150ODD in the first column shown is connected to the odd scan lines, and in Figure 8 and Figure 9 the output of stage 150EVEN in the second column shown is connected to the even scan lines. The scan lines receiving the scan signals extend to the display area 110 and are connected to the pixels 111.

[0137] Figure 11 Describe the structure of the fourth transistor T4, which has a structure forming two gate electrodes. The cross-sectional structures of the other transistors T1, T2, T3, T5, T6, T7, T8, and T9 are not significantly different from the cross-sectional structure of the fourth transistor T4, and thus will be described with reference to Figure 11 The different parts of each transistor are only different in how the doped semiconductor layer is connected to the remaining other parts.

[0138] Referring to Figure 11 , a transistor TFT has a polycrystalline semiconductor layer formed on a substrate Sub, and the polycrystalline semiconductor layer includes doped parts doped-1, doped-2, and doped-3 and an undoped part C therebetween. The undoped part C is the part forming the channel. The doped parts doped-1, doped-2, and doped-3 have characteristics similar to those of a conductor.

[0139] A first interlayer insulating film IL1 (also called a gate insulating film) is provided on the polycrystalline semiconductor layer. A gate electrode G is provided on the first interlayer insulating film IL1. Two gate electrodes G are formed, and the two gate electrodes G correspond to the undoped part C.

[0140] A second interlayer insulating film IL2, a third interlayer insulating film IL3, and a fourth interlayer insulating film IL4 covering the gate electrode G are provided. Although four interlayer insulating films IL1, IL2, IL3, and IL4 are shown in Figure 11 , one or two interlayer insulating films may be formed.

[0141] The third conductive layer is disposed on the fourth interlayer insulating film IL4, and they respectively form an input electrode TE1 and an output electrode TE2. Openings are provided in the interlayer insulating films IL1, IL2, IL3, and IL4 such that the input electrode TE1 is electrically connected to the first doped portion doped-1 of the semiconductor layer, and the output electrode TE2 is electrically connected to the second doped portion doped-2 of the semiconductor layer.

[0142] When a gate conduction voltage is applied to the gate electrode G, the voltage of the input electrode TE1 is transmitted to the first doped portion doped-1, and the first doped portion doped-1 having conductor characteristics transmits the voltage to the undoped portion C of the semiconductor layer. Since a channel is formed in the undoped portion C of the semiconductor layer, the voltage is transmitted through the channel to the third doped portion doped-3. Since the third doped portion doped-3 also has conductor characteristics, the voltage passes through it and is transmitted to the adjacent undoped portion C, passes through the channel formed in the undoped portion C, and is output to the output electrode TE2 through the second doped portion doped-2.

[0143] This transistor has a double-gate structure, thus reducing the leakage current. In addition, the input and output electrodes that may be additionally formed in the third doped portion doped-3 can be omitted, and only the doped semiconductor layer can be formed to reduce the area occupied by the transistor. The same applies to the eighth transistor T8 and the ninth transistor T9, and if electrodes are formed in portions corresponding to the third doped portion doped-3 exposed in the eighth transistor T8 and the ninth transistor T9, then due to the Figure 7 higher height of the eighth transistor T8 and the ninth transistor T9 in, the height Y of the stage 150 will also increase. However, a double-gate structure is used, and a doped portion (third doped portion doped-3) is formed in the middle to reduce the height Y of the stage 150 to twice the height P of the pixel 111.

[0144] Since the transistors formed in the stage 150 are formed on the substrate 100 by substantially the same process as the pixel circuit portion of the pixel 111, when the transistor included in the pixel 111 is an n-type transistor, the transistors in the stage 150 are formed as n-type transistors, and when the transistor included in the pixel 111 is a p-type transistor, the transistors in the stage 150 can be formed as p-type transistors. Here, in the case of an n-type transistor, a lightly doped drain (LDD) can be further formed between the doped portion and the undoped portion C. When the sidewall of the gate electrode G is inclined to have a tapered structure, if a doping process is performed using the gate electrode G as a mask, a lightly doped drain (LDD) provided between the doped portion and the undoped portion C is formed under the tapered structure. Through this process, a lightly doped drain (LDD) can be formed.

[0145] Meanwhile, Figure 12 shows a cross-sectional structure including two capacitors (Q-node capacitor C Q and QB-node capacitor C QB ) included in stage 150.

[0146] Referring to Figure 12 , in the capacitor, a first interlayer insulating film IL1 is disposed on a substrate Sub, and a first electrode CE1 is formed on the first interlayer insulating film IL1.

[0147] A second interlayer insulating film IL2 is disposed on the first electrode CE1, and a second electrode CE2 is disposed on the second interlayer insulating film IL2.

[0148] A third interlayer insulating film IL3 and a fourth interlayer insulating film IL4 covering the second electrode CE2 are provided. In an exemplary embodiment of the inventive concept, only one interlayer insulating film may cover the second electrode CE2.

[0149] An electrode SD is formed on the fourth interlayer insulating film IL4 and is electrically connected to the second electrode CE2 through an opening formed in the third interlayer insulating film IL3 and the fourth interlayer insulating film IL4.

[0150] The capacitor includes a first electrode CE1, a second electrode CE2, and a second interlayer insulating film IL2 disposed therebetween.

[0151] The cross-sectional structures of the transistor and the capacitor included in the scan driver have been described with reference to Figure 11 and Figure 12 . Since the scan driver of the present exemplary embodiment is formed on the substrate Sub together with the pixel 111, the scan driver may have the same or similar stacked structure as that of the transistor or the capacitor included in the pixel circuit portion that supplies current to the organic light-emitting diode in the pixel 111. In an exemplary embodiment of the inventive concept, the stacked structures may be different from each other. However, even if the stacked structures are different as described above, when forming the pixel circuit portion using three conductive layers, the scan driver may be formed using three conductive layers or fewer conductive layers.

[0152] Figure 11 and Figure 12 illustrate a structure in which four interlayer insulating films are provided between the conductive layers, and thus the pixel circuit portion may be formed using four conductive layers.

[0153] However, when using three conductive layers in the pixel circuit portion, the fourth interlayer insulating film IL4 may be omitted in Figure 11 and Figure 12 .

[0154] Hereinafter, modified embodiments of the exemplary embodiments described above will be described.

[0155] First, an exemplary embodiment of the inventive concept including virtual levels will be described with reference to Figure 13 an exemplary embodiment of the inventive concept including virtual levels will be described with reference to

[0156] Figure 13 A schematic diagram of a display device according to an exemplary embodiment of the inventive concept is illustrated.

[0157] In Figure 13 scan lines S1, S2, …, S2159, S2160, levels SL1, SL2, …, SL2159, SL216, and levels SR1, SR2, …, SR2159, SR216 are shown. Figure 13 Different from Figure 1 is that Figure 13 it further includes virtual levels SLdummy and SRdummy. In addition, four clock lines CLK1, CLK2, CLK3, and CLK4, a global clock signal line GCK, and a low voltage line VGL are not shown in Figure 13 but a carry signal CR is shown in Figure 13 In addition, in Figure 13 a start signal generator GW_FLM is further included in the signal controller 200.

[0158] Figure 13 The virtual level SLdummy of Figure 13 is formed after the last level SL2160 and is formed only in one of two columns of the levels. Thus, each two columns include one virtual level. However, in an exemplary embodiment of the inventive concept, more virtual levels may be further included, and the virtual levels may be formed in each of the two columns. Figure 13 The virtual level SLdummy of

[0159] is used to receive the carry signal CR, and since no line for applying the carry signal CR is formed, the virtual level SLdummy prevents the scan signal from changing differently from other scan lines when the resistance value connected to the last scan line (S2160 in

[0160] Figure 13 The height Y of the level is shown to be twice the height P of the pixel 111. Here, the pixel 111 may refer to a pixel circuit part including transistors, capacitors, etc. formed to operate an organic light emitting diode.

[0161] Hereinafter, reference will be made toFigure 14 Describes an exemplary embodiment arranged in three columns at the description level.

[0162] Figure 14 Schematic diagram of a display device according to an exemplary embodiment of the inventive concept.

[0163] Unlike Figure 1 the exemplary embodiment of Figure 14 the exemplary embodiment of Figure 14 forms stage 150 in three columns, and the height Y of stage 150 is three times the height P of pixel 111. In Figure 1 the exemplary embodiment of

[0164] In addition, in Figure 14 the exemplary embodiment of Figure 1 the exemplary embodiment of

[0165] In Figure 14 the exemplary embodiment of

[0166] the connection between the four clock lines CLK1, CLK2, CLK3, and CLK4 and stage 150 is substantially the same as the connection in the above exemplary embodiment. In other words, when the first stage 150 (e.g., SL1) is connected to the first clock line CLK1, the second clock line CLK2, and the third clock line CLK3, the second stage 150 (e.g., SL2) is connected to the second clock line CLK2, the third clock line CLK3, and the fourth clock line CLK4, and the third stage 150 (e.g., SL3) is connected to the third clock line CLK3, the fourth clock line CLK4, and the first clock line CLK1. Then, the fourth stage 150 (e.g., SL4) in the first column of the stage arranged in the second row is connected to the fourth clock line CLK4, the first clock line CLK1, and the second clock line CLK2, and in this way, stage 150 is connected to three of the four clock lines CLK1, CLK2, CLK3, and CLK4.

[0167] Hereinafter, an exemplary embodiment of forming a short line FLM for transmitting a start signal from the signal controller 200 to the first stage will be described with reference to Figure 15

[0168] Figure 15Schematic diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

[0169] Figure 15 Corresponding to Figure 1 but different from Figure 1 In Figure 15 the line FLM for transmitting a start signal is connected to stage 150 adjacent to signal controller 200.

[0170] According to an exemplary embodiment as shown in Figure 15 the start signal line FLM formed outside the four clock lines CLK1, CLK2, CLK3, and CLK4 may not be long.

[0171] In Figure 15 different from Figure 1 the high voltage of the scan signal is transmitted sequentially from the bottom to the top. This is because the first stage receiving the start signal is set at the bottom. In contrast, in the exemplary embodiment of Figure 1 the high voltage of the scan signal is transmitted sequentially from the top to the bottom.

[0172] Figure 1 And Figure 15 illustrate the case where signal controller 200 for transmitting a start signal is disposed under substrate 100, but in the exemplary embodiment of the inventive concept, signal controller 200 may be disposed on substrate 100.

[0173] When signal controller 200 is disposed on substrate 100, when forming stage 150 in the same order as in Figure 1 a shorter start signal line FLM is formed.

[0174] According to an exemplary embodiment of the inventive concept, since a high-resolution display device includes small pixels, when forming stages of a scan driver having a height corresponding to the height of n pixels (where n is an integer of 2 or greater), the pixels are arranged in n columns. Thus, even in a display device having small pixels, it is possible to appropriately form stages. In addition, by forming a signal line or a voltage line to intersect with the stages, it is possible to shorten the length of the lines in the stages and thus reduce the height occupied by the stages. Furthermore, by forming the transistors included in the stages to have a double-gate structure, it is possible to reduce leakage current and reduce the height occupied by the stages.

[0175] Although the inventive concept has been shown and described with reference to exemplary embodiments of the inventive concept, those of ordinary skill in the art should understand that various modifications can be made to its form and details without departing from the spirit and scope of the inventive concept as set forth by the appended claims.

Claims

1. A display device, wherein, The display device includes: a substrate including a display area for displaying an image and a non-display area surrounding the display area; a plurality of pixels disposed in the display area, each including an organic light-emitting diode and a pixel circuit portion configured to operate the organic light-emitting diode; a plurality of scan lines disposed in the display area and electrically connected to the plurality of pixels; a scan driver disposed in the non-display area and including a plurality of stages configured to output scan signals to the plurality of scan lines, wherein the plurality of stages include a plurality of first stages arranged in a first direction, and each of the plurality of stages includes a plurality of transistors, the plurality of transistors including at least a first transistor and a second transistor; and a plurality of lines disposed in the non-display area, and the plurality of lines include a first line for applying a control signal including a clock signal and a second line for applying a voltage used in the scan driver, wherein one of the first lines configured to apply the control signal including the clock signal or one of the second lines configured to apply the voltage used in the scan driver intersects at least one of the plurality of stages, wherein at least one of the first line and the second line passes between the first transistor and the second transistor included in each of the plurality of first stages, extends along the first direction, and continuously extends along the first direction by a length longer than the height of each of the plurality of first stages, wherein the plurality of stages are arranged in n columns, the height of one stage corresponds to the height of n pixels, and n is an integer of 2 or greater.

2. The display device according to claim 1, wherein the first line configured to apply the control signal including the clock signal includes four clock lines and a global clock signal line, and the second line configured to apply the voltage used in the scan driver includes a low voltage line, and Among them, the global clock signal line or the low voltage line intersects at least one of the plurality of stages.

3. The display device according to claim 2, wherein the four clock lines, the global clock signal line, and the low voltage line are formed in each of the plurality of stages, the four clock lines are arranged at the outer edge of the non-display area or between adjacent columns of the n columns, farthest from the display area, and further includes: a signal controller configured to respectively provide a clock signal, a global clock signal, and a low voltage to the four clock lines, the global clock signal line, and the low voltage line, a test line configured to test the display device and disposed on the substrate, and a driving low voltage line configured to apply a driving low voltage to the plurality of pixels, wherein the test line and the driving low voltage line are arranged to be farther from the display area than the four clock lines.

4. The display device according to claim 3, wherein, Each of the plurality of stages includes three clock input terminals, a global clock signal input terminal, a low voltage input terminal, a start signal input terminal, and an output terminal, Each of the plurality of stages is connected to three of the four clock lines. The first stage disposed in the first column of the first row is connected to the first clock line, the second clock line, and the third clock line. The second stage disposed in the second column of the first row is connected to the second clock line, the third clock line, and the fourth clock line. The third stage disposed in the third column of the first row is connected to the third clock line, the fourth clock line, and the first clock line, and The fourth stage disposed in the first column of the second row is connected to the fourth clock line, the first clock line, and the second clock line. Wherein, each of the plurality of stages further includes: Two buffer transistors connected to the output terminal configured to output one of the scan signals. Wherein, the cell transistor is connected to each of the two buffer transistors.

5. The display device according to claim 4, wherein, The start signal input terminal receives the output of the previous stage, and Wherein, the plurality of stages further includes a dummy stage configured to receive the output of the last stage.

6. The display device according to claim 1, wherein, Among the plurality of pixels, a red pixel configured to display red, a blue pixel configured to display blue, and two green pixels configured to display green are repeatedly formed as a unit, or Wherein, the plurality of pixels includes a red pixel configured to display red, a blue pixel configured to display blue, and a green pixel configured to display green, and the red pixel, the blue pixel, and the green pixel are formed in a ratio of 1:1:1, and Wherein, the plurality of stages are disposed on opposite sides of the display area, and Two of the plurality of stages are connected to one scan line, and the two stages apply the same scan signal to the one scan line.

7. A display device, wherein, The display device includes: A substrate including a display area for displaying an image and a non-display area surrounding the display area; A plurality of pixels disposed in the display area, each including an organic light-emitting diode and a pixel circuit portion configured to operate the organic light-emitting diode; A plurality of scan lines disposed in the display area and electrically connected to the plurality of pixels; A scan driver disposed in the non-display area and including a plurality of stages configured to output scan signals to the plurality of scan lines, wherein the plurality of stages include a plurality of first stages arranged in a first direction, and each of the plurality of stages includes a plurality of transistors, and the plurality of transistors at least include a first transistor and a second transistor; a signal controller configured to apply a control signal including a clock signal and a voltage used in the scan driver to the scan driver; and A plurality of lines disposed in the non-display area, and the plurality of lines include a first line for applying the control signal including the clock signal and a second line for applying the voltage used in the scan driver, Wherein, the first line for applying the control signal or the second line for applying the voltage used in the scan driver intersects at least one of the plurality of stages. At least one of the first line and the second line passes between the first transistor and the second transistor included in each of the plurality of first stages, extends along the first direction, and continuously extends along the first direction by a length longer than the height of each of the plurality of first stages.

8. The display device according to claim 7, wherein, In the non-display area of the substrate, Four clock lines, a global clock signal line, and a low-voltage line connect the signal controller and the plurality of stages, and The first line or the second line that intersects at least one of the plurality of stages is the global clock signal line or the low-voltage line.

9. The display device according to claim 7, wherein, Each of the plurality of stages includes: An output terminal connected to a scan line configured to transmit a scan signal to the pixel circuit portion, and Two buffer transistors connected to the output terminal, wherein the first line or the second line that intersects at least one of the plurality of stages passes between the two buffer transistors, and wherein the plurality of stages included in the scan driver are arranged in n columns, and n is an integer of 2 or greater.

Images