Method and system for increasing PSRR compensation range in an image sensor

Abstract

A method for compensating for a power supply rejection ratio (PSRR) in an image sensor, the method comprising: receiving, by a processing circuit, at least one analog signal from an active pixel sensor (APS) array, the at least one analog signal comprising power supply noise; combining, by the processing circuit, an amplified power supply noise with at least one ramp signal to obtain a combined power supply noise; and compensating, by the processing circuit, for the PSRR of the APS array by canceling the power supply noise of the at least one analog signal using the combined power supply noise.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and derives the benefit of Indian provisional application No. 201941033110 filed on August 16, 2019, the contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of image sensors, and more particularly to compensating for a Power Supply Rejection Ratio (PSRR) in an image sensor with an increased PSRR compensation range. Background Art

[0004] Typically, an image sensor (e.g., a complementary metal oxide semiconductor (CMOS) image sensor) converts a light signal / light energy into an electrical signal. The image sensor includes an active pixel sensor (APS) array including a plurality of pixels; and a readout circuit including an analog-to-digital converter (ADC). Each pixel of the APS array includes a photoelectric conversion element. The photoelectric conversion element collects free charge carriers generated by absorbing energy such as light energy, and converts the collected free charge carriers into electrical energy / analog signals, wherein the analog signal may be a voltage or current corresponding to the corresponding number of free charge carriers collected. The readout circuit reads the analog signal from each pixel of the APS array and converts the analog signal into a digital signal (by performing an analog-to-digital conversion). The ADC of the readout circuit performs the analog-to-digital conversion by comparing the analog signal of the pixel with a ramp signal using a comparator. The ADC starts counting using a counter from the time point when the comparator starts comparing the analog signal with the ramp signal, and adopts the count value as a digital signal when the ramp signal reaches the analog signal. The digital signal is used to generate an image corresponding to the amount of light energy detected.

[0005] In an image sensor, the analog signal output by the pixel of the APS array may include noise corresponding to the noise received from an external power supply (hereinafter referred to as power supply noise). PSRR is the ability of the APS array to suppress the power supply noise received from the external power supply. The PSRR of the APS array causes horizontal noise (HN), which may affect the quality of the generated image. In conventional methods, when the PSRR of the APS array is low (~12dB), the readout circuit compensates for the PSRR. However, when the APS array involves pixels in the sub-micron range, the PSRR may be further reduced (for example, less than 8dB). In this case, the readout circuit may not be able to compensate for the reduced PSRR. Therefore, in conventional methods, the readout circuit may have a limit on the lowest PSRR of the APS array that it may correct without affecting the performance of the image sensor. Summary of the invention

[0006] Example embodiments herein provide methods and systems for increasing a power supply rejection ratio (PSRR) compensation range in an image sensor to compensate for a reduced PSRR of an active pixel sensor (APS) array, wherein the reduced PSRR is compensated for by canceling power supply noise of an analog signal present on a pixel path using amplified power supply noise introduced by a power supply noise amplifier into a ramp signal present on a correction path.

[0007] Example embodiments provide methods and systems for compensating for high frequency power supply noise / PSRR by matching the phase delay of the power supply noise present on the correction path with the phase delay of the power supply noise present on the pixel path.

[0008] Therefore, example embodiments herein provide methods and systems for compensating for power supply rejection ratio (PSRR) in image sensors. The methods disclosed herein include: receiving, by a processing circuit, at least one analog signal from an active pixel sensor (APS) array, the at least one analog signal including power supply noise; combining, by the processing circuit, the amplified power supply noise with at least one ramp signal to obtain a combined power supply noise; and compensating, by the processing circuit, the PSRR of the APS array by canceling the power supply noise of the at least one analog signal using the combined power supply noise.

[0009] Therefore, example embodiments herein provide an image sensor comprising: an active pixel sensor (APS) array, and a readout circuit coupled to the APS array, the readout circuit being configured to compensate for a power supply rejection ratio (PSRR) of the APS array by: receiving at least one analog signal from the APS array, the at least one analog signal comprising power supply noise; combining the amplified power supply noise with at least one ramp signal to obtain a combined power supply noise; and canceling the power supply noise of the at least one analog signal using the combined power supply noise.

[0010] Example embodiments herein provide a power supply rejection ratio (PSRR) compensation circuit in an image sensor, the image sensor including an active pixel sensor (APS) array and a plurality of analog-to-digital converters (ADCs) connected to the APS array, the PSRR compensation circuit being configured to: generate generated power supply noise on a correction path based on reading at least one analog signal from the APS array on each of the plurality of ADCs; and compensate for the PSRR of the APS array by performing amplitude correction and phase correction on the generated power supply noise.

[0011] Example embodiments of the present invention provide an image sensor including: an active pixel sensor (APS) array; a plurality of analog-to-digital converters (ADCs) connected to the APS array; and a power supply rejection ratio (PSRR) compensation circuit configured to: generate power supply noise generated on a correction path based on at least one analog signal read from the APS array by each of the plurality of ADCs; and compensate for the PSRR of the APS array by performing amplitude correction and phase correction on the generated power supply noise.

[0012] These and other aspects of the example embodiments herein will be better understood and appreciated when considered in conjunction with the following description and accompanying drawings. However, it should be understood that although the following description indicates the example embodiments and many of their specific details, the following description is given by way of illustration and not limitation. Various changes and modifications may be made within the scope of the example embodiments herein without departing from the spirit of the present invention, and the example embodiments herein include all such modifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Example embodiments of the present invention are shown in the accompanying drawings, and like reference numerals indicate corresponding parts in the various drawings throughout the drawings. Example embodiments of the present invention will be better understood from the following description with reference to the accompanying drawings, in which:

[0014] Figure 1 An imaging system according to an example embodiment disclosed herein is depicted;

[0015] Figure 2 is a block diagram depicting components of an image sensor of an imaging system according to example embodiments disclosed herein;

[0016] Figure 3 An image sensor including a PSRR compensation circuit for increasing a PSRR compensation range in the image sensor by performing amplitude correction according to example embodiments disclosed herein is depicted;

[0017] Figure 4 An amplifier of a PSRR compensation circuit according to an example embodiment disclosed herein is depicted;

[0018] Figure 5 An image sensor including a PSRR compensation circuit for performing phase correction to increase a PSRR compensation range in the image sensor according to example embodiments disclosed herein is depicted;

[0019] Figure 6 is a flow chart depicting a method for increasing a PSRR compensation range in an image sensor by performing an amplitude / magnitude correction on a correction path according to example embodiments disclosed herein;

[0020] Figure 7 is a flow chart depicting a method for increasing the PSRR compensation range in an image sensor by performing phase correction on a correction path according to example embodiments disclosed herein;

[0021] Figure 8 is an example graph depicting PSRR versus pixel pitch according to example embodiments disclosed herein; and

[0022] Fig.9A and Fig. 9B is an example graph depicting improvement in PSRR in an image sensor due to performing amplitude correction and phase correction on power supply noise present on a correction path in simulations and silicon measurements, respectively, according to example embodiments disclosed herein. DETAILED DESCRIPTION

[0023] The example embodiments of this document and their various features and advantageous details are explained more fully with reference to the non-limiting examples shown in the accompanying drawings and described in detail in the following description. Descriptions of well-known components and processing techniques are omitted so as not to confuse the example embodiments herein. The description herein is intended only to facilitate understanding of the manner in which the example embodiments herein may be implemented and to further enable those skilled in the art to implement the example embodiments described herein. Therefore, the present disclosure should not be construed as limiting the scope of the example embodiments described herein.

[0024] Example embodiments herein disclose methods and systems for increasing a power supply rejection ratio (PSRR) range in an image sensor to compensate for a reduced PSRR of an active pixel sensor (APS) array of the image sensor.

[0025] Example embodiments herein disclose methods and systems for increasing the PSRR compensation range in an image sensor by performing amplitude correction and phase delay correction.

[0026] Example embodiments herein disclose methods and systems for integrating a power amplifier in a correction path to perform amplitude correction. Amplitude correction may involve:

[0027] - receiving an analog signal including power supply noise of an APS array on a pixel path and a ramp signal from a ramp signal generator on a correction path;

[0028] - introducing amplified power supply noise into the ramp signal on the correction path; and / or

[0029] - Increasing the PSRR compensation range by canceling the power supply noise of the analog signal present on the pixel path using the amplified power supply noise of the ramp signal present on the correction path to compensate for the PSRR.

[0030] Example embodiments herein disclose methods and systems for performing phase delay correction by matching the phase delay of power supply noise present on the correction path with the phase delay of power supply noise present on the pixel path over a frequency range of interest.

[0031] Referring now to the drawings, and more particularly to Figures 1 to 9B , example embodiments are shown, wherein like reference numerals denote corresponding features consistently throughout the drawings.

[0032] Figure 1 An imaging system 200 according to an example embodiment disclosed herein is depicted. The imaging system 200 referred to herein may be at least one of a digital camera system, an automotive image sensor system, a surveillance image sensor system, a mobile phone, a smart phone, a tablet, a phablet, a personal digital assistant (PDA), a laptop, a computer, a wearable computing device, a vehicle infotainment device, an Internet of Things (IoT) device, a virtual reality (VR) device, and / or any other device capable of capturing an image. In the examples herein, the image may be selected from, but not limited to, at least one of a still image, a moving image, a video, an animation, and the like. The example embodiments herein may use terms such as "image", "picture", "photo", "video", "digital video", "image frame", and the like interchangeably.

[0033] The imaging system 200 may include an image sensor 202, a processor 204, a display 206, an interface 208, and / or a memory 210. The image sensor 202 may be a sensor that may be used to capture an image. In an example embodiment, the image sensor 202 may be, but is not limited to, a complementary metal oxide semiconductor (CMOS) image sensor, a charge coupled device (CCD) image sensor, and the like. The image sensor 202 may be configured to generate an electrical signal by absorbing light reflected by at least one object (e.g., a person, a physical object, etc.), and convert the generated electrical signal into a digital signal. In the image sensor, incident light / absorbed light on a pixel of the image sensor 202 may be converted into electrons. The electrons may be further converted into an analog voltage signal. The analog voltage signal may then be converted into a digital signal using an analog-to-digital converter (ADC). The digital signal may include image data / information for depicting an image corresponding to the amount of light absorbed. The image sensor 202 may provide the captured image to the processor 204.

[0034] The processor 204 may be at least one of a single processor, multiple processors, multiple homogeneous cores, multiple heterogeneous cores, multiple central processing units (CPUs) of different types, etc. The processor 204 may also be an image processing circuit, a microprocessor, a microcontroller, an accelerator, a graphics processing unit, etc. The processor 204 may be configured to perform processing on the received image. The processing of the image may involve at least one of: applying a filter to the image, performing object recognition / face recognition, marking objects recognized in the image, etc.

[0035] Display 206 may be configured to receive processed images from processor 204 and display the processed images (eg, to a user).

[0036] The interface 208 may be configured to enable the processor 204 to transmit the processed image to at least one external device using a communication network, such as but not limited to a server, an external database, a cloud server, a chat application, a social media application / network, etc. Examples of the communication network may include but are not limited to a wired network (local area network (LAN), Ethernet, etc.), a wireless network (Wi-Fi network, cellular network, Wi-Fi hotspot, Bluetooth, Zigbee, etc.), etc.

[0037] The memory 210 may store processed images, captured images, and the like. Examples of the memory 210 may include, but are not limited to, NAND memory, embedded multimedia card (eMMC), secure digital (SD) card, universal serial bus (USB) drive, serial advanced technology attachment (SATA) drive, solid state drive (SSD), and the like. The memory 210 may also include one or more computer-readable storage media. The memory 210 may also include one or more non-volatile storage elements. Examples of non-volatile storage elements may include magnetic hard disks, optical disks, floppy disks, flash memory, and / or electrically programmable memory (EPROM) or electrically erasable programmable memory (EEPROM). In addition, in some examples, the memory 210 may be considered a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier or propagation signal. However, the term "non-transitory" should not be interpreted to mean that the memory 210 is non-removable. In some examples, a non-transitory storage medium may store data that may change over time (e.g., in a random access memory (RAM) and / or cache).

[0038] like Figure 2 As depicted, image sensor 202 includes an active pixel sensor (APS) array 302 , a timing generator 304 , a row driver 306 , a readout circuit 308 , and / or an image signal processor 310 .

[0039] The APS array 302 may include a plurality of pixels 402 (eg, Figure 3 ), the plurality of pixels 402 may be arranged in a row-column matrix. In an example, the row-column matrix may include m rows and n columns, so that the APS array 302 includes (m×n) pixels 402. The APS array 302 may include a certain amount of multiple pixels 402 based on the same size or a resolution of similar size. The size of the pixel 402 may range from sub-micron to tens of microns. In addition, the APS array 302 may be provided with a color filter array having a plurality of color filter elements, which allows a single image sensor 202 to sample light of different colors. The APS array 302 may be configured to absorb light energy using the pixels 402 and convert the absorbed light energy into an electrical / analog signal. The analog signal may be a voltage and / or a current, corresponding to the amount of light energy absorbed.

[0040] The timing generator 304 may be configured to generate timing control signals for operating the pixels 402 of the APS array 302. For example, the timing generator 304 may generate a shutter signal row by row that resets each photodiode of the pixels 402 in that particular row and marks the beginning of the exposure time. The timing generator 304 may also generate a read signal to the row of the APS array 302 that marks the end of the integration time and configures the readout circuit 308 to read the particular row of the APS array 302. The timing generator 304 may also be configured to provide a clock signal to the image sensor 202 and / or at least one other component of the system 200.

[0041] The row driver 306 may be configured to receive a row address from the readout circuit 308 and provide a drive signal to the pixels 402 of the APS array 302 for controlling the pixels 402 of the APS array 302 corresponding to the received row address. Examples of the drive signal may include, but are not limited to, a reset signal (Rx), a pixel selection signal (SEL), a transmission signal (Tx), etc. In an example, the signal Rx may be used to reset the pixels 402 of the APS array 302, the signal SEL may be used to select the pixels 402 of the APS array 302, and the signal Tx may be used to transmit an electrical signal / analog signal from the selected pixel 402 to the readout circuit 308. In the examples herein, the row driver 306 may provide the drive signal to the pixels 402 of the APS array 302 in a row-by-row manner.

[0042] The readout circuit 308 may be configured to receive electrical / analog signals from the pixels 402 of the APS array 302 and convert the analog signals into digital signals. The digital signals may be used to depict an image corresponding to the amount of light absorbed by the pixels 402 of the APS array 302. Example embodiments herein may use terms such as “digital signals,” “digital pixel data,” “digital image data,” etc. interchangeably.

[0043] The readout circuit 308 may include a ramp signal generator 312, a bias circuit 314, multiple column readout circuits / analog-to-digital converters (ADCs) 316, and / or multiple counters 318 for converting analog signals received from pixels 402 of the APS array 302 into digital signals.

[0044] The ramp signal generator 312 may be configured to generate a ramp signal. The ramp signal may be a single slope or a multi-slope ramp signal. The ramp signal may be generated using, but not limited to, a thermometric current steering digital-to-analog converter (DAC), a method of pumping current into a known capacitor, etc. The ramp signal generator 312 may provide the generated ramp signal to the column readout circuit 316.

[0045] The bias circuit 314 may be configured to generate current / bias signals for controlling the plurality of column readout circuits 316 , such as, but not limited to, comparator currents for each readout column, pixel load currents, etc. In an example, a bandgap reference voltage may be used to generate the bias signals.

[0046] The column readout circuit / ADC 316 (which may also be referred to herein as the column readout circuit 316, ADC 316, and / or ADC / column readout circuit) may be connected to multiple columns of the pixels 402 of the APS array 302. In the examples herein, the column readout circuit / ADC 316 may be a column-parallel single-slope ADC. According to some example embodiments, the column readout circuit / ADC 316 may include a column readout circuit and / or an ADC. The column readout circuit / ADC 316 may be configured to receive an electrical signal / analog signal from the respectively connected rows of the pixels 402 of the APS array 302 and a ramp signal from the ramp signal generator 312, and perform a comparison of the analog signal with the ramp signal. The column readout circuit 316 may compare the input analog signal with the ramp signal, and generate an output signal (e.g., an output signal indicating that the ramp signal exceeds the analog signal value, an output signal having a logic value of "1", etc.) when the ramp signal crosses the analog signal value. The counter 318 may be configured to start counting when the column readout circuit 316 is started to compare the analog signal with the ramp signal value. According to an example embodiment, the counter 318 may count the duration of time when no output signal is generated (e.g., by sampling the output signal according to a defined period and adding the number of samples that do not indicate the output signal). The counter 318 may stop counting when the output signal is received from the column readout circuit 316. The column readout circuit 316 and the counter 318 may be configured to operate as a correlated double sampler (CDS), wherein a reset measurement is performed and / or completed before the actual signal measurement. The counter 318 may further subtract the corresponding reset measurement value and the actual signal measurement value, and use the subtracted value as a digital representation of the light absorbed by the pixel 402. The correlated double sampling may remove or reduce mismatches between columns by eliminating offsets and low-frequency noise. The counter 318 may provide a digital representation / digital signal of the light absorbed by the pixel 402 to the image signal processor 310. Image signal processor 310 may be configured to perform at least one processing operation on the received digital signal and / or generate an image corresponding to the amount of light energy absorbed by APS array 302. Examples of processing operations may include, but are not limited to, dark level compensation, digital gain, bad pixel correction, etc.

[0047] Additionally, the analog signal received from the APS array 302 may include power supply noise (due to noise introduced by a power supply coupled to the APS array 302), which may degrade the horizontal noise (HN) performance of the image sensor 202. Figure 3As depicted, in each pixel 402 of the APS array 302, power supply noise can be coupled to a floating diffusion (FD) node 402b through parasitic capacitance 402e and the drain-to-source capacitance of the source follower transistor Tx1. The FD node 402b can be configured to minimize or reduce all capacitances to maximize or increase the conversion gain (CG) of the image sensor 202 (CG measures the ability of the image sensor 202 to convert one electron received from a photodiode (not shown) of a pixel 402 of the image sensor 202 into as large a voltage change as possible). The power supply noise on the FD node 402b can directly reach the output of the pixel 402. The source follower transistor Tx1 is also designed to have a minimum or small size in order to improve the fill factor of the pixel 402. The resulting low output impedance (1 / G ds ) can contribute to the reduction of the power supply rejection ratio (PSRR) of the pixel 402. The PSRR of the APS array 302 can be the ability of the APS array 302 to reject power supply noise in its output analog signal. The PSRR of a pixel array can be measured as the logarithmic ratio of the power supply noise present in its output analog signal to the received / input power supply noise.

[0048] In an example embodiment, to compensate / correct the PSRR, a PSRR compensation circuit / module 314a (also referred to herein as a PSRR compensation circuit) may be integrated within the bias circuit 314. The PSRR compensation circuit 314a may be connected to the column readout circuit / ADC 316. The PSRR compensation circuit 314a may be configured to perform amplitude correction and / or phase delay correction to compensate for the reduced PSRR, thereby increasing the PSRR correction range in the image sensor 202. The PSRR correction range describes (e.g., corresponds to) the compensation capability in the readout circuit 308 for compensating the PSRR of the APS array 302.

[0049] To perform amplitude correction, the PSRR compensation circuit 314a may generate power supply noise that closely matches the power supply noise associated with the APS array 302. In an example embodiment, the PSRR compensation circuit 314a may perform amplification to amplify the amplitude / magnitude of the generated power supply noise in a manner that the amplitude of the generated power supply noise matches the amplitude of the power supply noise of the analog signal received from the pixels 402 of the APS array 302. Example embodiments herein may interchangeably use terms such as “amplified power supply noise,” “guided power supply noise,” “larger power supply noise,” etc. to refer to power supply noise having an amplified amplitude.

[0050] Once the amplified power supply noise is generated, the PSRR compensation circuit 314a can introduce / direct the amplified power supply noise into the ramp signal generated (by the ramp signal generator 312) for the column readout circuit 316 (e.g., combine the power supply noise with the ramp signal and / or add the power supply noise to the ramp signal). Therefore, the column readout circuit 316 can compensate / correct the PSRR of the APS array 302 by canceling the power supply noise present in the received analog signal using the amplified power supply noise (also referred to herein as combined power supply noise) introduced into the ramp signal. Cancelling the power supply noise can involve measuring the difference between the amplitude of the power supply noise of the analog signal and the amplitude of the amplified power supply noise of the ramp signal. Since the amplitude of the amplified power supply noise of the ramp signal is adjusted to match the amplitude of the power supply noise of the analog signal, there can be a difference of approximately zero, assuming that the signal has zero phase delay, which depicts the cancellation of the power supply noise of the analog signal.

[0051] In an example embodiment, the column readout circuit 316 may use the introduction of amplified power supply noise in the ramp signal to compensate / correct for the lowest reduced PSRR (which may be due to lower pixel pitch and / or due to tighter routing constraints). Therefore, compensation for the reduced PSRR of the APS array 302 using amplified power supply noise may significantly increase / improve the PSRR compensation range in the image sensor 202 without affecting performance.

[0052] To perform phase delay correction, the PSRR compensation circuit / module 314a may match the phase delay of the amplified power supply noise in the ramp signal to the phase delay of the power supply noise present in the analog signal provided by the APS array 302 over a frequency range of interest. The frequency range of interest may include one or more expected switching frequencies of a switch mode power supply (SMPS), which may range from a few kHz to tens of MHz.

[0053] Figure 3 An image sensor 202 including a PSRR compensation circuit 314a for increasing a PSRR compensation range in the image sensor 202 by performing amplitude correction is depicted according to example embodiments disclosed herein. Figure 3 As depicted, APS array 302 may include a plurality of pixels 402 configured to output / generate analog signals corresponding to absorbed light energy. Example embodiments herein may use terms such as "pixel," "image sensor pixel," "image pixel," etc. interchangeably.

[0054] Each pixel 402 of the APS array 302 includes a charge detection element / FD region / node 402b, and / or a transfer element 402c. Each pixel 402 of the APS array 302 may also include a photoelectric conversion element (not shown).

[0055] The photoelectric conversion element mentioned herein may be at least one of a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), etc. The photoelectric conversion element may be configured to accumulate a charge corresponding to the absorbed light energy. When a photon of light energy (reflected from an object) hits the surface of the photoelectric conversion element of the pixel 402, a charge carrier may be generated. In this case, a transfer switch (TX) may be used to transfer the generated charge or electron to the FD node 402b. The FD node 402b may collect the generated charge carriers and convert the charge carriers into an output signal / electrical signal / analog signal. The generated analog signal may be output from the pixel 402 to the ADC316 using a source follower transistor Tx1 and a row select switch Tx2. The output signal may be at least one of a voltage, a current, etc. The example embodiments herein consider the output signal as an analog voltage for further explanation, but it is obvious to those skilled in the art that a current may also be considered.

[0056] FD node 402b can be a doped semiconductor region that can store voltage / charge. In the example herein, FD node 402b can be a capacitor (or an intrinsic capacitance of a device) that can store voltage / charge. FD node 402b can be configured to store an analog voltage / charge output by the photoelectric conversion element of pixel 402.

[0057] The transmission element 402c may include one or more switches / transistors configured to transmit the analog voltage stored at the FD node 402b to the ADC 316 of the readout circuit 308. In the example herein, the transmission element may include two transistors Tx1 and Tx2, where Tx1 is a source follower transistor and Tx2 is a row selection switch. The source follower transistor Tx1 may be connected to a power supply and the FD node 402b. The row selection switch Tx2 may be connected to a column line 402d. The column line 402d may be a conductor configured to read the analog voltage of the FD node 402b from the row selection switch Tx2 and provide the read analog voltage to the ADC 316 of the readout circuit 308.

[0058] Pixel 402 may also include parasitic capacitance 402e. Parasitic capacitance 402e may include capacitive coupling between a gate terminal and source and drain terminals of source follower transistor Tx1 of transfer element 402c. In addition, parasitic capacitance 402e may include capacitive coupling between a power supply (not shown) and FD node 402b, which may propagate power supply noise to FD node 402b while providing power to source follower transistor Tx1. Therefore, the analog voltage read from FD node 402b may include variations in the received power supply noise, which reduces the PSRR of APS array 302.

[0059] In an example embodiment, in the APS array 302, upon receiving a driving signal from the row driver 306 (e.g., when the row selection switch Tx2 is turned on), an analog voltage stored at the FD node 402b of the pixel 402 may be transmitted to the readout circuit 308. In order to transmit the analog voltage from the pixel 402 to the readout circuit 308, the row driver 306 may receive a row address from the readout circuit 308, wherein the row address specifies a pixel row 402 among the plurality of pixels 402 to be read. The row driver 306 may send a SEL signal to the APS array 302 to enable selection of the pixel 402 corresponding to the row address to be read in a row-by-row manner. Figure 3 As depicted, the SEL signal may be connected to the gate of the row select switch Tx2. The row driver 306 may further send a Tx signal to the transmission element 402c of the selected pixel 402 to transfer the charge stored in the photodiode to the FD node 402b. Upon receiving the Tx signal, the transistors (Tx1 and Tx2) of the transmission element 402c transmit / buffer the analog voltage stored at the FD node 402b to the readout circuit 308 via the column line 402d. The analog voltage transmitted to the readout circuit 308 includes power supply noise, which reduces the PSRR of the APS array 302.

[0060] The readout circuit 308 may include a plurality of column readout circuits / ADCs 316 connected to the plurality of pixels 402 and / or a bias circuit 314 having a PSRR compensation circuit 314 a for converting analog voltages read from the pixels 402 into digital voltages. The plurality of column readout circuits / ADCs 316 may be connected to the PSRR compensation circuit 314 a of the bias circuit 314.

[0061] The PSRR compensation circuit 314 a may include a bandgap current source 404 a , an amplifier 404 b , one or more capacitors 404 c , and / or a current mirror.

[0062] The bandgap current source 404a may generate a current for operating the column readout circuit / ADC 316. In the example herein, the current source 404a may generate a current of 10 microamperes (μA).

[0063] The amplifier 404b may be configured to generate power supply noise and amplify the generated power supply noise. In an example embodiment, the amplifier 404b may be a configurable gain two-stage power supply noise amplifier. The amplifier 404b may include two stages (such as Figure 4 ). The stages of amplifier 404b can be designed in a manner to provide sufficient power supply noise amplification to compensate for the reduced PSRR of sub-micron pixels. The design of amplifier 404b also minimizes or reduces phase effects caused by limited amplifier bandwidth over the frequency range of interest, and minimizes or reduces horizontal noise (HN) effects. The first stage of amplifier 404b can include a common source amplifier. The second stage of amplifier 404b can include a source follower with a feedforward path to increase gain and minimize or reduce output impedance. The first stage can generate sufficient gain on the power supply noise, but has a large output impedance. When the large output impedance directly drives a large capacitive load (capacitor coupling), the large output impedance may cause a phase lag in the power supply noise, thereby preventing or reducing the optimal or intended cancellation of the power supply noise in the pixel path. In order to prevent or reduce phase effects, the following can be done. Figure 4 A second stage is depicted being added. The second stage may be a P-type metal oxide semiconductor (PMOS) input source follower that provides a low output impedance to drive the capacitive load 404c. A small additional gain may be obtained using a feed forward path and may be used to increase the PSRR compensation range of the compensation circuit.

[0064] One or more capacitors 404c may be configured to be connected to ground or to the output of amplifier 404b. In an example embodiment, PSRR compensation circuit 314a may include multiple capacitors 404c, which are configured based on the amplitude of power supply noise that may be introduced into the ramp signal. In the examples herein, PSRR compensation circuit 314a may include a larger capacitor bank to further increase the PSRR compensation range. One or more capacitors 404c may be configured to be connected to the amplified power supply noise or ground. The ratio of the total capacitance connected to the output of amplifier 404b to the total capacitance including the device capacitance connected to ground represents the attenuation from the output of amplifier 404b to the gate of Mn1 transistor 404e of the current mirror.

[0065] The current mirror can be configured to provide bias voltage to the column readout circuit / ADC 316 and to correct for power supply noise. The current mirror can include multiple transistors. In the examples herein, Figure 3As depicted, the current mirror may include two transistors connected to each other: a first PMOS transistor (Mp1 transistor) and a first N-type metal oxide semiconductor (NMOS) transistor (Mn1 transistor). Mn1 transistor 404e (the gate of Mn1 transistor 404e) may be coupled to capacitor 404c. Mn1 transistor 404e may be configured to receive amplified power supply noise associated with the output of amplifier 404b at its gate (the gate of Mn1 transistor 404e), which already has a bias voltage that may be sampled at the start of analog-to-digital conversion. Mn1 transistor 404e may provide a bias current and amplified power supply noise to Mp1 transistor 404d. Mp1 transistor 404d may further forward the received current and amplified power supply noise to column readout circuit 316.

[0066] Each column readout circuit / ADC 316 may include a current source 406a, a buffer transistor 406b, and / or a comparator 406c. The current source 406a may be configured to provide a current for biasing the analog voltage of the pixel 402 received via the column line 402d. The amount of current provided by the current source 406a may determine the strength of the source follower transistor Tx1 in the pixel 402.

[0067] The buffer transistor 406b can be coupled to the ramp signal generator 312 and the PSRR compensation circuit 314a. Figure 3 As shown, the buffer transistor 406b may include two transistors connected to each other, for example, a second PMOS transistor (Mp2 transistor) and a third PMOS transistor (Mp3 transistor). The Mp2 transistor may be connected to the ramp signal generator 312, and the Mp3 transistor may be connected to the Mp1 transistor 404d of the PSRR compensation circuit / module 314a. The Mp3 and Mp2 transistors may be configured to buffer a ramp signal (e.g., considered as a ramp voltage hereinafter) received from the ramp signal generator 312. The Mp3 transistor may receive current and amplified power supply noise from the Mp1 transistor 404d of the PSRR compensation circuit 314a. The Mp3 transistor may introduce / guide the received amplified power supply noise into the buffered ramp signal / ramp buffer output, and the Mp2 transistor may forward the ramp buffer output including the amplified power supply noise to the comparator 406c.

[0068] Comparator 406c can receive an analog voltage (including power supply noise) from FD node 402b of connected pixel 402 through column line 402d at the positive terminal. The path including receiving the analog voltage at the positive terminal of comparator 406c can be referred to as a pixel path in this article. Comparator 406c can also receive a ramp voltage (including amplified power supply noise) from buffer transistor 406b at its negative terminal. The signal path including the following items can be referred to as a correction path in this article: receiving amplified power supply noise at ramp buffer transistor 406b; introducing amplified power supply noise into ramp voltage by buffer transistor 406b; and receiving a ramp voltage including amplified power supply noise at the negative terminal of comparator 406c.

[0069] The comparator 406c may be configured to perform a comparison of the analog voltage of the pixel 402 with a ramp voltage (e.g., a voltage used to convert the analog voltage into a digital voltage), and measure the difference between the analog voltage and the ramp voltage. The comparator 406c may compensate for the reduced PSRR of the APS array 302 by eliminating the power supply noise of the analog voltage of the pixel 402 while performing the comparison. The comparator 406c may eliminate the power supply noise by performing a subtraction of the amplitude of the power supply noise of the analog voltage of the pixel 402 from the amplitude of the amplified power supply noise of the ramp voltage. In an example embodiment, due to the introduction of the amplified power supply noise on the correction path, the PSRR compensation range of the comparator 406c in the image sensor 202 may be increased and / or improved. In an example embodiment, the PSRR compensation range in the image sensor 202 may be measured based on the gain of the amplifier and the transconductance and / or impedance of the Mp1 transistor 404d and the Mn1 transistor 404e. In the examples herein, the total PSRR compensation range may be measured as:

[0070]

[0071] Where A represents the gain of amplifier 404b, and represents the ratio of the transconductance and / or impedance of the Mp1 transistor 404d and the Mn1 transistor 404e for the normalized current.

[0072] Figure 4 An amplifier 404 b of the PSRR compensation circuit 314 a is depicted according to example embodiments disclosed herein.

[0073] Amplifier 404b may be configured to amplify power supply noise. In an example embodiment, amplifier 404b may be a power supply noise amplifier 404b, which may be a configurable gain two-stage amplifier. Amplifier 404b may include two stages connected to a power supply / current source 502 coupled to a transistor, wherein the first stage 504 may include a common source amplifier and the second stage 506 may include a source follower with a feed-forward path to increase gain and minimize or reduce output impedance. In the example herein, current source 502 may be configured to provide 150 μA of current to the first stage 504 and the second stage 506 of amplifier 404b.

[0074] The first stage 504 may include a capacitor 504a, a transistor 504b, and / or a resistor 504c. One terminal of the capacitor 504a may be connected to the gate of the fourth PMOS transistor (Mp4 transistor) 504b, and the other terminal may be connected to ground. The capacitor 504a may provide power supply noise as a current in the Mp4 transistor 504b, and the current is terminated using a resistor 504c. The source and drain of the Mp4 transistor may be connected to an external power supply and a resistor 504c, respectively. In the example of this article, the resistor 504c may be a resistor with a medium or large resistance value (e.g., 1.2Kohm). The current source 502 may provide a bias voltage (as shown) to the amplifier 404b or in the amplifier 404b, and then the bias voltage may be sampled on the gate of the Mp4 transistor. The Mp4 transistor may amplify the power supply noise together with the resistor 504c. The amplified power supply noise may be provided as a current in the Mp4 transistor, and then the current is terminated using a resistor 504c. Therefore, the gain of the power supply noise provided by the first stage 504 can be calculated as Where R is the 504c resistor.

[0075] The second stage 506 may be a source follower stage with a small feed-forward gain. In the example herein, the source follower stage 506 may include two P-type NMOS transistors (a fifth PMOS transistor (Mp5 transistor) and a sixth PMOS transistor (Mp6 transistor)). The Mp5 and Mp6 transistors may be source follower transistors. The Mp5 and Mp6 transistors may be connected to the first stage 504. The Mp5 and Mp6 transistors may be configured to receive amplified power supply noise from the first stage 504 by connecting to a component of the first stage 504. The Mp5 and Mp6 transistors may also be configured to forward the received amplified power supply noise to one or more capacitors 404c of the PSRR compensation circuit 314a. This may be advantageous because the first stage 504 may not be able to drive the amplified power supply noise to the one or more capacitors 404c due to its large resistance, and there is no significant phase lag. According to an example embodiment, the second stage 506 may forward the received amplifier power supply noise to the one or more capacitors 404c without phase delay within the frequency range of interest.

[0076] In an example embodiment, the introduction of amplified power supply noise on the correction path by amplifier 404b can increase the PSRR compensation range in image sensor 202. The PSRR compensation range can depend on the gain of amplifier 404b. For example, if "A" is the gain of amplifier 404b, the PSRR compensation range can be improved by "A" times. The gain (A) of amplifier 404b can be measured using the following formula:

[0077]

[0078] in, represents the transconductance of transistor Mp4, R represents the resistance of resistor 504c, Represents the ratio of the transconductance of the Mp5 transistor to the Mp6 transistor.

[0079] Figure 5An image sensor 202 including a PSRR compensation circuit 314a for performing phase correction to increase the PSRR compensation range in the image sensor 202 is depicted according to example embodiments disclosed herein. Example embodiments herein enable the PSRR compensation circuit 314a to match the phase delay of the amplified power supply noise introduced on the correction path with the phase delay of the power supply noise introduced by the pixel on the pixel path within a frequency range of interest. The frequency range of interest may be the expected switching frequency of the SMPS, which may range from a few kHz to tens of MHz. The readout circuit 308 may implement a correlated double sampler (CDS), in which the signal voltage and the reset voltage are measured within a small time delay between them, which effectively eliminates or reduces low frequency power supply noise. In addition, the comparator 406c used in the column readout circuit / ADC 316 of the readout circuit 308 may have a low pass characteristic to remove or reduce high frequency noise. Therefore, the effective frequency compensation range is between low-pass and high-pass cutoffs, where power supply noise can directly affect performance, and the effective frequency compensation range can vary from about 50 kHz to 2 MHz-3 MHz based on the design architecture, timing, etc. of the image sensor 202 .

[0080] like Figure 5 As depicted, the current mirror of the PSRR compensation circuit 314a can be connected via a wire (at Figure 5 4 (depicted as “Line A” in FIG. 4 ) is connected to a buffer transistor 406 b of the column readout circuit 316. Line A may be a conductive line that passes through all column readout circuits connected to all pixels 402. Line A may include parasitic elements, such as, but not limited to, resistors, capacitors, etc. When the current mirror of the PSRR compensation circuit 314 a provides power and amplified power supply noise to the buffer transistor 406 b of the column readout circuit 316 through Line A, Line A may introduce a resistor-capacitor (RC) phase delay on the correction path due to the parasitic elements of Line A and the transconductance of the MP1 transistor 404 d.

[0081] In an example embodiment, the PSRR compensation circuit 314a can perform phase correction by matching the RC phase delay on the correction path with the phase delay on the pixel path. The PSRR compensation circuit 314a can configure the RC phase delay on the correction path to match the phase delay on the pixel path by controlling the impedance and / or transconductance of the Mp1 transistor 404d of the current mirror. The PSRR compensation circuit 314a can control the impedance of the Mp1 transistor 404d by modifying the configuration of the Mp1 transistor 404d. In an example embodiment herein, modifying the configuration of the Mp1 transistor 404d can involve changing the size and / or multiplier of the Mp1 transistor 404d, where the Mn1 transistor 404e has a similar size change. In an example embodiment, the size / multiplier of the Mn1 transistor 404e can be changed in similar proportions so that the power / current provided to the buffer transistor 406b of the column readout circuit 316 can be unchanged or similar.

[0082] Figures 2 to 5 Example components of image sensor 202 are shown, but it should be understood that example embodiments are not limited thereto. In example embodiments, image sensor 202 may include fewer or more components. In addition, the labels or names of the components are for illustrative purposes only and do not limit the scope of example embodiments. One or more components may be combined together to perform the same or substantially similar functions in image sensor 202.

[0083] Figure 6 is a flow chart depicting a method 700 for increasing the PSRR compensation range in the image sensor 202 by performing an amplitude / magnitude correction on a correction path according to example embodiments disclosed herein.

[0084] At operation 702, the pixel 402 may accumulate charge generated by absorbing light energy reflected from an object and convert the accumulated charge into an electrical / analog signal. At operation 704, the column readout circuit / ADC 316 connected to the pixel 402 may read the analog signal from the pixel 402 on the pixel path. The read analog signal includes power supply noise introduced by the pixel 402, which may reduce the PSRR of the APS array 302.

[0085] At operation 706, the PSRR compensation circuit 314a may generate power supply noise that closely matches the power supply noise introduced by the pixel 402 and amplify the generated power supply noise. The generated power supply noise may be amplified in such a way that its amplitude closely matches the amplitude of the analog signal received on the pixel path.

[0086] At operation 708, the PSRR compensation circuit 314a may introduce the amplified power supply noise into the ramp signal buffered in the buffer transistor 406b of the column readout circuit 316. At operation 710, the column readout circuit 316 may receive the ramp signal including the amplified power supply noise from its buffer transistor 406b on the correction path.

[0087] At operation 712, the column readout circuit 316 may compensate for the reduced PSRR of the APS array 302 by subtracting the power supply noise of the analog signal from the amplified power supply noise of the ramp signal. The column readout circuit 316 may compare the amplitude of the power supply noise of the analog signal received on the pixel path with the ramp signal together with the amplified power supply noise and cancel the power supply noise of the analog signal because the amplitude of the amplified power supply noise of the ramp signal closely matches the amplitude of the analog signal. Thus, the reduced PSRR of the APS array 302 is compensated by the increased PSRR compensation range. The different operations 702 to 712 may be performed in the order presented, in a different order, or simultaneously or concurrently. Furthermore, in example embodiments, the operations 702 to 712 may be omitted. Figure 6 Some of the actions listed in .

[0088] Figure 7 is a flow chart depicting a method 800 for increasing the PSRR compensation range in image sensor 202 by performing phase correction on a correction path according to example embodiments disclosed herein.

[0089] At operation 802, line A connecting the PSRR compensation circuit 314a to the column readout circuit 316 may generate a phase delay on the correction path due to its parasitic elements.

[0090] At operation 804, the PSRR compensation circuit 314a may use the phase delay generated on the correction path and the phase delay introduced on the pixel path to modify the configuration of the Mp1 transistor 404d of the current mirror (in a similar proportion to the proportion of the Mn1 transistor 404e). The configuration may include a size / multiplier of the Mp1 transistor 404d.

[0091] At operation 806, the PSRR compensation circuit 314a may control the impedance of the Mp1 transistor 404d based on the modified configuration so that the phase delay on the correction path may be configured to match or be similar to the phase delay on the pixel path. The various operations 802 to 806 may be performed in the order presented, in a different order, or simultaneously or contemporaneously. Furthermore, in example embodiments, the operation 802 to 806 may be omitted. Figure 7 Some of the actions listed in .

[0092] Figure 8is an example graph depicting PSRR versus pixel pitch according to example embodiments disclosed herein. Conventional approaches may have limited scope for compensating for the lowest reduced PSRR due to reduced pixel size. In contrast, example embodiments herein compensate for the lowest reduced PSRR due to reduced size of pixels 402 of APS array 302. The lowest reduced PSRR may be compensated / corrected by performing amplitude correction and / or phase correction of power supply noise on a correction path. Figure 8 The PSRR compensation range for compensating for the reduced PSRR due to the reduction in pixel size is depicted in FIG.

[0093] Fig.9A and Fig. 9B is an example graph depicting improvement in PSRR in image sensor 202 due to performing amplitude correction and phase correction on power supply noise present on a correction path according to example embodiments disclosed herein.

[0094] Conventional devices for compensating the PSRR of an APS array have an insufficient PSRR compensation range and cannot adequately compensate the PSRR of an APS array having pixels in the sub-micron size range.

[0095] However, example embodiments provide for introducing amplified power supply noise on the correction path, thereby enabling an increase and / or improvement in the PSRR compensation range of the comparator 406c in the image sensor 202 (e.g., the PSRR compensation range corresponds to the gain of the amplifier 404b and the transconductance and / or impedance of the Mp1 transistor 404d and the Mn1 transistor 404e). Therefore, the example embodiments herein increase the range of the power supply rejection ratio (PSRR) compensation method used by the image sensor, which is advantageous for APS arrays with sub-micron pixels having a lower PSRR than APS arrays supported by existing / conventional designs. The example embodiments herein ensure that as the correction range increases, the design of sub-micron pixels can be performed without or with less PSRR constraints. Matching the amplitude and phase between the actual power supply noise path and the correction path helps to obtain high PSRR levels. The example embodiments disclosed herein increase the range of the PSRR compensation method without affecting other sensor performance parameters and the area / power of the image sensor.

[0096] The embodiments disclosed herein may be implemented by running at least one software program on at least one hardware device to control elements. Figures 1 to 5 The elements shown may be at least one of a hardware device or a combination of a hardware device and a software module.

[0097] In an example embodiment, the operations described herein by the imaging system 200, the image sensor 202, the processor 204, the APS array 302, the timing generator 304, the row driver 306, the readout circuit 308, the image signal processor 310, the ramp signal generator 312, the bias circuit 314, the multiple column readout circuits / ADC converters 316, the multiple counters 318, the PSRR compensation circuit 314a, the charge detection element / FD region / node 402b, the transmission element 402c, the comparator 406c and / or the amplifier 404b can be performed by a processing circuit. The term "processing circuit" as used in the present disclosure may refer to, for example, hardware including logic circuits; a hardware / software combination such as a processor that executes software; or a combination of the two. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0098] The various operations of the above methods can be performed by any suitable device (e.g., processing circuit) capable of performing the operations. For example, the operations of the above methods can be performed by various hardware and / or software implemented in some form of hardware (e.g., processor, ASIC, etc.).

[0099] Software may include an ordered listing of executable instructions for implementing logical functions and may be embodied in any "processor readable medium" for use by or in conjunction with an instruction execution system, apparatus or device (e.g., a single-core or multi-core processor or a system containing a processor).

[0100] The blocks or operations of the methods or algorithms and functions described in conjunction with the example embodiments disclosed herein may be implemented directly in hardware, in software modules executed by a processor, or in a combination of the two. If implemented in software, the functions may be stored as one or more instructions or codes on or transmitted through a tangible, non-transitory computer-readable medium. The software module may reside in a random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0101] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or intervening elements may be present. As used herein, the term "and / or" includes any and all combinations of one or more items listed in the association.

[0102] Example embodiments may be described with reference to actions and symbolic representations (e.g., in the form of flow charts, flow diagrams, data flow diagrams, structure diagrams, block diagrams, etc.) of operations that may be implemented in conjunction with units and / or devices discussed in greater detail below. Although discussed in a particular manner, the functions or operations specified in a particular block may be performed in a manner different from the processes specified in the flow charts, flow diagrams, etc. For example, functions or operations shown as being performed serially in two consecutive blocks may actually be performed in parallel, simultaneously, or in some cases in a reverse order.

[0103] The above description of the example embodiments fully reveals the general nature of the example embodiments of this document, so that other technicians can easily modify these example embodiments and / or adjust them for various applications without departing from the overall concept by applying existing knowledge, and such adjustments and modifications should and are intended to be included in the meaning and scope of the equivalents of the disclosed example embodiments. It is understood that the phrases or terms used herein are for descriptive purposes and not restrictive. Therefore, although the example embodiments of this document have been described according to examples, those skilled in the art will recognize that the examples of this document can be practiced by modification within the spirit and scope of the example embodiments as described herein.

Claims

1. A method for compensating a power supply rejection ratio (PSRR) in an image sensor, the method comprising: receiving, by a processing circuit, at least one analog signal from an active pixel sensor (APS) array, the at least one analog signal comprising power supply noise; combining, by the processing circuit, the amplified power supply noise with at least one ramp signal to obtain a combined power supply noise; as well as compensating, by the processing circuit, a PSRR of the APS array by canceling power supply noise of the at least one analog signal using the combined power supply noise, wherein the combining comprises amplifying the generated power supply noise using an amplifier to generate the amplified power supply noise, The amplifier comprises a first stage and a second stage, the first stage comprising a common source amplifier, the second stage comprising a source follower having a feedforward path, The first level includes: a capacitor connected between the first node and a ground node; a first transistor including a gate connected to the first node, a first terminal connected to a power supply node, and a second terminal; and a resistor connected between the second terminal of the first transistor and the ground node, and Wherein, the second level includes: a second transistor including a gate connected to the first node, a first terminal connected to the power supply node, and a second terminal; and A third transistor includes a gate connected to the second terminal of the first transistor, a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the ground node.

2. The method according to claim 1, wherein: The APS array includes a plurality of pixels arranged in a plurality of rows and columns for generating the at least one analog signal in response to absorbed light energy.

3. The method according to claim 1, wherein: Receiving the at least one analog signal comprises: reading the at least one analog signal from at least one column of the APS array, the APS array comprising a plurality of pixels, the power supply noise reducing a PSRR of the APS array; and The method further comprises: receiving the at least one ramp signal, and The at least one ramp signal is buffered using a buffer transistor.

4. The method according to claim 3, wherein: The at least one ramp signal includes a single slope ramp signal or a multi-slope ramp signal.

5. The method according to claim 3, wherein: The buffer transistor includes a first P-type metal oxide semiconductor (PMOS) transistor and a second PMOS transistor.

6. The method according to claim 1, wherein: The combination includes: generating the generated power supply noise to match the power supply noise of the at least one analog signal; and The amplified power supply noise is combined with the at least one ramp signal by introducing the amplified power supply noise into the at least one ramp signal buffered in a buffer transistor using at least one capacitor and a current mirror.

7. The method according to claim 6, wherein: The common-source amplifier is configured to generate the amplified power supply noise; as well as The source follower having the feed-forward path is configured to forward the amplified power supply noise to the at least one capacitor without phase delay within a frequency range.

8. The method according to claim 6, wherein: The current mirror includes a first N-type metal oxide semiconductor (NMOS) transistor Mn1 and a third PMOS transistor Mp1 connected to the at least one capacitor.

9. The method according to claim 8, further comprising: receiving, by the Mn1 transistor, the amplified power supply noise from the at least one capacitor; providing the amplified power supply noise together with a bias voltage to the Mp1 transistor by the Mn1 transistor; as well as The amplified power supply noise is provided to the buffer transistor together with the bias voltage by the Mp1 transistor.

10. The method according to claim 1, wherein: Eliminating power supply noise of the at least one analog signal comprises: The amplitude of the power supply noise of the at least one analog signal is subtracted from the amplitude of the combined power supply noise.

11. The method according to claim 1, further comprising: The PSRR of the APS array is compensated by the processing circuit by matching a phase delay of the combined power supply noise to a phase delay of the power supply noise of the at least one analog signal over a frequency range.

12. The method according to claim 11, wherein: the combining combining the amplified power supply noise with the at least one ramp signal by introducing the amplified power supply noise into the at least one ramp signal buffered in a buffer transistor using at least one capacitor and a current mirror, the current mirror comprising a third PMOS transistor Mp1 transistor connected to the at least one capacitor; as well as Matching the phase delay comprises: modifying a configuration of the Mp1 transistor based on a phase delay of power supply noise of the at least one analog signal, the configuration comprising a multiplier of the Mp1 transistor, and An impedance of the Mp1 transistor is controlled based on the configuration to match a phase delay of the combined power supply noise with a phase delay of the at least one analog signal.

13. An image sensor, comprising: Active pixel sensor APS array; as well as A readout circuit is coupled to the APS array, the readout circuit being configured to compensate for a power supply rejection ratio (PSRR) of the APS array by: receiving at least one analog signal from the APS array, the at least one analog signal comprising power supply noise, combining the amplified power supply noise with at least one ramp signal to obtain combined power supply noise, and canceling power supply noise of the at least one analog signal using the combined power supply noise, wherein the combining comprises amplifying the generated power supply noise using an amplifier to generate the amplified power supply noise, The amplifier comprises a first stage and a second stage, the first stage comprising a common source amplifier, the second stage comprising a source follower having a feedforward path, The first level includes: a capacitor connected between the first node and a ground node; a first transistor including a gate connected to the first node, a first terminal connected to a power supply node, and a second terminal; and a resistor connected between the second terminal of the first transistor and the ground node, and Wherein, the second level includes: a second transistor including a gate connected to the first node, a first terminal connected to the power supply node, and a second terminal; and A third transistor includes a gate connected to the second terminal of the first transistor, a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the ground node.

14. The image sensor according to claim 13, wherein: The APS array includes a plurality of pixels arranged in a plurality of rows and columns for generating the at least one analog signal in response to absorbed light energy.

15. The image sensor according to claim 13, wherein: The readout circuit comprises: A plurality of analog-to-digital converters (ADCs) are connected to a plurality of columns of the APS array, the plurality of columns comprising a plurality of pixels, wherein each of the plurality of ADCs is configured to: receiving the at least one analog signal by reading the at least one analog signal from at least one of the plurality of columns of the APS array, the power supply noise reducing a PSRR of the APS array, receiving the at least one ramp signal, and The at least one ramp signal is buffered using a buffer transistor.

16. The image sensor according to claim 15, wherein: The at least one ramp signal includes a single slope ramp signal or a multi-slope ramp signal.

17. The image sensor according to claim 15, wherein: The buffer transistor includes a first P-type metal oxide semiconductor (PMOS) transistor and a second PMOS transistor.

18. The image sensor according to claim 13, wherein: The readout circuit includes the amplifier.

19. The image sensor according to claim 18, wherein: The readout circuit is configured as: generating the generated power supply noise that matches the power supply noise of the at least one analog signal; as well as The amplified power supply noise is combined with the at least one ramp signal by introducing the amplified power supply noise into the at least one ramp signal buffered in a buffer transistor using at least one capacitor and a current mirror.

20. The image sensor according to claim 19, wherein: The common-source amplifier is configured to generate the amplified power supply noise; as well as The source follower having the feed-forward path is configured to forward the amplified power supply noise to the at least one capacitor without phase delay within a frequency range.

21. The image sensor according to claim 19, wherein: The current mirror includes a first N-type metal oxide semiconductor (NMOS) transistor Mn1 and a third PMOS transistor Mp1 connected to the at least one capacitor.

22. The image sensor according to claim 21, wherein: The Mn1 transistor is configured as: receiving the amplified power supply noise from the at least one capacitor, and providing the amplified power supply noise together with a bias voltage to the Mp1 transistor; as well as The Mp1 transistor is configured to provide the amplified power supply noise together with the bias voltage to the buffer transistor.

23. The image sensor according to claim 13, wherein: The readout circuit comprises: a plurality of analog-to-digital converters (ADCs) connected to a plurality of columns of the APS array, the plurality of columns comprising a plurality of pixels, each of the plurality of ADCs comprising a comparator, the comparator being configured to use the combined power supply noise to cancel power supply noise of the at least one analog signal by: receiving the at least one analog signal including the power supply noise at a positive terminal; receiving the combined power supply noise at a negative terminal; and The power supply noise of the at least one analog signal is cancelled by subtracting the amplitude of the power supply noise of the at least one analog signal from the amplitude of the combined power supply noise.

24. The image sensor according to claim 13, wherein: The readout circuit is configured as: The PSRR of the APS array is compensated by matching a phase delay of the combined power supply noise to a phase delay of the power supply noise of the at least one analog signal over a frequency range.

25. The image sensor according to claim 24, wherein: The readout circuit is configured as: combining the amplified power supply noise with the at least one ramp signal by introducing the amplified power supply noise into the at least one ramp signal buffered in a buffer transistor using at least one capacitor and a current mirror, the current mirror comprising a third PMOS transistor Mp1 transistor connected to the at least one capacitor; modifying a configuration of the Mp1 transistor based on a phase delay of power supply noise of the at least one analog signal, the configuration comprising a multiplier of the Mp1 transistor; as well as The impedance of the Mp1 transistor is controlled based on the configuration to match a phase delay of the amplified power supply noise with a phase delay of the at least one analog signal.

26. A power supply rejection ratio (PSRR) compensation circuit in an image sensor, the image sensor comprising an active pixel sensor (APS) array and a plurality of analog-to-digital converters (ADCs) connected to the APS array, the PSRR compensation circuit being configured as follows: generating the generated power supply noise on a correction path based on reading at least one analog signal from the APS array at each of the plurality of ADCs, and compensating the PSRR of the APS array by performing amplitude correction and phase correction on the generated power supply noise, in, The PSRR compensation circuit is configured to amplify the generated power supply noise using an amplifier to generate amplified power supply noise, The amplifier comprises a first stage and a second stage, the first stage comprising a common source amplifier, the second stage comprising a source follower having a feedforward path, The first level includes: a capacitor connected between the first node and a ground node; a first transistor including a gate connected to the first node, a first terminal connected to a power supply node, and a second terminal; and a resistor connected between the second terminal of the first transistor and the ground node, and Wherein, the second level includes: a second transistor including a gate connected to the first node, a first terminal connected to the power supply node, and a second terminal; and A third transistor includes a gate connected to the second terminal of the first transistor, a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the ground node.

27. The PSRR compensation circuit according to claim 26, wherein: The PSRR compensation circuit is configured to perform the amplitude correction by: generating the amplified power supply noise by amplifying the generated power supply noise to match the power supply noise of the at least one analog signal; as well as The amplified power supply noise is introduced into at least one ramp signal buffered in a buffer transistor of each of the plurality of ADCs on the correction path through at least one capacitor and a current mirror, and each of the plurality of ADCs compensates for the PSRR of the APS array by canceling power supply noise of the at least one analog signal based on the amplified power supply noise introduced into the at least one ramp signal on the correction path.

28. The PSRR compensation circuit according to claim 27, wherein: The common-source amplifier is configured to generate the amplified power supply noise; as well as The source follower having the feed-forward path is configured to forward the amplified power supply noise to the at least one capacitor.

29. The PSRR compensation circuit according to claim 27, wherein: The PSRR compensation circuit is configured to perform the phase correction by: modifying a configuration of an Mp1 transistor of a current mirror on the correction path based on a phase delay of power supply noise of the at least one analog signal, the Mp1 transistor being a P-type metal oxide semiconductor (PMOS) transistor, the configuration comprising a multiplier of the Mp1 transistor; as well as The impedance of the Mp1 transistor is controlled based on the configuration to match a phase delay of the amplified power supply noise with a phase delay of the power supply noise of the at least one analog signal.

30. An image sensor comprising: Active pixel sensor APS array; A plurality of analog-to-digital converters ADC connected to the APS array; as well as The power supply rejection ratio PSRR compensation circuit is configured as: generating the generated power supply noise on a correction path based on reading at least one analog signal from the APS array by each of the plurality of ADCs, and compensating the PSRR of the APS array by performing amplitude correction and phase correction on the generated power supply noise, wherein the PSRR compensation circuit is configured to amplify the generated power supply noise using an amplifier to generate amplified power supply noise, The amplifier comprises a first stage and a second stage, the first stage comprising a common source amplifier, the second stage comprising a source follower having a feedforward path, The first level includes: a capacitor connected between the first node and a ground node; a first transistor including a gate connected to the first node, a first terminal connected to a power supply node, and a second terminal; and a resistor connected between the second terminal of the first transistor and the ground node, and Wherein, the second level includes: a second transistor including a gate connected to the first node, a first terminal connected to the power supply node, and a second terminal; and A third transistor includes a gate connected to the second terminal of the first transistor, a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the ground node.

31. The image sensor according to claim 30, wherein: Each ADC is configured as: reading at least one analog voltage from at least one column of the APS array, the at least one column comprising a plurality of pixels, the at least one analog signal comprising power supply noise that reduces a PSRR of the APS array; reading at least one ramp signal; as well as The at least one ramp signal is buffered on the correction path using a buffer transistor.

32. The image sensor according to claim 30, wherein: The PSRR compensation circuit is configured to perform the amplitude correction by: generating the amplified power supply noise by amplifying the generated power supply noise to match the power supply noise of the at least one analog signal; as well as The amplified power supply noise is introduced into at least one ramp signal buffered in a buffer transistor of each of the plurality of ADCs on the correction path through at least one capacitor and a current mirror.

33. The image sensor according to claim 32, wherein: Each of the plurality of ADCs is configured to: The PSRR of the APS array is compensated by canceling power supply noise of the at least one analog signal based on the amplified power supply noise introduced into the at least one ramp signal on the correction path.

34. The image sensor according to claim 32, wherein: The PSRR compensation circuit is configured to perform the phase correction by: modifying a configuration of an Mp1 transistor of a current mirror on the correction path based on a phase delay of power supply noise of the at least one analog signal, the Mp1 transistor being a P-type metal oxide semiconductor (PMOS) transistor, the configuration comprising a multiplier of the Mp1 transistor; as well as The impedance of the Mp1 transistor is controlled based on the configuration to match a phase delay of the amplified power supply noise with a phase delay of the power supply noise of the at least one analog signal.

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