A method for automatic identification of address width

Abstract

The present invention provides a method for automatic address width identification, comprising the following steps: S1, pre-storing a sequence of known order in the 0 address space of SPI flash; S2, an SPI master device sends a command to read data from address 0, assuming that the address width is N; the actual address width of the SPI flash is addr; S3, after the SPI slave device parses the read command and the actual address width, it returns the data sequence corresponding to address 0 at the next clock; S4, the SPI master device receives data after the Nth 0 is sent; wherein, the SPI master device will discard discarded data, and the actual address width of the SPI flash is obtained according to addr=N-discarded. The present invention is to automatically identify the address width of the SPI Flash, and a simple method can be used to operate SPI flash devices with different address widths.

Description

Technical Field

[0001] The invention relates to the field of communications, and in particular to a method for automatically identifying address width. Background Art

[0002] With the continuous development of science and technology, SPI technology is becoming more and more widely used. SPI is the abbreviation of Serial Peripheral interface, which means serial peripheral interface. SPI is a communication interface. SPI Flash is a Flash that uses SPI communication. SPI interface is mainly used in EEPROM, FLASH, real-time clock, AD converter, and between digital signal processor and digital signal decoder. SPI is a high-speed, full-duplex, synchronous communication bus, and only occupies four wires on the chip pins, which saves the chip pins and saves space on the PCB layout, providing convenience.

[0003] The communication principle of SPI works in master-slave mode. This mode usually has one master device and one or more slave devices, and requires at least 4 wires. They are common to all SPI-based devices, namely SDI (data input), which is the master device data input and slave device data output; SDO (data output), which is the master device data output and slave device data input; SCK (clock), which is the clock signal generated by the master device; CS (chip select), which is the slave device enable signal, controlled by the master device.

[0004] Among them, CS controls whether the chip is selected, that is, only when the chip select signal is a pre-defined enable signal (high potential or low potential), the operation of this chip is valid. This allows multiple SPI devices to be connected on the same bus. Next are the three lines responsible for communication. Communication is completed through data exchange. SPI is a serial communication protocol, which means that data is transmitted one bit at a time. The clock pulse is provided by SCK, and SDI and SDO complete the data transmission based on this pulse. Data output is through the SDO line, and the data changes at the rising or falling edge of the clock, and is read at the next falling or rising edge. The same principle is used for input to complete one bit of data transmission. In this way, 8 bits of data can be transmitted after at least 8 changes in the clock signal (one rising edge and one falling edge).

[0005] The internal hardware of the SPI interface is actually two simple shift registers. The data transmitted is 8 bits. Under the slave enable signal and shift pulse generated by the master device, the high bit is first and the low bit is last. The data changes on the falling edge of SCLK, and one bit of data is stored in the shift register at the same time.

[0006] However, SPI Flash devices currently lack a unified protocol specification. SPI flashes of different manufacturers, models, and capacities have different address widths. When the system is powered on and booted through the SPI flash, or when reading and writing SPI flash devices, the address width of the SPI flash needs to be known in advance and filled into the boot code bootrom. Moreover, when the chip is mass-produced, the bootrom is fixed and does not support modification or expansion. It can only support a few fixed SPI flashes.

[0007] This requires knowing the address width of the SPI flash and using the corresponding fixed code. Only SPI flash devices with the same address width can be operated, which leads to compatibility issues with SPI flash devices with different address widths. Summary of the invention

[0008] In order to solve the above problems in the prior art, the purpose of the present invention is to automatically identify the address width of SPI Flash and operate SPI flash devices with different address widths in a simple way.

[0009] The present invention provides a method for automatically identifying address width, comprising the following steps:

[0010] S1, pre-store a sequence of known order in the 0 address space of the SPI flash;

[0011] S2, the SPI master sends a command to read data from address 0, assuming the address width is N;

[0012] The actual address width of SPI flash is addr;

[0013] S3, after the SPI slave device parses the read command and the actual address width, it sends the data to the next clock ( Figure 1 Point d) returns the data sequence corresponding to address 0;

[0014] S4, the SPI master receives data after the Nth 0 is sent ( Figure 1 middle point e);

[0015] Among them, the SPI master device will discard discarded data, and the actual address width of the SPIflash can be obtained according to addr=N-discarded.

[0016] The N is larger than the actual SPI flash address width.

[0017] The sequence of known order is a fixed sequence, and the position of each element in the sequence is fixed.

[0018] The value of the address 0 in step S1 is not affected by the address width.

[0019] In the step S4, the number of discarded data discarded can be calculated in sequence according to the position of the first data read by the master device in the known sequence.

[0020] The address width N is the maximum address width.

[0021] The address width N in step S1 is X zeros, where X is an integer.

[0022] The command for reading data in step S2 is a single-line read command.

[0023] The advantage of this application is that the compatibility problem can be solved by a simple method, which greatly reduces the cost and improves the efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present invention, constitute a part of this application, and do not constitute a limitation of the present invention.

[0025] Figure 1 is a schematic block diagram of the method of the present invention.

[0026] Figure 2 is a flow chart of the method of the present invention.

[0027] Figure 3 It is a schematic diagram of a specific embodiment of the present invention. DETAILED DESCRIPTION

[0028] At present, the commonly used technical terms in this technical field include:

[0029] Flash: A type of non-volatile memory.

[0030] SPI flash: A flash device that uses the SPI interface.

[0031] Bootrom: A boot code embedded in the chip.

[0032] The internal hardware of the SPI interface is actually two simple shift registers. The data transmitted is 8 bits. Under the slave enable signal and shift pulse generated by the master device, the high bit is first and the low bit is last. The data changes on the falling edge of SCLK, and one bit of data is stored in the shift register at the same time.

[0033] The command format for SPI flash reading data is:

[0034] S1, the SPI master sends a read data command, and then the SPI master sends an address with the corresponding address length.

[0035] S2, in the next clock, the SPI slave receives data.

[0036] In the figure below, cs is the chip select signal. clk is the clock. dt is the data transmission line. dr is the data receiving line. cmd is the single-line read command of SPI flash.

[0037] The length below is in bytes.

[0038] like Figure 1 As shown, the method for automatically identifying the address width involved in the present application utilizes the characteristics of the SPI bus protocol and the characteristic that the value of address 0 is not affected by the address width.

[0039] First, the SPI master sends a command to read data from address 0, assuming that the address width is N (N is larger than the actual SPI flash address width). A fixed sequence of known order is pre-stored in the 0 address space of the SPI flash. The position of each element in the sequence is fixed. The actual address length of the SPI flash is addr( Figure 1 Indicated by addr).

[0040] After the SPI slave device parses the read command and addr 0, it will send the data to the next clock ( Figure 1 Point d) returns the data sequence corresponding to address 0.

[0041] The SPI master receives data after the Nth 0 is sent ( Figure 1 The SPI master device will discard the discarded data ( Figure 1 According to the position of the first data read by the master device in the known sequence, the number of discarded data can be obtained. The address width of the SPI flash addr = N-discarded can be detected.

[0042] Specific implementation examples Figure 2 As shown:

[0043] The sequence 0x6, 0x5, 0x4, 0x3, 0x2 is pre-stored in the address space 0 of the spi flash. The maximum address width N detected is 6.

[0044] The SPI master sends a single-line read command and 6 zeros as the address to the SPI flash.

[0045] After spi flash parses cmd and address, Figure 2Point d returns the data stored in address space 0.

[0046] spi master device in Figure 2 Data is received at point e. Figure 2 0x6 and 0x5 in are discarded data. Judging from the first data received by the spi master device, the number of discarded data is 2. The address length addr = N-2 = 4 can be detected.

[0047] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for automatically identifying address width, characterized in that: The following steps are involved: S1, pre-store a sequence of known order in the 0 address space of the SPI flash; the sequence of known order is a fixed sequence, and the position of each element in the sequence is fixed; the 0 address space pre-stores the sequence 0x6, 0x5, 0x4, 0x3, 0x2; the value of the 0 address of S1 is not affected by the address width; the address width N in step S1 is X zeros, where X is an integer; S2, the SPI master device sends a command to read data from address 0, and the command to read data is a single-line read command; assuming that the address width N is the maximum address width, the maximum address width N=6, which is greater than the actual address width of the SPI flash, and the actual address width of the SPI flash is addr; S3, after parsing the read command and the actual address width, the SPI slave device returns the data sequence corresponding to address 0 in the next clock; S4, the SPI master device receives data after the Nth 0 is sent; wherein, the SPI master device will discard discarded data, and the actual address width of the SPI flash is obtained according to addr=N-discarded; in the step S4, according to the position of the first data read by the master device in the known sequence, the number of discarded data discarded can be calculated in sequence, which is an integer.

Images