Nanoridge engineering

Abstract

A method (100) for growing at least one III / V nanoridge (200) on a silicon substrate (310) within a cavity. The method includes: patterning (110) a region on the silicon substrate (310) to form a trench (320) on the silicon substrate; growing the III / V nanoridge (200) by: initiating the growth of the III / V nanoridge (200) in the trench (320) to form and fill a layer (200) of nanoridges within the trench; and continuing to grow (124) out of the trench (320) from the top of the filling layer (210) to form a top portion (220) of the nanoridge (200), wherein at least one surfactant is added to the cavity as the nanoridge grows outside the trench.

Description

Technical Field

[0001] This invention relates to the field of III-V semiconductors. More specifically, it relates to a method for monolithically integrating III-V devices on a silicon substrate. Background Technology

[0002] Due to the lattice mismatch between the III-V material and the silicon substrate, defects arise in the III-V material, making it difficult to monolithically integrate III-V devices onto the silicon substrate. To overcome these difficulties, nanoridges are grown in narrow trenches.

[0003] Nanoridges made of III / V materials are now being used in very different integration methods. For example, these nanoridges are InGaAs nanoridges (with varying In content) grown on patterned silicon substrates. The patterned substrate can be obtained by shallow trench isolation process flow. The nanoridges are obtained through trench filling and proliferation. Successful device integration on these nanoridges requires the collinear and uniform growth of the nanoridges on a patterned Si wafer with a distinctly flat (001) top surface. Nanoridge engineering is required to obtain this distinctly flat (001) top surface.

[0004] Depending on the growth conditions, very different types of shapes can be achieved. Examples of cross-sectional scanning electron micrographs of nanoridges from the prior art are shown in [the image / image / etc.]. Figure 2 The figure shows a nanoridge 10 grown within a trench in a dielectric layer 21. The dielectric layer 21 is situated on a silicon substrate 22. A first portion 12 of the nanoridge 10 grows within the trench, and a second portion 11 of the nanoridge extends beyond the trench. In this example, the nanoridge comprises InGaAs. By utilizing aspect ratio trapping techniques, defects arising from lattice mismatch between Si and InGaAs can be confined within the trench. As can be seen from this figure, the nanoridge does not include a flat top surface. This poses a problem for device integration.

[0005] To obtain nanoridges with flat top surfaces, some existing processes form nanoridges by employing low growth temperatures and / or high growth rates. Thus, box-shaped InGaAs with (001) top surfaces can be realized. However, the residual strain field (typically in III / V heteroepitaxial growth on Si) leads to the non-uniform formation of InGaAs nanoridges with rough top surfaces, which is problematic for arbitrary device integration.

[0006] Therefore, there is a need for methods that allow the growth of III / V materials on silicon substrates to compensate for the lattice mismatch between the III-V materials and silicon. Summary of the Invention

[0007] One object of the embodiments of the present invention is to provide a good method for growing III / V nanoridges on a silicon substrate.

[0008] The above-mentioned objectives are achieved by the method and apparatus described in this invention.

[0009] This invention relates to a method for growing at least one III / V nanoridge on a silicon substrate. To grow the nanoridge, the substrate is placed in an epitaxial growth chamber where growth conditions can be controlled. The method includes:

[0010] - Patterning areas on a silicon substrate to form trenches on the silicon substrate;

[0011] - Grow III / V nanoridges using the following process:

[0012] - This induces the growth of III / V nanoridges within the trench, thereby forming a filling layer on the nanoridges within the trench; this can be achieved by the following steps: forming a III / V seed layer on the top surface of the Si surface within the trench, and continuing growth within the trench to fill it, thus obtaining the filling layer.

[0013] - Continue growing from the top of the filling layer out of the trench to form the top portion of the nanoridge, wherein at least one surfactant is added to the chamber as the nanoridge grows out of the trench.

[0014] One advantage of this embodiment of the invention is the addition of a surfactant as growth continues beyond the trench. This surfactant alters the properties of the crystal surface and thus the growth characteristics. Another advantage of this embodiment is that, compared to the case without the surfactant, the use of a surfactant allows the formation of nanoridges with flat (001) surfaces at higher temperatures. Therefore, funnel-shaped or box-shaped III / V nanoridges can be formed at high growth temperatures. These temperatures can be, for example, above 400°C, or even above 500°C.

[0015] In embodiments of the invention, the amount of surfactant and the exposure time of the nanoridges are limited so that the surfactant alters the growth characteristics without being incorporated into the nanoridges in large quantities. This is why, in some embodiments of the invention, it is particularly advantageous to add at least one surfactant as growth continues beyond the trenches.

[0016] While III / V nanoridges with flat (001) surfaces can be grown at low growth temperatures, this easily leads to non-uniform nanoridges with rough top (001) surfaces. This poses a significant problem for device integration. Therefore, it is advantageous to increase the growth temperature by adding surfactants while still forming flat (001) surfaces.

[0017] Therefore, one advantage of the embodiments of the present invention is that it can heteroepitaxially integrate collinear and uniform III / V nanoridges on patterned Si substrates and has a significant and smooth (001) surface for device integration.

[0018] One advantage of this embodiment of the invention is that strain-induced defects caused by lattice mismatch between the III / V material and Si are trapped on the patterned sidewalls of the trenches near the III / V-Si surface. Therefore, the grown top III / V material exhibits a significantly reduced defect density, which is essential for device integration.

[0019] One advantage of this invention is that it allows for the implementation of multiple functions on a single substrate. Applications include silicon photonics, analog RF applications, imagers, and more. The functionality of III / V-based devices can be integrated with Si-based integrated electronics.

[0020] In an embodiment of the present invention, when nanoridges are grown on top of the filling layer, the temperature in the chamber is set to 400°C or higher.

[0021] In an embodiment of the present invention, the nanoridges are grown using metal-organic vapor phase epitaxy.

[0022] In an embodiment of the present invention, the nanoridges are grown using hydride vapor phase epitaxy.

[0023] In embodiments of the present invention, nanoridges are grown using molecular beam epitaxy.

[0024] In embodiments of the present invention, III / V nanoridges contain In x Ga (1-x) The ternary material system of As, where x is between 0 and 1, includes pure GaAs and pure InAs.

[0025] In an embodiment of the present invention, the III / V nanoridge comprises a quaternary material system.

[0026] In embodiments of the present invention, at least one surfactant is selected from a list of surfactants including gallium precursors, indium precursors, silicon precursors, tert-butylarsine, arsine, antimony precursors, bismuth precursors, tellurium precursors, zinc precursors, magnesium precursors, manganese precursors, tin precursors (e.g., tin chloride), hydrogen chloride, carbon tetrabromide, chlorine, bromochloromethane (e.g., CCl3Br, CCl2Br2, and CClBr3), and carbon tetrachloride.

[0027] In an embodiment of the present invention, the method includes: forming an RF device in at least one nanoridge.

[0028] In an embodiment of the present invention, the method includes: forming an optical device in at least one nanoridge.

[0029] In an embodiment of the present invention, the method includes: forming an imager in at least one nanoridge.

[0030] Specific and preferred aspects of the invention are set forth in the appended independent and dependent claims. Features in the dependent claims may be appropriately combined with features in the independent and other dependent claims, and are not limited to those expressly stated in the claims.

[0031] These and other aspects of the invention will be disclosed and illustrated with reference to the embodiments described below. Attached Figure Description

[0032] Figure 1 A flowchart illustrating an exemplary method according to an embodiment of the present invention is shown.

[0033] Figure 2 Cross-sectional scanning electron microscopy images of existing InGaAs nanoridges on Si substrates are shown.

[0034] Figure 3 This displays a cross-sectional scanning electron micrograph of a nanoridge obtained using the method according to an embodiment of the present invention.

[0035] Figure 4 This displays cross-sectional SEM images of InGaAs nanoridges grown from 80nm and 300nm trenches using existing techniques.

[0036] Figure 5 This displays cross-sectional SEM images of InGaAs nanoridges grown from 80 nm and 300 nm trenches using the method according to an embodiment of the present invention.

[0037] Any references in the claims should not be construed as limiting the scope of the invention.

[0038] In different figures, the same reference numerals denote the same or similar elements. Detailed Implementation

[0039] The invention will be described with reference to specific embodiments and certain accompanying drawings, but is not limited thereto, except by the claims. The drawings described are illustrative only and are not restrictive. In the drawings, the dimensions of some elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and relative dimensions described do not correspond to the actual reductions in practice with respect to the invention.

[0040] Furthermore, in the specification and claims, terms such as "top" and "below" are used for descriptive purposes and not necessarily to describe relative positions. It should be understood that such terms are interchangeable where appropriate, and embodiments of the invention can operate in orientations other than those described or illustrated herein.

[0041] It should be noted that the term "comprising" as used in the claims should not be construed as limiting to the portion listed thereafter, and does not exclude other elements or steps. Therefore, it should be understood as indicating the presence of the stated feature, integration, step, or component, but does not exclude the presence or addition of one or more other features, integrations, steps, or components, or combinations thereof. Thus, the scope of the expression "a device comprising components A and B" should not be limited to the device consisting solely of components A and B. It indicates that, for the present invention, the relevant components of the device are only A and B.

[0042] The phrase "one embodiment" or "an embodiment" as used in the specification refers to a specific feature, structure, or characteristic described in connection with the embodiment, which is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily all refer to the same embodiment, but may all refer to the same embodiment. Furthermore, specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments, as will be apparent to those skilled in the art.

[0043] Similarly, it should be understood that in the description of exemplary embodiments of the invention, different features of the invention are sometimes combined into a single embodiment, feature, or description thereof in order to simplify the disclosure and aid in understanding one or more different aspects of the invention. However, the methods in this disclosure should not be construed as reflecting an invention, and the claimed invention requires more features than expressly referenced in the claims. Furthermore, as reflected in the appended claims, inventive aspects may include fewer features than all the features of a single embodiment disclosed above. Therefore, the claims following the detailed description are expressly incorporated into this description, and each claim itself represents an independent embodiment of the invention.

[0044] Furthermore, when some embodiments described herein include, but are not included in, other features included in other embodiments, combinations of features from different embodiments are intended to be included within the scope of the invention and to form different embodiments, as will be understood by those skilled in the art. For example, in the following claims, any claimed embodiment may be used in any combination.

[0045] Numerous specific details are set forth in this description. However, it should be understood that embodiments of the invention may be implemented without these specific details. In other instances, well-known methods, structures, and techniques have not been described in detail to avoid obscuring the understanding of this specification.

[0046] This invention relates to a method 100 for growing at least one III / V nanoridge 200 on a silicon substrate 310. The method includes: patterning a region on the silicon substrate 310 110, thereby forming a trench 320 on the silicon substrate. Furthermore, the method includes: growing the III / V nanoridge 200 120. To grow the nanoridge, the substrate is placed in a chamber where growth conditions can be controlled. The growth of the nanoridge is accomplished by initiating the growth of the III / V nanoridge 200 in the trench 320 122. This forms a filling layer 210 within the trench. This can be achieved by initiating III / V nucleation on the Si substrate and subsequently filling the trench. Initiating III / V nucleation can therefore be performed under different growth conditions than filling the trench. The thickness of the seed layer can range from 5 nm to 30 nm. Furthermore, the method includes: the nanoridge continuing to grow 124 beyond the trench 320 on top of the nanoridge filling layer 210. This forms a top portion 220 of the nanoridge 200. When the nanoridges grow outside the trenches, one or more surfactants are added to the chamber. Figure 1 A flowchart of an exemplary method according to an embodiment of the present invention is illustrated. It shows the steps of patterning 110 and nanoridge growth 120, the nanoridge growth 120 including the steps of initiating growth 122 by forming a filler layer, and continuing growth 124 on top of the filler layer and growing beyond the trench. Figure 3 An example of a cross-sectional scanning electron micrograph of a nanoridge obtained using a method according to an embodiment of the present invention is shown. It shows a III / V nanoridge 200 on a silicon substrate 310. It also shows a dielectric layer 312 having trenches 320 therein. A filling layer 210 of the nanoridges is present in the trenches 320. For each nanoridge, a top portion 220 of the nanoridge 200 exists on top of the filling layer 210. These top portions grow outside the trenches.

[0047] By initiating the production of nanoridges within trenches, defects caused by lattice mismatch are confined within the trenches, as the release of strain due to lattice mismatch occurs within the trenches. The trench depth is preferably greater than the trench width.

[0048] As the nanoridges continue to grow beyond trench 320, the addition of a surfactant can alter the growth characteristics of the nanoridges. This allows for the formation of nanoridges with increased (001) surface area, even at higher growth temperatures than without a surfactant. For example, funnel-shaped or box-shaped III / V nanoridges (binary or ternary III / V nanoridges, e.g., InGaAs) can be formed at higher growth temperatures than without a surfactant. In embodiments of the invention, the growth temperature can be higher than that without a surfactant. When growing nanoridges on top of a filler layer, the temperature can be, for example, above 400°C. Without being bound by theory, it is assumed that the surfactant used in this embodiment of the invention reduces the mobility of group III and V atoms, as well as precursor molecules that are partially decomposed and adsorbed on the surface. By increasing the temperature, not only is the relaxation of the trench improved, but also the mobility of atoms and molecules on the surface is improved.

[0049] For example, surfactants that enhance the desorption rate on a surface by etching atoms and molecules alter the growth characteristics on different facets. Thus, surfactants manipulate the hierarchy of growth rates, promoting the evolution of box-shaped nanoridges or nanoridges with wide (100) surfaces.

[0050] By adding a surfactant, high-temperature conditions can be maintained even when the nanoridges grow beyond the trenches. This has a significant advantage: that is, uniform collinear III / V nanoridges with a prominent (001) surface can be obtained for device integration. Therefore, it is suitable for device integration. Furthermore, the surfactant is not heavily incorporated into the nanoridges and acts only on the surface. Therefore, it does not distort the normal operation of devices integrated in the nanoridges.

[0051] The patterning of the trenches can be accomplished in a dielectric layer 312 disposed on a silicon substrate 310. This can be a silicon oxide layer (SiO2). The thickness of the dielectric layer can be, for example, about 300 nm. Patterning 110 can be accomplished using a shallow trench isolation process, thereby obtaining one or more trenches in the dielectric layer 312. As described above, defects are trapped in the trenches. Therefore, the width of the trench is effectively smaller than the depth of the trench. For example, for a 300 nm thick dielectric layer, the trench width ranges from, for example, 50 nm to 150 nm, but can be wider for thicker dielectric layers. Importantly, the aspect ratio (trench depth relative to trench width) is significantly greater than 1.43 to capture all mismatch-induced defects. Fabricating trenches through the dielectric layer means that direct contact with the silicon substrate is possible through the trenches. In some embodiments of the invention, the dielectric layer can have a V-shaped silicon bottom to avoid anti-phase disorder in the III / V layer. However, the invention is not limited to this. The bottom can also be, for example, flat. As discussed above, trenches are formed in dielectric layer 312. In embodiments of the invention, the filling layer 210 of the nanoridges grows within the trenches. A surfactant is added when the nanoridges grow beyond the trenches, i.e., when the nanoridges grow above the top surface of dielectric layer 312. An essential feature of the invention is the addition of a surfactant when the nanoridges grow beyond the trenches. In some embodiments of the invention, the surfactant may also be added when the nanoridges grow on top of the filling layer, still within the trenches. The optimal time to add the surfactant is when the III / V layer is fully relaxed and all fit-induced defects are trapped in the sidewalls, which can still be achieved within the trench pattern. Depending on the trench depth, the moment when the III / V layer is fully relaxed can be when the filling layer is still within the trench (for deeper trenches, the location of complete relaxation of the III / V layer will be deeper within the trench).

[0052] In embodiments of the present invention, III / V nanoridges contain In x Ga (1-x)Binary and ternary material systems of As, where x is 0 to 1. Typically, the range from GaAs to InAs can be covered. In embodiments of the invention, the composition of the III / V material is such that it contains 50% (total atomic percentage) of group V material and 50% of group III material. Group III and group V can be considered as 100%. In some embodiments of the invention, the In concentration is 0% to 100% (x is 0 to 1) when selecting group III material, and the Ga concentration is 100% to 0% when selecting group III material, such that the sum of the two is 100%. When selecting group V material, the As concentration can be, for example, 100%. In embodiments of the invention, the nanoridge contains two group III materials and two group V materials. For example, in group V, P, Sb, and N can also be mixed. Therefore, quaternary III / V materials can be formed. For example, the following material systems can be formed: (InGa)(AsP), (InGa)(AsSb), etc.

[0053] Different surfactants or combinations of surfactants can be used. As previously mentioned, these can be applied, for example, after the deposition of the filler layer (which can be performed at low temperatures). Precursors for III-V nanoridge growth can be selected, for example, from the following list: triethylgallium (TEGa), trimethylgallium (TMGa), trimethylindium (TMIn), tert-butylarsine (TBAs), arsine (AsH3), triethylantimony (TESb), trimethylantimony (TMSb), or more preferably trimethylgallium (TMGa) and triethylantimony (TESb). Furthermore, this list can include hydrogen chloride (HCl), carbon tetrabromide (CBr4), or chlorine (Cl2). Compared to other surfactants, hydrogen chloride (HCl), chlorine (Cl2), and carbon tetrabromide (CBr4) etch the surface, but their effect as surfactants on nanoridge growth works in the same way because they alter the growth characteristics on different nanoridge facets. Other surfactants that can be used are bromochloromethane (e.g., CCl3Br, CCl2Br2, and CClBr3) and carbon tetrachloride. These surfactants will also etch the surface. Other surfactants that can be used are silicone surfactants, such as silane and ethylsilane.

[0054] Different techniques (e.g., metal-organic vapor phase epitaxy, hydride vapor phase epitaxy, or molecular beam epitaxy) can be used to grow nanoridges.

[0055] According to an exemplary embodiment of the present invention, typical ranges of growth parameters (In% from 0% to 100%) for InGaAs growth, covering GaAs to InAs, are listed in the following sections. In this exemplary method, a 300 mm MOVPE chamber from Applied Materials is used. Depending on the MOVPE epitaxial (epi) tool, different parameter ranges may be required.

[0056] The trenches can be formed in the top layer of a silicon wafer. For example, the Si to oxide ratio of the layer is 1 to 50%, or more preferably 5 to 15%. However, the invention is not limited thereto. Depending on the mask layout, different ranges of growth parameters may be required.

[0057] The advantage is that, compared to the case without surfactant, by adding surfactant as growth continues beyond the trench, nanoridges with flat surfaces can be formed at higher temperatures. The temperature can be, for example, above 500°C. The temperature can be, for example, above 525°C. For example, it can be a temperature from 500°C to 700°C, or preferably from 525°C to 625°C.

[0058] The carrier gas used in the MOVPE chamber can be, for example, H2 or N2. In this example, H2 is a more preferred choice.

[0059] In this exemplary embodiment of the invention, the chamber pressure range can be from 5 torr to 450 torr, more preferably from 10 torr to 150 torr.

[0060] In this exemplary embodiment of the present invention, the total carrier gas flux can range from 10 l / min to 30 l / min, more preferably from 15 l / min to 25 l / min.

[0061] Precursors for InGaAs proliferation can be selected from the surfactants listed above. The following precursor combinations are possible:

[0062] TMGa, TMIn, TBAs, TESb

[0063] TMGa, TMIn, TBAs, TMSb

[0064] TMGa, TMIn, AsH3, TESb

[0065] TMGa, TMIn, AsH3, TMSb

[0066] TEGa, TMI, TBAs, TESb

[0067] TEGa, TMI, TBAs, TMSb

[0068] TEGa, TMI, AsH3, TESb

[0069] TEGa, TMI, AsH3, TMSb

[0070] For example, the applied molar flux can range between the following values:

[0071] For TMGa, the molar flux range may be, for example, 1.0E-5 to 2.0E-4 [mol / min], or more preferably 1.5E-5 to 1E-4 [mol / min], or for TEGa, the molar flux range may be, for example, 0.2E-5 to 2.0E-4 [mol / min], or more preferably 1.0E-5 to 1E-4 [mol / min].

[0072] For TMIn, the molar flux range can be, for example, 1.9E-5 to 1.9E-4 [mol / min], or more preferably 3.8E-5 to 1.5E-4 [mol / min].

[0073] For TESb or TMSb, the molar flux range can be, for example, 1.0E-5 to 6.5E-4 [mol / min], more preferably 3.8E-5 to 3.2E-4 [mol / min].

[0074] The flux of TBAs can be adjusted according to the mole / min flux of Ga+In to meet a specific TBA / (TMGa+TMIn) ratio or TBA / (TEGa+TMIn) ratio. This ratio is preferably 5 to 200, more preferably 10 to 80.

[0075] The flux of AsH3 can be adjusted according to the mole / min flux of Ga+In to meet a specific TBAs / (TMGa+TMIn) ratio or TBAs / (TEGa+TMIn) ratio. This ratio is preferably 50 to 1000, more preferably 50 to 500.

[0076] In embodiments of the invention, the growth of III / V nanoridges is initiated by forming a seed layer and a filler layer of nanoridges in the trench. The seed layer (III / V nucleation on the Si surface) can be completed, for example, at 300°C to 450°C, and the filler layer can be completed at 350°C to 500°C. For example, the growth of InGaAs nanoridges begins with the deposition of a thin InGaAs seed layer at a low temperature, followed by the deposition of a filler layer. The seed layer needs to provide a well-wetted Si surface for the next layer and, together with the filler layer, compensate for the lattice mismatch between Si and InGaAs without affecting the shape of the grown nanoridges. After the deposition of the seed and filler layers, growth continues at a higher temperature for 124 to fill the trench and form nanoridges (growth step). An advantage of embodiments of the invention is that a surfactant is used to control the growth in this stage.

[0077] The following section discusses the growth of In 0.55 Ga 0.45 Growth conditions for InGaAs. To demonstrate that the use of a surfactant leads to the deposition of funnel-shaped or box-shaped InGaAs nanoridges, two experiments were conducted under the same growth conditions, one with and one without TESb precursors as surfactants. In these experiments, growth was performed in a 300 mm epitaxial chamber at Applied Materials using metal-organic vapor phase epitaxy (MOVPE). In this example, the silicon substrate was STI (shallow trench isolation) with a 10% open trench area (in other words, the ratio between the Si surface and the SiO2 surface was approximately 10%). The STI oxide thickness was approximately 300 nm. The overgrowth temperature was maintained at 570 °C, the operating pressure at 50 Torr, the total flux at 20 standard liters per minute (slm), and the carrier gas at H2. The precursors used for InGaAs growth were TBAs, TMI, and TMGa. To form nanoridges with approximately 55%, the TMGa molar flux was set to 3.4E-05 mol / min, and the TMIn molar flux was set to 8.4E-05 mol / min. The TBAs molar flux was maintained at 8.9E-03 mol / min, providing a BAs / (TMGa+TMIn) ratio of 75.

[0078] In the absence of surfactants, Figure 4 The cross-sectional SEM images show that the outgrowth InGaAs material has a {111} top facet. The left image shows InGaAs nanoridges grown from trenches with a width of 80 nm, and the right image shows InGaAs nanoridges grown from trenches with a width of 300 nm.

[0079] One advantage of this invention is that, if a TESb flux of 2.4E-04 mol / min is used during high-temperature growth, InGaAs nanoridges with a box-like profile can be grown. This is shown in... Figure 5 The left image shows InGaAs nanoridges 200 grown in an 80nm trench 320. The right image shows InGaAs nanoridges 200 grown in a 300nm trench. In both images, a silicon substrate 310, a silicon oxide layer 312, and a trench 320 on the silicon substrate 310 can be seen. The seed and filling layers 210 of the nanoridges are formed in the trench 320 and are in contact with the silicon substrate 310. As can be seen from the images, the top portion 220 of the nanoridges has a flat surface.

[0080] X-ray diffraction ((224) reciprocal space plot) results indicate the formation of fully relaxed InGaAs with Sb and an In concentration of approximately 55%.

[0081] The advantage of this invention is that high electron mobility transistors can be formed on nanoridges obtained using the method according to embodiments of the invention. For example, they can be based on GaAs, InP, or InGaAs (with different In contents). This transistor can be used, for example, in high-frequency applications.

[0082] In the method according to an embodiment of the present invention, an RF device, an optical device (e.g., a laser, a DFB laser, a waveguide), or an imager may be formed in at least one nanoridge.

Claims

1. A method (100) for growing at least one III / V nanoridge (200) on a silicon substrate (310) within an epitaxial growth chamber, the method comprising: - Patterning (110) the area on the silicon substrate (310) to form trenches (320) on the silicon substrate; - The (120)III / V nanoridges (200) were grown using the following process: -Initiates the growth (122) of III / V nanoridges (200) in the trench (320), thereby forming a nanoridge filling layer (210) within the trench. - Continue growing (124) from the top of the filling layer (210) beyond the trench (320) to form the top portion (220) of the nanoridge (200), wherein, as the nanoridge grows beyond the trench, at least one surfactant is added to the chamber, the surfactant altering the properties on the crystal surface and thus altering the growth characteristics, the amount of surfactant and the exposure time of the nanoridge causing the growth characteristics of the nanoridge to change, but the surfactant is not incorporated into the nanoridge in large quantities.

2. The method as described in claim 1, wherein, When the nanoridges continue to grow on top of the filling layer (210), the temperature in the chamber is set to 400°C or higher.

3. The method (100) as described in claim 1, wherein, Nanoridges (200) are grown using metal-organic vapor phase epitaxy (120).

4. The method (100) as described in claim 2, wherein, Nanoridges (200) are grown using metal-organic vapor phase epitaxy (120).

5. The method (100) as claimed in claim 1, wherein, Nanoridges (200) are grown using hydride vapor phase epitaxy (120).

6. The method (100) as claimed in claim 2, wherein, Nanoridges (200) are grown using hydride vapor phase epitaxy (120).

7. The method (100) as claimed in claim 1, wherein, Nanoridges (200) are grown using molecular beam epitaxy (120).

8. The method (100) as claimed in claim 2, wherein, Nanoridges (200) are grown using molecular beam epitaxy (120).

9. The method (100) according to any one of claims 1 to 8, wherein, III / V nanoridges contain In x Ga (1-x) The ternary material system of As, where x is a value between 0 and 1, including 0 and 1.

10. The method (100) according to any one of claims 1 to 8, wherein, III / V nanoridges comprise a quaternary material system.

11. The method (100) according to any one of claims 1 to 8, wherein, At least one surfactant is selected from the list of surfactants, which includes one or more gallium precursors, one or more indium precursors, tert-butylarsine, arsine, one or more antimony precursors, one or more bismuth precursors, one or more tellurium precursors, one or more zinc precursors, one or more magnesium precursors, one or more manganese precursors, one or more tin precursors, hydrogen chloride, carbon tetrabromide, chlorine, one or more bromochloromethanes, and carbon tetrachloride.

12. The method (100) as claimed in claim 9, wherein, At least one surfactant is selected from the list of surfactants, which includes one or more gallium precursors, one or more indium precursors, tert-butylarsine, arsine, one or more antimony precursors, one or more bismuth precursors, one or more tellurium precursors, one or more zinc precursors, one or more magnesium precursors, one or more manganese precursors, one or more tin precursors, hydrogen chloride, carbon tetrabromide, chlorine, one or more bromochloromethanes, and carbon tetrachloride.

13. The method of any one of claims 1 to 8 and 12, the method further comprising forming an RF device in at least one nanoridge.

14. The method of any one of claims 1 to 8 and 12, the method further comprising forming an optical device in at least one nanoridge.

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