Display device and method of manufacturing the same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes: a substrate; a display region disposed on the substrate and including a plurality of pixels; a first planarization layer disposed on the substrate; a second planarization layer disposed on the first planarization layer; a pixel defining layer disposed on the second planarization layer and covering at least one edge of a first electrode of each of the plurality of pixels; a plurality of first holes disposed between the plurality of pixels and separated from the first electrode; and a first etch prevention layer disposed on a bottom surface of each of the plurality of first holes and located on the first planarization layer. Each of the plurality of first holes includes an opening passing through the second planarization layer and the pixel defining layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0109576, filed with the Korean Intellectual Property Office on Sep. 4, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Exemplary embodiments include a display device and a method of manufacturing the same. Background Art

[0003] A display device is a device that visually displays data. Recently, the use of display devices has diversified, and the thickness and weight of display devices have decreased, thus expanding the scope of use of display devices.

[0004] To protect a display area of a display device from external moisture and impurities, the display area is encapsulated with an encapsulation member. With the recent increase in demand for thin and flexible display devices, there is a trend to use a thin film encapsulation layer that is not metal or glass and includes a flexible organic insulating film and / or an inorganic insulating film. Summary of the Invention

[0005] In a subsequent process after forming the thin film encapsulation layer, a defect may occur in which the thin film encapsulation layer is peeled off from a backplane of the display device. For example, such a defect may occur in a process of forming a touch sensor layer on the thin film encapsulation layer or a process of removing a protective film adhered to the thin film encapsulation layer before attaching a polarizing film.

[0006] Exemplary embodiments include a display device and a method of manufacturing the same that can reduce a defect in which the thin film encapsulation layer is peeled off from the backplane. However, these objects are merely examples, and the scope of the present disclosure is not limited thereto.

[0007] According to an exemplary embodiment, a display device includes: a substrate; a display area disposed on the substrate and including a plurality of pixels; a first planarization layer disposed on the substrate; a second planarization layer disposed on the first planarization layer; a pixel defining layer disposed on the second planarization layer and covering at least one edge of a first electrode of each of the plurality of pixels; a plurality of first holes disposed between the plurality of pixels and spaced apart from the first electrode; and a first etch prevention layer disposed on a bottom surface of each of the plurality of first holes and on the first planarization layer. Each of the plurality of first holes includes an opening that passes through the second planarization layer and the pixel defining layer, respectively.

[0008] In an exemplary embodiment, at a boundary surface between the pixel defining layer and the second planarization layer, a first width of an opening formed in the pixel defining layer is smaller than a second width of an opening formed in the second planarization layer.

[0009] In an exemplary embodiment, the display device further includes a second etch prevention layer disposed between the second planarization layer and the pixel defining layer.

[0010] In an exemplary embodiment, the display device further includes a third etch prevention layer disposed on the second etch prevention layer.

[0011] In an exemplary embodiment, each pixel of the plurality of pixels includes an intermediate layer disposed on the first electrode and a second electrode disposed on the intermediate layer. The intermediate layer includes an emission layer, and the intermediate layer and the second electrode are disposed inside each of the plurality of first holes.

[0012] In an exemplary embodiment, the emission layer is disposed on the first electrode and is not disposed inside each of the plurality of first holes.

[0013] In an exemplary embodiment, the display device further includes a thin film encapsulation layer encapsulating the plurality of pixels. The thin film encapsulation layer includes a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer, and the organic encapsulation layer is disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer. The first inorganic encapsulation layer covers the entirety of the second electrode inside each of the plurality of first holes and the entirety of the inner surface of each of the plurality of first holes, and the entirety of each of the plurality of first holes is filled with the organic encapsulation layer.

[0014] In an exemplary embodiment, the display device further includes a thin film transistor disposed between the substrate and the first planarization layer and a connection line disposed between the first planarization layer and the second planarization layer and connecting the thin film transistor to the first electrode. The connection line includes the same material as the first etch prevention layer.

[0015] In an exemplary embodiment, the display device further includes: a plurality of second holes passing through the second planarization layer and the pixel defining layer in a non-display area disposed outside the display area; and a second etch prevention layer disposed on the bottom surface of each of the plurality of second holes and the first planarization layer. The first planarization layer, the second planarization layer, and the pixel defining layer extend into the non-display area.

[0016] In an exemplary embodiment, the intermediate layer and the second electrode extend into the non-display area, and the intermediate layer and the second electrode are disposed inside each of the plurality of second holes.

[0017] In an exemplary embodiment, the first inorganic encapsulation layer, the organic encapsulation layer, and the second inorganic encapsulation layer extend into the non-display area. The first inorganic encapsulation layer covers the entirety of the second electrode inside each of the plurality of second holes and the entirety of the inner surface of each of the plurality of second holes. The entirety of each of the plurality of second holes is filled with the organic encapsulation layer.

[0018] In an exemplary embodiment, the display device further includes a power voltage line disposed in the non-display area and surrounding a part of the display area. The second electrode extending into the non-display area is electrically connected to the power voltage line.

[0019] In an exemplary embodiment, the display device further includes a first dam portion and a second dam portion disposed outside the display area. Both the first dam portion and the second dam portion include a layer containing the same material as the second planarization layer and the pixel defining layer. The second dam portion covers an end portion of the power voltage line.

[0020] In an exemplary embodiment, the display device further includes a second etch prevention layer disposed between the second planarization layer and the pixel defining layer.

[0021] In an exemplary embodiment, at a boundary surface between the pixel defining layer and the second planarization layer, a first width of an opening formed in the pixel defining layer and a second width of an opening formed in the second planarization layer are substantially equal to each other.

[0022] According to an exemplary embodiment, a display device includes a substrate and a display area disposed on the substrate and including a plurality of pixels. Each pixel of the plurality of pixels includes a first electrode, a second electrode, and an intermediate layer disposed between the first electrode and the second electrode. The intermediate layer includes an emission layer. The display device further includes a thin film encapsulation layer that encapsulates the plurality of pixels and includes a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer, and the organic encapsulation layer is disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer. The display device further includes: a non-display area disposed outside the display area; a first planarization layer extending from the display area into the non-display area and disposed between the substrate and the first electrode; a second planarization layer extending from the display area into the non-display area and disposed on the first planarization layer; a pixel defining layer covering at least one edge of the first electrode, extending from the display area into the non-display area, and disposed on the second planarization layer; and a plurality of holes disposed in the non-display area. Each hole of the plurality of holes includes an opening passing through the second planarization layer and the pixel defining layer, respectively. The display device further includes a first etch prevention layer disposed on the first planarization layer and under the plurality of holes. The intermediate layer and the second electrode extend into the non-display area and are disposed inside each of the plurality of holes. The first inorganic encapsulation layer extends into the non-display area and covers the entirety of the second electrode inside each of the plurality of holes and the entirety of the inner surface of each of the plurality of holes. The entirety of each of the plurality of holes is filled with the organic encapsulation layer.

[0023] In an exemplary embodiment, the display device further includes a first dam portion and a second dam portion. Both the first dam portion and the second dam portion include at least one layer, and the at least one layer includes the same material as the second planarization layer and / or the pixel defining layer. The first inorganic encapsulation layer extends from a plurality of holes and covers the first dam portion and the second dam portion, and is in direct contact with the second inorganic encapsulation layer outside the second dam portion.

[0024] According to an exemplary embodiment, a method of manufacturing a display device includes: forming a first planarization layer on a substrate; forming a first etch stop layer on the first planarization layer; forming a second planarization layer on the first etch stop layer; forming a pixel defining layer on the second planarization layer; and forming a plurality of first holes passing through the second planarization layer and the pixel defining layer in a display area. The display area is provided on the substrate and includes a plurality of pixels. Each pixel of the plurality of pixels includes a first electrode, a second electrode, and an intermediate layer. The intermediate layer includes an emission layer and is disposed between the first electrode and the second electrode. The display device includes a thin film encapsulation layer that encapsulates the display area and includes a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer. The organic encapsulation layer is disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer. The intermediate layer and the second electrode are formed on the top surface of the first etch stop layer and the top surface of the pixel defining layer. The first inorganic encapsulation layer covers the entirety of the second electrode inside each of the plurality of first holes and the entirety of the inner surface of each of the plurality of first holes, and the entirety of each of the plurality of first holes is filled with the organic encapsulation layer.

[0025] In an exemplary embodiment, the method further includes: forming a first contact hole in the pixel defining layer; and forming a barrier layer on the pixel defining layer. The barrier layer surrounds the first contact hole, and the plurality of first holes are formed by dry etching the second planarization layer and the pixel defining layer.

[0026] In an exemplary embodiment, the method further includes: after forming the plurality of first holes, removing the barrier layer by wet etching.

[0027] In an exemplary embodiment, the method further includes: forming a second etch stop layer between the second planarization layer and the pixel defining layer.

[0028] In an exemplary embodiment, the second etch stop layer is formed simultaneously with the first electrode.

[0029] In an exemplary embodiment, the method further includes forming a third etch stop layer on the second etch stop layer.

[0030] In an exemplary embodiment, the method further includes: forming a plurality of second holes through the second planarization layer and the pixel definition layer; and forming a second etch stop layer on the bottom surface of each of the plurality of second holes and on the first planarization layer. The first planarization layer, the second planarization layer, and the pixel definition layer extend into a non-display area disposed outside the display area.

[0031] In an exemplary embodiment, an intermediate layer and a second electrode are formed on the top surface of the second etch stop layer and on the top surface of the pixel definition layer. The first inorganic encapsulation layer covers the entirety of the second electrode inside each of the plurality of second holes and the entirety of the inner surface of each of the plurality of second holes, and each of the plurality of second holes is filled with an organic encapsulation layer.

[0032] In an exemplary embodiment, the plurality of first holes are formed by irradiating a position corresponding to the first etch stop layer with a laser. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0034] Figure 1 is a plan view schematically showing a display device according to an exemplary embodiment.

[0035] Figure 2A and Figure 2B is an equivalent circuit diagram of a pixel included in a display device according to an exemplary embodiment.

[0036] Figure 3 is schematically showing according to an exemplary embodiment Figure 1 a plan view of Region III of.

[0037] Figure 4 is according to an exemplary embodiment Figure 3 a cross-sectional view of the display device taken along line IVA-IVB.

[0038] Figures 5A to 5H is schematically showing a manufacturing process of forming Figure 4 the first hole in Region A of.

[0039] Figure 6 is a cross-sectional view schematically showing a part of a display device according to an embodiment.

[0040] Figure 7 is a cross-sectional view schematically showing a part of a display device according to an exemplary embodiment.

[0041] Figure 8is a cross-sectional view schematically showing a part of a display device according to an exemplary embodiment.

[0042] Figures 9A to 9E is a cross-sectional view schematically showing a manufacturing process of a first hole formed according to an exemplary embodiment Figure 8 thereof.

[0043] Figure 10 is a cross-sectional view taken along line XA-XB of a display device according to an exemplary embodiment Figure 1 thereof.

[0044] Figures 11A to 11D is a partial plan view schematically showing a process of forming a second hole according to an exemplary embodiment Figure 10 thereof. DETAILED DESCRIPTION

[0045] Exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings. Throughout the drawings, like reference numerals may refer to like elements.

[0046] As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items. Throughout the disclosure, the expressions "at least one of a, b or c" and "at least one of a, b and c" indicate only a, only b, only c, both a and b, both a and c, both b and c, and all of a, b and c.

[0047] It will be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. Thus, a "first" element in an exemplary embodiment may be described as a "second" element in another exemplary embodiment.

[0048] As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are also intended to include the plural forms.

[0049] It will also be understood that the terms "comprises" and / or "comprising" as used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0050] It will be understood that when an element such as a film, region, layer or component is referred to as being "on", "connected to", "coupled to" or "adjacent to" another component, it can be directly on, connected to, coupled to or adjacent to the other component, or intervening components may be present. For example, it will be understood that when a layer, region or element is referred to as being "electrically connected to" another layer, region or element, it can be directly electrically connected or indirectly electrically connected to the other layer, region or element. It will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. It will also be understood that when an element is referred to as "covering" another element, it can be the only element covering the other element, or one or more intervening elements may also cover the other element. Other words used to describe the relationship between elements should be interpreted in the same manner.

[0051] When some exemplary embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0052] Here, when a value is described as being approximately equal to another value or substantially the same or equal to another value, it will be understood that the values are equal to each other within the measurement error, or if measurably unequal, then as would be understood by a person of ordinary skill in the art, they are numerically close enough to be functionally equal to each other. For example, the term "about" as used herein includes the stated value and means within an acceptable deviation of the specific value determined by a person of ordinary skill in the art, taking into account the measurement being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, as would be understood by a person of ordinary skill in the art, "about" can mean within one or more standard deviations. In addition, it will be understood that although a parameter may be described herein according to an exemplary embodiment as having an "about" specific value, as would be understood by a person of ordinary skill in the art, the parameter can be an exact specific value or an approximate specific value within the measurement error.

[0053] In the following examples, the x-axis, y-axis and z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0054] Examples of display devices capable of using and displaying images in the exemplary embodiments described herein may include, for example, liquid crystal display (LCD) devices, electrophoretic display devices, organic light emitting diode (OLED) display devices, inorganic electroluminescent (EL) display devices, field emission display devices, surface conduction electron emitter display devices, plasma display devices, and cathode ray tube display devices.

[0055] Hereinafter, an organic light emitting diode (OLED) display device will be described as an example of a display device according to an exemplary embodiment. However, the display device according to the exemplary embodiment is not limited thereto, and various types of display devices may be used, including but not limited to the above types of display devices.

[0056] Figure 1 is a plan view schematically showing a display device according to an exemplary embodiment. Figure 2A and Figure 2B is an equivalent circuit diagram of one pixel in a display device according to an exemplary embodiment, Figure 3 is schematically showing according to an exemplary embodiment Figure 1 a plan view of region III of Figure 4 is according to an exemplary embodiment Figure 3 a cross-sectional view of the display device taken along line IVA-IVB.

[0057] Referring to Figure 1 , the display device 1 includes a display area DA on a substrate 100. The display area DA includes a plurality of data lines DL extending in a first direction and pixels P connected to the plurality of data lines DL and a plurality of scan lines SL extending in a second direction intersecting the first direction. Each of the pixels P may be connected to a driving voltage line PL extending in the first direction.

[0058] One pixel P may emit red, green, blue, or white light. In an example, one pixel P may include an organic light emitting diode (OLED). In addition, each pixel P may further include devices such as thin film transistors, capacitors, etc.

[0059] The display area DA may provide a certain image by light emitted from the pixels P. The non-display area NDA is outside the display area DA. For example, the non-display area NDA may surround the display area DA.

[0060] The non-display area NDA where no pixels P are arranged does not provide an image. The first power supply voltage line 10 and the second power supply voltage line 20 providing a voltage different from that of the first power supply voltage line 10 may be located in the non-display area NDA.

[0061] The first power supply voltage line 10 may include a first main voltage line 11 and a first connection line 12, and the first main voltage line 11 and the first connection line 12 are located at one side of the display area DA. For example, when the display area DA has a rectangular shape, the first main voltage line 11 may be positioned to correspond to one side of the display area DA. The first connection line 12 may extend away from the display area DA from the first main voltage line 11 in a first direction. The first connection line 12 may be connected to a second terminal 32 of the terminal unit 30.

[0062] The second power supply voltage line 20 may include a second main voltage line 21 and a second connection line 22, the second main voltage line 21 partially surrounds both ends of the first main voltage line 11 and the display area DA, and the second connection line 22 extends away from the display area DA from the second main voltage line 21 in a first direction. For example, when the display area DA has a rectangular shape, the second main voltage line 21 may extend along both ends of the first main voltage line 11 and the sides of the display area DA except the side adjacent to the first main voltage line 11. The second connection line 22 may extend substantially parallel to the first connection line 12 in the first direction, and may be connected to a third terminal 33 of the terminal unit 30. The second power supply voltage line 20 may be bent to surround an end of the first power supply voltage line 10.

[0063] The terminal unit 30 may be located at an end of the substrate 100 and may include a plurality of terminals, the plurality of terminals including a first terminal 31, a second terminal 32, and a third terminal 33. In an exemplary embodiment, the terminal unit 30 is not covered by an insulating layer. In this case, the terminal unit 30 may be exposed, so the terminal unit 30 may be electrically connected to a controller such as a flexible printed circuit board or a driver integrated circuit (IC) chip as an example.

[0064] The controller may convert a plurality of image signals provided from the outside into a plurality of image data signals, and may provide the converted signals to the display area DA through the first terminal 31. In addition, the controller may receive a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, may generate control signals for controlling the driving of each of the first gate driving unit and the second gate driving unit, and may provide the generated control signals to each of the first gate driving unit and the second gate driving unit through the terminals.

[0065] The controller may provide different voltages to each of the first power supply voltage line 10 and the second power supply voltage line 20 through the second terminal 32 and the third terminal 33.

[0066] The first power supply voltage line 10 may supply a first power supply voltage (see Figure 2A and Figure 2B ELVDD) to each pixel P, and the second power supply voltage line 20 may supply a second power supply voltage (seeFigure 2A and Figure 2B ELVSS) is provided to each pixel P.

[0067] For example, the first power supply voltage ELVDD may be supplied to each pixel P through the driving voltage line PL connected to the first power supply voltage line 10. The second power supply voltage ELVSS may be supplied to the organic light emitting diode (see FIG. Figure 2A and Figure 2B In this case, the second main voltage line 21 of the second power supply voltage line 20 may contact the cathode of the organic light emitting diode OLED in the non-display area NDA.

[0068] A scan driver for supplying scan signals to the plurality of scan lines SL of each pixel P and a data driver for supplying data signals to the plurality of data lines DL may be further located in the non-display area NDA.

[0069] A first dam 110 surrounding the display area DA and a second dam 120 spaced apart from the first dam 110 may be disposed in the non-display area NDA.

[0070] When an inkjet process is used to form a thin film encapsulation layer (see Figure 4 400) monomer as an example of an organic encapsulation layer of an organic material (see Figure 4 420), the first dam portion 110 and the second dam portion 120 may serve as dams for preventing the organic material from flowing in the direction of the edge of the substrate 100. Therefore, the first dam portion 110 and the second dam portion 120 may prevent an edge tail from being formed by the organic encapsulation layer 420 at the edge of the substrate 100.

[0071] Reference Figure 2A , each pixel P may include a pixel circuit PC connected to the scan line SL and the data line DL and an organic light emitting diode OLED connected to the pixel circuit PC.

[0072] The pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2 may be configured to transfer a data signal Dm input through the data line DL to the driving thin film transistor T1 according to a scan signal Sn input through the scan line SL.

[0073] The storage capacitor Cst may be connected to the switching thin film transistor T2 and the driving voltage line PL and may store a voltage corresponding to a difference between a voltage transmitted from the switching thin film transistor T2 and a first power source voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0074] The driving thin-film transistor T1 can be connected to a driving voltage line PL and a storage capacitor Cst, and can control a driving current flowing from the driving voltage line PL through the organic light-emitting diode OLED according to the voltage value stored in the storage capacitor Cst. Due to the driving current, the organic light-emitting diode OLED can emit light with a certain brightness.

[0075] In Figure 2A it, the pixel circuit PC includes two thin-film transistors and a storage capacitor. However, the exemplary embodiment is not limited thereto.

[0076] Referring to Figure 2B , the pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensating thin-film transistor T3, a first initialization thin-film transistor T4, a first emission control thin-film transistor T5, a second emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0077] In Figure 2B it, signal lines SLn (where n is a positive integer), SLn-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL are provided in each pixel P. However, the exemplary embodiment is not limited thereto. For example, in the exemplary embodiment, at least one of the signal lines SLn, SLn-1, EL, and DL and / or the initialization voltage line VL may be shared among adjacent pixels.

[0078] The drain electrode of the driving thin-film transistor T1 can be electrically connected to the organic light-emitting diode OLED via the second emission control thin-film transistor T6. The driving thin-film transistor T1 can receive a data signal Dm and supply a driving current to the organic light-emitting diode OLED according to the switching operation of the switching thin-film transistor T2.

[0079] The gate electrode of the switching thin-film transistor T2 can be connected to the first scan line SLn, and the source electrode of the switching thin-film transistor T2 can be connected to the data line DL. The drain electrode of the switching thin-film transistor T2 can be connected to the source electrode of the driving thin-film transistor T1 and can be connected to the driving voltage line PL via the first emission control thin-film transistor T5.

[0080] The switching thin-film transistor T2 can be turned on according to the first scan signal Sn provided through the first scan line SLn and can perform a switching operation of providing the data signal Dm provided to the data line DL to the source electrode of the driving thin-film transistor T1.

[0081] The gate electrode of the compensation thin film transistor T3 may be connected to the first scan line SLn. The source electrode of the compensation thin film transistor T3 may be connected to the drain electrode of the driving thin film transistor T1 and may be connected to the pixel electrode of the organic light emitting diode OLED via the second emission control thin film transistor T6. The drain electrode of the compensation thin film transistor T3 may be commonly connected to one electrode of the storage capacitor Cst, the source electrode of the first initialization thin film transistor T4, and the gate electrode of the driving thin film transistor T1. The compensation thin film transistor T3 may be turned on according to the first scan signal Sn provided through the first scan line SLn and may connect the gate electrode of the driving thin film transistor T1 to the drain electrode, thereby diode-connecting the driving thin film transistor T1.

[0082] The gate electrode of the first initialization thin film transistor T4 may be connected to the second scan line SLn-1 (previous scan line). The drain electrode of the first initialization thin film transistor T4 may be connected to the initialization voltage line VL. The source electrode of the first initialization thin film transistor T4 may be commonly connected to one electrode of the storage capacitor Cst, the drain electrode of the compensation thin film transistor T3, and the gate electrode of the driving thin film transistor T1. The first initialization thin film transistor T4 may be turned on according to the second scan signal Sn-1 provided through the second scan line SLn-1 and may perform an initialization operation of initializing the voltage of the gate electrode of the driving thin film transistor T1 by providing the initialization voltage VINT to the gate electrode of the driving thin film transistor T1.

[0083] The gate electrode of the first emission control thin film transistor T5 may be connected to the emission control line EL. The source electrode of the first emission control thin film transistor T5 may be connected to the driving voltage line PL. The drain electrode of the first emission control thin film transistor T5 may be connected to the source electrode of the driving thin film transistor T1 and the drain electrode of the switching thin film transistor T2.

[0084] The gate electrode of the second emission control thin film transistor T6 may be connected to the emission control line EL. The source electrode of the second emission control thin film transistor T6 may be connected to the drain electrode of the driving thin film transistor T1 and the source electrode of the compensation thin film transistor T3. The drain electrode of the second emission control thin film transistor T6 may be electrically connected to the pixel electrode of the organic light emitting diode OLED. The first emission control thin film transistor T5 and the second emission control thin film transistor T6 may be simultaneously turned on according to the emission control signal En provided through the emission control line EL. Accordingly, the first power supply voltage ELVDD may be provided to the organic light emitting diode OLED, and a driving current may flow through the organic light emitting diode OLED.

[0085] The gate electrode of the second initialization thin film transistor T7 may be connected to the second scan line SLn-1. The source electrode of the second initialization thin film transistor T7 may be connected to the pixel electrode of the organic light emitting diode OLED. The drain electrode of the second initialization thin film transistor T7 may be connected to the initialization voltage line VL. The second initialization thin film transistor T7 may be turned on according to the second scan signal Sn-1 provided through the second scan line SLn-1, and thus the pixel electrode of the organic light emitting diode OLED may be initialized.

[0086] In Figure 2B , the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the second scan line SLn-1. However, the exemplary embodiment is not limited thereto. For example, in the exemplary embodiment, the first initialization thin film transistor T4 may be connected to the second scan line SLn-1 as the previous scan line and may be driven according to the second scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to an additional signal line (e.g., the subsequent scan line) and may be driven according to the signal provided to the corresponding scan line.

[0087] One electrode of the storage capacitor Cst may be connected to the driving voltage line PL. The other electrode of the storage capacitor Cst may be connected together to the gate electrode of the driving thin film transistor T1, the drain electrode of the compensation thin film transistor T3, and the source electrode of the first initialization thin film transistor T4.

[0088] The counter electrode (e.g., the cathode of the organic light emitting diode OLED) may receive the second power supply voltage ELVSS (or the common power supply voltage). The organic light emitting diode OLED may receive a driving current from the driving thin film transistor T1, and thus may emit light.

[0089] It will be understood that the pixel circuit PC is not limited to the number of thin film transistors and storage capacitors and the circuit design described above with reference to Figure 2A and Figure 2B . For example, according to the exemplary embodiment, various modifications may be made to the number of thin film transistors and storage capacitors and the circuit design.

[0090] Referring to Figure 3 , a plurality of pixels P are arranged in Figure 1 region III. The plurality of pixels P may be surrounded by the pixel defining layer 113, and the spacers 115 may be arranged on the pixel defining layer 113. A plurality of first holes TH1 passing through the organic insulating layer may be formed between the pixels (the plurality of pixels) P.

[0091] In Figure 3 , each of the pixels P has a rectangular shape of the same size. However, the exemplary embodiment is not limited thereto. For example, according to the exemplary embodiment, the size, shape, and arrangement of the pixels P may be modified.

[0092] The spacer 115 may be disposed between some of the plurality of pixels P. For example, the spacer 115 may be disposed between some of the plurality of pixels P rather than all of the pixels P, and may be disposed in a non-uniform manner. The spacer 115 may maintain a separation between the mask and the substrate during a process of depositing an intermediate layer (see Figure 4 320) including an emission layer using a mask, and thus may prevent or reduce a defect in which the intermediate layer 320 is stamped or torn by the mask during the deposition process.

[0093] The spacer 115 may include the same material as the pixel defining layer 113. When the pixel defining layer 113 is formed using a halftone mask, the spacer 115 may be formed of the same material as the pixel defining layer 113 to have a different height from the pixel defining layer 113.

[0094] The first hole TH1 may be formed between some of the plurality of pixels P. For example, the first hole TH1 may be formed between some of the plurality of pixels P rather than all of the pixels P, and may be formed in a non-uniform manner. The first hole TH1 may be formed in the pixel defining layer 113 and the second planarization layer 111 (see Figure 4 ) to have a certain opening space penetrating the pixel defining layer 113 and the second planarization layer 111, so that a thin film encapsulation layer 400 described below can be fixed to a back plane.

[0095] Referring to Figure 4 , the buffer layer 101 may be located on the substrate 100, and the driving thin film transistor T1, the switching thin film transistor T2, and the storage capacitor Cst may be located on the buffer layer 101.

[0096] The substrate 100 may include various materials such as, for example, glass, metal, or plastic. For example, the substrate 100 may include a flexible substrate including a polymer resin (such as polyether sulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP)).

[0097] The buffer layer 101 may include, for example, silicon oxide (SiO x ) and / or silicon nitride (SiN x ) and may be formed on the substrate 100 to prevent or reduce the intrusion of impurities.

[0098] The driving thin film transistor T1 may include a driving semiconductor layer A1 and a driving gate electrode G1, and the switching thin film transistor T2 may include a switching semiconductor layer A2 and a switching gate electrode G2. A first gate insulating layer 103 is disposed between the driving semiconductor layer A1 and the driving gate electrode G1 and between the switching semiconductor layer A2 and the switching gate electrode G2. The first gate insulating layer 103 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON) as an example.

[0099] The driving semiconductor layer A1 and the switching semiconductor layer A2 may include, for example, amorphous silicon or polycrystalline silicon. In an exemplary embodiment, the driving semiconductor layer A1 and the switching semiconductor layer A2 may include an oxide containing at least one of, for example, indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn).

[0100] The driving semiconductor layer A1 may include a driving channel region that overlaps with the driving gate electrode G1 and in which no impurities are doped, and a driving source region and a driving drain region that are located on both sides of the driving channel region and in which impurities are doped. The driving source electrode S1 and the driving drain electrode D1 may be connected to the driving source region and the driving drain region, respectively.

[0101] The switching semiconductor layer A2 may include a switching channel region that overlaps with the switching gate electrode G2 and in which no impurities are doped, and a switching source region and a switching drain region that are located on both sides of the switching channel region and in which impurities are doped. The switching source electrode S2 and the switching drain electrode D2 may be connected to the switching source region and the switching drain region, respectively.

[0102] The driving gate electrode G1 and the switching gate electrode G2 may include, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a single-layer or multi-layer structure.

[0103] In an exemplary embodiment, the storage capacitor Cst may overlap with the driving thin film transistor T1. In this case, the areas of the storage capacitor Cst and the driving thin film transistor T1 can be reduced, and high-quality images can be provided. For example, the driving gate electrode G1 may be a first storage capacitor electrode CE1 of the storage capacitor Cst. A second storage capacitor electrode CE2 may overlap with the first storage capacitor electrode CE1, and a second gate insulating layer 105 is disposed between the first storage capacitor electrode CE1 and the second storage capacitor electrode CE2. The second gate insulating layer 105 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiON) as an example.

[0104] The driving thin film transistor T1, the switching thin film transistor T2, and the storage capacitor Cst may be covered by an interlayer insulating layer 107.

[0105] The interlayer insulating layer 107 may include an inorganic material layer, such as silicon oxynitride (SiON), silicon oxide (SiO x ), and / or silicon nitride (SiN x ), as examples.

[0106] The data line DL may be located on the interlayer insulating layer 107, and the data line DL may be in contact with the switching semiconductor layer A2 of the switching thin film transistor T2 through a contact hole penetrating into the interlayer insulating layer 107, the second gate insulating layer 105, and the first gate insulating layer 103. The data line DL may serve as the switching source electrode S2.

[0107] The driving source electrode S1, the driving drain electrode D1, the switching source electrode S2, and the switching drain electrode D2 may be disposed on the interlayer insulating layer 107, and the driving source electrode S1 and the driving drain electrode D1 or the switching source electrode S2 and the switching drain electrode D2 may be in contact with the driving semiconductor layer A1 or the switching semiconductor layer A2 through a contact hole penetrating into the interlayer insulating layer 107, the second gate insulating layer 105, and the first gate insulating layer 103.

[0108] In addition, the data line DL, the driving source electrode S1, the driving drain electrode D1, the switching source electrode S2, and the switching drain electrode D2 may be covered by an inorganic protective layer.

[0109] The inorganic protective layer may have a single-layer or multi-layer structure of, for example, silicon nitride (SiN x ) and silicon oxide (SiO x ). The inorganic protective layer may prevent the partial wiring exposed in the non-display area NDA (for example, the wiring formed together in the same process as the data line DL) from being damaged by the etchant used when patterning the pixel electrode 310.

[0110] The driving voltage line PL may be located on a layer different from the layer of the data line DL. Here, when component A and component B are described as being located on different layers, it may mean that at least one insulating layer is provided between component A and component B (for example, one of component A and component B is located below at least one insulating layer, and the other of component A and component B is located above the at least one insulating layer). The first planarization layer 109 may be provided between the driving voltage line PL and the data line DL, and the driving voltage line PL may be covered by the second planarization layer 111.

[0111] The driving voltage line PL may have a single-layer or multi-layer structure including at least one of, for example, aluminum (Al), copper (Cu), titanium (Ti), and alloys thereof. In an exemplary embodiment, the driving voltage line PL may have a three-layer structure of Ti / Al / Ti.

[0112] Figure 4 A configuration in which the driving voltage line PL is located on the first planarization layer 109 is shown. However, the exemplary embodiment is not limited thereto. For example, in an exemplary embodiment, the driving voltage line PL may be in contact with a lower additional voltage line formed on the same layer as the data line DL through a via hole formed in the first planarization layer 109.

[0113] The first planarization layer 109 and the second planarization layer 111 may have a single-layer or multi-layer structure.

[0114] The first planarization layer 109 and the second planarization layer 111 may include an organic insulating material. In an example, the organic insulating material may include general polymers such as polymethyl methacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylate polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, and vinyl alcohol polymers.

[0115] In addition, the first planarization layer 109 and the second planarization layer 111 may include an inorganic insulating material. In an exemplary embodiment, the inorganic insulating material may include, for example, silicon oxynitride (SiON), silicon oxide (SiO x ) and silicon nitride (SiN x ).

[0116] The organic light-emitting diode OLED may be located on the second planarization layer 111. The organic light-emitting diode OLED may include a pixel electrode 310, a counter electrode 330, and an intermediate layer 320 disposed between the pixel electrode 310 and the counter electrode 330 and including an emission layer 320b.

[0117] The pixel electrode 310 may be connected to a connection line CL formed on the first planarization layer 109, and the connection line CL may be connected to the driving drain electrode D1 of the driving thin-film transistor T1.

[0118] The pixel electrode 310 may include a transparent electrode or a reflective electrode.

[0119] When the pixel electrode 310 includes a transparent electrode, the pixel electrode 310 may include a transparent conductive layer. The transparent conductive layer may include at least one of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In this case, in addition to the transparent conductive layer, the pixel electrode 310 may further include a semi-transparent layer that can improve light efficiency. The semi-transparent layer may include at least one of, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and ytterbium (Yb) formed as a thin film having a thickness of several micrometers (μm) to several tens of micrometers (μm).

[0120] When the pixel electrode 310 includes a reflective electrode, the pixel electrode 310 may include a reflective layer and a transparent conductive layer. The reflective layer includes at least one of, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and their compounds. The transparent conductive layer is on and / or under the reflective layer. The transparent conductive layer may include at least one of, for example, ITO, IZO, ZnO, In2O3, IGO, and AZO.

[0121] However, the exemplary embodiments are not limited thereto, and the pixel electrode 310 may include various materials. In addition, various modifications in which the structure of the pixel electrode 310 has a single-layer or multi-layer structure may be made according to the exemplary embodiments.

[0122] The pixel defining layer 113 may be located on the pixel electrode 310. As Figure 4 shown, the pixel defining layer 113 may cover at least one edge of the pixel electrode 310. For example, as Figure 4 shown, the pixel defining layer 113 may cover the first edge of the pixel electrode 310 and may cover the second edge of the pixel electrode 310 opposite to the first edge. Accordingly, the pixel defining layer 113 may cover at least one edge of the pixel electrode 310 of each of the plurality of pixels P.

[0123] The pixel defining layer 113 may have an opening exposing the pixel electrode 310, thereby defining the pixel P. In addition, the pixel defining layer 113 may increase the distance between the end of the pixel electrode 310 and the counter electrode 330, thereby preventing an arc from being generated therebetween. The pixel defining layer 113 may include an organic material, such as polyimide or hexamethyldisiloxane (HMDSO) as an example.

[0124] The intermediate layer 320 may include an emission layer 320b, a first functional layer 320a disposed under the emission layer 320b, and / or a second functional layer 320c disposed on the emission layer 320b. The emission layer 320b may include a polymer or a small-molecular-weight organic material that emits light of a specific color.

[0125] The first functional layer 320a may have a single-layer or multi-layer structure. For example, when the first functional layer 320a includes a polymer material, the first functional layer 320a may include a hole transport layer (HTL) having a single-layer structure and may include poly-(3,4)-ethylenedioxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer 320a includes a small-molecular-weight material, the first functional layer 320a may include a hole injection layer (HIL) and a hole transport layer (HTL).

[0126] In an exemplary embodiment, the second functional layer 320c may not be included in the intermediate layer 320. However, the exemplary embodiment is not limited thereto. For example, when the first functional layer 320a and the emission layer 320b include small-molecular-weight materials, the second functional layer 320c may be formed. The second functional layer 320c may have a single-layer or multi-layer structure. The second functional layer 320c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0127] The emission layer 320b of the intermediate layer 320 may be located in each of the pixels P in the display area DA. The emission layer 320b may be formed above the pixel electrode 310 exposed through the opening of the pixel defining layer 113. The first functional layer 320a and the second functional layer 320c of the intermediate layer 320 may be formed as an integral layer on the plurality of pixel electrodes 310. Various methods such as vacuum deposition may be used to form the intermediate layer 320.

[0128] The counter electrode 330 may be located in the upper part of the display area DA to cover the display area DA. For example, the counter electrode 330 may be integrally formed in the plurality of organic light-emitting diodes OLEDs and may correspond to the plurality of pixel electrodes 310. The counter electrode 330 may be electrically connected to the second power supply voltage line 20 to be described below.

[0129] The counter electrode 330 may include a transparent electrode or a reflective electrode. When the counter electrode 330 includes a transparent electrode, the counter electrode 330 may include, for example, at least one of Ag, Al, Mg, Li, Ca, Cu, LiF / Ca, LiF / Al, MgAg, and CaAg, and may have the form of a thin film with a thickness of several micrometers (μm) to several tens of micrometers (μm).

[0130] When the counter electrode 330 includes a reflective electrode, the counter electrode 330 may include at least one of, for example, Ag, Al, Mg, Li, Ca, Cu, LiF / Ca, LiF / Al, MgAg, and CaAg. However, the configuration and material of the counter electrode 330 are not limited thereto and may be modified according to the exemplary embodiments.

[0131] The spacer 115 may be disposed on the pixel defining layer 113. The spacer 115 may protrude from the pixel defining layer 113 in a direction toward the thin film encapsulation layer 400, and may maintain a separation between the mask and the substrate 100 during the process of depositing the intermediate layer 320 including the emission layer 320b, thereby preventing defects such as the intermediate layer 320 being stamped or torn by the mask during the deposition process.

[0132] The spacer 115 may include an organic material, such as polyimide or HMDSO as an example. The spacer 115 may be disposed on at least one of the first dam part 110 and the second dam part 120 to be described later, and thus may be used to prevent or reduce moisture movement and to form a dam part having a stepped height.

[0133] The thin film encapsulation layer 400 may cover and protect the organic light emitting diode OLED from being damaged by, for example, moisture or oxygen.

[0134] The thin film encapsulation layer 400 may cover the display area DA and may extend to the outside of the display area DA. The thin film encapsulation layer 400 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. In the exemplary embodiment, the thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

[0135] The first inorganic encapsulation layer 410 may cover the counter electrode 330 and may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0136] An additional layer (such as a cover layer as an example) may be provided between the first inorganic encapsulation layer 410 and the counter electrode 330. The cover layer may include, for example, silicon oxide (SiO2), silicon nitride (SiN x) at least one organic or inorganic material such as zinc oxide (ZnO2), titanium dioxide (TiO2), zirconium dioxide (ZrO2), indium tin oxide (ITO), indium zinc oxide (IZO), Alq3, CuPc, CBP, a-NPB, and ZiO2 to improve light efficiency. In an exemplary embodiment, the cover layer can cause a plasma resonance phenomenon with respect to the light generated in the organic light emitting diode OLED. For example, the cover layer can include nanoparticles. In addition, the cover layer can prevent the organic light emitting diode OLED from being damaged by the heat and plasma generated in the chemical vapor deposition (CVD) process or sputtering process used to form the thin film encapsulation layer 400. For example, the cover layer can include an epoxy material formed of at least one of bisphenol type epoxy resin, epoxy butadiene resin, fluorine type epoxy resin, and linear phenolic epoxy resin.

[0137] In addition, a layer including LiF can be disposed between the first inorganic encapsulation layer 410 and the cover layer.

[0138] The first inorganic encapsulation layer 410 is formed along the structure below it. Therefore, the top surface of the first inorganic encapsulation layer 410 is not substantially flat. The organic encapsulation layer 420 can cover and flatten the first inorganic encapsulation layer 410. The top surface of the organic encapsulation layer 420 corresponding to the display area DA can be substantially flat (e.g., completely flat or approximately flat within the measurement error).

[0139] The organic encapsulation layer 420 can include, for example, at least one or a combination of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resins (e.g., polymethyl methacrylate, polyacrylic acid).

[0140] The second inorganic encapsulation layer 430 can cover the organic encapsulation layer 420 and can include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The second inorganic encapsulation layer 430 can be deposited to directly contact the first inorganic encapsulation layer 410 at the end of the display device 1, so that the organic encapsulation layer 420 can be sealed such that the organic encapsulation layer 420 is not exposed to the outside of the display device 1.

[0141] However, in the subsequent process after forming the thin film encapsulation layer 400, a defect of peeling of the thin film encapsulation layer 400 from the backplane of the display device 1 occurs. The subsequent process can be, for example, a process of forming a touch sensor layer (not shown) on the thin film encapsulation layer 400 or a process of removing the protective film adhered to the thin film encapsulation layer 400 before attaching a polarizing film (not shown) to the thin film encapsulation layer 400. During the above processes, when an external force is applied to the thin film encapsulation layer 400, a peeling defect occurs. The backplane can be the structure of the display device 1 immediately before forming the thin film encapsulation layer 400.

[0142] For example, when the counter electrode 330 is formed immediately before the formation of the thin film encapsulation layer 400, peeling defects may occur between the display device 1 including the counter electrode 330 and the thin film encapsulation layer 400. For example, when the above-described cover layer is formed between the counter electrode 330 and the thin film encapsulation layer 400 immediately before the formation of the thin film encapsulation layer 400, peeling defects may occur between the display device 1 including the cover layer and the thin film encapsulation layer 400. For example, when a layer including LiF is formed between the cover layer and the first inorganic encapsulation layer 410, peeling defects may occur between the display device 1 including the layer containing LiF and the thin film encapsulation layer 400. In addition, when another functional layer is further added between the counter electrode 330 and the thin film encapsulation layer 400 immediately before the formation of the thin film encapsulation layer 400, the display device 1 including the organic light emitting diode OLED and the functional layer can be understood as a backplane.

[0143] In an exemplary embodiment, in order to reduce peeling defects of the thin film encapsulation layer 400, a plurality of first holes TH1 serving as anchors with respect to the thin film encapsulation layer 400 may be formed between a plurality of pixels P in the display area DA. The plurality of first holes TH1 may increase the adhesion strength between the thin film encapsulation layer 400 and the backplane, thereby preventing the occurrence of the above-described defects.

[0144] The plurality of first holes TH1 may be separated from the pixel electrode 310, may pass through the second planarization layer 111 and the pixel defining layer 113, and may be formed to have a certain opening space.

[0145] The first etch stop layer ES1 is located on the first planarization layer 109 at the position where the first holes TH1 are formed. For example, the position of the first etch stop layer ES1 may correspond to the position of the first holes TH1. The first etch stop layer ES1 may be separated from the connection line CL, may include the same material as the connection line CL, and may be formed in the same process as the connection line CL. The first etch stop layer ES1 may be configured to prevent deterioration of the first planarization layer 109 and various wirings, electrodes, and circuits of the display device 1 thereunder or reduce deterioration of the first planarization layer 109 and various wirings, electrodes, and circuits of the display device 1 thereunder during the process of forming the first holes TH1 (for example, when the opening space of the first holes TH1 is formed by dry etching).

[0146] The intermediate layer 320 and the counter electrode 330 may be formed on the bottom surface of the first hole TH1. For example, the intermediate layer 320 and the counter electrode 330 may be formed between the first hole TH1 and the first etch stop layer ES1. In an exemplary embodiment, the first functional layer 320a and the second functional layer 320c of the intermediate layer 320 are formed inside (and outside) the first hole TH1, and the emission layer 320b of the intermediate layer 320 is not formed inside the first hole TH1. This is because the emission layer 320b is deposited only in the emission regions patterned in each pixel P using a patterned metal mask, and the first functional layer 320a and the second functional layer 320c are not patterned in each pixel P but may be deposited as a common layer on all pixels P. The counter electrode 330 may be deposited as a common layer on all pixels P in a manner similar to the first functional layer 320a and the second functional layer 320c.

[0147] The first inorganic encapsulation layer 410 of the thin film encapsulation layer 400 is formed on the counter electrode 330 inside the first hole TH1. The first inorganic encapsulation layer 410 is not formed only on the bottom surface of the first hole TH1, but is formed integrally on the inner surface of the first hole TH1 including the side surface 111S of the second planarization layer 111, the side surface 113S of the pixel defining layer 113, and the bottom surface 113B of the pixel defining layer 113. For example, the first inorganic encapsulation layer 410 may be formed conformally along the entire inner surface of the first hole TH1 such that there are no breaks or gaps in the first inorganic encapsulation layer 410 inside the first hole TH1.

[0148] The first inorganic encapsulation layer 410 is in direct contact with the counter electrode 330 on the bottom surface inside the first hole TH1, in direct contact with the second planarization layer 111 on the side surface 111S of the second planarization layer 111, and in direct contact with the pixel defining layer 113 on the bottom surface 113B and the side surface 113S of the pixel defining layer 113. As a result, the contact area between the first inorganic encapsulation layer 410 and the organic insulating layer can be increased, and thus, the adhesion of the thin film encapsulation layer 400 can be improved.

[0149] The organic encapsulation layer 420 fills the entire interior of the first hole TH1. For example, the organic encapsulation layer 420 fills the entirety of the first hole TH1. For example, in an exemplary embodiment, the shape of the opening formed in the first hole TH1 is an undercut shape, in which, at the boundary surface where the pixel defining layer 113 and the second planarization layer 111 meet each other, the side surface 113S of the pixel defining layer 113 protrudes further into the first hole TH1 than the side surface 111S of the second planarization layer 111. Accordingly, the undercut-shaped opening is filled with the organic encapsulation layer 420 such that the first hole TH1 can be used as an anchor for increasing the adhesion strength between the thin film encapsulation layer 400 and the backplane. For example, in an exemplary embodiment, the width of the portion of the organic encapsulation layer 420 disposed in the first hole TH1 and in the region below the pixel defining layer 113 (e.g., in the region within the second planarization layer 111) is larger than the width of the portion of the organic encapsulation layer 420 disposed in the first hole TH1 and in the region above the second planarization layer 111 (e.g., in the region within the pixel defining layer 113), thereby forming an anchor structure for increasing the adhesion strength between the thin film encapsulation layer 400 and the backplane.

[0150] As described above, in the display device 1 according to the exemplary embodiment, a plurality of first holes TH1 are formed between the plurality of pixels P in the display area DA. As a result, the adhesion strength between the thin film encapsulation layer 400 and the backplane can be increased, and thus, the defect of the thin film encapsulation layer 400 peeling off from the backplane can be reduced.

[0151] Hereinafter, with reference to Figures 5A to 5H the manufacturing process of forming the first hole TH1 according to the exemplary embodiment will be described. Figure 4 the first hole TH1 will be described.

[0152] Figures 5A to 5H FIG. is a cross-sectional view schematically showing the manufacturing process of the first hole TH1 in the region A of forming Figure 4 according to the exemplary embodiment.

[0153] Referring to Figure 5A , a first etch stop layer ES1 may be formed on the first planarization layer 109, and a second planarization layer 111 may be formed on the first etch stop layer ES1. A pixel defining layer 113 having a first contact hole CNT1 formed therein may be formed on the second planarization layer 111.

[0154] Referring to Figure 5B , a photoresist PR may be formed on the second planarization layer 111 and the pixel defining layer 113, and a photolithography process may be performed using a first mask M1 having a light-transmitting portion M11 and a light-blocking portion M12, where light is transmitted through the light-transmitting portion M11 and not through the light-blocking portion M12.

[0155] Referring toFigure 5C , it is possible to develop the photoresist PR, such that a part of the photoresist pattern PR' can be retained.

[0156] Referring to Figure 5D , a barrier layer BL can be formed using a deposition process, and the remaining photoresist pattern PR' can be removed. When viewed from a plan view, the barrier layer BL surrounds the first contact hole CNT1.

[0157] Referring to Figure 5E , the barrier layer BL can be used as an etching mask to etch the pixel defining layer 113 and the second planarization layer 111, thereby forming a first hole TH1. The first hole TH1 can be formed by, for example, dry etching.

[0158] Referring to Figure 5F , the barrier layer BL can be removed by, for example, wet etching, and then the first hole TH1 can be formed. The shape of the opening formed in the first hole TH1 can be the shape of an undercut UC, in which, at the boundary surface where the pixel defining layer 113 and the second planarization layer 111 meet, the side surface 113S of the pixel defining layer 113 protrudes more into the first hole TH1 than the side surface 111S of the second planarization layer 111. Based on the boundary surface between the pixel defining layer 113 and the second planarization layer 111, a first width W1 of the opening formed in the pixel defining layer 113 can be smaller than a second width W2 of the opening formed in the second planarization layer 111. For example, at the boundary surface, the end of the pixel defining layer 113 can protrude further into the first hole TH1 by ΔW than the end of the second planarization layer 111, and thus, the undercut UC can be formed on the bottom surface of the pixel defining layer 113.

[0159] The width W0 of the first etching prevention layer ES1 can be larger than the first width W1 and the second width W2. Therefore, it is possible to prevent the first planarization layer 109 and various wirings, electrodes, and circuits of the display device 1 provided under the first planarization layer 109 from being deteriorated due to dry etching.

[0160] Referring to Figure 5G , an intermediate layer 320 and a counter electrode 330 can be deposited in the first hole TH1. The intermediate layer 320 and the counter electrode 330 can be formed on the bottom surface of the first hole TH1 and the top surface of the pixel defining layer 113. For example, the intermediate layer 320 and the counter electrode 330 can be cut off based on the undercut UC of the first hole TH1. The intermediate layer 320 formed in the first hole TH1 can include a first functional layer 320a and a second functional layer 320c, and does not include an emission layer 320b.

[0161] The intermediate layer 320 and the counter electrode 330 can be formed by, for example, physical vapor deposition (PVD). In an example, one of the processes such as sputtering, thermal evaporation, electron beam evaporation, laser molecular beam epitaxy, and pulsed laser deposition can be used to form the intermediate layer 320 and the counter electrode 330.

[0162] Referring to Figure 5H , a thin film encapsulation layer 400 including a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430 can be formed in the first hole TH1.

[0163] The first inorganic encapsulation layer 410 is not only formed on the bottom surface of the first hole TH1, but can also be formed on the entire inner surface of the first hole TH1 including the side surface 111S of the second planarization layer 111, the side surface 113S of the pixel defining layer 113, and the bottom surface 113B of the pixel defining layer 113.

[0164] The first inorganic encapsulation layer 410 can be formed by, for example, CVD or atomic layer deposition (ALD) having a higher step coverage than PVD. In an example, one of the processes such as thermal CVD, plasma CVD, metalorganic CVD (MOCVD), and hydride vapor phase epitaxy (HVPE) can be used to form the first inorganic encapsulation layer 410.

[0165] After forming the first inorganic encapsulation layer 410, the organic encapsulation layer 420 is formed. The entire inside of the first hole TH1 can be filled with the organic encapsulation layer 420. After forming the organic encapsulation layer 420, the second inorganic encapsulation layer 430 can be formed.

[0166] Figure 6 is a cross-sectional view schematically showing a part of the display device 2 according to an exemplary embodiment. For example, Figure 6 corresponds to the cross-sectional view taken along line IVA-IVB of the display device 1 according to Figure 3 the exemplary embodiment.

[0167] For ease of explanation, the following description will mainly focus on Figure 6 the differences between the exemplary embodiments of Figure 4 and the above-described exemplary embodiments, and further descriptions of the previously described elements and aspects can be omitted.

[0168] Referring to Figure 6 , the second etch stop layer ES2 can be located between the second planarization layer 111 and the pixel defining layer 113. The second etch stop layer ES2 can be separated from the pixel electrode 310. The second etch stop layer ES2 can include the same material as the pixel electrode 310.

[0169] When performing dry etching to form the opening of the first hole TH1, due to the process dispersion of dry etching, the pixel defining layer 113 may be over-etched. However, in an exemplary embodiment, the second etch stop layer ES2 may be located between the pixel defining layer 113 and the second planarization layer 111, and may prevent the over-etching of the pixel defining layer 113, so that the undercut shape of the first hole TH1 is effectively formed.

[0170] As described above, the undercut shape of the first hole TH1 can be effectively formed. Therefore, the first inorganic encapsulation layer 410 can be formed on the entire inner surface of the first hole TH1. Accordingly, the contact area where the first inorganic encapsulation layer 410 contacts the organic insulating layers (such as the pixel defining layer 113 and the second planarization layer 111 for example) can be increased, and the adhesion of the thin film encapsulation layer 400 can be improved. In addition, the entire first hole TH1 having an undercut shape is filled with the organic encapsulation layer 420, thereby increasing the adhesion strength between the thin film encapsulation layer 400 and the backplane.

[0171] Figure 7 is a cross-sectional view schematically showing a part of the display device 3 according to an exemplary embodiment. For example, Figure 7 is corresponding to the cross-sectional view taken along line IVA-IVB of the display device 1 according to an exemplary embodiment Figure 3 as described above.

[0172] For ease of explanation, the following description will mainly focus on Figure 7 the differences between the exemplary embodiment of Figure 6 and the above-described exemplary embodiment of

[0173] and the further description of the previously described elements and aspects may be omitted. Figure 7 Referring to

[0174] Even in the exemplary embodiment of Figure 7 including the second etch stop layer ES2, the pixel defining layer 113 may be over-etched while performing dry etching to form the opening of the first hole TH1. Therefore, an undercut having a desired shape may not be obtained. However, in an exemplary embodiment, the third etch stop layer ES3 may be further formed on the second etch stop layer ES2. Accordingly, the over-etching of the pixel defining layer 113 can be prevented, so that an undercut having a desired shape can be formed.

[0175] Figure 8is a cross-sectional view schematically showing a part of a display device 4 according to an exemplary embodiment. For example, Figure 8 corresponds to a cross-sectional view taken along line IVA-IVB of the display device 1 according to an exemplary embodiment. Figure 3

[0176] For ease of explanation, the following description will mainly focus on Figure 8 the differences between the exemplary embodiments of Figure 4 and the above-described exemplary embodiments of

[0177] and further descriptions of previously described elements and aspects may be omitted. Figure 8 Referring to

[0178] , the shape of the first hole TH1 is not an undercut shape. For example, based on the boundary surface between the pixel defining layer 113 and the second planarization layer 111, the width of the opening formed in the pixel defining layer 113 and the width of the opening formed in the second planarization layer 111 may be substantially equal to each other. Figure 8 Although the first hole TH1 in the exemplary embodiment of

[0179] Figures 9A to 9E does not have an undercut shape, the first inorganic encapsulation layer 410 is formed over the entire inside of the first hole TH1, so that the contact area between the first inorganic encapsulation layer 410 and the organic insulating layers (such as the pixel defining layer 113 and the second planarization layer 111 for example) can be increased. Therefore, the adhesion of the thin film encapsulation layer 400 can be improved. In addition, the entire inside of the first hole TH1 can be filled with the organic encapsulation layer 420, so that the adhesion strength between the thin film encapsulation layer 400 and the backplane can be increased. Figure 8 is a cross-sectional view schematically showing a manufacturing process of forming the first hole TH1 according to an exemplary embodiment.

[0180] Referring to Figure 9A , a first etch stop layer ES1 may be formed on the first planarization layer 109, and a second planarization layer 111 may be formed on the first etch stop layer ES1. The pixel defining layer 113 is formed on the second planarization layer 111. At this time in the manufacturing process, compared with Figure 5A , the first contact hole CNT1 is not formed in the pixel defining layer 113.

[0181] Referring to Figure 9B , a second mask M2 may be disposed on the pixel defining layer 113. The second mask M2 includes a light transmissive portion M21 and a light blocking portion M22. Light is transmitted through the light transmissive portion M21, and light cannot be transmitted through the light blocking portion M22, and the second mask M2 may be irradiated with a laser L.

[0182] Referring to Figure 9C ​, the first hole TH1 can be formed after irradiating the position corresponding to the first hole TH1 with the laser L. The shape of the opening formed in the first hole TH1 is not an undercut shape. For example, based on the boundary surface between the pixel defining layer 113 and the second planarization layer 111, the width W12 of the opening formed in the pixel defining layer 113 and the width W12 of the opening formed in the second planarization layer 111 can be substantially equal to each other.

[0183] Refer to Figure 9D , the intermediate layer 320 and the counter electrode 330 can be deposited in the first hole TH1. The intermediate layer 320 and the counter electrode 330 can be formed on the bottom surface of the first hole TH1 and the top surface of the pixel defining layer 113. The intermediate layer 320 formed in the first hole TH1 can include a first functional layer 320a and a second functional layer 320c, and does not include an emission layer 320b.

[0184] Since the intermediate layer 320 and the counter electrode 330 can be formed by PVD, which has a lower step coverage compared to CVD, in the exemplary embodiment, the intermediate layer 320 and the counter electrode 330 are not deposited on the inner surface of the first hole TH1.

[0185] Refer to Figure 9E , a thin film encapsulation layer 400 including a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430 can be formed in the first hole TH1.

[0186] The first inorganic encapsulation layer 410 is not only formed on the bottom surface of the first hole TH1, but can also be formed on the entire inner surface of the first hole TH1 including the side surface 111S of the second planarization layer 111 and the side surface 113S of the pixel defining layer 113. The first inorganic encapsulation layer 410 can be formed by CVD, which has a higher step coverage compared to PVD.

[0187] After the first inorganic encapsulation layer 410 is formed, the organic encapsulation layer 420 is formed. The entire inside of the first hole TH1 can be filled with the organic encapsulation layer 420. After the organic encapsulation layer 420 is formed, the second inorganic encapsulation layer 430 is formed.

[0188] In Figures 9A to 9E , the first etch prevention layer ES1 is shown. However, the exemplary embodiment is not limited thereto. For example, since the irradiation depth of the laser beam can be adjusted by adjusting the power of the laser, even when the first etch prevention layer ES1 is removed, the first planarization layer 109 and the elements under the first planarization layer 109 can be prevented from deteriorating. In addition, in the exemplary embodiment, the first etch prevention layer ES1 can be removed to prevent an increase in the reflectance due to the first etch prevention layer ES1.

[0189] In addition, inFigure 9B In [the above], a second mask M2 including a light-transmitting portion M21 and a light-blocking portion M22 may be used to specify a laser irradiation area. However, the exemplary embodiments are not limited thereto. For example, according to the exemplary embodiments, various methods for transmitting / shielding laser irradiation other than the second mask M2 may be used.

[0190] Figures 9A to 9E The process of forming the first hole TH1 using the laser L is shown in [the above]. However, the exemplary embodiments are not limited thereto. For example, in the exemplary embodiments, different processes (including, for example, a photolithography process) may be used to form Figure 8 the first hole TH1. Figure 8

[0191] Hereinafter, a display device 5 according to an exemplary embodiment will be described with reference to Figure 10 . Figure 10 It corresponds to a cross-sectional view taken along the line XA-XB of the display device 1 according to the exemplary embodiment of Figure 1 .

[0192] Referring to Figure 10 , in the exemplary embodiment, a plurality of second holes TH2 may be formed in the non-display area NDA, and the first dam portion 110 and the second dam portion 120 may be located outside the second holes TH2. Similar to the exemplary embodiment of Figure 4 , in the exemplary embodiment of Figure 10 , the first hole TH1 may be formed in the display area DA.

[0193] The first planarization layer 109, the second planarization layer 111, and the pixel definition layer 113 extending from the display area DA may extend into the non-display area NDA such that they are provided in both the non-display area NDA and the display area DA.

[0194] A plurality of fourth etch-stop layers ES4 may be located on the first planarization layer 109, and a fifth etch-stop layer ES5 may be located between the second planarization layer 111 and the pixel definition layer 113. The plurality of second holes TH2 passing through the pixel definition layer 113 and the second planarization layer 111 may be located on the fourth etch-stop layer ES4.

[0195] The fourth etch-stop layer ES4 may include the same material as the first etch-stop layer ES1 and / or the connection line CL of Figure 4 , and may be formed in the same process as the first etch-stop layer ES1 and / or the connection line CL of Figure 4 . During the process of forming the second holes TH2 (for example, when forming the opening space of the second holes TH2 by, for example, dry etching), the fourth etch-stop layer ES4 may prevent deterioration of various wirings, electrodes, and circuits of the display device 5 under the first planarization layer 109.​

[0196] The fifth etch stop layer ES5 may include the same material as the pixel electrode 310. When performing dry etching to form the opening of the second hole TH2, due to the process dispersion of the dry etching, the pixel defining layer 113 may be over-etched. However, in an exemplary embodiment, the fifth etch stop layer ES5 disposed between the pixel defining layer 113 and the second planarization layer 111 may prevent the pixel defining layer 113 from being over-etched, thereby effectively forming the undercut shape of the second hole TH2.

[0197] In an exemplary embodiment, the intermediate layer 320 and the counter electrode 330 are not only formed in the display area DA, but may also extend to and be formed in a part of the non-display area NDA outside the display area DA.

[0198] The intermediate layer 320 may be formed on the bottom surface of the second hole TH2 above the fourth etch stop layer ES4. In an exemplary embodiment, the first functional layer 320a and the second functional layer 320c of the intermediate layer 320 may be formed inside the second hole TH2, and the emission layer 320b of the intermediate layer 320 is not formed inside the second hole TH2.

[0199] The counter electrode 330 may be formed above the intermediate layer 320. Similar to the intermediate layer 320, in an exemplary embodiment, the counter electrode 330 may be formed on the bottom surface of the second hole TH2 and not formed on the side surface of the second hole TH2.

[0200] Similar to the first functional layer 320a and the second functional layer 320c, the counter electrode 330 may be deposited as a common layer on all pixels P. The counter electrode 330 may be formed on the bottom surface inside the second hole TH2 and may also be formed on the top surface outside the second hole TH2.

[0201] Since the counter electrode 330 can be integrally connected outside the opening where the second hole TH2 is formed, when viewed from a plane substantially parallel to the substrate 100, the counter electrode 330 extending from the display area DA can be electrically connected to the second power supply voltage line 20 described above.

[0202] The layout relationship of the fifth etch stop layer ES5, the pixel defining layer 113, and the counter electrode 330 in the plan view will be described with reference to the area where the second hole TH2 is formed Figures 11A to 11D for description. Figures 11A to 11D is a plan view schematically showing a part of the process of forming Figure 10 the second hole TH2 according to an exemplary embodiment.

[0203] Refer to Figure 11A, a fifth etch stop layer ES5 having a plurality of openings OP1 may be formed on the second planarization layer 111. The openings OP1 may be formed using a patterning process, such as a lithography process for example. The fifth etch stop layer ES5 may be integrally connected in the space outside the openings OP1. In this case, in the exemplary embodiment, the second planarization layer 111 inside the openings OP1 is not removed, and the second planarization layer 111 may be located inside the openings OP1.

[0204] Referring to Figure 11B , a pixel defining layer 113 may be formed on the openings OP1 and the fifth etch stop layer ES5.

[0205] Referring to Figure 11C , the second planarization layer 111 and the pixel defining layer 113 may be dry-etched so that a second via hole TH2 can be formed.

[0206] The fifth etch stop layer ES5 may prevent the pixel defining layer 113 from being over-etched, so that the second via hole TH2 having an undercut shape can be effectively formed. In this case, the second planarization layer 111 provided inside the second via hole TH2 may be removed, and the pixel defining layer 113 may be stacked on the fifth etch stop layer ES5 outside the second via hole TH2.

[0207] Although a plurality of first via holes TH1 as described with reference to Figure 3 may be formed in the display area DA, additionally arranging the first via holes TH1 in the non-emitting areas between the pixels P may cause space limitations as the resolution increases. However, to take this into account, in the exemplary embodiment, the second via hole TH2 may be formed in the non-display area NDA. Since various wirings, electrodes, and circuits of the display device 5 may be arranged in the non-display area NDA below the second via hole TH2, a larger number of second via holes TH2 than the number of first via holes TH1 can be densely formed per unit area without space limitations caused by the resolution.

[0208] Although Figure 11C the shape of the second via hole TH2 is shown as a circular shape, the exemplary embodiment is not limited thereto. For example, various modifications may be made to the shape and arrangement of the second via hole TH2.

[0209] Referring to Figure 11D , after forming the second via hole TH2, an intermediate layer 320 and a counter electrode 330 are sequentially deposited. Figure 11DThe counter electrode 330 is shown, while the intermediate layer 320 is omitted. The counter electrode 330 may cover the entirety of the intermediate layer 320 and may be formed in a region wider than the intermediate layer 320. After the intermediate layer 320 is formed, the counter electrode 330 may be formed on the bottom surface inside the second hole TH2 and may also be formed on the top surface outside the second hole TH2.

[0210] Since the counter electrode 330 is integrally connected outside the opening of the second hole TH2 formed therein, when viewed from a plane substantially parallel to the substrate 100, the counter electrode 330 extending from the display region DA can be electrically connected to the second power supply voltage line 20 described above.

[0211] Returning to Figure 10 , the counter electrode 330 may be connected to the second power supply voltage line 20 via a pixel electrode connection line 310a provided between the second hole TH2 and the first dam portion 110. The pixel electrode connection line 310a may be a line extending from the above-described fifth etch prevention layer ES5. The pixel electrode connection line 310a may include the same material as the pixel electrode 310.

[0212] The first inorganic encapsulation layer 410 may be formed on the counter electrode 330. The first inorganic encapsulation layer 410 is not only formed on the bottom surface of the second hole TH2 but may also be formed on the entire inner surface of the second hole TH2 including the side surface 111S of the second planarization layer 111, the side surface 113S of the pixel defining layer 113, and the bottom surface 113B of the pixel defining layer 113.

[0213] The first inorganic encapsulation layer 410 is in direct contact with the counter electrode 330 on the bottom surface inside the second hole TH2, in direct contact with the second planarization layer 111 on the side surface 111S of the second planarization layer 111, and in direct contact with the pixel defining layer 113 on the bottom surface 113B and the side surface 113S of the pixel defining layer 113. As a result, the adhesion of the thin film encapsulation layer 400 can be improved by increasing the contact area between the first inorganic encapsulation layer 410 and the organic insulating layer.

[0214] The entirety of the inside of the second hole TH2 may be filled with the organic encapsulation layer 420. Since the shape of the opening formed in the second hole TH2 is an undercut shape (in the undercut shape, at the boundary surface where the pixel defining layer 113 and the second planarization layer 111 meet, the side surface 113S of the pixel defining layer 113 protrudes further into the second hole TH2 than the side surface 111S of the second planarization layer 111), the undercut-shaped opening is filled with the organic encapsulation layer 420 such that the second hole TH2 can be used as an anchor for increasing the adhesion strength between the thin film encapsulation layer 400 and the backplane.

[0215] Outside the second hole TH2, the first dam portion 110 and the second dam portion 120 may be located at positions where they overlap with the second power supply voltage line 20.

[0216] The first dam portion 110 may be formed to have a first layer 111a including the same material as the second planarization layer 111, a second layer 113a including the same material as the pixel defining layer 113, and a third layer 115a including the same material as the spacer 115. However, the layers constituting the first dam portion 110 are not limited thereto, and the number and materials of the layers may be modified.

[0217] A portion of the first dam portion 110 may overlap with the counter electrode 330 extending in the non-display area NDA. The end of the counter electrode 330 may extend to the second power supply voltage line 20. As a result, noise that would otherwise affect the touch sensor layer formed on the thin film encapsulation layer 400 can be prevented or reduced.

[0218] The second dam portion 120 may be formed to have a first layer 109b including the same material as the first planarization layer 109, a second layer 111b including the same material as the second planarization layer 111, a third layer 113b including the same material as the pixel defining layer 113, and a fourth layer 115b including the same material as the spacer 115. However, the layers constituting the second dam portion 120 are not limited thereto, and the number and materials of the layers may be modified.

[0219] The second dam portion 120 may be formed to be higher than the first dam portion 110. For example, with respect to the substrate 100, the height of the second dam portion 120 may be greater than the height of the first dam portion 110. As a result, it is possible to prevent the organic encapsulation layer 420 from forming an edge tail by climbing over the second dam portion 120, and it is possible to maintain the separation between the mask and the substrate 100 during the process of depositing the intermediate layer 320 using a mask. Therefore, defects in which the intermediate layer 320 may be stamped or torn by the mask during the deposition process can be prevented or reduced.

[0220] The first layer 109b of the second dam portion 120 may cover the end of the second power supply voltage line 20, thereby preventing the second power supply voltage line 20 from deteriorating during wet etching. For example, the first layer 109b of the second dam portion 120 may cover the end of the second power supply voltage line 20.

[0221] The first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may pass through the display area DA and the area where the second hole TH2 is formed, may cover the first dam part 110 and the second dam part 120, and may extend near the edge of the substrate 100. Outside the second dam part 120, the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may be in direct contact with each other, so that external moisture or impurities can be prevented from penetrating into the display device 5 through the organic encapsulation layer 420.

[0222] In addition, as described above, the second hole TH2 formed in the non-display area NDA in the exemplary embodiment may be configured to improve the adhesion strength between the thin film encapsulation layer 400 and the backplane, thereby preventing the peeling of the thin film encapsulation layer 400. In addition, since an opening space reaching the height of the second planarization layer 111 and the pixel defining layer 113 is formed in a direction substantially perpendicular to the substrate 100, the reflux speed of the flowable organic insulating material in the process of forming the organic encapsulation layer 420 using a flowable organic material can be reduced.

[0223] The height of the second dam part 120 may be greater than the height of the first dam part 110, so that the organic encapsulation layer 420 can be prevented from forming an edge tail at the edge of the substrate 100 by climbing over the second dam part 120. However, when the distance between the first dam part 110 and the second dam part 120 is reduced to reduce the width of the dead zone, it will be difficult to control the reflux speed of the organic encapsulation layer 420. Therefore, the organic encapsulation layer 420 will climb over the second dam part 120.

[0224] As the second hole TH2 according to the exemplary embodiment of the plurality of opening spaces formed between the display area DA and the first dam part 110, the reflux speed of the flowable organic insulating material (for example, the organic encapsulation layer 420) flowing in the direction of the edge of the substrate 100 can be reduced, so that the organic insulating material can be sufficiently hardened before reaching the second dam part 120, thereby preventing the formation of an edge tail caused by the organic insulating material.

[0225] According to the exemplary embodiment, a plurality of holes may be formed in the display area and / or the non-display area, so that the adhesion strength between the thin film encapsulation layer and the backplane can be improved, and the peeling of the thin film encapsulation layer can be prevented.

[0226] Although the present disclosure has been specifically shown and described with reference to the exemplary embodiments of the present disclosure, those of ordinary skill in the art will understand that various changes in form and details may be made thereto without departing from the spirit and scope of the present disclosure defined by the claims.

Claims

1. A display device, the display device comprising: a substrate; a display area disposed on the substrate and including a plurality of pixels; a first planarization layer disposed on the substrate; a second planarization layer disposed on the first planarization layer; a pixel defining layer disposed on the second planarization layer and covering at least one edge of a first electrode of each of the plurality of pixels; a plurality of first holes disposed between the plurality of pixels and separated from the first electrodes, wherein each of the plurality of first holes includes an opening passing through the second planarization layer and the pixel defining layer respectively; and a first etching prevention layer disposed on a bottom surface of each of the plurality of first holes and located on the first planarization layer, wherein each of the plurality of pixels includes an intermediate layer disposed on the first electrode and a second electrode disposed on the intermediate layer, and the intermediate layer and the second electrode are disposed on the bottom surface of each of the plurality of first holes and not on a side surface of the second planarization layer.

2. The display device according to claim 1, wherein at a boundary surface between the pixel defining layer and the second planarization layer, a first width of the opening formed in the pixel defining layer is smaller than a second width of the opening formed in the second planarization layer.

3. The display device according to claim 1, wherein the intermediate layer includes an emission layer.

4. The display device according to claim 1, wherein at a boundary surface between the pixel defining layer and the second planarization layer, a first width of the opening formed in the pixel defining layer and a second width of the opening formed in the second planarization layer are equal to each other.

5. A display device, the display device comprising: a substrate; a display area disposed on the substrate and including a plurality of pixels, wherein each of the plurality of pixels includes a first electrode, a second electrode, and an intermediate layer, the intermediate layer being disposed between the first electrode and the second electrode, and wherein the intermediate layer includes an emission layer; a thin film encapsulation layer encapsulating the plurality of pixels and including a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer, the organic encapsulation layer being disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer; a non-display area disposed outside the display area; a first planarization layer extending from the display area into the non-display area and disposed between the substrate and the first electrode; a second planarization layer extending from the display area into the non-display area and disposed on the first planarization layer; a pixel defining layer covering at least one edge of the first electrode, extending from the display area into the non-display area, and disposed on the second planarization layer; a plurality of holes disposed in the non-display area, wherein each of the plurality of holes includes an opening passing through the second planarization layer and the pixel defining layer respectively; and A first etch prevention layer is disposed on the first planarization layer under the plurality of holes, wherein, the intermediate layer and the second electrode extend into the non-display area and are disposed inside each of the plurality of holes, the first inorganic encapsulation layer extends into the non-display area and covers the entirety of the second electrode inside each of the plurality of holes and the entirety of the inner surface of each of the plurality of holes, the inner surface including the side surface of the second planarization layer, the side surface of the pixel defining layer, and the bottom surface of the pixel defining layer, and the entirety of each of the plurality of holes is filled with the organic encapsulation layer.

6. The display device according to claim 5, wherein the display device further comprises: a first dam portion and a second dam portion, each comprising at least one layer, the at least one layer comprising the same material as the second planarization layer and / or the pixel defining layer, wherein, the first inorganic encapsulation layer extends from the plurality of holes and covers the first dam portion and the second dam portion, and is in direct contact with the second inorganic encapsulation layer outside the second dam portion.

7. A method of manufacturing a display device, the method comprising: forming a first planarization layer on a substrate; forming a first etch prevention layer on the first planarization layer; forming a second planarization layer on the first etch prevention layer; forming a pixel defining layer on the second planarization layer; and forming a plurality of first holes passing through the second planarization layer and the pixel defining layer in a display area, wherein, the display area is disposed on the substrate and comprises a plurality of pixels, each pixel of the plurality of pixels comprises a first electrode, a second electrode, and an intermediate layer, the intermediate layer comprising an emission layer and being disposed between the first electrode and the second electrode, the display device comprises a thin film encapsulation layer, the thin film encapsulation layer encapsulating the display area and comprising a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer, the organic encapsulation layer being disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer, the intermediate layer and the second electrode are formed on the top surface of the first etch prevention layer and the top surface of the pixel defining layer, and the first inorganic encapsulation layer covers the entirety of the second electrode inside each of the plurality of first holes and the entirety of the inner surface of each of the plurality of first holes, the inner surface including the side surface of the second planarization layer, the side surface of the pixel defining layer, and the bottom surface of the pixel defining layer, and the entirety of each of the plurality of first holes is filled with the organic encapsulation layer.

8. The method according to claim 7, wherein the method further comprises: forming a first contact hole in the pixel defining layer; and forming a barrier layer on the pixel defining layer, wherein, the barrier layer surrounds the first contact hole, and the plurality of first holes are formed by dry etching the second planarization layer and the pixel defining layer using the barrier layer as an etch mask.

9. The method according to claim 7, wherein the method further comprises: A plurality of second holes penetrating the second planarization layer and the pixel definition layer are formed in a non-display area outside the display area; and A second etch prevention layer is formed on the bottom surface of each of the plurality of second holes and on the first planarization layer, wherein the first planarization layer, the second planarization layer, and the pixel definition layer extend into the non-display area.

10. The method according to claim 7, wherein, the plurality of first holes are formed by irradiating a position corresponding to the first etch prevention layer with a laser.

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