Display device

Abstract

The present disclosure relates to a display device, the display device including: a first semiconductor layer located on a first buffer layer and including a first active layer; a first gate insulating layer located on the first semiconductor layer and covering the first active layer; a first conductive layer located on the first gate insulating layer and including a first gate electrode; a second conductive layer located on the first conductive layer and including a first source / drain electrode; a first interlayer insulating layer located on the first conductive layer; a second semiconductor layer located on the first interlayer insulating layer and including a second active layer; a second gate insulating layer located on the second semiconductor layer and covering the second active layer; and a third conductive layer located on the second gate insulating layer and including a second gate electrode and a second source / drain electrode. The first gate insulating layer and the second gate insulating layer include insulating materials different from each other.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0111612, filed with the Korean Intellectual Property Office on September 9, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of example embodiments of the present disclosure relate to a display device, and more particularly, to a display device including transistors disposed at different layers from each other (e.g., disposed on different layers from each other) and a plurality of gate insulating layers different from each other. Background Art

[0004] With the development of multimedia, the importance of display devices is increasing. Accordingly, various display devices such as organic light emitting display (OLED) devices and liquid crystal display (LCD) devices are used.

[0005] A display device is a device that displays an image and includes a display panel such as an organic light emitting display panel or a liquid crystal display panel. Among these display panels, the display device may include a light emitting element as a light emitting display panel. For example, a light emitting diode (LED) may include an organic light emitting diode (OLED) using an organic material as a fluorescent material or an inorganic light emitting diode using an inorganic material as a fluorescent material, etc.

[0006] Such a display device includes a display panel, a gate driving circuit, a data driving circuit, and a timing controller. The display panel includes data lines, gate lines, and pixels. Each pixel is formed at an intersection between each data line and each gate line. When a gate signal is supplied to the gate line, each pixel uses a thin film transistor as a switching element to receive a data voltage from the data line. Each pixel emits light having a desired or appropriate brightness (e.g., a predetermined brightness) according to the data voltage.

[0007] Recently, display devices capable of displaying images with a high resolution of ultra high definition (UHD) have been released, and display devices capable of displaying images with a high resolution of 8K ultra high definition (8K UHD) have been developed. UHD refers to a resolution of 3840×2160, and 8K UHD refers to a resolution of 7680×4320.

[0008] In the case of a high resolution display device, as the number of pixels increases, the driving current of each pixel may decrease. Accordingly, the range of the driving voltage of the driving transistor of each pixel may decrease.

[0009] The above information disclosed in this background art section is used to enhance the understanding of the background of the present disclosure, and thus, the above information may include information that does not constitute the prior art. Summary of the Invention

[0010] Aspects of example embodiments of the present disclosure relate to a display device including different gate insulating layers according to the device characteristics of driving transistors and switching transistors.

[0011] It should be noted that the aspects and features of the example embodiments of the present disclosure are not limited to the above aspects and features, and according to the following description, other aspects and features of the present disclosure will be apparent to those skilled in the art.

[0012] According to an exemplary embodiment of the present disclosure, a display device includes: a substrate; a first buffer layer on the substrate; a first semiconductor layer on the first buffer layer and including a first active layer; a first gate insulating layer on the first semiconductor layer and the first buffer layer and covering the first active layer; a first conductive layer on the first gate insulating layer and including a first gate electrode; a second conductive layer on the first conductive layer and including a first source / drain electrode; a first interlayer insulating layer on the first conductive layer; a second semiconductor layer on the first interlayer insulating layer and including a second active layer; a second gate insulating layer on the second semiconductor layer and covering the second active layer; and a third conductive layer on the second gate insulating layer and including a second gate electrode and a second source / drain electrode. The first gate insulating layer and the second gate insulating layer include different insulating materials from each other.

[0013] In an exemplary embodiment, the first gate insulating layer may include a single layer containing silicon oxide, and the second gate insulating layer may include: a first insulating layer containing silicon oxide; and a second insulating layer on the first insulating layer and containing silicon nitride or silicon oxynitride.

[0014] In an exemplary embodiment, the first insulating layer of the second gate insulating layer may be in contact with the second active layer.

[0015] In an exemplary embodiment, the thickness of the first insulating layer may be greater than the thickness of the second insulating layer.

[0016] In an exemplary embodiment, the first gate insulating layer may include: a third insulating layer including silicon oxide; and a fourth insulating layer on the third insulating layer and containing silicon nitride or silicon oxynitride.

[0017] In an exemplary embodiment, the third insulating layer of the first gate insulating layer may be in contact with the first active layer.

[0018] In an exemplary embodiment, the hydrogen content of the fourth insulating layer may be lower than the hydrogen content of the second insulating layer.

[0019] In an exemplary embodiment, the width in one direction of the portion of the first active layer overlapping with the first gate electrode may be greater than the width in the one direction of the portion of the second active layer overlapping with the second gate electrode.

[0020] In an exemplary embodiment, the thickness of the first gate insulating layer may be greater than the thickness of the second gate insulating layer.

[0021] In an exemplary embodiment, the thickness of the first active layer may be greater than the thickness of the second active layer.

[0022] In an exemplary embodiment, the display device may further include: a second buffer layer located between the second active layer and the first interlayer insulating layer.

[0023] In an exemplary embodiment, the second semiconductor layer may further include a third active layer located on the second buffer layer, and the second gate insulating layer may be located on the third active layer.

[0024] In an exemplary embodiment, the third conductive layer may further include: a third gate electrode and third source / drain electrodes located on the second gate insulating layer and overlapping at least a portion of the third active layer.

[0025] In an exemplary embodiment, the display device may further include: a first protective layer located between the second conductive layer and the first conductive layer and between the second conductive layer and the first gate insulating layer, and the second conductive layer may be located on the first protective layer, and the second conductive layer may further include one electrode of a first capacitor, and at least a portion of the first capacitor overlaps with the first gate electrode.

[0026] In an exemplary embodiment, the display device may further include: a second interlayer insulating layer located on the third conductive layer; data signal lines located on the second interlayer insulating layer; a second protective layer located on the data signal lines; and a conductive pattern located on the second protective layer and including at least a portion overlapping with the data signal lines.

[0027] According to an exemplary embodiment of the present disclosure, a display device includes: a substrate; a first buffer layer located on the substrate; a first semiconductor layer located on the first buffer layer and including a first active layer; a first gate insulating layer located on the first semiconductor layer and the first buffer layer and covering the first active layer; a first conductive layer located on the first gate insulating layer and including a first gate electrode; a first interlayer insulating layer located on the first conductive layer; a second semiconductor layer located on the first interlayer insulating layer and including a second active layer; a second gate insulating layer located on the second semiconductor layer and covering the second active layer; and a second conductive layer located on the second gate insulating layer and including a second gate electrode. The thickness of the first gate insulating layer is greater than the thickness of the second gate insulating layer.

[0028] In an exemplary embodiment, the thickness of the first active layer may be greater than the thickness of the second active layer.

[0029] In an exemplary embodiment, the first gate insulating layer may include a single layer containing silicon oxide, and the second gate insulating layer may include: a first insulating layer containing silicon oxide; and a second insulating layer located on the first insulating layer and containing silicon nitride.

[0030] In an exemplary embodiment, the second insulating layer of the second gate insulating layer may contain silicon oxynitride.

[0031] According to an exemplary embodiment of the present disclosure, a display device includes: a substrate; a driving transistor located on the substrate and including a first active layer, a first gate electrode, and a first source / drain electrode; a first interlayer insulating layer located on the driving transistor; a first switching transistor located on the first interlayer insulating layer and including a second active layer, a second gate electrode, and a second source / drain electrode; a first gate insulating layer located between the first active layer and the first gate electrode; and a second gate insulating layer located between the second active layer and the second gate electrode. The width of the channel region of the first active layer in one direction is greater than the width of the channel region of the second active layer in the one direction, and the dielectric constant of the first gate insulating layer is lower than the dielectric constant of the second gate insulating layer. Description of the Drawings

[0032] Through the following detailed description of the exemplary embodiments of the present disclosure with reference to the accompanying drawings, the above and other aspects and features of the present disclosure will become more apparent to those skilled in the art. In the drawings:

[0033] Figure 1 is a perspective view showing a display device according to an exemplary embodiment;

[0034] Figure 2is a plan view showing an example of a display device according to an exemplary embodiment;

[0035] Figure 3 is a block diagram showing a display device according to an exemplary embodiment;

[0036] Figure 4 is showing Figure 2 an equivalent circuit diagram of a pixel of;

[0037] Figure 5 is a cross-sectional view showing a part of a display device according to an exemplary embodiment;

[0038] Figure 6 is a graph showing changes in drain-induced barrier lowering values according to the width of a channel region of a transistor and the type of a gate insulating layer;

[0039] Figures 7 to 9 is a cross-sectional view showing a part of a display device according to various exemplary embodiments;

[0040] Figure 10 is a graph showing changes in threshold voltage values according to the width of a channel region of a transistor and the type of a gate insulating layer;

[0041] Figures 11 to 13 is a cross-sectional view showing a part of a display device according to various exemplary embodiments;

[0042] Figure 14 is a plan view showing an example of a display device according to an exemplary embodiment;

[0043] Figure 15 is showing Figure 14 an equivalent circuit diagram of a pixel of;

[0044] Figure 16 is showing Figure 14 a cross-sectional view of a part of a display device of; and

[0045] Figure 17 is an equivalent circuit diagram of a pixel of a display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0046] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numerals always refer to like elements. However, the present disclosure may be implemented in various different forms and should not be construed as limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the aspects and features of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise indicated, like reference numerals refer to like elements throughout the drawings and the written description, and thus, their description may not be repeated.

[0047] In the drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated and / or simplified. For ease of explanation, spatially relative terms such as "under", "below", "lower", "beneath", "above", "upper", "left", and "right" may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the drawings. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawing is flipped, an element described as "under", "below", or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the example terms "under" and "beneath" can cover both an upper and a lower orientation. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0048] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, first component, first region, first layer, or first part described below may be named a second element, second component, second region, second layer, or second part without departing from the spirit and scope of the present disclosure.

[0049] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or there can be one or more intervening elements or layers. Additionally, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the sole element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0050] The terms used herein are for the purpose of describing particular embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are also intended to include the plural forms. It will also be understood that when used in this specification, the terms "comprises," "comprising," "includes," and "having" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When an expression such as "at least one of..." is placed after a list of elements, it modifies the entire list of elements and not individual elements within the list.

[0051] As used herein, the terms "substantially," "about," and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations of measured or calculated values that would be recognized by a person of ordinary skill in the art. Additionally, when describing embodiments of the present disclosure, the use of "may" means "one or more embodiments of the present disclosure." As used herein, the term "use" can be considered synonymous with the term "utilize." Additionally, the term "exemplary" is intended to mean an example or illustration.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms such as those defined in a general dictionary should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense.

[0053] Figure 1 is a perspective view showing a display device according to an exemplary embodiment.

[0054] Refer to Figure 1, the display device 1 displays video images and / or still images. The display device 1 may refer to any suitable electronic device provided with a display screen. For example, the display device 1 may include a television, a laptop computer, a monitor, a digital sign, a device for the Internet of Things, a mobile phone, a smartphone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation system, a gaming machine, a digital camera, and / or a portable video camera, etc.

[0055] The display device 1 includes a display panel 10 that provides a display screen. Examples of the display panel 10 may include a light-emitting diode (LED) display panel, an organic light-emitting display panel, a quantum dot light-emitting display panel, a plasma display panel, and a field emission display panel, etc. Hereinafter, for convenience, the LED display panel will be described as an example of the display panel 10, but the present disclosure is not limited thereto, and the display panel 10 may include (or may be) any suitable type of display panel. More specifically, hereinafter, as an example, the display panel 10 may be mainly described as an organic light-emitting display (OLED) panel, but the present disclosure is not limited thereto.

[0056] As used in the present disclosure, the terms "above", "upper", "top", and "upper surface" refer to the upward direction with respect to the thickness direction of the display panel 10, for example, the Z-axis direction, and the terms "below", "lower", "bottom", and "lower surface" refer to the downward direction with respect to the thickness direction of the display panel 10, for example, the direction opposite to the Z-axis direction. In addition, the terms "right", "left", "up", and "down" refer to the directions when the display panel 10 is observed in a plan view. As used herein, a plan view refers to a plan view observed from a plane parallel to or substantially parallel to (or perpendicular to) the top surface of the relevant element, component, and / or layer, etc. (for example, the top surface of the display panel 10 and / or the display device 1, etc.). For example, the term "right" may refer to the X-axis direction, the term "left" may refer to the direction opposite to the X-axis direction, the term "up" may refer to the Y-axis direction, and the term "down" may refer to the direction opposite to the Y-axis direction.

[0057] The display device 1 may have various suitable shapes. For example, the display device 1 may have various suitable shapes such as a rectangular shape in which its lateral sides are longer sides (or long sides), a rectangular shape in which its longitudinal sides are longer sides (or long sides), a square shape, a quadrilateral shape in which its corners (e.g., vertices) are rounded, other suitable polygonal shapes, and / or a circular shape. The shape of the display area DA of the display device 1 may correspond to the shape of the display device 1. For example, the shape of the display area DA may have the same or substantially the same shape (or a similar shape) as the overall shape of the display device 1. In Figure 1 FIG. 2, the display device 1 and the display area DA are shown as having a rectangular shape in which its longitudinal sides are long sides, but the present disclosure is not limited thereto.

[0058] The display device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where an image can be displayed, and the non-display area NDA is an area where an image cannot be displayed. The display area DA may be referred to as an active area, and the non-display area NDA may be referred to as a passive area.

[0059] Generally, the display area DA may substantially occupy the center (e.g., the central area) of the display device 1. The display area DA may include a plurality of pixels PX (see Figure 2 FIG. 3). The plurality of pixels PX may be arranged in a matrix form. In a plan view, the shape of each of the pixels PX may be a rectangular shape or a square shape, but the present disclosure is not limited thereto, and each of the pixels PX may have any suitable shape. For example, the shape of each of the pixels PX may be a rhombus shape in which its sides are inclined with respect to a first direction (e.g., the X-axis direction).

[0060] The non-display area NDA may be provided around the display area DA (e.g., provided at the periphery of the display area DA). For example, the non-display area NDA may completely or partially surround the display area DA (e.g., around the periphery of the display area DA). For example, when the display area DA has a rectangular shape, the non-display area NDA may be arranged adjacent to the four sides of the display area DA. The non-display area NDA may define (e.g., may form) the border of the display device 1.

[0061] Figure 2 is a plan view showing an example of a display device according to an exemplary embodiment. Figure 3 is a block diagram showing a display device according to an exemplary embodiment.

[0062] Combined with Figure 1 Referring to Figure 2 and Figure 3 FIG. 3, the display device 1 includes a display panel 10, a display driving circuit 20, and a circuit board 30.

[0063] The display panel 10 may be formed to have a flat surface with a rectangular shape, the flat surface having a short side in a first direction (e.g., the X-axis direction) and a long side in a second direction (e.g., the Y-axis direction) intersecting the first direction (e.g., the X-axis direction). The corner where the short side in the first direction (e.g., the X-axis direction) intersects (e.g., meets or combines with) the long side in the second direction (e.g., the Y-axis direction) may be formed to be rounded with a curvature (e.g., a predetermined curvature), or may be formed at a right angle. The planar shape of the display panel 10 (e.g., the shape in a plan view) is not limited to a rectangular shape, and may be formed to have various suitable shapes such as, for example, another polygon shape, a circular shape, and / or an elliptical shape. The display panel 10 may be formed flat, but the present disclosure is not limited thereto, and the display panel 10 may include curved surface portions formed at its left and right ends. For example, the display panel 10 (e.g., the curved surface portions of the display panel 10) may have a constant curvature or various curvatures. Additionally, the display panel 10 may be formed to be flexible so as to be bendable, foldable, and / or rollable, etc.

[0064] The display panel 10 may include: a display area DA including a plurality of pixels PX formed thereon to display an image; and a non-display area NDA that may define (or may be) a peripheral area of the display area DA. At the display area DA (e.g., in the display area DA or on the display area DA), in addition to the pixels PX, scan lines SL1 to SLn (e.g., SL1, SL2, ……, SLn - 1, and SLn), data lines DL1 to DLm (e.g., DL1, DL2, ……, DLm - 1, and DLm), a first voltage line VDDL, and a second voltage line VSSL connected to the pixels PX may also be provided. The scan lines SL1 to SLn may be provided (e.g., may be formed) to extend in a first direction (e.g., the X-axis direction), and may be parallel or substantially parallel to each other, and the data lines DL1 to DLm may be provided (e.g., may be formed) to extend in a second direction (e.g., the Y-axis direction) intersecting the first direction (e.g., the X-axis direction), and may be parallel or substantially parallel to each other. The first voltage line VDDL may be formed to extend in the second direction (e.g., the Y-axis direction) in the display area DA, and may be parallel or substantially parallel to each other. The first voltage lines VDDL that are parallel or substantially parallel to each other and are formed to extend in the second direction (Y-axis direction) may be connected to each other at the non-display area NDA (e.g., may be in the non-display area NDA or may be on the non-display area NDA).

[0065] ​Each of the pixels PX can be connected to one of the data lines DL1 to DLm, one of the first voltage lines VDDL, and at least one of the scan lines SL1 to SLn. Additionally, each of the pixels PX can be electrically connected to the second voltage line VSSL. In Figure 2 each pixel PX is shown as being connected to one scan line, one data line, and one first voltage line VDDL, but the present disclosure is not limited thereto.

[0066] Each of the pixels PX can include a plurality of transistors, a light-emitting element, and a capacitor. The plurality of transistors can include a driving transistor and at least one switching transistor. The driving transistor can be configured to control a driving current flowing through the light-emitting element in accordance with a data voltage applied to a gate electrode of the driving transistor. The plurality of transistors can include (or can be) thin-film transistors. The light-emitting element can emit light in accordance with the driving current of the driving transistor. The capacitor can be used to hold or substantially hold (e.g., continuously hold) the data voltage applied to the gate electrode of the driving transistor.

[0067] The non-display area NDA can be defined as a peripheral area of the display area DA. In the non-display area NDA (e.g., in the non-display area NDA or on the non-display area NDA), a scan driver 40 for applying a scan signal to the scan lines SL1 to SLn, fan-out lines FL respectively connected to the pads DP, and the pads DP connected to the circuit board 30 can be provided. The pads DP can be provided at one side edge of the display panel 10. For example, as Figure 2 shown, the pads DP can be provided at one of the short sides of the display panel 10, but the present disclosure is not limited thereto.

[0068] The scan driver 40 can be connected to the pads DP through a plurality of scan control lines SCL. Thus, the scan driver 40 can receive a scan control signal CTL1 from the display driving circuit 20 through the plurality of scan control lines SCL. The scan driver 40 can generate a scan signal in accordance with the scan control signal CTL1, and can output (e.g., can sequentially output) the scan signal to the scan lines SL1 to SLn.

[0069] The scan driver 40 can include a plurality of thin-film transistors. The scan driver 40 can be formed at the same layer or a different layer as the layer of the thin-film transistors of the pixels PX (e.g., can be formed on the same layer or a different layer as the layer of the thin-film transistors of the pixels PX).

[0070] In Figure 2The scan driver 40 is shown as being formed in the non-display area NDA located on one side of the display area DA (e.g., formed in the non-display area NDA located on one side of the display area DA or formed on the non-display area NDA located on one side of the display area DA). For example, it is formed in the non-display area NDA located on the left side of the display area DA (e.g., formed in the non-display area NDA located on the left side of the display area DA or formed on the non-display area NDA located on the left side of the display area DA). However, the present disclosure is not limited thereto. For example, the scan driver 40 may be formed in the non-display areas NDA located on both sides (e.g., two opposite sides) of the display area DA (e.g., may be formed in the non-display areas NDA located on both sides (e.g., two opposite sides) of the display area DA or may be formed on the non-display areas NDA located on both sides (e.g., two opposite sides) of the display area DA). For example, it may be formed in the non-display areas NDA located on the left and right sides of the display area DA (e.g., may be formed in the non-display areas NDA located on the left and right sides of the display area DA or may be formed on the non-display areas NDA located on the left and right sides of the display area DA).

[0071] The display driving circuit 20 may be disposed at the display panel 10 by, for example, a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic welding method (e.g., may be disposed in the display panel 10 by, for example, a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic welding method or may be disposed on the display panel 10 by, for example, a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic welding method). As another example, the display driving circuit 20 may be formed of an integrated circuit (IC) and may be disposed on the circuit board 30. As Figure 3 shown, the display driving circuit 20 may include a timing controller 21 and a data driver 22.

[0072] The timing controller 21 receives video data (e.g., digital video data) DATA and a timing signal CTL. The timing controller 21 may generate a scan control signal CTL1 for controlling the operation timing of the scan driver 40 and a data control signal CTL2 for controlling the operation timing of the data driver 22 according to the timing signal CTL. The timing controller 21 may also generate a power control signal CTL3 for controlling the operation timing of the power circuit 23. The timing controller 21 may output the scan control signal CTL1 to the scan driver 40 through a plurality of scan control lines SCL, and may output the video data (e.g., digital video data) DATA and the data control signal CTL2 to the data driver 22. The timing controller 21 may output the power control signal CTL3 to the power circuit 23.

[0073] The data driver 22 converts video data (e.g., digital video data) into data voltages (e.g., analog positive / negative data voltages), and outputs the data voltages (e.g., analog positive / negative data voltages) to the data lines DL1 to DLm through the fan-out lines FL. When a pixel PX is selected according to the scan signal of the scan driver 40, the data voltage is supplied to the selected pixel PX.

[0074] The power supply circuit 23 may be formed of an IC and may be provided on the circuit board 30. The power supply circuit 23 may generate a first voltage VDD according to the input power and the power control signal CTL3, and may supply the first voltage VDD to the first voltage line VDDL. The power supply circuit 23 may generate a second voltage VSS, and may supply the second voltage VSS to the second voltage line VSSL. In addition, the power supply circuit 23 may generate an initialization voltage, and may supply the initialization voltage Vint to the initialization voltage line VintL (see Figure 4 ). In addition to the first voltage VDD, the second voltage VSS, and the initialization voltage Vint, the power supply circuit 23 may also generate various driving voltages for driving the display device 1. The power supply circuit 23 may include a DC-DC converter.

[0075] The circuit board 30 may be connected to the pad DP using an anisotropic conductive film (e.g., may be attached to the pad DP using an anisotropic conductive film). Accordingly, the circuit board 30 may be electrically connected to the pad DP. The circuit board 30 may be a flexible printed circuit board, a printed circuit board, and / or a flexible film such as a chip on film.

[0076] Figure 4 is a diagram showing Figure 2 the equivalent circuit of the pixel.

[0077] Referring to Figure 4 , the pixel PX may be connected to the k-th scan line SLk (where k is a positive integer), the j-th data line DLj (where j is a positive integer), the initialization voltage line VintL to which the initialization voltage Vint is applied, the first voltage line VDDL to which the first voltage VDD is applied, and the second voltage line VSSL to which the second voltage VSS is applied. The pixel PX may include a light-emitting element EL, a driving transistor DT, a first switching transistor ST1, a first capacitor Cst, and a second capacitor Cpr. Figure 4 shows that the pixel PX has a two-transistor-two-capacitor (2T2C) structure including one driving transistor DT, one switching transistor ST1, and two capacitors Cst and Cpr. However, the present disclosure is not limited thereto, and each pixel PX may include a larger number (e.g., a greater number) of transistors and / or capacitors.

[0078] In addition,Figure 4 It is shown that the driving transistor DT and the first switching transistor ST1 are formed of P-type metal oxide semiconductor (PMOS) transistors, but the present disclosure is not limited thereto. For example, each of the driving transistor DT and the first switching transistor ST1 may be formed of N-type metal oxide semiconductor (NMOS) transistors, or one of the driving transistor DT and the first switching transistor ST1 may be formed of PMOS transistors, and the other of the driving transistor DT and the first switching transistor ST1 may be formed of NMOS transistors. The PMOS transistor conducts through a gate conduction voltage lower than the gate cut-off voltage, and the NMOS transistor conducts through a gate conduction voltage higher than the gate cut-off voltage.

[0079] The light-emitting element EL emits light according to the driving current Id of the driving transistor DT. For example, the emission brightness of the light-emitting element EL may be proportional to the driving current Id.

[0080] As an example of the light-emitting element EL, an organic light-emitting diode (OLED) may be used, which includes a first electrode, a second electrode, and an organic light-emitting layer provided between the first electrode and the second electrode. As another example of the light-emitting element EL, an inorganic light-emitting diode may be used instead of the organic light-emitting diode (OLED), which includes a first electrode, a second electrode, and an inorganic semiconductor provided between the first electrode and the second electrode. As other examples of the light-emitting element EL, a quantum dot light-emitting diode or a micro light-emitting diode may be used instead of the organic light-emitting diode (OLED), which includes a first electrode, a second electrode, and a quantum dot light-emitting layer provided between the first electrode and the second electrode.

[0081] The first electrode of the light-emitting element EL may be connected to the second node N2, and the second electrode of the light-emitting element EL may be connected to the second voltage line VSSL. A parasitic capacitance Cel may be formed between the first electrode and the second electrode of the light-emitting element EL.

[0082] The driving transistor DT may be provided between the first voltage line VDDL and the second node N2. The driving transistor DT may control the drain-source current (hereinafter referred to as the driving current) Id according to the data voltage applied to its gate electrode. In the driving transistor DT, the driving current Id flowing through the channel may be proportional to the square of the difference between the gate-source voltage and the threshold voltage. The gate-source voltage may correspond to the voltage between the gate electrode of the driving transistor DT and the first electrode of the driving transistor DT.

[0083] The first switching transistor ST1 is disposed between a first node N1 and a second node N2. The first switching transistor ST1 is turned on by a k-th scan signal of a k-th scan line SLk and connects the first node N1 to the second node N2. A gate electrode of the first switching transistor ST1 may be connected to the k-th scan line SLk, a first electrode of the first switching transistor ST1 may be connected to the first node N1, and a second electrode of the first switching transistor ST1 may be connected to the second node N2.

[0084] When the first switching transistor ST1 is turned on, a gate electrode and a second electrode of the driving transistor DT are electrically connected to each other, and thus, the driving transistor DT operates as a diode. In other words, when the first switching transistor ST1 is turned on, the first switching transistor ST1 may connect the driving transistor DT in a diode manner.

[0085] When a first electrode of the driving transistor DT and a first electrode of the first switching transistor ST1 are source electrodes, a second electrode of the driving transistor DT and a second electrode of the first switching transistor ST1 may be drain electrodes. When a first electrode of the driving transistor DT and a first electrode of the first switching transistor ST1 are drain electrodes, a second electrode of the driving transistor DT and a second electrode of the first switching transistor ST1 may be source electrodes.

[0086] As will be described below, an active layer of the driving transistor DT and an active layer of the first switching transistor ST1 may be formed of polysilicon, amorphous silicon, or an oxide semiconductor. However, the present disclosure is not limited thereto, and an active layer of one of the driving transistor DT and the first switching transistor ST1 may be formed of polysilicon, and an active layer of the other of the driving transistor DT and the first switching transistor ST1 may be formed of an oxide semiconductor. For example, an active layer of the driving transistor DT may be formed of polysilicon, and an active layer of the first switching transistor ST1 may be formed of an oxide semiconductor.

[0087] A first capacitor Cst is disposed between the first node N1 and an initialization voltage line VintL. For example, the first capacitor Cst may include a first capacitor electrode connected to the first node N1 and a second capacitor electrode connected to the initialization voltage line VintL. The first capacitor Cst may be disposed between a gate electrode of the driving transistor DT and the initialization voltage line VintL and may be used to hold or substantially hold (e.g., continuously hold) a voltage applied to the gate electrode of the driving transistor DT.

[0088] A second capacitor Cpr is provided between a second node N2 and a j-th data line DLj. For example, the second capacitor Cpr may include a first capacitor electrode connected to the second node N2 and a second capacitor electrode connected to the j-th data line DLj. The capacitance of the second capacitor Cpr may be greater than (e.g., higher than) the capacitance of the first capacitor Cst.

[0089] The first node N1 may be a contact point among a gate electrode of a driving transistor DT, a first capacitor electrode of a first capacitor Cst, and a first electrode of a first switching transistor ST1. The second node N2 may be a contact point among a second electrode of the first switching transistor ST1, a first capacitor electrode of the second capacitor Cpr, a second electrode of the driving transistor DT, and a first electrode of a light-emitting element EL.

[0090] Hereinafter, the structure and arrangement (e.g., disposition) of transistors provided in each pixel PX will be described in more detail.

[0091] Figure 5 is a cross-sectional view showing a part of a display device according to an exemplary embodiment.

[0092] In Figure 5 a cross-sectional view of a part of a pixel PX including a driving transistor DT and a first switching transistor ST1 of the display device 1 is shown. However, the display device 1 is not limited to Figure 5 the cross-sectional view shown in

[0093] Referring to Figure 5 the display device 1 may include a first substrate 110, a plurality of conductive layers, a plurality of semiconductor layers, and a plurality of insulating layers. For example, the display device 1 includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer as its conductive layers and semiconductor layers. Each of the plurality of conductive layers and each of the plurality of semiconductor layers may be included in the driving transistor DT and the first switching transistor ST1 (e.g., may constitute the driving transistor DT and the first switching transistor ST1, or may be a part of the driving transistor DT and the first switching transistor ST1). In addition, the display device 1 may include a first buffer layer 121, a first gate insulating layer 130, a first protective layer 140, a first interlayer insulating layer 150, a second buffer layer 122, a second gate insulating layer 160, a second interlayer insulating layer 170, a second protective layer 180, and a first planarization film 190 as its plurality of insulating layers.

[0094] More specifically, the driving transistor DT includes a first active layer 350, a first gate electrode 310, and source / drain electrodes 330 and 340. The first switching transistor ST1 includes a second active layer 450, a second gate electrode 410, and source / drain electrodes 430 and 440. According to an exemplary embodiment, a plurality of transistors such as the driving transistor DT and the first switching transistor ST1 of the display device 1 may be disposed at different layers from each other (e.g., may be disposed on different layers from each other). For example, as Figure 5 shown in, the first switching transistor ST1 may be disposed above the driving transistor DT, and the second active layer 450 of the first switching transistor ST1 may overlap the first active layer 350 of the driving transistor DT in the thickness direction (e.g., the Z-axis direction). Accordingly, when the display device 1 includes a large number of pixels PX, the channel regions of the transistors may each have a width greater than or equal to a predetermined level. Accordingly, excellent device characteristics may be ensured in the transistors, and the display device 1 may have a high-resolution display quality.

[0095] Specifically, since the driving transistor DT and the first switching transistor ST1 are disposed at different layers from each other (e.g., are disposed in different layers from each other or are disposed on different layers from each other), the gate insulating layer between the gate electrode and the active layer of the driving transistor DT may be different from the gate insulating layer between the gate electrode and the active layer of the first switching transistor ST1. The display device 1 according to an exemplary embodiment may include a plurality of different gate insulating layers, and may control materials and / or thicknesses, etc. of the gate insulating layers to ensure or improve desired device characteristics of the driving transistor DT and the first switching transistor ST1.

[0096] Figure 5 It is shown that the driving transistor DT and the first switching transistor ST1 of the pixel PX are each formed in a coplanar structure. The coplanar structure has a top-gate structure in which a gate electrode is formed above an active layer. However, the present disclosure is not limited thereto, and the driving transistor DT and the first switching transistor ST1 of each pixel PX may each have a bottom-gate structure in which a gate electrode is formed below an active layer. Hereinafter, the driving transistor DT and the first switching transistor ST1 will be described in more detail.

[0097] The first substrate 110 may provide a region where the driving transistor DT and the first switching transistor ST1 are formed (e.g., in or on which). The first substrate 110 may include plastic or glass (e.g., may be made of plastic or glass).

[0098] The first buffer layer 121 is disposed on the first substrate 110. The first buffer layer 121 may be formed on the first substrate 110 to protect the transistors of the pixels PX and the organic light-emitting layer OL of the light-emitting element EL from moisture that may penetrate the first substrate 110, which may be vulnerable to moisture penetration. The first buffer layer 121 may be formed of a plurality of inorganic layers stacked alternately. For example, the first buffer layer 121 may be formed to have a multilayer structure in which silicon oxide (SiO x ) layers, silicon nitride (SiN x ) layers, and silicon oxynitride (SiON) layers, one or more inorganic layers are stacked alternately.

[0099] The first semiconductor layer is disposed on the first buffer layer 121. The first semiconductor layer includes a first active layer 350 of the driving transistor DT. The first active layer 350 may include polycrystalline silicon, single-crystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor (for example, may be made of polycrystalline silicon, single-crystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor).

[0100] The first active layer 350 may include a first conductive region 350a, a second conductive region 350b, and a channel region 350c. The channel region 350c may be disposed between the first conductive region 350a and the second conductive region 350b. The first conductive region 350a and the second conductive region 350b may be in contact with the source / drain electrodes 330 and 340 of the driving transistor DT to be described below.

[0101] The first gate insulating layer 130 may be disposed on the first semiconductor layer. The first gate insulating layer 130 may be disposed on the first buffer layer 121 including at least the first active layer 350. More specifically, the first gate insulating layer 130 may be disposed on a portion of the first buffer layer 121 where the first active layer 350 is not disposed, and may be disposed on a region where the first gate insulating layer 130 overlaps with the channel region 350c of the first active layer 350. In Figure 5 FIG., the first gate insulating layer 130 is shown as being disposed to cover the entire first buffer layer 121 including the upper surface and the side surfaces of the first active layer 350, but the present disclosure is not limited thereto. For example, the first gate insulating layer 130 may be disposed only on the upper surface of the first active layer 350, and thus, the first gate insulating layer 130 may be disposed only between the first gate electrode 310 and the first active layer 350 to be described in more detail below.

[0102] The first gate insulating layer 130 may include an inorganic material such as silicon oxide (SiO x ) or silicon nitride (SiN x ) or a stacked structure thereof (for example, may be made of an inorganic material such as silicon oxide (SiO x)), silicon nitride (SiN x ) or an inorganic material such as a stacked structure thereof). In Figure 5 , the first gate insulating layer 130 is shown as including one layer (e.g., formed of one layer), but the present disclosure is not limited thereto. As described above, in the display device 1 according to an exemplary embodiment, the driving transistor DT and the first switching transistor ST1 may be disposed at different layers from each other (e.g., may be disposed in different layers from each other or may be disposed on different layers from each other), such that the display device 1 includes a plurality of gate insulating layers. Various modifications (e.g., various selections) may be made to the material and / or thickness, etc. of the first gate insulating layer 130 to ensure or improve the desired device characteristics of the driving transistor DT. A detailed description thereof will be further described below.

[0103] A first conductive layer is disposed on the first gate insulating layer 130. The first conductive layer includes a first gate electrode 310 of the driving transistor DT. The first gate electrode 310 may overlap at least a part of the first active layer 350, and the first gate insulating layer 130 is interposed between the first gate electrode 310 and at least a part of the first active layer 350. For example, as Figure 5 shown, the width of the first gate electrode 310 measured in one direction (e.g., in the X-axis direction) crossing the thickness direction (e.g., the Z-axis direction) may be smaller than the width of the first active layer 350 measured in the one direction. The first gate electrode 310 may be disposed to overlap at least the channel region 350c of the first active layer 350, and the width of the first gate electrode 310 measured in the one direction may be equal to or substantially equal to the width of the channel region 350c of the first active layer 350 measured in the one direction.

[0104] The first gate electrode 310 of the first conductive layer may be formed as a single-layer structure or a multi-layer structure, the single-layer structure or multi-layer structure including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof (e.g., the single-layer structure or multi-layer structure is made of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) or an alloy thereof). However, the present disclosure is not limited thereto.

[0105] A first protective layer 140 is disposed on the first conductive layer. The first protective layer 140 may be disposed to cover the first gate insulating layer 130 and the first gate electrode 310. The first protective layer 140 may include, for example, SiO x , SiN x or a stacked structure thereof (e.g., may be made of SiO x , SiN xor their stacked structure is formed). A first contact hole CT1 extending through (e.g., passing through) the first protective layer 140 to partially expose the first active layer 350 and the first gate electrode 310 may be formed in the first protective layer 140.

[0106] A second conductive layer is disposed on the first protective layer 140. The second conductive layer may include a first source / drain electrode 330 and a second source / drain electrode 340 of the driving transistor DT, a first conductive pattern 370, and a second conductive pattern 710.

[0107] The second conductive pattern 710 may be disposed on the first protective layer 140 such that at least a portion of the second conductive pattern 710 overlaps with the first gate electrode 310. A first capacitor Cst may be formed between the first gate electrode 310 and the second conductive pattern 710. In other words, the second conductive pattern 710 may be a capacitor electrode of the first capacitor Cst.

[0108] The first source / drain electrode 330 of the driving transistor DT may be connected to the first active layer 350 through the first contact hole CT1 (e.g., may be in contact with the first active layer 350 through the first contact hole CT1), and the first contact hole CT1 partially exposes the upper surface of the first conductive region 350a of the first active layer 350. The second source / drain electrode 340 of the driving transistor DT may be connected to the first active layer 350 through the first contact hole CT1 (e.g., may be in contact with the first active layer 350 through the first contact hole CT1), and the first contact hole CT1 partially exposes the upper surface of the second conductive region 350b of the first active layer 350. The first source / drain electrode 330 of the driving transistor DT may be electrically connected to a first voltage line 810 (e.g., VDDL) through a third conductive pattern 610 to be described in more detail below. The second source / drain electrode 340 of the driving transistor DT may be electrically connected to a first electrode AE of the light-emitting element EL through a fifth conductive pattern 650 and a sixth conductive pattern 850 to be described in more detail below.

[0109] The first conductive pattern 370 is disposed to overlap with the first gate electrode 310 of the driving transistor DT, and a first gate insulating layer 130 is interposed between the first conductive pattern 370 and the first gate electrode 310 of the driving transistor DT. The first conductive pattern 370 may be connected to the first gate electrode 310 through the first contact hole CT1 (e.g., may be in contact with the first gate electrode 310 through the first contact hole CT1), and the first contact hole CT1 partially exposes the upper surface of the first gate electrode 310. The first conductive pattern 370 may be connected to a first source / drain electrode 430 of a first switching transistor ST1 to be described in more detail below (e.g., may be in contact with the first source / drain electrode 430 of the first switching transistor ST1 to be described in more detail below).

[0110] The second conductive layer may include (e.g., may be formed as) a single-layer structure or a multi-layer structure, and the single-layer structure or multi-layer structure includes at least one selected from Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof (e.g., the single-layer structure or multi-layer structure is made of at least one selected from Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof). However, the present disclosure is not limited thereto.

[0111] The first interlayer insulating layer 150 is disposed on the second conductive layer. More specifically, the first interlayer insulating layer 150 may be formed to cover the entire surfaces of the first protective layer 140 and the second conductive pattern 710. A second contact hole CT2 may be formed in the first interlayer insulating layer 150, and the second contact hole CT2 extends through (e.g., passes through) the first interlayer insulating layer 150 to partially expose the second conductive layer. For example, the second contact hole CT2 may partially expose the upper surfaces of each of the first source / drain electrode 330 of the driving transistor DT, the second source / drain electrode 340 of the driving transistor DT, the first conductive pattern 370, and the second conductive pattern 710. In addition, the second contact hole CT2 may be formed to extend through (e.g., pass through) the second buffer layer 122 and the second gate insulating layer 160, which will be described in more detail below. Furthermore, a third conductive layer, which will be described in more detail below, may be connected to the second conductive layer through the second contact hole CT2 (e.g., may be in contact with the second conductive layer through the second contact hole CT2), and the second conductive layer is, for example, the first source / drain electrode 330 and the second source / drain electrode 340 of the driving transistor DT, the first conductive pattern 370, and the second conductive pattern 710.

[0112] The first interlayer insulating layer 150 may include an inorganic material such as, for example, SiO x , SiN x or a stacked structure thereof (e.g., may be made of an inorganic material such as, for example, SiO x , SiN x or a stacked structure thereof).

[0113] The second buffer layer 122 is disposed on the first interlayer insulating layer 150. The display device 1 includes a driving transistor DT and a first switching transistor ST1 disposed at different layers from each other (e.g., disposed in different layers from each other or disposed on different layers from each other), such that the display device 1 may include at least one buffer layer on which each of the driving transistor DT and the first switching transistor ST1 is disposed. The display device 1 according to an exemplary embodiment includes a first buffer layer 121 and a second buffer layer 122 disposed above the first buffer layer 121. The first active layer 350 of the driving transistor DT may be disposed on the first buffer layer 121, the first buffer layer 121 is disposed on the first substrate 110, and the second active layer 450 of the first switching transistor ST1 may be disposed on the second buffer layer 122. The second buffer layer 122 may be disposed on the entire upper surface of the first interlayer insulating layer 150. The structure, material, and / or function of the second buffer layer 122 may be the same as or substantially the same as the structure, material, and / or function of the first buffer layer 121, and thus, its detailed description may not be repeated.

[0114] A second semiconductor layer is disposed on the second buffer layer 122. The second semiconductor layer includes the second active layer 450 of the first switching transistor ST1. The second active layer 450 may include polysilicon, single crystal silicon, low temperature polysilicon, amorphous silicon, or an oxide semiconductor (e.g., may be made of polysilicon, single crystal silicon, low temperature polysilicon, amorphous silicon, or an oxide semiconductor).

[0115] The second active layer 450 may include a third conductive region 450a, a fourth conductive region 450b, and a channel region 450c. The channel region 450c may be disposed between the third conductive region 450a and the fourth conductive region 450b. The third conductive region 450a and the fourth conductive region 450b may be respectively connected to the first source / drain electrode 430 and the second source / drain electrode 440 of the first switching transistor ST1 to be described in more detail below (e.g., may be respectively in contact with the first source / drain electrode 430 and the second source / drain electrode 440 of the first switching transistor ST1 to be described in more detail below).

[0116] A second gate insulating layer 160 may be disposed on the second semiconductor layer. The second gate insulating layer 160 may be disposed on the second buffer layer 122 and at least the second active layer 450. More specifically, the second gate insulating layer 160 may be disposed on a portion of the second buffer layer 122 on which the second active layer 450 is not disposed, and may be disposed on a region where the second gate insulating layer 160 overlaps with the channel region 450c of the second active layer 450. In Figure 5In [the figure], the second gate insulating layer 160 is shown as being disposed to cover the entire second buffer layer 122 including the upper surface and side surfaces of the second active layer 450, but the present disclosure is not limited thereto. For example, the second gate insulating layer 160 may be disposed only on the upper surface of the second active layer 450, and thus, may be disposed only between the second gate electrode 410 and the second active layer 450, which will be described in detail below.

[0117] The second gate insulating layer 160 may include an inorganic material such as, for example, SiO x , SiN x or a stacked structure thereof (for example, may be made of an inorganic material such as, for example, SiO x , SiN x or a stacked structure thereof). Similar to the first gate insulating layer 130, various modifications (for example, various selections) may be made to the material and / or thickness, etc. of the second gate insulating layer 160 to ensure or improve the device characteristics of the first switching transistor ST1. In the display device 1 according to the exemplary embodiment, the first gate insulating layer 130 and the second gate insulating layer 160 may have different physical properties from each other to ensure or improve the device characteristics desired for different transistors, such as the driving transistor DT and the first switching transistor ST1.

[0118] In the case of the display device 1 having a high resolution, the width of the channel region of the active layer of each transistor in each pixel PX can be shortened, so that a larger number of pixels PX can be provided per unit area. As described above, in the display device 1, since the driving transistor DT and the first switching transistor ST1 are disposed at different layers from each other (for example, disposed in different layers from each other or disposed on different layers from each other), the first active layer 350 and the second active layer 450 can be disposed at different layers from each other (for example, can be disposed in different layers from each other or can be disposed on different layers from each other), and thus, the driving transistor DT and the first switching transistor ST1 can be formed to have different structures from each other. For example, the channel region of the driving transistor DT may have a relatively larger width than the channel region of the first switching transistor ST1 to ensure a wide range of driving voltages.

[0119] According to an exemplary embodiment, the width of the channel region 350c of the first active layer 350 of the driving transistor DT measured in one direction (e.g., the X-axis direction) may be greater than the width of the channel region 450c of the second active layer 450 of the first switching transistor ST1 measured in the one direction. In the display device 1, since the driving transistor DT and the first switching transistor ST1 are disposed at different layers from each other (e.g., disposed in different layers from each other or disposed on different layers from each other), the driving transistor DT may have a wide channel region to ensure excellent device characteristics, and the first switching transistor ST1 may have a relatively narrow channel region, thereby implementing the display device 1 having a high resolution. For example, the channel region 350c of the first active layer 350 may have a width of about 15 μm or more, and the channel region 450c of the second active layer 450 may have a width of about 4.5 μm or more. However, the present disclosure is not limited thereto.

[0120] According to an exemplary embodiment, the desired device characteristics of the driving transistor DT and the first switching transistor ST1 may be controlled according to the characteristics of the gate insulating layers between the active layers and the gate electrodes provided in each of the driving transistor DT and the first switching transistor ST1. For example, since the first gate insulating layer 130 of the driving transistor DT and the second gate insulating layer 160 of the first switching transistor ST1 are disposed at different layers from each other (e.g., disposed in different layers from each other or disposed on different layers from each other), the first gate insulating layer 130 and the second gate insulating layer 160 may be formed by different processes. By forming the first gate insulating layer 130 and the second gate insulating layer 160 differently from each other, the desired device characteristics of the driving transistor DT and the first switching transistor ST1 may be improved.

[0121] According to an exemplary embodiment, in the display device 1, the first gate insulating layer 130 and the second gate insulating layer 160 may include different insulating materials from each other. For example, the first gate insulating layer 130 may have a low dielectric constant to ensure or improve a wide range of driving voltages in the driving transistor DT, and the second gate insulating layer 160 may have a high dielectric constant to suppress or reduce the deterioration of the device characteristics of the first switching transistor ST1 that may be caused by the first switching transistor ST1 having a short channel region.

[0122] In one or more exemplary embodiments, the first gate insulating layer 130 may include SiO x , and the second gate insulating layer 160 may include: a first insulating layer 161 including SiO x ; and a second insulating layer 163 disposed on the first insulating layer 161 and including SiN x or SiON. For example, the first gate insulating layer 130 may be formed to include SiOx a single layer, and the second gate insulating layer 160 may be formed to include SiO x a first insulating layer 161 and SiN x or a multi-layer of a second insulating layer 163 of SiON.

[0123] SiN x and / or SiON may have a dielectric constant higher than that of SiO x In this case, the second gate insulating layer 160 provided on the second active layer 450 of the first switching transistor ST1 may include SiN x or a second insulating layer 163 of SiON, and thus, may have a dielectric constant higher than that of the first gate insulating layer 130. Accordingly, even when the first switching transistor ST1 has a short channel region, deterioration of device characteristics of the first switching transistor ST1 can be suppressed or reduced.

[0124] Figure 6 is a graph showing changes in the drain-induced barrier lowering (DIBL) value according to the width of the channel region of the transistor and the type of the gate insulating layer.

[0125] Figure 6 shows according to the PMOS transistor including a gate insulating layer formed as a single layer of SiO x and the PMOS transistor including a gate insulating layer formed as a multi-layer of SiO x / SiN x changes in the DIBL value according to the width of the channel region. Referring to Figure 6 , in a transistor, as the width of the channel region is shortened, the DIBL value increases. The increase in the DIBL value may adversely affect the desired device characteristics of the first switching transistor ST1.

[0126] As Figure 6 shown, in the case where the gate insulating layer is formed as a multi-layer (e.g., a multi-layer of SiO x / SiN x ), the DIBL value is lower than that in the case where the gate insulating layer is formed as a single layer of SiO x . In other words, in the display device 1 having high resolution, since the second gate insulating layer 160 includes SiN having a high dielectric constant xThe second insulating layer 163 is formed, so that even when the first switching transistor ST1 has a short channel region, an increase in the DIBL value can be suppressed or reduced. Therefore, in the display device 1, since the driving transistor DT has a wide channel region, the driving transistor DT can have a wide range of driving voltages, and by including the second gate insulating layer 160 having a high dielectric constant, deterioration of the device characteristics of the first switching transistor ST1 can be suppressed or reduced.

[0127] In Figure 5 the second gate insulating layer 160 is shown as being formed as a bilayer of SiO x / SiN x However, the present disclosure is not limited thereto. In some exemplary embodiments, the first gate insulating layer 130 may also be formed as a multilayer, the second insulating layer 163 of the second gate insulating layer 160 may include other materials, and the first gate insulating layer 130 and the second gate insulating layer 160 may be formed to have different thicknesses from each other. This will be described in more detail below with reference to one or more other exemplary embodiments.

[0128] However, even when the first gate insulating layer 130 and the second gate insulating layer 160 are formed as a single layer or a multilayer by including different insulating materials from each other, an insulating layer including SiO x (for example, made of SiO x ) may be provided on the first active layer 350 and / or the second active layer 450. In other words, in some exemplary embodiments, the first insulating layer 161 of the second gate insulating layer 160 may be in contact with the second active layer 450 (for example, may be in direct contact with the second active layer 450). In order to ensure or improve the stable device characteristics of the driving transistor DT and / or the first switching transistor ST1, a gate insulating layer or an insulating layer of SiO x may be provided on the active layers 350 and 450. In addition, in some exemplary embodiments, the first insulating layer 161 of SiO x may have a greater thickness than the thickness of the second insulating layer 163 of SiN x . However, the present disclosure is not limited thereto.

[0129] Referring back to Figure 5 , a third conductive layer is provided on the second gate insulating layer 160. The third conductive layer may include a third conductive pattern 610, a fourth conductive pattern 630, a fifth conductive pattern 650, a second gate electrode 410 of the first switching transistor ST1, and a first source / drain electrode 430 of the first switching transistor ST1.

[0130] The second gate electrode 410 of the first switching transistor ST1 may overlap at least a part of the second active layer 450, and the second gate insulating layer 160 is interposed between the second gate electrode 410 of the first switching transistor ST1 and at least a part of the second active layer 450. For example, as Figure 5 shown, the width of the second gate electrode 410 measured in one direction (e.g., the X-axis direction) may be smaller than the width of the second active layer 450 measured in the one direction. The second gate electrode 410 may be disposed to overlap at least the channel region 450c of the second active layer 450, and the width of the second gate electrode 410 measured in the one direction may be equal to or substantially equal to the width of the channel region 450c of the second active layer 450 measured in the one direction.

[0131] The first source / drain electrode 430 of the first switching transistor ST1 may be connected to the second active layer 450 through a contact hole (e.g., may be in contact with the second active layer 450 through a contact hole), and the contact hole partially exposes the upper surface of the third conductive region 450a of the second active layer 450. In addition, the first source / drain electrode 430 of the first switching transistor ST1 may be connected to the first conductive pattern 370 through a second contact hole CT2 (e.g., may be in contact with the first conductive pattern 370 through a second contact hole CT2), and the second contact hole CT2 partially exposes the upper surface of the first conductive pattern 370. The first source / drain electrode 430 of the first switching transistor ST1 may be connected to the first gate electrode 310 of the driving transistor DT.

[0132] Each of the third conductive pattern 610, the fourth conductive pattern 630, and the fifth conductive pattern 650 may be connected to the second conductive layer exposed through the second contact hole CT2 (e.g., may be in contact with the second conductive layer exposed through the second contact hole CT2). For example, the third conductive pattern 610 may be connected to the first source / drain electrode 330 of the driving transistor DT exposed through the second contact hole CT2 (e.g., may be in contact with the first source / drain electrode 330 of the driving transistor DT exposed through the second contact hole CT2), and the fifth conductive pattern 650 may be connected to the second source / drain electrode 340 of the driving transistor DT exposed through the second contact hole CT2 (e.g., may be in contact with the second source / drain electrode 340 of the driving transistor DT exposed through the second contact hole CT2). In addition, the fourth conductive pattern 630 may be connected to the second conductive pattern 710 exposed through the second contact hole CT2 (e.g., may be in contact with the second conductive pattern 710 exposed through the second contact hole CT2). The third conductive pattern 610 may be connected to the first voltage line 810 (e.g., may be in contact with the first voltage line 810), and the first source / drain electrode 330 of the driving transistor DT may be electrically connected to the first voltage line 810 (e.g., VDDL). The fourth conductive pattern 630 may be connected to the initialization voltage line 830 (e.g., may be in contact with the initialization voltage line 830), and the second conductive pattern 710 may be electrically connected to the initialization voltage line 830. The fifth conductive pattern 650 may be connected to the sixth conductive pattern 850 (e.g., may be in contact with the sixth conductive pattern 850), and the second source / drain electrode 340 of the driving transistor DT may be electrically connected to the first electrode AE of the light-emitting element EL through the sixth conductive pattern 850.

[0133] The third conductive layer may be formed as a single layer or a multi-layer including at least one selected from Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof (e.g., made of at least one selected from Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof). However, the present disclosure is not limited thereto.

[0134] The second interlayer insulating layer 170 is disposed on the third conductive layer. More specifically, the second interlayer insulating layer 170 may be formed to cover the entire surface of the second gate insulating layer 160 and the third conductive layer. Third contact holes CT3 extending through (e.g., passing through) the second interlayer insulating layer 170 to partially expose the third conductive layer may be formed in the second interlayer insulating layer 170. For example, the third contact holes CT3 may partially expose the upper surfaces of each of the third conductive pattern 610, the fourth conductive pattern 630, and the fifth conductive pattern 650. Additionally, some of the third contact holes CT3 may be formed to extend through (e.g., pass through) the second gate insulating layer 160 to partially expose the upper surface of the second active layer 450 of the first switching transistor ST1. The fifth conductive layer, which will be described in more detail below, may be connected to the third conductive layer or the second active layer 450 through the third contact holes CT3 (e.g., may be in contact with the third conductive layer or the second active layer 450 through the third contact holes CT3).

[0135] The second interlayer insulating layer 170 may include an inorganic material such as, for example, SiO x , SiN x or a stacked structure thereof (e.g., may be made of an inorganic material such as, for example, SiO x , SiN x or a stacked structure thereof).

[0136] The fourth conductive layer is disposed on the second interlayer insulating layer 170. The fourth conductive layer may include data signal lines 720 through which data signals DL are transmitted. The data signal lines 720 may overlap with the sixth conductive pattern 850, and the second protective layer 180 is interposed between the data signal lines 720 and the sixth conductive pattern 850. The second capacitor Cpr may be formed in a region where the sixth conductive pattern 850 and the data signal lines 720 overlap each other (e.g., may be formed in or on a region where the sixth conductive pattern 850 and the data signal lines 720 overlap each other), and the sixth conductive pattern 850 may be a capacitor electrode of the second capacitor Cpr. The fourth conductive layer may be formed as a single layer or multiple layers including at least one selected from Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof (e.g., may be made of at least one selected from Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof). However, the present disclosure is not limited thereto.

[0137] The second protective layer 180 is disposed on the fourth conductive layer and the second interlayer insulating layer 170. The second protective layer 180 may be disposed on the entire surfaces of the second interlayer insulating layer 170 and the data signal lines 720. The structure, material, and / or function of the second protective layer 180 may be the same as or substantially the same as those of the first protective layer 140, and thus, redundant descriptions thereof may not be repeated.

[0138] The fifth conductive layer is disposed on the second protective layer 180. The fifth conductive layer may include a first voltage line 810, an initialization voltage line 830, and a sixth conductive pattern 850.

[0139] The first voltage line 810 may be connected to the third conductive pattern 610 exposed through the third contact hole CT3 (e.g., may be in contact with the third conductive pattern 610 exposed through the third contact hole CT3). The first source / drain electrode 330 of the driving transistor DT may be electrically connected to the first voltage line 810 through the third conductive pattern 610, and the driving transistor DT may be connected to the first voltage line 810 (e.g., VDDL).

[0140] The initialization voltage line 830 may be connected to the fourth conductive pattern 630 exposed through the third contact hole CT3 (e.g., may be in contact with the fourth conductive pattern 630 exposed through the third contact hole CT3). The second conductive pattern 710 may be electrically connected to the initialization voltage line 830 through the fourth conductive pattern 630.

[0141] The sixth conductive pattern 850 may be disposed such that at least a portion of the sixth conductive pattern 850 overlaps with the data signal lines 720. As described above, the second capacitor Cpr may be formed at an area where the sixth conductive pattern 850 and the data signal lines 720 overlap each other (e.g., may be formed in an area where the sixth conductive pattern 850 and the data signal lines 720 overlap each other or may be formed on an area where the sixth conductive pattern 850 and the data signal lines 720 overlap each other), and a portion of the sixth conductive pattern 850 that overlaps with the data signal lines 720 (e.g., an area of the sixth conductive pattern 850 that overlaps with the data signal lines 720) may form a capacitor electrode of the second capacitor Cpr.

[0142] In addition, the sixth conductive pattern 850 may be connected to the fifth conductive pattern 650 through the third contact hole CT3 (e.g., may be in contact with the fifth conductive pattern 650 through the third contact hole CT3), and the third contact hole CT3 partially exposes the upper surface of the fifth conductive pattern 650. As will be described in more detail below, the fifth conductive pattern 650 may be connected to the first electrode AE of the light-emitting element EL (e.g., may be in contact with the first electrode AE of the light-emitting element EL), and the second source / drain electrode 340 of the driving transistor DT may be connected to the first electrode AE of the light-emitting element EL through the fifth conductive pattern 650 and the sixth conductive pattern 850.

[0143] At least a part of the sixth conductive pattern 850 may be connected to the second active layer 450 through the third contact hole CT3 (e.g., may be in contact with the second active layer 450 through the third contact hole CT3), and the third contact hole CT3 extends through (e.g., passes through) the second interlayer insulating layer 170 and the second gate insulating layer 160 to partially expose the upper surface of the second active layer 450. For example, at least a part of the sixth conductive pattern 850 may be connected to the fourth conductive region 450b of the second active layer 450 (e.g., may be in contact with the fourth conductive region 450b of the second active layer 450), and this part of the sixth conductive pattern 850 may form the second source / drain electrode 440 of the first switching transistor ST1.

[0144] The fifth conductive layer may be formed as a single layer or multiple layers, and the single layer or multiple layers include at least one selected from Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof (e.g., made of at least one selected from Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof). However, the present disclosure is not limited thereto.

[0145] The first planarization film 190 is disposed on the fifth conductive layer and the second protective layer 180. The first planarization film 190 may planarize the stepped portions caused by thin film transistors such as the driving transistor DT and the first switching transistor ST1 as examples. The first planarization film 190 may be formed of an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin, etc. (e.g., made of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin, etc.).

[0146] Although in Figure 5 the first planarization film 190 is shown as being directly disposed on the fifth conductive layer, the present disclosure is not limited thereto. For example, in some embodiments, another protective layer may also be disposed between the first planarization film 190 and the second protective layer 180 and between the first planarization film 190 and the fifth conductive layer.

[0147] On the first planarization film 190, a pixel defining film 195 and a light-emitting element EL including a first electrode AE, an organic light-emitting layer OL, and a second electrode CE may be formed.

[0148] The first electrode AE may be formed on the first planarization film 190. The first electrode AE may be a pixel electrode formed for each pixel (e.g., for every pixel) PX. The first electrode AE may be connected to a sixth conductive pattern 850 exposed through an electrode contact hole CNTD (e.g., may be in contact with the sixth conductive pattern 850 exposed through the electrode contact hole CNTD), and the electrode contact hole CNTD extends through (e.g., passes through) the first planarization film 190, and thus, the first electrode AE may be connected to the second source / drain electrode 440 of the first switching transistor ST1 and the second source / drain electrode 340 of the driving transistor DT.

[0149] To define the pixel PX, a pixel defining film 195 may be formed on the first planarization film 190 to cover the edge of the first electrode AE. In other words, the pixel defining film 195 may be used as (e.g., may be) a pixel defining film that defines the pixel PX. Here, each pixel PX represents an area where (e.g., in which or on which) the first electrode AE, the organic light-emitting layer OL, and the second electrode CE are sequentially stacked, such that holes from the first electrode AE and electrons from the second electrode CE are combined with each other in the organic light-emitting layer OL to emit light.

[0150] The organic light-emitting layer OL may be disposed on the first electrode AE and the pixel defining film 195. The organic light-emitting layer OL may include a hole transport layer, a light-emitting layer, and an electron transport layer. In addition, the organic light-emitting layer OL may be formed in two or more stacked tandem structures, and in this case, a charge generation layer may be formed between the stacks. In Figure 5 FIG., the organic light-emitting layer OL is shown as being formed at a portion corresponding to the first electrode AE (e.g., formed in a portion corresponding to the first electrode AE or formed on a portion corresponding to the first electrode AE), but the present disclosure is not limited thereto. In some exemplary embodiments, the organic light-emitting layer OL may be formed above the entire surface of the display area DA.

[0151] The second electrode CE may be formed on the organic light-emitting layer OL. The second electrode CE may be a common electrode formed in the pixels PX in common.

[0152] The light-emitting element EL can be formed as a top-emitting light-emitting element, which emits light in the upward direction. In this case, the first electrode AE can include a conductive (e.g., metal) material having a high reflectivity (e.g., can be made of a conductive (e.g., metal) material having a high reflectivity), and can have a stacked structure such as aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), a silver-palladium-copper (APC) alloy and / or a stacked structure of an APC alloy and ITO (ITO / APC / ITO). Additionally, the second electrode CE can include a transparent conductive (e.g., metal) material (TCO) such as ITO or indium zinc oxide (IZO) that can transmit light (e.g., can be made of a transparent conductive (e.g., metal) material (TCO) such as ITO or indium zinc oxide (IZO) that can transmit light), or can include a semi-transmissive conductive (e.g., metal) material such as magnesium (Mg), Ag, or an alloy of Mg and Ag (e.g., can be made of a semi-transmissive conductive (e.g., metal) material such as magnesium (Mg), Ag, or an alloy of Mg and Ag). When the second electrode CE includes a semi-transmissive conductive (e.g., metal) material (e.g., made of a semi-transmissive conductive (e.g., metal) material), the light extraction efficiency can be improved due to the microcavity.

[0153] An encapsulation layer TFE configured to prevent or substantially prevent oxygen or moisture from permeating therethrough can be formed on the second electrode CE. The encapsulation layer TFE can include at least one inorganic film. The inorganic film can include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, and / or titanium oxide (e.g., can be made of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, and / or titanium oxide). Additionally, the encapsulation layer TFE can include at least one organic film to prevent or substantially prevent particles from permeating through the encapsulation layer TFE and / or prevent or substantially prevent particles from being introduced into the organic light-emitting layer OL and the second electrode CE. The organic film can include epoxy resin, acrylate, or polyurethane acrylate (e.g., can be formed of epoxy resin, acrylate, or polyurethane acrylate).

[0154] In the display device 1 according to an exemplary embodiment, the driving transistor DT and the first switching transistor ST1 may be disposed at different layers from each other (e.g., may be disposed in different layers from each other or may be disposed on different layers from each other), and the active layers of the driving transistor DT and the first switching transistor ST1 may have different widths from each other. The driving transistor DT may have a long channel region to ensure a wide range of driving voltages. In addition, the first gate insulating layer 130 and the second gate insulating layer 160 may be formed in different processes from each other, and thus, the characteristics of the first gate insulating layer 130 and the second gate insulating layer 160 may be controlled. Therefore, even when the first switching transistor ST1 has a relatively short channel region, since the second gate insulating layer 160 has a high dielectric constant, deterioration of device characteristics may be suppressed or reduced. The display device 1 according to an exemplary embodiment may have a high-resolution display quality by including a large number of pixels PX.

[0155] Hereinafter, various exemplary embodiments of the display device 1 will be described with reference to other drawings.

[0156] Figures 7 to 9 is a cross-sectional view showing a part of a display device according to various exemplary embodiments.

[0157] Referring to Figure 7 , in the display device 1 according to an exemplary embodiment, the second gate insulating layer 160_1 may include a first insulating layer 161_1 and a second insulating layer 163_1, and the second insulating layer 163_1 of the second gate insulating layer 160_1 may include SiN having a low hydrogen (H) content x . This exemplary embodiment may be different from the exemplary embodiment described with reference to Figure 5 in that the materials of the second gate insulating layer 160_1 and the second insulating layer 163_1 may be different from the materials of the corresponding insulating layers of Figure 5 . Hereinafter, the differences from the above one or more embodiments may be mainly described in more detail, and redundant descriptions thereof may not be repeated.

[0158] During the process of forming the second insulating layer 163_1 including SiN x (e.g., made of SiN x ), the hydrogen (H) content in SiN x may be controlled by adjusting the flow rate of ammonia (NH3), and ammonia (NH3) may be a precursor including nitrogen (N) (e.g., made of nitrogen (N)). When the second insulating layer 163_1 of the second gate insulating layer 160_1 includes SiN having a low hydrogen content xWhen it is the case, it is possible to further suppress or reduce an increase in the DIBL value that may occur as the channel region is shortened. In other words, when the second insulating layer 163_1 of the second gate insulating layer 160_1 includes SiN having a low hydrogen content x it is possible to further improve the device characteristics of the first switching transistor ST1.

[0159] As described above, the first gate insulating layer 130 may also be formed to include multiple layers of different insulating materials.

[0160] Referring to Figure 8 in the display device 1 according to another exemplary embodiment, the first gate insulating layer 130_2 may include: a third insulating layer 131_2 including SiO x (e.g., made of SiO x ); and a fourth insulating layer 133_2 disposed on the third insulating layer 131_2 and including SiN x (e.g., made of SiN x ). The difference between this exemplary embodiment and the exemplary embodiment described with reference to Figure 5 is that the first gate insulating layer 130_2 is formed as multiple layers. Hereinafter, the differences from the above-described one or more embodiments may be mainly described in more detail, and redundant descriptions thereof may not be repeated.

[0161] In Figure 8 the display device 1, since the second gate insulating layer 160_2 may include the first insulating layer 161_2 and the second insulating layer 163_2, it is possible to ensure or improve the device characteristics of the first switching transistor ST1. In addition, since the first gate insulating layer 130_2 may include the third insulating layer 131_2 and the fourth insulating layer 133_2, it is possible to improve the device characteristics of the driving transistor DT.

[0162] Different from the first switching transistor ST1, the driving transistor DT may have a wide channel region such that a sufficient range of driving voltage can be ensured in the driving transistor DT. Here, when the dielectric constant of the first gate insulating layer 130_2 increases because the first gate insulating layer 130_2 includes the fourth insulating layer 133_2 containing silicon nitride (e.g., made of silicon nitride), the hysteresis in the driving transistor DT decreases. Since the dielectric constant of the first gate insulating layer 130_2 increases, the hysteresis of the driving transistor DT decreases even when the driving transistor DT is repeatedly turned on and off.

[0163] However, as described above, even when the first gate insulating layer 130_2 is formed as multiple layers, including SiO x (e.g., made of SiO xThe third insulating layer 131_2 (formed, for example) may also be disposed on the first active layer 350. In other words, according to another exemplary embodiment, the third insulating layer 131_2 of the first gate insulating layer 130_2 may be in contact with the first active layer 350 (e.g., may be in direct contact with the first active layer 350).

[0164] In addition, when the first gate insulating layer 130_2 and the second gate insulating layer 160_2 each include a fourth insulating layer 133_2 and a second insulating layer 163_2 formed of SiN x respectively, the fourth insulating layer 133_2 and the second insulating layer 163_2 may have different physical properties from each other according to the device characteristics desired for the driving transistor DT and the first switching transistor ST1. In an exemplary embodiment, the fourth insulating layer 133_2 of the first gate insulating layer 130_2 may have a lower hydrogen content than the second insulating layer 163_2 of the second gate insulating layer 160_2. In other words, the fourth insulating layer 133_2 of the first gate insulating layer 130_2 may include SiN with a low hydrogen content x (e.g., may be formed of SiN with a low hydrogen content) x . However, the present disclosure is not limited thereto.

[0165] As described above, the second insulating layer 163 of the second gate insulating layer 160 may include SiON. In this case, in the first switching transistor ST1, the threshold voltage Vth may be shifted, and the device characteristics of the first switching transistor ST1 as a switching transistor may also be improved.

[0166] Referring to Figure 9 , in a display device 1 according to another exemplary embodiment, the second gate insulating layer 160_4 may include: a first insulating layer 161_4 including SiO x (e.g., formed of SiO x ); and a second insulating layer 163_4 including SiON (e.g., formed of SiON). The difference between this exemplary embodiment and the exemplary embodiment described with reference to Figure 5 may be that the second insulating layer 163_4 may include SiON (e.g., may be formed of SiON).

[0167] When, as in the display device 1 of Figure 9 , the second gate insulating layer 160_4 includes a first insulating layer 161_4 containing SiO x (e.g., formed of SiO x ) and a second insulating layer 163_4 containing SiON (e.g., formed of SiON), the threshold voltage Vth of the PMOS transistor may be further reduced.

[0168] Figure 10 is a graph showing changes in the threshold voltage Vth value according to the width of the channel region of a transistor and the type of gate insulating layer.

[0169] Figure 10 shows according to including formed as SiO x of a single-layer gate insulating layer of a PMOS transistor and including formed as SiO x / SiON of a multi-layer gate insulating layer of a PMOS transistor changes in the threshold voltage Vth with respect to the width of the channel region. In Figure 10 the region represented by "ST Vth" represents the range of the threshold voltage Vth desired for the first switching transistor ST1 of the display device 1. Referring to Figure 10 , in the case of a PMOS transistor, the absolute value of the threshold voltage Vth decreases as the width of the channel region decreases. In some cases, the first switching transistor ST1 may have a threshold voltage Vth value outside the range of the threshold voltage Vth desired for the first switching transistor ST1.

[0170] On the other hand, in the case where the gate insulating layer is formed as a multi-layer of SiO x / SiON, the absolute value of the threshold voltage Vth of the PMOS transistor may become greater than the absolute value of the threshold voltage Vth of the PMOS transistor in the case where the gate insulating layer is formed as a single-layer of SiO x . In other words, in the display device 1 having a high resolution, since the second gate insulating layer 160_4 includes a second insulating layer 163_4 containing SiON (e.g., made of SiON), even when the first switching transistor ST1 has a short-width channel region, the threshold voltage Vth can be suppressed from being outside the range desired for the switching transistor. Therefore, since the display device 1 includes the second gate insulating layer 160_4 containing SiON, a reduction in the device characteristics of the first switching transistor ST1 can be suppressed or substantially suppressed.

[0171] Figure 11 is a cross-sectional view showing a part of a display device according to another exemplary embodiment.

[0172] Referring to Figure 11 , in the display device 1 according to another exemplary embodiment, the second gate insulating layer 160_5 may include: a first insulating layer 161_5 including SiON (e.g., made of SiON); and a second insulating layer 163_5 including SiO x (e.g., made of SiO x ). The first gate insulating layer 130_5 may include: a third insulating layer 131_5 including SiO x(e.g., made of SiO x ); and a fourth insulating layer 133_5, which includes SiN x (e.g., made of SiN x ). The difference between this exemplary embodiment and the exemplary embodiment described with reference to Figure 9 may be that the first gate insulating layer 130_5 may be formed as a multi-layer. The detailed description of this exemplary embodiment may be the same as or substantially the same as the detailed description of the exemplary embodiment described above with reference to Figure 8 and Figure 9 , and thus, the redundant description thereof may not be repeated.

[0173] In addition, in some exemplary embodiments, the device characteristics of the driving transistor DT and the first switching transistor ST1 may be controlled by adjusting the thickness of the first gate insulating layer 130 and the second gate insulating layer 160 or the thickness of the first active layer 350 and the second active layer 450.

[0174] Figure 12 and Figure 13 are cross-sectional views showing a part of a display device according to various exemplary embodiments.

[0175] Referring to Figure 12 , in a display device 1 according to another exemplary embodiment, the thickness of the first gate insulating layer 130_6 (e.g., in the Z-axis direction) may be greater than the thickness of the second gate insulating layer 160_6 (e.g., in the Z-axis direction). The difference between this exemplary embodiment and the exemplary embodiment described with reference to Figure 5 may be that the first gate insulating layer 130_6 and the second gate insulating layer 160_6 may each be formed as a single layer of SiO x , but may have different thicknesses from each other. Hereinafter, the differences from the above one or more embodiments may be mainly described in more detail, and the redundant description thereof may not be repeated.

[0176] As described above, since the driving transistor DT and the first switching transistor ST1 are disposed at different layers from each other (e.g., disposed in different layers or on different layers from each other), the first gate insulating layer 130_6 and the second gate insulating layer 160_6 may each be formed by different processes having different physical properties. In the case of the driving transistor DT, as the thickness of the first gate insulating layer 130_6 increases, the controllability of the first gate electrode 310 with respect to the channel region 350c may decrease. However, since the driving transistor DT has a channel region 350c wider than the channel region of the first switching transistor ST1, the controllability of the first gate electrode 310 of the driving transistor DT may be less affected, and a wide range of driving voltages may be ensured.

[0177] On the other hand, in the case of the first switching transistor ST1, as the thickness of the second gate insulating layer 160_6 decreases, the controllability of the second gate electrode 410 with respect to the channel region 450c can increase. Since the second gate insulating layer 160_6 has a thin thickness, excellent device characteristics can be ensured in the first switching transistor ST1 even when the first switching transistor ST1 includes a channel region 450c having a short width.

[0178] In Figure 12 each of the first gate insulating layer 130_6 and the second gate insulating layer 160_6 is shown as being formed of a single layer of SiO x However, the present disclosure is not limited thereto. For example, as described above, the first gate insulating layer 130_6 and the second gate insulating layer 160_6 can each be formed as a multi-layer by further including a fourth insulating layer 133 and a second insulating layer 163, respectively, and each of the fourth insulating layer 133 and the second insulating layer 163 is made of SiN x or SiON. Therefore, its redundant description may not be repeated.

[0179] Referring to Figure 13 , in the display device 1 according to another exemplary embodiment, the thickness of the first active layer 350 of the driving transistor DT can be greater than the thickness of the second active layer 450 of the first switching transistor ST1. The difference between this exemplary embodiment and the exemplary embodiment described with reference to Figure 5 can be that the first gate insulating layer 130_6 and the second gate insulating layer 160_6 can each be formed as a single layer of SiO having the same or substantially the same thickness as each other, x but the first active layer 350 and the second active layer 450 can have different thicknesses from each other. Hereinafter, the regions related to one or more of the above embodiments may be mainly described in more detail, and its redundant description may not be repeated.

[0180] As described above, since the driving transistor DT and the first switching transistor ST1 are provided at different layers from each other (for example, provided in different layers from each other or provided on different layers from each other), the first active layer 350 and the second active layer 450 can each be formed by different processes and can each have different physical properties. In the case of the driving transistor DT, as the thickness of the first active layer 350 increases, a wide range of driving voltages can be ensured, and in the case of the first switching transistor ST1, as the thickness of the second active layer 450 decreases, excellent device characteristics can be ensured even when the width of the channel region 450c is shortened.

[0181] In Figure 13In [the figure], each of the first gate insulating layer 130_6 and the second gate insulating layer 160_6 is shown as being formed as a single layer of SiO x However, the present disclosure is not limited thereto. As described above, the first gate insulating layer 130_6 and the second gate insulating layer 160_6 may further include a fourth insulating layer 133 and a second insulating layer 163, respectively, and each of the fourth insulating layer 133 and the second insulating layer 163 includes SiN x or SiON (for example, made of SiN x or SiON). Therefore, redundant descriptions thereof may not be repeated.

[0182] The display device 1 may include a larger number of scan lines, and each pixel PX may include a larger number of transistors.

[0183] Figure 14 is a plan view showing an example of a display device according to another exemplary embodiment. Figure 15 shows Figure 14 an equivalent circuit diagram of a pixel of

[0184] Referring to Figure 14 and Figure 15 , control scan lines CL1 to CLn (for example, CL1, CL2,..., CLn-1, and CLn) may be further provided in the display area DA of the display panel 10 (for example, may be further provided in or on the display area DA of the display panel 10). The control scan lines CL1 to CLn may be formed to extend in a first direction (for example, the X-axis direction) and may be parallel to each other. Each pixel PX may be connected to at least one of the control scan lines CL1 to CLn. Therefore, each pixel PX may further include one of the control scan lines CL1 to CLn and a second switching transistor ST2.

[0185] Figure 15 The pixel PX of Figure 4 may be different from the pixel of the exemplary embodiment described with reference to Figure 15 in that the pixel PX of

[0186] Figure 15 also includes a k-th control scan line CLk and a second switching transistor ST2. Hereinafter, the arrangement of the k-th control scan line CLk and the second switching transistor ST2 will be described in more detail, and redundant descriptions of other components except the k-th control scan line CLk and the second switching transistor ST2 may be simplified or not repeated.

[0187] The driving transistor DT may be disposed between the first voltage line VDDL and the third node N3, the first switching transistor ST1 may be disposed between the first node N1 and the second node N2, and the second switching transistor ST2 may be disposed between the second node N2 and the third node N3.

[0188] The second switching transistor ST2 is turned on by the k-th control scan signal of the k-th control scan line CLk and connects the second node N2 to the third node N3. The gate electrode of the second switching transistor ST2 may be connected to the k-th control scan line CLk, the first electrode of the second switching transistor ST2 may be connected to the third node N3, and the second electrode of the second switching transistor ST2 may be connected to the second node N2.

[0189] When both the first switching transistor ST1 and the second switching transistor ST2 are turned on, the gate electrode and the second electrode of the driving transistor DT are connected to each other, and thus, the driving transistor DT operates as a diode. In other words, when both the first switching transistor ST1 and the second switching transistor ST2 are turned on, the driving transistor DT may be connected in a diode manner.

[0190] The first node N1 may be a contact point between the gate electrode of the driving transistor DT, the first capacitor electrode of the first capacitor Cst, and the second electrode of the first switching transistor ST1. The second node N2 may be a contact point between the first electrode of the first switching transistor ST1, the second electrode of the second switching transistor ST2, and the first capacitor electrode of the second capacitor Cpr. The third node N3 may be a contact point between the second electrode of the driving transistor DT, the first electrode of the second switching transistor ST2, and the first electrode of the light-emitting element EL.

[0191] In the exemplary embodiment described with reference to Figure 15 each pixel PX includes the second switching transistor ST2 disposed between the second node N2 and the third node N3. Accordingly, the second node N2 and the third node N3 may be separated from each other through the second switching transistor ST2, and thus, even when a leakage current flowing from the first voltage line VDDL to the third node N3 is generated through the driving transistor DT while applying the data voltage of the j-th data line DLj to the gate electrode (e.g., the first node N1) of the driving transistor DT, it does not affect the data voltage of the j-th data line DLj applied to the gate electrode of the driving transistor DT, thereby preventing or reducing the deterioration of the display quality.

[0192] In addition, since the second capacitor Cpr is disposed between the second node N2 and the j-th data line DLj, it is possible to prevent or reduce a decrease in the luminance of the light-emitting element due to the parasitic capacitor of the electrode overlapping with the first node N1. Accordingly, it is possible to prevent or reduce deterioration of the display quality.

[0193] Figure 16 is a cross-sectional view showing Figure 14 a part of the display device.

[0194] Referring to Figure 16 , the display device 1 may include a driving transistor DT, a first switching transistor ST1, and a second switching transistor ST2. The second switching transistor ST2 includes a third active layer 550, a third gate electrode 510, and source / drain electrodes 530 and 540. The second switching transistor ST2 may be disposed above the driving transistor DT and may be disposed on the same or substantially the same layer as the layer of the first switching transistor ST1. Accordingly, the second gate insulating layer 160 may also be disposed between the third active layer 550 and the third gate electrode 510. Referring to Figure 16 The exemplary embodiment described Figure 5 may be different from the exemplary embodiment described

[0195] in that Figure 16 it may further include a second switching transistor ST2. Hereinafter, the differences from the above-described one or more embodiments may be mainly described in more detail, and redundant descriptions thereof may not be repeated.

[0196] More specifically, the third active layer 550 may be disposed on the second buffer layer 122 and may include polysilicon, single-crystalline silicon, low-temperature polysilicon, amorphous silicon, or an oxide semiconductor (e.g., may be made of polysilicon, single-crystalline silicon, low-temperature polysilicon, amorphous silicon, or an oxide semiconductor). The third active layer 550 may include a fifth conductive region 550a, a sixth conductive region 550b, and a channel region 550c. The channel region 550c may be disposed between the fifth conductive region 550a and the sixth conductive region 550b. The fifth conductive region 550a and the sixth conductive region 550b may be respectively connected to a first source / drain electrode 530 and a second source / drain electrode 540 of a second switching transistor ST2 to be described in more detail below (e.g., may be in contact with the first source / drain electrode 530 and the second source / drain electrode 540 of the second switching transistor ST2 to be described in more detail below).

[0197] The second gate insulating layer 160 may also be disposed on the third active layer 550.

[0198] The third conductive layer may also include a third gate electrode 510 and a second source / drain electrode 540 of the second switching transistor ST2. The third gate electrode 510 may overlap at least a portion of the third active layer 550, and the second gate insulating layer 160 may be interposed between the third gate electrode 510 and at least a portion of the third active layer 550. For example, as Figure 16 shown, the width of the third gate electrode 510 measured in one direction (e.g., the X-axis direction) may be less than the width of the third active layer 550 measured in the one direction. The third gate electrode 510 may be disposed to overlap at least the channel region 550c of the third active layer 550, and the width of the third gate electrode 510 measured in the one direction may be equal to or substantially equal to the width of the channel region 550c of the third active layer 550 measured in the one direction.

[0199] The second source / drain electrode 540 of the second switching transistor ST2 may be connected to the third active layer 550 through a contact hole (e.g., may be in contact with the third active layer 550 through a contact hole), and the contact hole partially exposes the upper surface of the sixth conductive region 550b of the third active layer 550. In addition, the second source / drain electrode 540 of the second switching transistor ST2 may be connected to a part of the upper surface of the second source / drain electrode 340 of the driving transistor DT through a second contact hole CT2 (e.g., may be in contact with a part of the upper surface of the second source / drain electrode 340 of the driving transistor DT through the second contact hole CT2), and the second contact hole CT2 exposes this part of the upper surface of the second source / drain electrode 340 of the driving transistor DT. Additionally, the second source / drain electrode 540 of the second switching transistor ST2 may be connected to the sixth conductive pattern 850 (e.g., may be in contact with the sixth conductive pattern 850), and the driving transistor DT may be electrically connected to the first electrode AE of the light-emitting element EL through the second source / drain electrode 540 of the second switching transistor ST2 and the sixth conductive pattern 850.

[0200] At least a part of the sixth conductive pattern 850 may be connected to the third active layer 550 through a third contact hole CT3 (e.g., may be in contact with the third active layer 550 through the third contact hole CT3), and the third contact hole CT3 extends through (e.g., passes through) the second interlayer insulating layer 170 and the second gate insulating layer 160 to partially expose the upper surface of the third active layer 550. For example, at least a part of the sixth conductive pattern 850 may be connected to the fifth conductive region 550a of the third active layer 550 (e.g., may be in contact with the fifth conductive region 550a of the third active layer 550), and this part of the sixth conductive pattern 850 may form the first source / drain electrode 530 of the second switching transistor ST2.

[0201] In addition, the detailed description of other components may be the same as or substantially the same as the detailed description of other components referred to above Figure 5 and thus, the redundant description thereof may not be repeated.

[0202] The display device 1 according to another exemplary embodiment may include a greater number of transistors.

[0203] Figure 17 is an equivalent circuit diagram showing a pixel of a display device according to another exemplary embodiment.

[0204] Refer to Figure 17, each pixel PX may include a driving transistor DT, a light-emitting element EL, a first switching transistor ST1, a second switching transistor ST2, a third switching transistor ST3, a fourth switching transistor ST4, a fifth switching transistor ST5, a sixth switching transistor ST6, and a first capacitor Cst. Additionally, the pixel PX may be connected to the (k-1)-th scan line SLk-1 (where k is a positive integer greater than or equal to 2), the k-th scan line SLk, the (k + 1)-th scan line SLk+1, the j-th data line DLj (where j is a positive integer), a first voltage line VDDL to which a first voltage VDD is applied, an initialization voltage line VintL to which an initialization voltage Vint is applied, and a second voltage line VSSL to which a second voltage VSS is applied. Hereinafter, the differences from one or more of the above embodiments may be mainly described in more detail, and redundant descriptions thereof may not be repeated.

[0205] The first electrode of the light-emitting element EL may be connected to the first electrode of the fourth switching transistor ST4 and the second electrode of the sixth switching transistor ST6. The second electrode of the light-emitting element EL may be connected to the second voltage line VSSL. A parasitic capacitance Cel may be formed between the first electrode and the second electrode of the light-emitting element EL.

[0206] The first switching transistor ST1 is turned on by a scan signal of the k-th scan line SLk and connects the first electrode of the driving transistor DT to the j-th data line DLj. The gate electrode of the first switching transistor ST1 may be connected to the k-th scan line SLk, the first electrode of the first switching transistor ST1 may be connected to the first electrode of the driving transistor DT, and the second electrode of the first switching transistor ST1 may be connected to the data line DLj.

[0207] The second switching transistor ST2 may be formed as a dual transistor including a (2-1)th switching transistor ST2-1 and a (2-2)th switching transistor ST2-2. The (2-1)th switching transistor ST2-1 and the (2-2)th switching transistor ST2-2 are turned on by a scanning signal of the k-th scanning line SLk, and connect the gate electrode and the second electrode of the driving transistor DT to each other. In other words, when the (2-1)th switching transistor ST2-1 and the (2-2)th switching transistor ST2-2 are turned on, the gate electrode and the second electrode of the driving transistor DT are connected to each other, so that the driving transistor DT operates as a diode (for example, is connected in a diode manner). The gate electrode of the (2-1)th switching transistor ST2-1 may be connected to the k-th scanning line SLk, the first electrode of the (2-1)th switching transistor ST2-1 may be connected to the second electrode of the (2-2)th switching transistor ST2-2, and the second electrode of the (2-1)th switching transistor ST2-1 may be connected to the gate electrode of the driving transistor DT. The gate electrode of the (2-2)th switching transistor ST2-2 may be connected to the k-th scanning line SLk, the first electrode of the (2-2)th switching transistor ST2-2 may be connected to the second electrode of the driving transistor DT, and the second electrode of the (2-2)th switching transistor ST2-2 may be connected to the first electrode of the (2-1)th switching transistor ST2-1.

[0208] The third switching transistor ST3 may be formed as a dual transistor including a (3-1)th switching transistor ST3-1 and a (3-2)th switching transistor ST3-2. The (3-1)th switching transistor ST3-1 and the (3-2)th switching transistor ST3-2 are turned on by a scanning signal of the (k-1)-th scanning line SLk-1, and connect the gate electrode of the driving transistor DT to the initialization voltage line VintL. The gate electrode of the driving transistor DT may be discharged to have the initialization voltage of the initialization voltage line VintL. The gate electrode of the (3-1)th switching transistor ST3-1 may be connected to the (k-1)-th scanning line SLk-1, the first electrode of the (3-1)th switching transistor ST3-1 may be connected to the gate electrode of the driving transistor DT, and the second electrode of the (3-1)th switching transistor ST3-1 may be connected to the first electrode of the (3-2)th switching transistor ST3-2. The gate electrode of the (3-2)th switching transistor ST3-2 may be connected to the (k-1)-th scanning line SLk-1, the first electrode of the (3-2)th switching transistor ST3-2 may be connected to the second electrode of the (3-1)th switching transistor ST3-1, and the second electrode of the (3-2)th switching transistor ST3-2 may be connected to the initialization voltage line VintL.

[0209] The fourth switching transistor ST4 is turned on by the scanning signal of the (k + 1)-th scanning line SLk+1, and connects the first electrode of the light-emitting element EL to the initialization voltage line VintL. The first electrode of the light-emitting element EL can be discharged to have the initialization voltage. The gate electrode of the fourth switching transistor ST4 is connected to the (k + 1)-th scanning line SLk+1, the first electrode of the fourth switching transistor ST4 is connected to the first electrode of the light-emitting element EL, and the second electrode of the fourth switching transistor ST4 is connected to the initialization voltage line VintL.

[0210] The fifth switching transistor ST5 is turned on by the emission control signal of the k-th emission line Ek, and connects the first electrode of the driving transistor DT to the first voltage line VDDL. The gate electrode of the fifth switching transistor ST5 is connected to the k-th emission line Ek, the first electrode of the fifth switching transistor ST5 is connected to the first voltage line VDDL, and the second electrode of the fifth switching transistor ST5 is connected to the first electrode of the driving transistor DT.

[0211] The sixth switching transistor ST6 is provided between the second electrode of the driving transistor DT and the first electrode of the light-emitting element EL. The sixth switching transistor ST6 is turned on by the emission control signal of the k-th emission line Ek, and connects the second electrode of the driving transistor DT to the first electrode of the light-emitting element EL. The gate electrode of the sixth switching transistor ST6 is connected to the k-th emission line Ek, the first electrode of the sixth switching transistor ST6 is connected to the second electrode of the driving transistor DT, and the second electrode of the sixth switching transistor ST6 is connected to the first electrode of the light-emitting element EL. When both the fifth switching transistor ST5 and the sixth switching transistor ST6 are turned on, the drive current Id can be supplied to the light-emitting element EL.

[0212] The first capacitor Cst is formed between the gate electrode of the driving transistor DT and the first voltage line VDDL. One electrode of the first capacitor Cst can be connected to the gate electrode of the driving transistor DT, and the other electrode of the first capacitor Cst can be connected to the first voltage line VDDL. The first capacitor Cst can be used to hold or substantially hold the voltage of the gate electrode of the driving transistor DT within one frame period.

[0213] Although each pixel PX includes a driving transistor DT and a plurality of switching transistors ST1, ST2, ST3, ST4, ST5, and ST6, the driving transistor DT and the switching transistors ST1, ST2, ST3, ST4, ST5, and ST6 may be disposed on different layers. Different gate insulating layers, such as a first gate insulating layer 130 and a second gate insulating layer 160, may be disposed between the active layer and the gate electrode of each transistor in the driving transistor DT and the switching transistors ST1, ST2, ST3, ST4, ST5, and ST6, and the different gate insulating layers may exhibit different device characteristics. In other words, in the driving transistor DT, the active layer may be disposed on the first buffer layer 121, and the first gate insulating layer 130 may be disposed between the gate electrode and the active layer. In each of the switching transistors ST1, ST2, ST3, ST4, ST5, and ST6, the active layer may be disposed on the second buffer layer 122, and the second gate insulating layer 160 may be disposed between the gate electrode and the active layer. The description may be the same as or substantially the same as the description referred to above with reference to one or more exemplary embodiments, and thus, its redundant description may not be repeated.

[0214] A display device according to one or more exemplary embodiments includes a driving transistor and a switching transistor disposed at different layers from each other (e.g., disposed in different layers from each other or disposed on different layers from each other) and a plurality of gate insulating layers having different physical properties from each other. The plurality of gate insulating layers may include different insulating materials from each other, or may have different thicknesses from each other, and each gate insulating layer may be disposed on the active layer of each transistor in the driving transistor and the switching transistor.

[0215] Therefore, the display device may control desired device characteristics of the driving transistor and the switching transistor by including gate insulating layers having different physical properties from each other, and thus, in a display device having a high resolution, excellent device characteristics may be ensured in the transistors disposed at each pixel (e.g., disposed in each pixel or disposed on each pixel).

[0216] Although various exemplary embodiments of the present disclosure have been described herein, these exemplary embodiments are used only in a descriptive sense and not for purposes of limitation. Thus, those skilled in the art will understand that various modifications can be made to the exemplary embodiments of the present invention without departing from the spirit and scope of the invention as defined by the present disclosure and its equivalents.

Claims

1. A display device, wherein, The display device includes: a substrate; a first buffer layer located on the substrate; a first semiconductor layer located on the first buffer layer and including a first active layer; a first gate insulating layer located on the first semiconductor layer and the first buffer layer and covering the first active layer; a first conductive layer located on the first gate insulating layer and including a first gate electrode; a second conductive layer located on the first conductive layer and including a first source / drain electrode; a first interlayer insulating layer located on the first conductive layer; a second semiconductor layer located on the first interlayer insulating layer and including a second active layer; a second gate insulating layer located on the second semiconductor layer and covering the second active layer; and a third conductive layer located on the second gate insulating layer and including a second gate electrode and a second source / drain electrode, wherein the first gate insulating layer and the second gate insulating layer include different insulating materials from each other, the first active layer and the second active layer overlap with each other.

2. The display device according to claim 1, wherein, The first gate insulating layer includes a single layer containing silicon oxide, and the second gate insulating layer includes: a first insulating layer including silicon oxide; and a second insulating layer located on the first insulating layer and containing silicon nitride or silicon oxynitride.

3. The display device according to claim 2, wherein, The first insulating layer of the second gate insulating layer is in contact with the second active layer.

4. The display device according to claim 3, wherein, The thickness of the first insulating layer is greater than the thickness of the second insulating layer.

5. The display device according to claim 2, wherein, The first gate insulating layer includes: a third insulating layer containing silicon oxide; and a fourth insulating layer located on the third insulating layer and containing silicon nitride or silicon oxynitride. The display device according to claim 5 , wherein: The third insulating layer of the first gate insulating layer is in contact with the first active layer.

7. The display device according to claim 5, wherein The hydrogen content of the fourth insulating layer is lower than the hydrogen content of the second insulating layer.

8. The display device according to claim 1, wherein, The width in one direction of the portion of the first active layer overlapping with the first gate electrode is greater than the width in the one direction of the portion of the second active layer overlapping with the second gate electrode.

9. The display device according to claim 8, wherein, The thickness of the portion of the first gate insulating layer overlapping with the first active layer is greater than the thickness of the portion of the second gate insulating layer overlapping with the second active layer.

10. The display device according to claim 8, wherein, The thickness of the first active layer is greater than the thickness of the second active layer.

11. The display device according to claim 1, wherein, The display device further includes: a second buffer layer located between the second active layer and the first interlayer insulating layer.

12. The display device according to claim 11, wherein, The second semiconductor layer further includes a third active layer located on the second buffer layer, and the second gate insulating layer is located on the third active layer.

13. The display device according to claim 12, wherein, The third conductive layer further includes: a third gate electrode and a third source / drain electrode, located on the second gate insulating layer and overlapping at least a part of the third active layer.

14. The display device according to claim 1, wherein The display device further includes: a first protective layer located between the second conductive layer and the first conductive layer and between the second conductive layer and the first gate insulating layer, wherein the second conductive layer is located on the first protective layer, and the second conductive layer further includes one electrode of a first capacitor, and at least a part of the first capacitor overlaps with the first gate electrode.

15. The display device according to claim 14, wherein The display device further includes: a second interlayer insulating layer located on the third conductive layer; A data signal line, located on the second interlayer insulating layer; A second protective layer, located on the data signal line; and A conductive pattern, located on the second protective layer and including at least a part overlapping with the data signal line.

16. A display device, wherein: The display device includes: A substrate; A first buffer layer, located on the substrate; A first semiconductor layer, located on the first buffer layer and including a first active layer; A first gate insulating layer, located on the first semiconductor layer and the first buffer layer and covering the first active layer; A first conductive layer, located on the first gate insulating layer and including a first gate electrode; A first interlayer insulating layer, located on the first conductive layer; A second semiconductor layer, located on the first interlayer insulating layer and including a second active layer; A second gate insulating layer, located on the second semiconductor layer and covering the second active layer; and A second conductive layer, located on the second gate insulating layer and including a second gate electrode, wherein, the thickness of the part of the first gate insulating layer overlapping with the first active layer is greater than the thickness of the part of the second gate insulating layer overlapping with the second active layer.

17. The display device according to claim 16, wherein, The thickness of the first active layer is greater than the thickness of the second active layer.

18. The display device according to claim 17, wherein, The first gate insulating layer includes a single layer containing silicon oxide, and The second gate insulating layer includes: A first insulating layer, containing silicon oxide; and A second insulating layer, located on the first insulating layer and containing silicon nitride.

19. The display device according to claim 18, wherein The second insulating layer of the second gate insulating layer contains silicon oxynitride.

20. A display device, wherein: The display device includes: A substrate; A driving transistor, located on the substrate and including a first active layer, a first gate electrode, and a first source / drain electrode; A first interlayer insulating layer, located on the driving transistor; A first switching transistor, located on the first interlayer insulating layer and including a second active layer, a second gate electrode, and a second source / drain electrode; A first gate insulating layer, located between the first active layer and the first gate electrode; and A second gate insulating layer, located between the second active layer and the second gate electrode, wherein, the width of the channel region of the first active layer in one direction is greater than the width of the channel region of the second active layer in the one direction, and The dielectric constant of the first gate insulating layer is lower than the dielectric constant of the second gate insulating layer.

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