Display device and method for driving the same

Abstract

An embodiment provides a display device and a driving method for the display device, the display device including: a light emitting diode; a driving transistor configured to supply current to the light emitting diode; a switching transistor having an input electrode connected to a data line; and a voltage transfer capacitor arranged between an output electrode of the switching transistor and a gate electrode of the driving transistor, wherein a data voltage applied to the data line can be transferred to the gate electrode of the driving transistor through the voltage transfer capacitor, and the data voltage can have a data voltage value from which a voltage variation variable is removed based on leakage of the switching transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0105904, filed on August 28, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The technical field relates to a display device and a driving method of the display device, and more particularly, to a display device including a lookup table and a driving method of the display device. Background Art

[0004] Liquid crystal display devices and organic light emitting diode display devices are typical flat panel displays that are widely used. Among such display devices, the use of organic light emitting diode display devices is increasing, and the organic light emitting diode display includes a light emitting diode (LED) whose brightness is controlled by current.

[0005] In addition, a pixel of an organic light emitting diode display device may include a light emitting diode, a driving transistor that controls the amount of current supplied to the light emitting diode, and a switching transistor that transmits a data voltage to the driving transistor.

[0006] The above information in this Background section is only for enhancement of understanding of the background of the described technology and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Summary of the Invention

[0007] Embodiments have provided a display device that can compensate for the characteristics of transistors included in pixels. Embodiments have provided a display device in which a Vth compensation period and a programming period are separated. Embodiments have provided a display device that can display an image in which parasitic capacitance and leakage of transistors are compensated.

[0008] An embodiment provides a display device including: a light emitting diode; a driving transistor configured to supply current to the light emitting diode; a switching transistor having an input electrode connected to a data line; and a voltage transfer capacitor arranged between an output electrode of the switching transistor and a gate electrode of the driving transistor, wherein a data voltage applied to the data line can be transferred to the gate electrode of the driving transistor through the voltage transfer capacitor, wherein the data voltage can have a data voltage value from which a voltage variation variable is removed based on leakage of the switching transistor.

[0009] The compensated data voltage may be a voltage compensated based on a parasitic capacitance of a first electrode among two electrodes of the voltage transfer capacitor, the first electrode being connected to the gate electrode of the driving transistor.

[0010] The compensated data voltage may be compensated based on the magnitude of the data voltage before and after being applied to one data line.

[0011] Each of the plurality of pixels may include a light emitting diode, a driving transistor, a switching transistor, and a voltage transfer capacitor, and the display device may include: a display portion formed with the plurality of pixels and including scan lines and data lines; a data driver connected to the data lines; a scan driver connected to the scan lines; and a signal controller configured to control the data driver and the scan driver.

[0012] The signal controller may include a lookup table, and the value stored in the lookup table is based on leakage of the switching transistor.

[0013] The plurality of pixels are configured to have an initialization period, a threshold voltage compensation period, and a programming period, and the threshold voltage compensation period and the programming period do not overlap.

[0014] The signal controller may further include an image data converter configured to generate final grayscale data by using the continuous grayscale data input to one pixel PX in the programming period and a lookup table.

[0015] The second electrode, which is the other electrode among the two electrodes of the voltage transfer capacitor, may be connected to the switching transistor through a first node, and the first node may be configured to have a reference voltage before the switching transistor is turned on.

[0016] The compensated data voltage can be applied so that the voltage of the gate electrode of the driving transistor is VELVDD-Vth+K(VD(n)-VREF), where VELVDD is the voltage value of the first power supply voltage, Vth is the threshold voltage value of the driving transistor, K is [C2 / (C2+Cp)], C2 is the capacitance of the voltage transfer capacitor, Cp is the parasitic capacitance of the first electrode adjacent to the voltage transfer capacitor, VD(n) is the voltage value of D(n) as the currently applied grayscale data, and VREF is the reference voltage value.

[0017] An input electrode of the driving transistor may be connected to a first power supply voltage, wherein the holding capacitor is arranged between the first power supply voltage and a first node which may further be included.

[0018] The display device may further include a compensation transistor having an input electrode connected to the output electrode of the driving transistor and an output electrode connected to the first node.

[0019] The display device may further include a current transfer transistor having an output electrode connected to the light emitting diode and an input electrode connected to the output electrode of the driving transistor.

[0020] The display device may further include: a gate initialization transistor configured to initialize a voltage of a gate electrode of the driving transistor; and a first node initialization transistor configured to initialize a voltage of the first node to a reference voltage.

[0021] The display device may further include an anode initialization transistor configured to initialize an anode electrode that is one electrode of the light emitting diode.

[0022] Another embodiment provides a driving method for a display device, wherein the display device includes a light emitting diode, a driving transistor, a switching transistor provided with an input electrode connected to a data line, and a first capacitor arranged between an output electrode of the switching transistor and a gate electrode of the driving transistor, the driving method including: obtaining a value of α which is a difference between an adjacent previous data voltage and a current data voltage to be applied to a data line; determining a lookup table capable of removing a voltage change variable caused by leakage of the switching transistor based on the obtained α value; and changing grayscale data corresponding to the current data voltage based on the determined lookup table to generate final grayscale data.

[0023] The final grayscale data is compensated based on a parasitic capacitance of a first electrode of a first capacitor connected to a gate electrode of the driving transistor.

[0024] Determining the lookup table may include determining whether the voltage changes in a positive direction or a negative direction or does not change based on the value of α, and changing the lookup table except when the value of α is zero.

[0025] Changing the lookup table may include: determining a correction parameter based on the value of α; replacing the value of α based on the correction parameter; and performing the conversion by multiplying the replaced value of α by a value stored in the lookup table.

[0026] The correction parameter may be a value determined based on the value of α or a value determined based on a weight.

[0027] The voltage of the gate electrode of the driving transistor obtained by the final grayscale data can be VELVDD-Vth+K(VD(n)-VREF), where VELVDD is the voltage value of the first power supply voltage, Vth is the threshold voltage value of the driving transistor, K is [C2 / (C2+Cp)], C2 is the capacitance of the first capacitor, Cp is the parasitic capacitance of the first electrode adjacent to the first capacitor, VD(n) is the voltage value of D(n) as the currently applied grayscale data, and VREF is the voltage of the first node connecting the first capacitor and the switching transistor before the switching transistor is turned on.

[0028] According to the embodiment, the display quality can be improved by eliminating charging failure caused by leakage current of the transistor. The display quality is not affected by parasitic capacitance changes in the pixel. Each pixel included in the display device can display a predetermined brightness regardless of the threshold voltage of the driving transistor. In addition, Vth compensation can be clearly and independently performed by separating the Vth compensation period and the programming period. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A block diagram of a display device according to an embodiment is illustrated.

[0030] Figure 2 An equivalent circuit diagram of one pixel of an organic light emitting diode display device according to an embodiment is illustrated.

[0031] Figure 3 The diagram shows the application Figure 2 The waveform diagram of the pixel signal.

[0032] Figure 4 A table summarizing the voltage changes in each programming period is illustrated.

[0033] Figure 5 、 Figure 6 and Figure 7 is a diagram illustrating a process of converting image data in each programming period.

[0034] Figure 8 A block diagram of an image data converter in a signal controller is shown.

[0035] Figure 9 A table illustrating whether an image data converter is operated according to various embodiments is shown.

[0036] Figure 10 Schematic diagrams illustrating areas for converting image data in a display device according to various embodiments.

[0037] Figure 11 An equivalent circuit diagram of one pixel of an organic light emitting diode display device according to another embodiment is illustrated.

[0038] Figure 12 The diagram shows the application Figure 11 The waveform diagram of the pixel signal.

[0039] Figure 13 The diagram shows the application Figure 2 or Figure 11 The waveform diagram of the pixel signal.

[0040] Figure 14 The diagram shows Figure 13 A table summarizing the voltage changes in each programming period is provided in the embodiment of FIG.

[0041] Figure 15 、 Figure 16 and Figure 17 The diagram shows the application Figure 2 or Figure 11 The waveform diagram of the pixel signal. DETAILED DESCRIPTION

[0042] The present inventive concept will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the present inventive concept are shown. As those skilled in the art will realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0043] Throughout this disclosure, like reference numerals may denote like elements.

[0044] In addition, in the drawings, for ease of description, the size and thickness of each element are arbitrarily illustrated, and the present disclosure is not necessarily limited to those illustrated in the drawings. In the drawings, the size of the elements may be exaggerated for clarity.

[0045] When a first element is referred to as being "on" a second element, the first element may be directly or indirectly on the second element. One or more intermediate elements may be present between the first and second elements. In addition, in the specification, the words "on" or "above" mean being positioned on or below an object part, and do not necessarily mean being positioned above the object part based on the direction of gravity.

[0046] In this specification, unless otherwise expressly stated, the word "comprise" and variations such as "comprises" or "comprising" may imply the inclusion of the stated elements, but may not require the exclusion of any other elements. Although the terms "first," "second," etc. may be used to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. Without departing from the teachings of one or more embodiments, a first element may be referred to as a second element. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first," "second," etc. may be used to distinguish elements of different categories or sets. For simplicity, the terms "first," "second," etc. may respectively represent "first type (or first set)," "second type (or second set)," etc.

[0047] Each of the elements described (such as "controller", "driver", "generator", etc.) can be hardware or software. For example, these elements can be circuits, microcontrollers, processors, RAM memories and other such electronic devices.

[0048] Furthermore, throughout this specification and the claims that follow, when it is described that an element is “coupled” to another element, the element may be “coupled” to the other element or “electrically coupled” to the other element through a third element.

[0049] In the following, reference will be made to Figure 1 A display device according to an embodiment is described.

[0050] Figure 1 A block diagram of a display device according to an embodiment is illustrated.

[0051] refer to Figure 1 , the display device includes a signal controller 100 , a scan driver 200 , a data driver 300 , a gamma voltage generator 350 , a light emitting control driver 400 , and a display portion 600 .

[0052] The signal controller 100 includes an input control signal and an image signal ImS input from outside the display device. The image signal ImS includes brightness information of each pixel PX, where the brightness information includes a predetermined number of grayscale levels. The input control signal may include a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync. The input control signal may be used to display an image based on the image signal ImS.

[0053] The signal controller 100 receives an image signal ImS and an input control signal from the outside, and can divide the image signal ImS into frames according to a vertical synchronization signal Vsync. The signal controller 100 can also divide the image signal ImS into scan lines SL1-SLn according to a horizontal synchronization signal Hsync. The signal controller 100 can generate an image data signal DAT, a scan control signal CONT1, a data control signal CONT2, a light emission control signal CONT3, and a gamma voltage control signal CONT4 based on the image signal ImS and the input control signal.

[0054] The signal controller 100 transmits the scan control signal CONT1 to the scan driver 200 , the data control signal CONT2 and the image data signal DAT to the data driver 300 , the emission control signal CONT3 to the emission control driver 400 , and the gamma voltage control signal CONT4 to the gamma voltage generator 350 .

[0055] The signal controller 100 may further include a lookup table LUT (see Figure 5 The signal controller 100 uses the lookup table LUT when converting the image signal ImS into the image data signal DAT. The lookup table LUT may be stored in a storage device such as a memory.

[0056] The signal controller 100 separates the received image signal ImS into grayscale data corresponding to each pixel PX and converts the image signal ImS into final grayscale data through a lookup table LUT. The final grayscale data can then be bundled into an image data signal DAT that can be transmitted to the data driver 300.

[0057] The final grayscale data has a grayscale data value that allows the pixel PX to actually display the brightness to be displayed by the pixel PX in the image signal ImS.

[0058] The lookup table LUT may include a plurality of lookup tables and includes a table for compensating the driving transistor ( Figure 2 A lookup table for the characteristics of the driving transistor T1 (hereinafter referred to as a lookup table for threshold voltage compensation) is provided. Since the driving transistor T1 may have a different threshold voltage for each pixel PX, the lookup table for threshold voltage compensation is used to compensate for the characteristics of the driving transistor T1. In some embodiments, a lookup table for compensating for other characteristics of each pixel PX may be further included.

[0059] The display portion 600 includes a plurality of scan lines SL1-SLn, a plurality of data lines DL1-DLm, a plurality of emission control lines EL1-ELn, and a plurality of pixels PX. The plurality of pixels PX can be connected to the plurality of scan lines SL1-SLn, the plurality of data lines DL1-DLm, and the plurality of emission control lines EL1-ELn so as to be arranged in a matrix. A pixel included in an organic light emitting diode display device can be divided into a light emitting diode (LED) and a pixel circuit portion for driving the light emitting diode (LED), and the pixel circuit portion can be arranged in a matrix.

[0060] The plurality of scan lines SL1-SLn may extend substantially in the row direction and may be substantially parallel to each other. The plurality of light emission control lines EL1-ELn may extend substantially in the row direction and may be substantially parallel to each other. The plurality of data lines DL1-DLm may extend substantially in the column direction and may be substantially parallel to each other.

[0061] The display portion 600 may be supplied with a first power supply voltage ELVDD (also referred to as a driving high voltage), a second power supply voltage ELVSS (also referred to as a driving low voltage), a reference voltage VREF, and an initialization voltage Vint. The first power supply voltage ELVDD may be a voltage having a power level supplied to a light emitting diode (see FIG. 1 ) included in each of the plurality of pixels PX. Figure 2 The first power supply voltage ELVDD and the second power supply voltage ELVSS are driving voltages transmitted to the plurality of pixels PX. The reference voltage VREF and the initialization voltage Vint may be constant voltages used to initialize or reset a specific node or element of the pixel PX to a predetermined voltage. Here, the reference voltage VREF may be a voltage at the same level as the first power supply voltage ELVDD, or a voltage at a different level. In addition, the initialization voltage Vint may be a voltage at a different level from the second power supply voltage ELVSS.

[0062] The scan driver 200 is connected to the plurality of scan lines SL1-SLn. The scan driver 200 applies a scan signal formed by a combination of a gate-on voltage and a gate-off voltage to the plurality of scan lines SL1-SLn according to a scan control signal CONT1. The scan driver 200 may sequentially apply the scan signal having the gate-on voltage to the plurality of scan lines SL1-SLn.

[0063] The data driver 300 is connected to a plurality of data lines DL1-DLm. The data driver 300 samples and holds the image data signal DAT according to the data control signal CONT2, and adjusts the data voltage (see Figure 2The data driver 300 may apply a data voltage Vdat having a predetermined voltage range to the plurality of data lines DL1-DLm in response to a scan signal of a gate-on voltage.

[0064] The gamma voltage generator 350 provides a reference gamma voltage to the data driver 300. The gamma voltage generator 350 can adjust the level of the reference gamma voltage according to the gamma voltage control signal CONT4 and provide the reference gamma voltage to the data driver 300. The data driver 300 generates a data voltage Vdat corresponding to each grayscale data included in the image data signal DAT based on the reference gamma voltage. When the reference gamma voltage is adjusted, the voltage level of the data voltage Vdat can be adjusted.

[0065] The light emitting control driver 400 is connected to a plurality of light emitting control lines EL1-ELn. The light emitting control driver 400 may generate a light emitting signal (see FIG. 1 ) formed by a combination of a gate-on voltage and a gate-off voltage according to a light emitting control signal CONT3. Figure 3 The EM signal (e.g., an EM signal) is applied to the emission control lines EL1-ELn. The emission signal EM is applied to the plurality of pixels PX via the plurality of emission control lines EL1 to ELn. The emission control driver 400 can control the pulse width of the emission signal EM based on the emission control signal CONT3. The emission control driver 400 can sequentially apply a gate-off voltage and a gate-on voltage to the emission control lines EL1-ELn. Thus, the pixels PX can be sequentially turned off and on for each row.

[0066] In the following, reference will be made to Figures 2 to 3 The structure and operation of the pixel PX are described.

[0067] Figure 2 An equivalent circuit diagram of one pixel of an organic light emitting diode display device according to an embodiment is illustrated, and Figure 3 The diagram shows the application Figure 2 The waveform diagram of the pixel signal.

[0068] Figure 2 The pixel PX is formed in Figure 1 An example pixel PX located in an n-th pixel row and an m-th pixel column among a plurality of pixels PX in a display portion 600 of a display device of FIG.

[0069] refer to Figure 2 The pixel PX includes a light emitting diode LED and a pixel circuit portion for driving the light emitting diode LED, and the pixel circuit portion is arranged in a matrix form. The pixel circuit portion may include the pixel PX except Figure 2All components except the light-emitting diode LED in the pixel circuit portion may include a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, and a second capacitor C2. In addition, a first scan line SLn, a second scan line SLin, a third scan line SLBn, a fourth scan line SLBn+1, a data line DLm, and a light emission control line ELn may be connected to the pixel circuit portion.

[0070] The driving transistor T1 includes a second electrode (output electrode) for outputting current based on the voltage of the gate electrode connected to the first electrode of the second capacitor C2, a first electrode (input electrode) connected to the first power supply voltage ELVDD, and a gate electrode. The second electrode of the driving transistor T1 is connected to the first electrode of the third transistor T3 and the first electrode of the sixth transistor T6. The output current of the driving transistor T1 is transmitted to the light-emitting diode LED through the sixth transistor T6, allowing the light-emitting diode LED to emit light. The intensity of the output current determines the brightness of the light emitted by the light-emitting diode LED.

[0071] The second transistor T2 (hereinafter also referred to as a switching transistor) includes a gate electrode connected to the first scan line SLn, a first electrode connected to the data line DLm, and a second electrode connected to a node A (also referred to as a first node). The second transistor T2 allows a data voltage Vdat to be input to the pixel PX according to the scan signal and stored in the second capacitor C2.

[0072] The second capacitor C2 (also referred to as a voltage transfer capacitor) includes a first electrode connected to the gate electrode of the driving transistor T1 and a second electrode connected to the node A. The second capacitor C2 transmits the data voltage Vdat output from the second transistor T2 to the gate electrode of the driving transistor T1. In the pixel PX of this embodiment, the data voltage Vdat is transmitted through the second capacitor C2 instead of being directly transmitted to the gate electrode of the driving transistor T1. This method of indirectly transmitting the data voltage Vdat to the gate electrode of the driving transistor T1 relies on the fact that when the voltage of the second electrode of the second capacitor C2 suddenly increases, the voltage of the first electrode of the second capacitor C2 also increases. Therefore, even if leakage from the second transistor T2 occurs, the voltage of the gate electrode of the driving transistor T1 does not leak directly.

[0073] At the same time, Figure 2 In FIG, the parasitic capacitance is represented by the parasitic capacitance Cp next to the first electrode of the second capacitor C2, and is the equivalent parasitic capacitance observed through the first electrode in the second capacitor C2.

[0074] When the capacitance of the second capacitor C2 and the parasitic capacitance Cp are used, a voltage variation of the first electrode according to a voltage variation of the second electrode of the second capacitor C2 may be represented by Equation 1 below.

[0075] (Equation 1)

[0076]

[0077] Here, the capacitance of the second capacitor C2 is represented by C2, is the voltage change of the first electrode of the second capacitor C2, and is the voltage change of the second electrode of the second capacitor C2.

[0078] The voltage variation of the first electrode of the second capacitor C2 is the same as the voltage variation of the gate electrode of the driving transistor T1. Therefore, when the data voltage Vdat is applied, the voltage variation of the gate electrode of the driving transistor T1 can be calculated according to Equation 1. When the parasitic capacitance Cp is not considered in Equation 1, the voltage variation of the first electrode of the second capacitor C2 can be the same as the voltage variation of the second electrode of the second capacitor C2.

[0079] A first capacitor C1 (also referred to as a holding capacitor) is further connected to node A. A first electrode of the first capacitor C1 is connected to node A, and a second electrode of the first capacitor C1 receives a first power supply voltage ELVDD. As a result, the voltage of node A may not change and may be maintained at a constant voltage even when the surrounding signal changes.

[0080] The third transistor T3 (also referred to as a compensation transistor) may include a gate electrode connected to the second scan line SLIn, a first electrode connected to the second electrode of the driving transistor T1, and a second electrode connected to the first electrode of the second capacitor C2. The third transistor T3 forms a compensation path Pcom for compensating for the threshold voltage of the driving transistor T1, so that the threshold voltage of the driving transistor T1 is transmitted to the first electrode of the second capacitor C2 and compensated. Therefore, even if the threshold voltage of the driving transistor T1 included in each pixel PX of the display portion 600 is different from each other, each driving transistor T1 can output a constant output current according to the applied data voltage Vdat.

[0081] The fourth transistor T4 (hereinafter also referred to as the gate initialization transistor) includes a gate electrode connected to the third scan line SLBn, a first electrode to which an initialization voltage Vint is applied, and a second electrode connected to the first electrode of the second capacitor C2 (or the gate electrode of the driving transistor T1). The fourth transistor T4 initializes the first electrode of the second capacitor C2 and the gate electrode of the driving transistor T1 using the initialization voltage Vint.

[0082] The fifth transistor T5 (hereinafter referred to as a node A initialization transistor) includes a gate electrode connected to the second scan line SLIn, a first electrode to which a reference voltage VREF is applied, and a second electrode connected to the node A. The fifth transistor T5 changes the node A to the reference voltage VREF.

[0083] The sixth transistor T6 (also referred to as a current transfer transistor) includes a gate electrode connected to the light emitting control line ELn, a first electrode connected to the second electrode of the driving transistor T1, and a second electrode connected to the anode electrode of the light emitting diode LED. The sixth transistor T6 transfers the output current of the driving transistor T1 to the light emitting diode LED or blocks the output current of the driving transistor T1 from reaching the light emitting diode LED.

[0084] The seventh transistor T7 (also referred to as the anode initialization transistor) includes a gate electrode connected to the fourth scan line SLBn+1, a first electrode to which an initialization voltage Vint is applied, and a second electrode connected to the anode electrode of the light-emitting diode LED. The seventh transistor T7 initializes the anode electrode of the light-emitting diode LED using the initialization voltage Vint. In some embodiments, the fourth scan line SLBn+1 used to operate the seventh transistor T7 and the third scan line SLBn used to operate the fourth transistor T4 can be the same scan line. Figure 11 This embodiment is shown in FIG.

[0085] exist Figure 2 In the embodiment of FIG, since all transistors are formed as p-type transistors, they are turned on when a high voltage is applied and turned off when a low voltage is applied. In other words, the gate-on voltage is a low-level voltage, and the gate-off voltage is a high-level voltage.

[0086] The light-emitting diode LED includes an anode electrode connected to the second electrode of the sixth transistor T6 and a cathode electrode connected to the second power supply voltage ELVSS. The light-emitting diode LED can be connected between the pixel circuit portion and the second power supply voltage ELVSS to emit light with a brightness corresponding to the current supplied from the pixel circuit portion (specifically, the driving transistor T1). The light-emitting diode LED may include a light-emitting layer that includes at least one of an organic light-emitting material and an inorganic light-emitting material. Holes and electrons are injected into the light-emitting layer from the anode electrode and the cathode electrode, respectively, and light is emitted when excitons formed by the recombination of the injected holes and electrons enter a ground state from an excited state. The light-emitting diode LED may emit light of one of the primary colors or white light. Examples of primary colors may include red, green, and blue. Another example of primary colors may include yellow, cyan, and magenta. In some embodiments, an additional color filter or color conversion layer may be further included to improve color display characteristics.

[0087] In the following, reference will be made to Figure 3 describe Figure 2 The operation of the pixel PX.

[0088] The signal applied to the pixel PX mainly includes an initialization period (Initial), a Vth compensation period, a programming period (Programming), and a light emitting period (Emission).

[0089] exist Figure 3 1H represents one horizontal period, and one horizontal period may correspond to one horizontal synchronization signal Hsync. 1H may mean a time when a gate-on voltage is applied to a scan line of a next row after a gate-on voltage is applied to a scan line.

[0090] First, the light emitting period is a period during which the light emitting diode LED emits light, wherein the current output from the driving transistor T1 is transmitted to the light emitting diode LED through the sixth transistor T6. In this period, since the sixth transistor T6 is turned on, the gate-on voltage (low level voltage) is applied as the light emitting signal EM. Figure 3 , the light emission period in which the light emission signal EM is applied as the gate-on voltage is briefly shown. This is because the gate-off voltage (high-level voltage) is constantly applied to the corresponding scan lines (the first scan line SLn, the second scan line SLin, the third scan line SLBn, and the fourth scan line SLBn+1), and the pixel PX only performs the above-mentioned simple operation.

[0091] When the light-emitting signal EM is changed to the gate-off voltage, the light-emitting period ends. The period during which the gate-off voltage of the light-emitting signal EM is applied may be greater than the sum of the periods during which the gate-on voltage is applied in the initialization period, the Vth compensation period, and the programming period by a total of 2 hours. That is, when 1 hour has passed after the light-emitting signal EM is changed to the gate-off voltage, the initialization period begins, and when approximately 1 hour has passed after the end of the programming period, the light-emitting signal EM may be changed to the gate-on voltage. The length of the light-emitting period may vary.

[0092] After the light-emitting period ends, when the gate-on voltage is applied to the third scan line SLBn, the first initialization period begins. During the first initialization period, the voltage of the gate electrode of the driving transistor T1 is changed to the initialization voltage Vint. The fourth transistor T4 is turned on to transmit the initialization voltage Vint to the gate electrode of the driving transistor T1. In this case, the first electrode of the second capacitor C2 and the second electrode of the third transistor T3 are also changed to the initialization voltage Vint.

[0093] In an embodiment, the gate-on voltage among the scan signals applied to the third scan line SLBn is applied during a period of 3 H. Among the scan signals applied to the third scan line SLBn, the time when the gate-on voltage is applied may be changed.

[0094] Thereafter, when the gate-on voltage is applied to the fourth scan line SLBn+1, a second initialization period begins. During the second initialization period, the voltage at the anode electrode of the light-emitting diode LED is changed to the initialization voltage Vint. To this end, the seventh transistor T7 is turned on to transmit the initialization voltage Vint to the anode electrode of the light-emitting diode LED. In this case, the second electrode of the sixth transistor T6 is also changed to the initialization voltage Vint.

[0095] In an embodiment, the gate-on voltage in the scan signal applied to the fourth scan line SLBn+1 is applied during a 3H period. In addition, the first initialization period and the second initialization period are separated by 1H. In some embodiments, the two initialization periods may be the same. In addition, the time for applying the gate-on voltage in the scan signal applied to the fourth scan line SLBn+1 may be changed.

[0096] During a 2H period in which the first initialization period and the second initialization period overlap, the gate electrode of the driving transistor T1 and the anode electrode of the light emitting diode LED are simultaneously initialized.

[0097] Thereafter, when the gate-on voltage is applied to the second scan line SLIn, the Vth compensation period (i.e., the threshold voltage compensation period) begins. During the Vth compensation period, the driving transistor T1 outputs current, but this current passes through the third transistor T3 to the second capacitor C2. As time passes, the output of the driving transistor T1 gradually decreases, and when the voltage difference between the gate electrode and the first electrode of the driving transistor T1 is the threshold voltage Vth of the driving transistor T1, the driving transistor T1 does not output current. As a result, the voltage of the gate electrode of the driving transistor T1 has the same value as VELVDD-Vth. Here, VELVDD is the voltage value of the first power supply voltage ELVDD. In this case, since the sixth transistor T6 is turned off, the output of the driving transistor T1 is not transmitted to the light-emitting diode LED.

[0098] In order to make the driving transistor T1 output current during the Vth compensation period, the fifth transistor T5 is turned on and the voltage of the second electrode of the second capacitor C2 is changed to the reference voltage VREF. In this case, the voltage of the first electrode of the second capacitor C2 is also changed because the voltage of the gate electrode of the driving transistor T1 is changed so that the driving transistor T1 generates an output current.

[0099] In this case, since the third transistor T3 is also turned on, the output current of the driving transistor T1 is transmitted to the first electrode of the second capacitor C2, and the voltage of the first electrode of the second capacitor C2 has the same value as VELVDD-Vth.

[0100] exist Figure 3 In the embodiment, the gate-on voltage among the scan signals applied to the second scan line SLIn is applied during a period of 3 H. In addition, the time when the gate-on voltage is applied among the scan signals applied to the second scan line SLIn may vary according to the embodiment.

[0101] At the same time, Figure 3 In the embodiment of FIG. 1 , the period during which the gate-on voltage is applied to the second scan line SLIn overlaps with the second initialization period by 1H. In this case, the driving transistor T1 outputs a current, so that the voltage of the first electrode of the second capacitor C2 is changed to a voltage value of VELVDD-Vth, and the voltage of the anode electrode of the light emitting diode LED is also changed to the initialization voltage Vint.

[0102] In this embodiment, the Vth compensation period and the first initialization period do not overlap. This is because both periods are used to change the voltage of the first electrode of the second capacitor C2. However, since the Vth compensation period continues after the first initialization period, even if some periods overlap, some periods may overlap after the Vth compensation is completed. In addition, in embodiments, the Vth compensation period and the first initialization period may be separated by 1 hour or more.

[0103] After the Vth compensation period, the programming period begins while the gate-on voltage is applied to the first scan line SLn. During the programming period, the data voltage Vdat is transmitted to the gate electrode of the driving transistor T1. To this end, the second transistor T2 is turned on to transmit the data voltage Vdat to the node A. At the same time, the voltage of the gate electrode of the driving transistor T1 is also changed according to Equation 1, and these voltages are respectively stored in the first electrode and the second electrode of the second capacitor C2.

[0104] In addition, the Vth compensation period and the programming period are separated from each other. The threshold voltage compensation can be performed more clearly than when the Vth compensation period and the programming period are performed simultaneously. Therefore, the display quality degradation caused by the difference between the threshold voltages of the corresponding driving transistors T1 is prevented. In other words, the Vth compensation period and the programming period do not overlap.

[0105] exist Figure 3 In the embodiment of the present invention, the gate-on voltage among the scan signals applied to the first scan line SLn is applied during 3H. The time during which the gate-on voltage is applied among the scan signals applied to the first scan line SLn may vary.

[0106] exist Figure 3In the figure, the programming period is applied for a total of 3H, which is divided into an A programming period, a B programming period and a C programming period, where the C programming period is shown as the (n)th H, the B programming period is shown as the (n-1)th H, and the A programming period is shown as the (n-2)th H.

[0107] In the following, reference will be made to Figure 4 Together Figure 3 A change in the voltage Vg of the gate electrode of the driving transistor T1 according to a plurality of data voltages input in corresponding programming periods (A programming period, B programming period, and C programming period) is described.

[0108] Figure 4 A table summarizing the voltage changes in each programming period is illustrated.

[0109] exist Figure 4 , the voltage Vg of the gate electrode of the driving transistor T1 will be described while taking into account the parasitic capacitance Cp at the first electrode side of the second capacitor C2.

[0110] Hereinafter, the voltage Vg of the gate electrode of the driving transistor T1 is simply referred to as a gate voltage Vg.

[0111] Before describing the respective programming periods, it may be necessary to check the voltage of the node A and the gate voltage Vg after a Vth compensation period preceding the respective programming periods has passed. Figure 4 As shown in FIG, the voltage of the node A has the reference voltage VREF, and the gate voltage Vg has a value of VELVDD-Vth, wherein the threshold voltage of the driving transistor T1 is compensated.

[0112] Based on this, a change in voltage according to a programming period will be described.

[0113] First, in the A programming period, in a state where the voltage of the node A is the reference voltage VREF, while the gate-on voltage is applied to the first scan line SLn, the data voltage Vdat is transmitted to the node A. As a result, the voltage of the node A is changed to the data voltage Vdat applied to the data line DLm in the A programming period.

[0114] The grayscale data applied during the programming period A is referred to as "D(n-2)", the voltage of the grayscale data D(n-2) is referred to as VD(n-2), and K is the capacitance ratio of Equation 1, that is, C2 / (C2+Cp), corresponding to Figure 4 The corresponding voltage described in the programming period A.

[0115] That is, since the grayscale data corresponding to the A programming period is D(n-2), the data voltage Vdat applied along the data line DLm is VD(n-2).

[0116] Since the voltage of the node A changes from VREF to VD(n-2) as the Vth compensation period changes to the A programming period, the voltage of the first electrode of the second capacitor C2 changes It also becomes (VD(n-2)-VREF)×[C2 / (C2+Cp)] according to Equation 1.

[0117] Here, since [C2 / C2+Cp)] is set to K, the voltage change (ΔV1) of the first electrode of the second capacitor C2 is K(VD(n-2)-VREF). Since the voltage of the first electrode of the second capacitor C2 is equal to the gate voltage Vg, the change value of the Vg voltage in Table 4 becomes K(VD(n-2)-VREF).

[0118] Since the change value of the gate voltage Vg is known when entering the A programming period, when the change value is added to the gate voltage Vg in the Vth compensation period, the gate voltage Vg in the A programming period is known. Since the gate voltage Vg in the Vth compensation period is VELVDD-Vth, and the change value of the gate voltage Vg in the A programming period is K(VD(n-2)-VREF), the gate voltage Vg in the A programming period becomes as follows Figure 4 VELVDD-Vth+K(VD(n-2)-VREF) as described in.

[0119] The B programming period will now be described based on the voltage of the A programming period as described above.

[0120] When the gate-on voltage is continuously applied to the first scan line SLn in a state where the voltage of the node A is VD(n-2), the data voltage Vdat of the B programming period is transferred to the node A. As a result, the voltage of the node A is changed to the data voltage Vdat applied to the data line DLm in the B programming period.

[0121] The grayscale data applied during the B programming period is referred to as D(n-1), and the voltage of the grayscale data D(n-1) is referred to as VD(n-1). Figure 4 Each voltage described in the B programming period corresponds to.

[0122] That is, since the grayscale data corresponding to the B programming period is D(n-1), the data voltage Vdat applied along the data line DLm is VD(n-1).

[0123] Since the voltage of the node A changes from VD(n-2) to VD(n-1) as the A programming period changes to the B programming period, the voltage of the first electrode of the second capacitor C2 changes It also becomes (VD(n-1)-VD(n-2))×[C2 / (C2+Cp)] according to Equation 1.

[0124] Here, since [C2 / C2+Cp)] is set to K, the voltage change (ΔV1) of the first electrode of the second capacitor C2 is K(VD(n-1)-VD(n-2)). Since the voltage of the first electrode of the second capacitor C2 is equal to the gate voltage Vg, the change value of the Vg voltage in Table 4 becomes K(VD(n-1)-VD(n-2)).

[0125] Since the change value of the gate voltage Vg is known when entering the B programming period, when the change value is added to the gate voltage Vg in the A programming period, the gate voltage Vg in the B programming period is known. Therefore, since the gate voltage Vg in the A programming period is VELVDD-Vth+K(VD(n-2)-VREF), and the change value of the gate voltage Vg in the B programming period is K(VD(n-1)-VD(n-2)), the gate voltage Vg in the B programming period is VELVDD-Vth+K(VD(n-2)-VREF)+K(VD(n-1)-VD(n-2)), and when grouped by K, a portion of VD(n-2) is removed, resulting in VELVDD-Vth+K(VD(n-1)-VREF).

[0126] In the same manner, the gate voltage Vg of the C programming period can also be obtained based on the voltage of the B programming period.

[0127] That is, when the grayscale data applied during the C programming period is referred to as D(n) and the voltage of the grayscale data D(n) is referred to as VD(n), Figure 4 The gate voltage Vg in the C programming period shown in FIG is VELVDD-Vth+K(VD(n)-VREF). This is because when K is used for grouping when calculating the gate voltage Vg value, the portion of the voltage value VD(n-1) applied to the existing data line is eliminated.

[0128] Since the K value included in the above-mentioned gate voltage Vg includes the parasitic capacitance Cp on the first electrode side of the second capacitor C2 , the K value is calculated based on the parasitic capacitance Cp.

[0129] However, in the actual pixel PX, when there is leakage in the second transistor T2 as a switching transistor that receives the data voltage Vdat and transmits it to the second electrode side of the second capacitor C2, the actual gate voltage may be slightly different from the calculated gate voltage Vg.

[0130] That is, under ideal and theoretical conditions, Figure 4 The value of the gate voltage Vg shown in is obtained because when grouping is performed with K, part of the previously applied data voltage is removed.

[0131] However, in an empirical case, in a portion where an existing data voltage is applied, voltage leakage occurs for 1 H. Considering this, the value of the gate voltage Vg for each period may be changed and expressed as shown in the following table.

[0132] (Table 1)

[0133] A Vg during programming period VELVDD-Vth+K(VD(n-2)-VREF)±X1 B Vg during programming period VELVDD-Vth+K(VD(n-1)-VREF)±X2 Vg during C programming period VELVDD-Vth+K(VD(n)-VREF)±X3

[0134] Here, X1, X2, and X3 represent voltage variation variables generated during the corresponding programming period due to leakage of the second transistor T2. In an embodiment, the three voltage variation variables may be the same or different, and the voltage variation variables may be changed according to the data voltage Vdat and the voltage stored in the second capacitor C2, and may also need to be added or subtracted.

[0135] Considering this, the voltage change variable X2 may be a concept including the voltage change variable X1, and the voltage change variable X3 may be a concept including the voltage change variables X2 and X1. However, depending on the magnitude and direction of the data voltage Vdat and the voltage stored in the second capacitor C2, the value of the voltage change variable may increase or decrease as the programming period passes.

[0136] If the voltage variation variation due to such leakage is not eliminated, the gate voltage Vg may incorrectly have a higher voltage or a lower voltage than desired, causing different brightness displayed by the light emitting diode LED for different pixels.

[0137] Therefore, it is desirable to eliminate the voltage variation variation based on the leakage of the second transistor T2 (eg, based on the sensitivity to the leakage of the second transistor T2), and this can be achieved by using a circuit such as Figures 5 to 7 The lookup table LUT shown in FIG eliminates voltage variation variables.

[0138] Hereinafter, an embodiment of eliminating voltage variation variables by converting a stored lookup table such as a lookup table for threshold voltage compensation will be described.

[0139] Figures 5 to 7 is a diagram illustrating a process of converting image data in each programming period.

[0140] Figures 5 to 7 is a diagram illustrating a sequence of compensation using the lookup table LUT in consideration of the leakage of the second transistor T2 and the parasitic capacitance Cp at the first electrode side of the second capacitor C2 .

[0141] First, refer to Figure 5 Describe the sequence for eliminating the voltage change variable X1 in the A programming period.

[0142] exist Figure 5In the A programming period, the grayscale data applied during the A programming period is referred to as D(n-2), and the final grayscale data compensated based on the lookup table LUT is referred to as D(n-2)'. In addition, Figure 5 Flowchart illustrating the operation of the signal controller 100 (also refer to the image data converter 110 included in the signal controller 100) Figure 8 ).

[0143] When the image signal ImS is transmitted from the outside to the signal controller 100 , the image signal ImS is divided into grayscale data corresponding to each pixel PX.

[0144] Gray data separated in this manner may be reset in the process of being applied to one data line DL1 -DLm based on the connection structure of the pixels PX and the data lines DL1 -DLm of the display part 600 .

[0145] Three consecutive grayscale data among the reset grayscale data are applied to one pixel PX as D(n-2), D(n-1), and D(n) during the A programming period, the B programming period, and the C programming period.

[0146] Among these grayscale data, Figure 5 The grayscale data corresponding to the A programming period is D(n-2).

[0147] In the signal controller 100, when D(n-2) is determined from the image signal ImS, D(n-2) is transmitted to the image data converter 110 (see Figure 8 ) Figure 5 The final grayscale data D(n-2)' is generated in the order shown in .

[0148] The value of α is obtained by comparing VD(n-2), which is the voltage value of the transmitted grayscale data D(n-2), with the voltage value VREF of the node A (step S10). The value of α determines whether the voltage changes in the positive direction, in the negative direction, or there is no change.

[0149] The final grayscale data D(n-2)' may be generated by modifying the lookup table LUT or using a separate lookup table LUT, except when the value of α is 0.

[0150] exist Figure 5 In the example, when the value of α is greater than 0, the lookup table LUT is converted (step S20), and the grayscale data D(n-2) is converted based on the converted lookup table (step S120). In this way, the final grayscale data D(n-2)' is generated.

[0151] The method for converting the lookup table LUT uses a β value in addition to the already obtained α value. The β value is determined based on the α value and is a correction parameter. The degree of correction of the lookup table LUT is adjusted according to the magnitude of the α value. Various β values ​​based on the α value can be stored in the memory of the display device. The β value can be stored based on a weight or by considering all grayscale data values ​​of each pixel PX for which grayscale data is input.

[0152] When the α value and the β value are determined as described above, the α value is replaced with α′ by a predetermined correction parameter β, and the replacement of α′ can be performed according to Equation 2.

[0153] (Equation 2)

[0154] α'=α×β

[0155] The replaced α' value is used to convert the lookup table LUT by multiplying the value provided by the lookup table LUT by the α' value.

[0156] exist Figure 5 At step S20, the conversion is represented by |α|×βLUT, and since |α|×β is the α' value, the conversion can be simplified to α'×LUT. Since α of |α| can be a negative value, the absolute value sign is commonly used, and when α is positive, |α| is the same as the α value. Specifically, Figure 5 The LUT in refers to a value provided from a lookup table LUT.

[0157] Based on the data of the lookup table after conversion as described above, the grayscale data D(n-2) is converted at step S120 to generate final grayscale data D(n-2)'.

[0158] In the above description, the value of α' is a value changed so that the corrected final grayscale data D(n-2)' cancels the voltage variation variable of ±X1 in Table 1. As a result, the gate voltage Vg at the moment of entering the B programming period is equal to Figure 4 The voltage represented in (VELVDD-Vth+K(VD(n-2)-VREF)).

[0159] exist Figure 5 In the accompanying drawings, as described above, the final grayscale data generated by using the continuous grayscale data input to one pixel PX in the corresponding programming period and the lookup table LUT is referred to as PDC. PDC is an abbreviation of "previous data coupling compensation", which means correcting the current grayscale data by using the previous grayscale data. Here, the previous grayscale data and the current grayscale data are named based on the data programmed (or written) in one pixel PX. In the following, the data voltage converted by the previous grayscale data is referred to as the previous data voltage, and the data voltage converted by the current grayscale data is referred to as the current data voltage.

[0160] Hereinafter, the Figure 5 When α is less than 0.

[0161] When the α value is less than 0, the β value used when the α value is greater than 0 is not used, so the lookup table LUT is converted using the β' value as another correction parameter (step S30). At step S130, the grayscale data D(n-2) is converted based on the converted lookup table to generate final grayscale data D(n-2)'.

[0162] The β' value is a correction parameter determined according to the α value, and the degree of correction of the lookup table LUT is adjusted according to the magnitude of the α value. Various β' values ​​according to the α value can be stored in the memory of the display device. The β' value can be stored based on weights or by considering all grayscale data values ​​of each pixel PX to which grayscale data is input.

[0163] When the α value and the β′ value are determined as described above, the α value is replaced with α″ by a predetermined correction parameter β′, and the replacement of α″ can be performed according to Equation 3.

[0164] (Equation 3)

[0165] α"=|α|×β'

[0166] The replaced α″ value is used to convert the lookup table LUT by multiplying the value provided by the lookup table LUT by the α″ value.

[0167] exist Figure 5 At step S30 , the conversion is represented by |α|×β′LUT and can be simplified to α″×LUT. Since α of |α| can be a negative value, the absolute value sign is used, and when α is negative, |α| is the same as the −α value.

[0168] Based on the data of the lookup table after conversion as described above, the grayscale data D(n-2) is converted at step S130 to generate final grayscale data D(n-2)'.

[0169] In the above description, the value of α' is a value changed so that the corrected final grayscale data D(n-2)' cancels the voltage variation variable of ±X1 in Table 1. As a result, the gate voltage Vg at the moment of entering the B programming period is equal to Figure 4 The voltage represented in (VELVDD-Vth+K(VD(n-2)-VREF)).

[0170] Figure 5The case where the value of α is zero is also shown. In this case, at step S40, the value of α is converted to 1, and the value of β is also used as 1, so that the existing lookup table LUT is not changed. In other words, even when the values ​​of α and β are multiplied, there is no change even when the product value of 1 is multiplied by the value provided from the lookup table LUT. In other words, the final grayscale data D(n-2)' is generated by using the original lookup table LUT.

[0171] In other words, when Figure 5 When the value of α is 0, at step S40, the value of α is converted to 1, and the value of β is also used as 1, so that the lookup table LUT is not converted. Since the grayscale data D(n-2) is converted based on the unconverted lookup table LUT (step S140), the final grayscale data D(n-2)' can be substantially the same as the original grayscale data D(n-2).

[0172] Despite Figure 5 , it is described that the lookup table LUT is not changed only when the value of α is 0, but in an embodiment, the lookup table LUT may not be changed when the value of α is less than or equal to a predetermined level (for example, -1 or greater to 1 or less).

[0173] In the following, reference will be made to Figure 6 The operations converted into the final grayscale data D(n-1)' in the B programming period are described.

[0174] When with Figure 6 The grayscale data corresponding to the B programming period is D(n-1), and when D(n-1) is determined by the signal controller 100 according to the image signal ImS, D(n-1) is transmitted to the image data converter 110 (see Figure 8 ) Figure 6 The final grayscale data D(n-1)' is generated in the process shown in FIG.

[0175] The value of α is obtained by comparing VD(n-1) which is the voltage value of the transmitted grayscale data D(n-1) with the voltage value VREF of the node A (step S11). The value of α determines whether the voltage changes in the positive direction, in the negative direction, or there is no change.

[0176] The final grayscale data D(n-1)' may be generated by modifying the lookup table LUT or using a separate lookup table LUT, except when the value of α is 0.

[0177] When the value of α is greater than 0, the lookup table LUT is converted (step S21 ), the grayscale data D(n−1) is converted based on the converted lookup table (step S121 ), and thus final grayscale data D(n−1)′ is generated.

[0178] The method for converting the lookup table LUT uses a β value in addition to the already obtained α value. The β value is determined based on the α value and is a correction parameter. The degree of correction of the lookup table LUT is adjusted according to the magnitude of the α value. Various β values ​​based on the α value can be stored in the memory of the display device. The β value can be stored based on a weight or by considering all grayscale data values ​​of each pixel PX for which grayscale data is input.

[0179] When the α value and the β value are determined as described above, the α value is replaced with α′ by a predetermined correction parameter β, and the replacement of α′ may be performed according to Equation 2.

[0180] The replaced α′ value is used to convert the lookup table LUT by multiplying the value provided by the lookup table LUT by the α′ value.

[0181] Based on the data of the lookup table after conversion as described above, the grayscale data D(n-1) is converted at step S121 to generate final grayscale data D(n-1)'.

[0182] In the above description, the value of α' is a value changed so that the corrected final grayscale data D(n-1)' cancels the voltage variation variable of ±X2 in Table 1. As a result, the gate voltage Vg at the moment of entering the C programming period is equal to Figure 4 The voltage represented in (VELVDD-Vth+K(VD(n-1)-VREF)).

[0183] Hereinafter, the Figure 6 When α is less than 0.

[0184] When the α value is less than 0, the β value used when the α value is greater than 0 is not used, so the lookup table LUT is converted by using the β' value as another correction parameter (step S31). At step S131, the grayscale data D(n-1) is converted based on the converted lookup table to generate final grayscale data D(n-1)'.

[0185] The β' value is determined according to the α value and is a correction parameter. The degree of correction of the lookup table LUT is adjusted according to the magnitude of the α value, and various β' values ​​according to the α value can be stored in the memory of the display device. The β' value can be stored based on a weight or by considering all grayscale data values ​​of each pixel PX to which grayscale data is input.

[0186] When the α value and the β′ value are determined as described above, the α value is replaced with α″ by a predetermined correction parameter β′, and the replacement of α″ can be performed according to Equation 3.

[0187] The replaced α″ value is used to convert the lookup table LUT by multiplying the value provided by the lookup table LUT by the α″ value.

[0188] Based on the data of the lookup table after conversion as described above, the grayscale data D(n-1) is converted at step S131 to generate final grayscale data D(n-1)'.

[0189] In the above description, the value of α' is a value changed so that the corrected final grayscale data D(n-1)' cancels the voltage variation variable of ±X2 in Table 1. As a result, the gate voltage Vg at the moment of entering the C programming period is equal to Figure 4 The voltage represented in (VELVDD-Vth+K(VD(n-1)-VREF)).

[0190] Figure 6 The case where the value of α is zero is also shown. In this case, at step S41, the α value is converted to 1, and the β value is also used as 1, so that the existing lookup table LUT is not changed. That is, when Figure 6 When the value of α is 0, at step S41, the value of α is converted to 1, and the value of β is also used as 1, so that the lookup table LUT is not converted. Since the grayscale data D(n-1) is converted based on the unconverted lookup table LUT (step S141), the final grayscale data D(n-1)' can be substantially the same as the original grayscale data D(n-1).

[0191] although Figure 6 It is illustrated that the lookup table LUT is not changed only when the value of α is 0, but in an embodiment, the lookup table LUT may not be changed when the value of α is less than or equal to a predetermined level (eg, -1 or greater to 1 or less).

[0192] In the following, reference will be made to Figure 7 The operations converted into the final grayscale data D(n)' in the C programming period are described.

[0193] When with Figure 7 The grayscale data corresponding to the C programming period is D(n), and when D(n) is determined by the signal controller 100 according to the image signal ImS, D(n) is transmitted to the image data converter 110 (see Figure 8 ) Figure 7 The final grayscale data D(n)' is generated in the process shown in FIG.

[0194] The value of α is obtained by comparing VD(n), which is the voltage value of the transmitted grayscale data D(n), with the voltage value VD(n-1) of the node A (step S12). The value of α determines whether the voltage changes in the positive direction, in the negative direction, or there is no change.

[0195] The final grayscale data D(n-1)' may be generated by modifying the lookup table LUT or using a separate lookup table LUT, except when the value of α is 0.

[0196] exist Figure 7 When the value of α is greater than 0, the lookup table LUT is converted (step S22 ), and the grayscale data D(n) is converted based on the converted lookup table (step S122 ), thereby generating final grayscale data D(n)′.

[0197] The method for converting the lookup table LUT uses a β value in addition to the already obtained α value. The β value is determined based on the α value and is a correction parameter. The degree of correction of the lookup table LUT is adjusted according to the magnitude of the α value. Various β values ​​based on the α value can be stored in the memory of the display device. The β value can be stored based on a weight or by considering all grayscale data values ​​of each pixel PX for which grayscale data is input.

[0198] When the α value and the β value are determined as described above, the α value is replaced with α′ by a predetermined correction parameter β, and the replacement of α′ can be performed according to Equation 2.

[0199] The replaced α' value is used to convert the lookup table LUT by multiplying the value provided by the lookup table LUT by the α' value.

[0200] Based on the data of the lookup table after conversion as described above, the grayscale data D(n) is converted at step S122 to generate final grayscale data D(n)′.

[0201] In the above description, the value of α' is a value changed so that the corrected final grayscale data D(n)' cancels the voltage variation variable of ±X3 in Table 1. As a result, the gate voltage Vg at the end of the C programming period is equal to Figure 4 The voltage represented in (VELVDD-Vth+K(VD(n)-VREF)).

[0202] Hereinafter, the Figure 7 When α is less than 0.

[0203] When the α value is less than 0, the β value used when the α value is greater than 0 is not used, so the lookup table LUT is converted by using the β' value as another correction parameter (step S32). At step S132, the grayscale data D(n) is converted based on the converted lookup table to generate final grayscale data D(n)'.

[0204] The β' value is determined based on the α value and is a correction parameter. The degree of correction of the lookup table LUT is adjusted according to the magnitude of the α value. Various β' values ​​based on the α value can be stored in the memory of the display device. The β' value can be stored based on a weight or by considering all grayscale data values ​​of each pixel PX to which grayscale data is input.

[0205] When the α value and the β′ value are determined as described above, the α value is replaced with α″ by a predetermined correction parameter β′, and the replacement of α″ can be performed according to Equation 3.

[0206] The replaced α″ value is used to convert the lookup table LUT by multiplying the value provided by the lookup table LUT by the α″ value.

[0207] Based on the data of the lookup table after conversion as described above, the grayscale data D(n) is converted at step S132 to generate final grayscale data D(n)′.

[0208] In the above description, the value of α' is a value changed so that the corrected final grayscale data D(n)' cancels the voltage variation variable of ±X3 in Table 1. As a result, the gate voltage Vg at the end of the C programming period is equal to Figure 4 The voltage represented in (VELVDD-Vth+K(VD(n)-VREF)).

[0209] Figure 7 The case where the value of α is zero is also shown. In this case, at step S42, the value of α is converted to 1, and the value of β is also used as 1, so that the existing lookup table LUT is not changed. That is, when the value of α is 0, at step S42, the value of α is converted to 1, and the value of β is also used as 1, so that the lookup table LUT is not converted. Since the grayscale data D(n) is converted based on the unconverted lookup table LUT (step S142), the final grayscale data D(n)' can be substantially the same as the original grayscale data D(n).

[0210] Despite Figure 7 , the lookup table LUT is illustrated as not being changed only when the value of α is 0, but in an embodiment, the lookup table LUT may not be changed when the value of α is less than or equal to a predetermined level (eg, -1 or greater to 1 or less).

[0211] Reference above Figures 5 to 7 The described methods can be integrated and summarized as follows.

[0212] An absolute change amount (|α|) according to a difference between nth grayscale data and (n-1)th grayscale data among grayscale data output along one data line is calculated.

[0213] Regarding the calculated absolute amount of change (|α|), the characteristics of the display section 600 and a plurality of optimum correction parameters (β and β′) for each display device used are stored.

[0214] An appropriate correction parameter among the stored correction parameters (β and β′) is selected based on the calculated absolute change amount (|α|).

[0215] The α value is then replaced by the α' or α" value depending on the selected correction parameter (β or β').

[0216] The lookup table LUT is converted based on the replaced values ​​α′ and α″, and in the present embodiment, the conversion is performed by multiplying the replaced values ​​α′ and α″ by the values ​​of the lookup table LUT.

[0217] By using the final lookup table LUT after the conversion, the output value of the n-th grayscale data is changed. The changed n-th grayscale data has a grayscale data value that can compensate for the leakage characteristics of the transistor in the pixel PX.

[0218] In the above, it is described that the lookup table LUT is not changed when there is no difference between the nth grayscale data and the (n-1)th grayscale data, but may not be changed even if the difference is equal to or greater than a predetermined level.

[0219] exist Figures 5 to 7 In an embodiment, the final grayscale data is converted by converting a previously stored lookup table LUT.

[0220] However, in an embodiment, different lookup tables LUTs may be stored according to α values ​​and / or β and β′ values, and the final grayscale data D(n−2)′ may be generated based on the different lookup tables LUTs.

[0221] In the above embodiment, the lookup table LUT may include a table for compensating the driving transistor ( Figure 2 A first lookup table (also referred to as a lookup table for threshold voltage compensation) is used to calculate the characteristics of the second transistor T1 of the pixel PX and a second lookup table (also referred to as a lookup table for leakage current compensation) is used to compensate for the leakage current of the second transistor T2 transmitting the data voltage to the pixel PX.

[0222] In an embodiment, the second lookup table may be configured to compensate for characteristics of other elements included in the pixel PX.

[0223] In an embodiment, the first lookup table and the second lookup table may be formed as only one lookup table. In this case, the values ​​stored in one lookup table are values ​​stored based on the information to be compensated in the first lookup table and the second lookup table.

[0224] In the following, reference will be made to Figure 8 The structure of the image data converter 110 included in the signal controller 100 is described.

[0225] Figure 8 A block diagram of an image data converter in a signal controller is shown.

[0226] The image data converter 110 is formed in the signal controller 100 , and the final grayscale data converted by the image data converter 110 is reset to be transmitted to the data driver 300 .

[0227] The image data converter 110 includes a memory such as a line memory that stores grayscale data. Figure 8 , the boxes surrounding the grayscale data (D(n-2), D(n-1), D(n), D(n-2)', D(n-1)', and D(n)' schematically illustrate a memory storing the corresponding grayscale data. In addition, the value of the reference voltage VREF is also stored in the memory.

[0228] refer to Figure 8 , three grayscale data (D(n-2), D(n-1), D(n)) to be programmed (written) to one pixel PX during the programming period are sequentially allocated and stored in the memory.

[0229] Starting from D(n-2), PDC processing is performed on the corresponding stored grayscale data in sequence.

[0230] First, the grayscale data D(n-2) is subjected to PDC processing by using the lookup table LUT3 and the reference voltage VREF (see Figure 5 ) to generate final grayscale data D(n-2)' and store it in the memory. The final grayscale data D(n-2)' stored in the memory is grayscale data to be output to the data driver 300, and the grayscale data is used for the PDC processing of D(n-1).

[0231] By using the final grayscale data D(n-2)' and the lookup table LUT2 to perform PDC processing on the grayscale data D(n-1) (such as Figure 6 ), to generate final grayscale data D(n-1)' and store the final grayscale data D(n-1)' in the memory. The final grayscale data D(n-1)' stored in the memory is grayscale data to be output to the data driver 300, and the grayscale data is used for PDC processing of D(n).

[0232] By using the final grayscale data D(n-1)' and the lookup table LUT1 to perform PDC processing on the grayscale data D(n) (such as Figure 7 ), to generate final grayscale data D(n)′ and store it in the memory. The final grayscale data D(n)′ stored in the memory is grayscale data to be output to the data driver 300.

[0233] The plurality of final grayscale data (D(n−2)′, D(n−1)′, and D(n)′) are rearranged together with other grayscale data, bundled into the image data signal DAT, and transmitted to the data driver 300 .

[0234] exist Figure 8, the 1H interval is shown together with the scan signal SCAN applied to the first scan line SLn so that the time when each PDC operation is transmitted from the data driver 300 to the display portion 600 can be known. This may be different from the time when the PDC operation is actually performed in the image data converter 110.

[0235] Can be changed by Figures 5 to 7 The lookup table shown in uses Figure 8 There are three lookup tables LUT1, LUT2 and LUT3 shown in FIG, and these lookup tables can store different lookup tables in the memory accordingly.

[0236] That is, based on the difference between the reference voltage VREF and the voltage of the input grayscale data D(n-2), the grayscale data D(n-2) can be changed to the final grayscale data D(n-2)' by using LUT3 as the optimized lookup table. In addition, based on the difference between the voltage of the grayscale data D(n-2) and the voltage of the input grayscale data D(n-1), the grayscale data D(n-1) can be changed to the final grayscale data D(n-1)' by using LUT2 as the optimized lookup table. Based on the difference between the voltage of the grayscale data D(n-1) and the voltage of the input grayscale data D(n), D(n) can be changed to the final grayscale data D(n)' by using LUT1 as the optimized lookup table.

[0237] refer to Figures 4 to 8 When the leakage of the second transistor T2 is greater than or equal to a predetermined level, the grayscale data may need to be corrected to the final grayscale data by compensation based on the leakage consideration, as shown in FIG. Figures 5 to 8 However, although PDC correction may be performed in all programming periods, PDC correction may be performed only in some of the programming periods.

[0238] In this way, Figure 9 An embodiment in which PDC correction may be selectively applied only in some of the programming periods is illustrated in FIG.

[0239] Figure 9 A table illustrating whether an image data converter is operated according to various embodiments is shown.

[0240] Figure 9 The table shows that the PDC correction may be selectively applied to some of the A programming period, the B programming period, and the C programming period.

[0241] Even if the final grayscale data is generated by PDC correction in the A programming period, when the brightness difference displayed by the light emitting diode LED is small in the actual light emitting period, PDC correction may not be applied to the A programming period. Figure 9 The third row from the bottom illustrates this situation.

[0242] In this way, even if the PDC correction is not performed, when the brightness change displayed by the light emitting diode LED is not recognized, the PDC correction may not be performed.

[0243] In some embodiments, PDC correction may not be performed in all pixels PX included in the display portion 600, but may be performed only in pixels PX included in the display portion 600. Figure 10 PDC correction is performed in some of the pixels PX shown in .

[0244] Figure 10 Schematic diagrams illustrating areas for converting image data in a display device according to various embodiments.

[0245] exist Figure 10 , rows for performing PDC correction in the display portion 600 according to the embodiment are denoted by reference numerals 610 , 611 , and 612 , respectively.

[0246] That is, the embodiment corresponding to reference numeral 610 is a case where PDC correction is performed on all rows of pixels PX included in the display section 600. In this case, Figure 9 As shown in , PDC correction can be performed only in part of the programming period.

[0247] The embodiments corresponding to reference numerals 611 and 612 are cases where PDC correction is performed on pixels PX included in some of the rows of the display portion 600. The embodiment of reference numeral 611 is a case where PDC correction is performed only from the first row to a predetermined number of pixel rows, and the embodiment of reference numeral 612 is a case where PDC correction is performed only from the middle pixel row to a predetermined number of pixel rows. In this case, as Figure 9 As shown in , PDC correction can be performed only in part of the programming period.

[0248] As described above, even if a specific PDC correction is not performed in the corresponding pixel PX, since the brightness of the displayed light emitting diode LED is not changed, the PDC correction may not be performed.

[0249] When magnified Figure 9 and Figure 10 In the embodiment of the present invention, even when the corresponding pixel row is selected for PDC correction, some of the pixels PX included in the pixel row are not subjected to PDC correction. This is because PDC correction can be selectively performed, so that all PDC correction for a specific pixel PX can be excluded.

[0250] Figure 11 An equivalent circuit diagram of one pixel of an organic light emitting diode display device according to an embodiment is illustrated, and Figure 12 The diagram shows the application Figure 11 The waveform diagram of the pixel signal.

[0251] exist Figure 11 In the embodiment of the present invention, the scan line connected to the gate electrode of the seventh transistor T7 is not the fourth scan line SLBn+1, but the third scan line SLBn. Since the third scan line SLBn is the scan line connected to the gate electrode of the fourth transistor T4, the fourth transistor T4 and the seventh transistor T7 receive the same scan signal.

[0252] Therefore, in Figure 12 In the embodiment, the waveform applied to the fourth scan line SLBn+1 is eliminated.

[0253] In the pixel PX, the timing of initializing the anode electrode of the light emitting diode LED to the initialization voltage Vint through the seventh transistor T7 is the same as the timing of initializing the gate electrode of the driving transistor T1 to the initialization voltage Vint through the fourth transistor T4.

[0254] The remaining operations are the same as Figure 2 and Figure 3 The other operations are the same, and Figures 4 to 10 All embodiments can be applied according to Figure 11 and Figure 12 Pixel PX of the embodiment.

[0255] At the same time, Figure 3 and Figure 12 In the waveform diagram of FIG. 1 , the gate-on voltages applied to the first scan line SLn, the second scan line SLIn, and the third scan line SLBn may overlap with each other.

[0256] To illustrate this point, we will describe Figure 11 The structure of the pixel PX has the following Figure 13 An embodiment of the time periods overlapping each other shown in .

[0257] Figure 13 The diagram shows the application Figure 2 or Figure 11 The waveform diagram of the pixel signal.

[0258] exist Figure 13 In an embodiment of the present invention, the initialization period and the Vth compensation period overlap with each other by approximately 1H, and the Vth compensation period and the programming period overlap with each other by 1H.

[0259] The overlapping portions of the respective periods will now be described.

[0260] First, the operation of the pixel PX in the period in which the initialization period and the Vth compensation period overlap is as follows.

[0261] When the initialization period and the Vth compensation period are Figure 11 When the first and second electrodes of the second capacitor C2 overlap with each other in the pixel PX, the first and second electrodes of the second capacitor C2 are fixed to the initialization voltage Vint and the reference voltage VREF, respectively. Therefore, the operation in the Vth compensation period does not usually continue, wherein the operation corresponds to the following operation: when the reference voltage VREF is applied to the second electrode of the second capacitor C2, the voltage of the first electrode of the second capacitor C2 is changed according to Equation 1, and thus the driving transistor T1 generates an output current, and while being transmitted to the first electrode of the second capacitor C2 after passing through the third transistor T3, the voltage of the gate electrode of the driving transistor T1 is changed to VELVDD-Vth reflecting the threshold voltage Vth. The initialization voltage Vint becomes the voltage of the first electrode of the second capacitor C2.

[0262] As described above, although the Vth compensation operation is not performed, Figure 13 As shown in , since there is a Vth compensation period that does not overlap with the initialization period, the Vth compensation operation is performed. That is, since the Vth compensation period does not overlap with another period by 1H or more, the Vth compensation operation is performed during the corresponding period, so that there is no problem with the display quality in the pixel PX.

[0263] At the same time, reference will be made Figure 14 The operation of the pixel PX in a period in which the Vth compensation period and the programming period overlap with each other is described.

[0264] Figure 14 The diagram shows Figure 13 A table summarizing the voltage changes in each programming period is provided in the embodiment of FIG.

[0265] exist Figure 14 , a period in which the programming period overlaps with the Vth compensation period is represented as an A′ programming period.

[0266] In the A' programming period, the data voltage VD(n-2) is applied from the data line to be transmitted to the second electrode of the second capacitor C2, but since the reference voltage VREF is applied to the second electrode of the second capacitor C2, the reference voltage VREF can be maintained. As a result, the voltage of the second electrode of the second capacitor C2 does not change, and therefore, it will be difficult to see that the data voltage is written.

[0267] However, during the B programming period and the C programming period, the data voltages VD(n-1) and VD(n) are applied, and Figures 6 to 8 The PDC compensation represented in can be applied so that the light emitting diode LED can display accurate brightness during the light emitting period.

[0268] That is, reference Figure 14The gate voltage Vg changes even in the B programming period. Figure 4 The gate voltage Vg varies with the value of the gate voltage. Figure 14 The gate voltage Vg changes with the Figure 4 The gate voltage Vg in K(VD(n-1)-VD(n-2)) is different from K(VD(n-1)-VREF). However, it can be seen that in Figure 4 and Figure 14 The gate voltage Vg in the programming period B is VELVDD-Vth+K(VD(n-1)-VREF), which is the same voltage.

[0269] Therefore, despite Figure 13 As in the embodiment of the present invention, there is an overlapping programming period A', since the gate voltage Vg in the B programming period has the same voltage as the embodiment of the present invention having a non-overlapping A programming period ( Figure 3 The gate voltage Vg of each of the LEDs is the same voltage, so the light emitting diodes LED can display the same brightness. Therefore, there is no display quality problem.

[0270] Figures 6 to 8 PDC compensation as described in Figure 9 and Figure 10 The PDC compensation embodiments described in the present invention can also be applied to Figure 13 Example of .

[0271] In addition, waveforms having periods overlapping each other may be applied to Figure 2 The pixel PX can have the same effect.

[0272] In the following, reference will be made to Figures 15 to 17 Description applied to have Figure 11 Another waveform of the structure of the pixel PX.

[0273] Figures 15 to 17 The diagram shows the application Figure 2 or Figure 11 The waveform diagram of the pixel signal.

[0274] Figure 15 The waveform of is spaced about 1H between periods. Therefore, the initialization period, the Vth compensation period, and the programming period operate independently, and therefore, these periods are Figure 2 and Figure 11 The same operation is performed in .

[0275] In addition, if Figure 16 As shown in the waveform of , one period may not last for 3 hours, and may only last for 2 hours. In this case, the initialization operation, the Vth compensation operation, and the programming (writing) operation must all be completed within 2 hours.

[0276] Meanwhile, in an embodiment, each period may last for 4 hours, such as Figure 17 As shown in . In this case, for high-speed drive or high-resolution display, even if 3H is used alone, the initialization operation, Vth compensation operation, and programming operation may not be sufficient. The time that one period can have should be 1H or greater, and there is no upper limit on the period. However, since the time of one frame is shared, it actually has a limited time.

[0277] according to Figure 3 、 Figure 12 、 Figure 13 、 Figure 15 、 Figure 16 and Figure 17 , the rising edge and falling edge of the signal are slightly different from the line between the adjacent 1H. The difference between the edge and the line between the adjacent 1H can mean a margin that does not cross the line between the adjacent 1H.

[0278] In addition, in an embodiment, some periods may be performed for 2 H or 4 H, and other periods may be performed for 3 H. If the Vth compensation period requires the longest time, only the Vth compensation period may be extended, and other periods may be shorter than the Vth compensation period.

[0279] Therefore, various embodiments that can be modified can be realized.

[0280] above Figures 15 to 17 The description can also be applied to Figure 2 The pixel PX can provide the same effect.

[0281] While the present disclosure has been described with respect to what are presently considered to be practical example embodiments, it is to be understood that the inventive concept is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, comprising: light-emitting diodes; a drive transistor configured to supply current to the light emitting diode; a switching transistor having an input electrode connected to the data line; a voltage transfer capacitor disposed between the output electrode of the switching transistor and the gate electrode of the driving transistor; as well as a current transfer transistor having an output electrode connected to the light emitting diode and an input electrode connected to the output electrode of the driving transistor, wherein a data voltage applied to the data line is transferred to the gate electrode of the driving transistor through the voltage transfer capacitor, wherein the data voltage is a compensated data voltage having a data voltage value from which a voltage variation variable based on leakage of the switching transistor is removed, wherein the voltage variation variable represents a voltage variation based on leakage of the switching transistor, wherein the compensated data voltage is a voltage compensated based on a parasitic capacitance of a first electrode of two electrodes of the voltage transfer capacitor, the first electrode being connected to the gate electrode of the driving transistor, and When the current transfer transistor is turned off, the compensated data voltage is transferred to the gate electrode of the driving transistor through the voltage transfer capacitor.

2. The display device according to claim 1, wherein The compensated data voltage is compensated based on magnitudes of the data voltage before and after being applied to one data line.

3. The display device according to claim 2, wherein Each of the plurality of pixels includes the light emitting diode, the driving transistor, the switching transistor, and the voltage transfer capacitor, and The display device comprises: a display portion formed with the plurality of pixels and including scan lines and data lines; a data driver connected to the data line; a scan driver connected to the scan lines; and A signal controller configured to control the data driver and the scan driver.

4. The display device according to claim 3, wherein The signal controller includes a lookup table, and The values ​​stored in the lookup table are based on leakage of the switching transistor.

5. The display device according to claim 4, wherein The plurality of pixels are configured to have an initialization period, a threshold voltage compensation period, and a programming period, and the threshold voltage compensation period and the programming period do not overlap. The display device according to claim 5 , wherein: The signal controller further includes an image data converter, and the image data converter is configured to generate final grayscale data by using the continuous grayscale data input to one pixel in the programming period and the lookup table.

7. The display device according to claim 1, wherein A second electrode, which is the other electrode among the two electrodes of the voltage transfer capacitor, is connected to the switching transistor through a first node, and the first node is configured to have a reference voltage before the switching transistor is turned on.

8. The display device according to claim 7, wherein The compensated data voltage is applied so that the voltage of the gate electrode of the driving transistor is VELVDD-Vth+K(VD(n)-VREF), where VELVDD is the voltage value of the first power supply voltage, Vth is the threshold voltage value of the driving transistor, K is [C2 / (C2+Cp)], C2 is the capacitance of the voltage transfer capacitor, Cp is the parasitic capacitance of the first electrode adjacent to the voltage transfer capacitor, VD(n) is the voltage value of D(n) as the currently applied grayscale data, and VREF is the reference voltage value.

9. The display device according to claim 8, wherein The input electrode of the driving transistor is connected to the first power supply voltage, and A holding capacitor is arranged between the first power supply voltage and the first node.

10. The display device according to claim 9, further comprising: The compensation transistor has an input electrode connected to the output electrode of the driving transistor and an output electrode connected to the first node.

11. The display device according to claim 10, further comprising: a gate initialization transistor configured to initialize a voltage of the gate electrode of the driving transistor; as well as The first node initialization transistor is configured to initialize the voltage of the first node to the reference voltage.

12. The display device according to claim 11, further comprising: The anode initialization transistor is configured to initialize an anode electrode serving as one electrode of the light emitting diode.

13. A method for driving a display device, wherein the display device includes a light emitting diode, a driving transistor, a switching transistor provided with an input electrode connected to a data line, and a first capacitor arranged between an output electrode of the switching transistor and a gate electrode of the driving transistor, the driving method comprising: obtaining a value of α that is a difference between adjacent previous data voltages and a current data voltage to be applied to one data line; determining a lookup table capable of removing voltage variation variables caused by leakage of the switching transistor based on the obtained α value; as well as changing the grayscale data corresponding to the current data voltage based on the lookup table to generate final grayscale data, Wherein, determining the lookup table includes: determining whether the voltage changes in a positive direction or a negative direction or does not change based on the value of α, and The lookup table is changed except when the value of α is zero.

14. The method for driving a display device according to claim 13, wherein: The final grayscale data is compensated based on a parasitic capacitance of a first electrode of the first capacitor connected to the gate electrode of the driving transistor.

15. The method for driving a display device according to claim 13, wherein: Changing the lookup table includes: determining a correction parameter based on the value of α; replacing the value of α based on the correction parameter; and The conversion is performed by multiplying the value replaced from the value of α by the value stored in the lookup table.

16. The method for driving a display device according to claim 15, wherein: The correction parameter is a value determined based on the value of α or a value determined based on a weight.

17. The method for driving a display device according to claim 16, wherein: The voltage of the gate electrode of the driving transistor obtained by the final grayscale data is VELVDD-Vth+K(VD(n)-VREF), where VELVDD is the voltage value of the first power supply voltage, Vth is the threshold voltage value of the driving transistor, K is [C2 / (C2+Cp)], C2 is the capacitance of the first capacitor, Cp is the parasitic capacitance of the first electrode adjacent to the first capacitor, VD(n) is the voltage value of D(n) as the currently applied grayscale data, and VREF is the voltage of the first node connecting the first capacitor and the switching transistor before the switching transistor is turned on.

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