Apparatus and method for capturing register state

Abstract

The present disclosure relates to apparatuses and methods of capturing register state. Some aspects of the present disclosure relate to an apparatus comprising a register circuit implementing a plurality of registers, and a processing circuit to perform data processing operations on data stored in the registers. The apparatus comprises a store buffer circuit to temporarily store given data prior to providing the given data to a memory in response to a store instruction on the given data. In response to receiving a request at the processing circuit to perform a state save trigger operation, the register circuit is configured to capture a state of a subset of registers of the plurality of registers in shadow registers of the register circuit, and to provide the captured state from the shadow registers to the memory.

Description

TECHNICAL FIELD

[0001] The present technology relates to the field of processing apparatuses. BACKGROUND

[0002] Some processing apparatuses have a set of registers that are accessible to execution circuitry for storing data that is undergoing processing operations. In some circumstances, such as when an interrupt is executed, the contents of these registers can be stored in a storage device such as a memory. The delay associated with performing this storage can cause a bottleneck in processing capacity. SUMMARY

[0003] At least some examples provide an apparatus comprising:

[0004] register circuitry to implement a plurality of registers;

[0005] processing circuitry to perform data processing operations on data stored in the registers;

[0006] storage buffer circuitry to temporarily store given data prior to providing the given data to a memory in response to a store instruction in respect of the given data;

[0007] wherein, in response to receiving a request at the processing circuitry to perform a state save trigger operation, the register circuitry is configured to:

[0008] capture a state of a subset of the plurality of registers in shadow registers of the register circuitry; and

[0009] provide the captured state from the shadow registers to the memory.

[0010] Further examples provide an apparatus comprising:

[0011] register means to implement a plurality of registers;

[0012] processing means to perform data processing operations on data stored in the registers;

[0013] storage buffer means to temporarily store given data prior to providing the given data to a memory in response to a store instruction in respect of the given data;

[0014] wherein, in response to receiving a request at the processing means to perform a state save trigger operation, the register means is configured to:

[0015] capture a state of a subset of the plurality of registers in shadow registers of the register means; and

[0016] provide the captured state from the shadow registers to the memory.

[0017] A further example provides a method comprising:

[0018] storing data in registers associated with the processing circuitry;

[0019] receiving a request to perform a state save trigger operation in respect of given data of the data; and

[0020] in response to the request:

[0021] capturing a state of a subset of the registers in shadow registers corresponding to the registers; and

[0022] providing the captured state from the shadow registers to memory.

[0023] Further aspects, features and advantages of the technology will be apparent from the following description of examples, which is to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 A processing apparatus according to an example is schematically depicted.

[0025] Figure 2A and Figure 2B Differences between processing of a state save trigger operation in a system according to the present disclosure and a comparative system not implementing the present disclosure are illustrated.

[0026] Figure 3 A method for processing operations according to an example is shown.

[0027] Figure 4 A method for mitigating data risk associated with memory requests according to an example is shown. DETAILED DESCRIPTION

[0028] As described above, a processing apparatus can comprise register circuitry to implement a plurality of registers, and processing circuitry to perform data processing operations on data stored in the registers. This data can be fetched from memory to be stored in the registers when required for processing operations.

[0029] The apparatus comprises a store buffer circuit to temporarily store given data prior to providing said given data to memory in response to a store instruction in respect of the given data (e.g. if the given data is at least temporarily no longer required for processing operations or a register storing the given data needs to store other data). This data is stored in the store buffer together with an associated memory address to which it is to be stored. The delay associated with providing given data to the store buffer is lower than the delay associated with storing given data in memory. The data to be stored can thereby be provided relatively quickly to the store buffer, after which processing operations continue whilst the relatively slower process of storing the data in memory is performed in parallel.

[0030] When data to be stored has been provided to the store buffer, but before it is actually stored in memory, the version of that data in memory will potentially be incorrect if it was modified when stored in a register. Load operations are therefore checked against the store buffer so that if the data to be loaded is in the store buffer, these load operations can be serviced from the store buffer rather than memory. To improve cost and processing efficiency, the store buffer in some systems has a lower number of entries than the number of registers. This causes a processing bottleneck if data is to be stored from a larger number of registers at approximately the same time, e.g. when performing a state save operation to store the state of a set of registers, e.g. in response to receiving an interrupt signal.

[0031] Increasing the size of the store buffer to reduce this bottleneck would incur a cost in terms of physical resources (increased circuit area and power consumption due to larger circuitry required due to the increased number of store buffer entries against which each load operation is to be checked).

[0032] To alleviate this, a shadow register is provided. In response to receiving a request to perform a state save trigger operation such as an interrupt, the register circuitry is configured to capture the state of a subset of the registers in a plurality of registers in a shadow register. The register circuitry then provides the captured state from the shadow register to memory. This provision can be via a direct path from the shadow register to memory. Alternatively, the shadow register can be enqueued in existing store buffer storage. The captured state can thereby be stored without incurring the bottleneck described above, and also without increasing the size of the store buffer. Although the provision of the shadow register does use additional resources, examples are provided below by which the impact of this can be reduced relative to a comparative system which instead scales up the store buffer. If the captured state (i.e. the stack) is defined as non-shared memory, it can be possible to omit storing the shadow register contents in memory without detecting a risk.

[0033] The apparatus can be configured to restore the captured state in the registers after performing the state save trigger operation. Restoring the captured state can comprise restoring the captured state from the shadow registers in response to determining that there is no overwrite to the shadow registers. This can be more efficient in terms of processing resource usage compared to restoring the captured state from the memory.

[0034] In an example, the processing circuitry is configured to initiate performance of the requested state save trigger operation before completing the provision of the captured state from the register circuitry to the memory. The state save trigger operation (e.g. starting execution of an interrupt handler) can thereby be performed in parallel with storing the captured state in the memory, thereby improving processing capacity.

[0035] In an example, the state of the subset of the registers comprises copying contents of the subset of the registers to shadow registers. For example, each shadow register can correspond to one of the subset of the registers, and the state of a given register of the subset of the registers can comprise storing contents of the given register in a corresponding shadow register. The (non-shadow) registers can then be available for more data (associated with the state save trigger operation).

[0036] Alternatively, the state of the subset of the registers can comprise updating mapping information identifying which of the plurality of registers are shadow registers. For example, at a given time, a first group of registers can be identified as active non-shadow registers, and a second group can be identified as shadow registers. To capture the state, the mapping information (e.g. a single bit flag) can be updated so that the first group is identified as shadow registers, and the second group is identified as active non-shadow registers for performing the state save trigger operation. The state can thereby be efficiently saved without the need to perform multiple copy operations. Thus, in some examples, rather than providing a dedicated set of shadow registers, a single set of registers can be variably divided into active non-shadow registers and shadow registers - there need not be a fixed allocation of shadow registers.

[0037] In one example, the processing circuitry performs a risk check in response to receiving a memory access request to detect whether the memory access request causes a data risk condition. A data risk condition occurs at least when a memory access request has a possibility of accessing a memory address to which data from one of the shadow registers will still be saved to memory before the captured state is provided to memory. It is not necessary for the risk check to determine whether the memory access request will actually access a memory address of memory to which data from a shadow register will still be saved - a memory access request that has a possibility of accessing such a memory address can be determined to be risky even if it will not actually access such a memory address. In contrast to a store buffer (in which a memory address can be stored for each entry thereof), a simpler and hence faster and / or more efficient query function can be provided for the shadow registers. Thus, using shadow registers to stack register state instead of a store buffer gives the opportunity to use a simpler, less expensive risk scheme to save circuit area and power compared to what would be provided by a store buffer to cope with general load / store hazards.

[0038] A consequence of the above simpler risk check is that the risk check can allow false positive detection of data risk conditions. This probability of false positive detection of data risk conditions can be higher for a risk check performed for shadow registers than for a risk check performed for a store buffer, for example where a given data risk is detected for an entire shadow register rather than for individual memory addresses, or where any stack pointer relative load is considered to be risky if there is still register state to be saved from the shadow register to memory. Implementing shadow registers in this way, such that the probability of false positive detection is higher than for a store buffer, allows the shadow registers to be implemented with simpler circuitry than a store buffer.

[0039] Despite the increased probability of false positives, the actual incidence of false positives is reduced when the state save trigger operation is unlikely to require data stored in a register at the time a request to perform this operation is received. For example, in the case of an interrupt, it is unlikely that an interrupt will coincidentally require data that the processing circuitry happens to be performing processing operations on at the time the interrupt is received, since the operations performed by an interrupt handler tend to be independent of the operations performed before the interrupt occurred. The incidence of false positives can thus be relatively low, such that processing performance is not significantly reduced. Thus, by removing the additional comparison circuitry that would be required to implement a risk check scheme that would avoid such false positives, power and circuit area can be reduced, however this can not significantly impact performance.

[0040] In one example, capturing the state of the subset of registers comprises storing an indication of a stack frame address range to which data from the subset of registers is to be saved to memory. For example, the indication of the stack frame address range can comprise a base address of the stack frame address range and an indication of a span of the stack frame address range. This provides an efficient way of identifying the memory addresses associated with the registers to be captured without requiring a memory address to be stored for each register. This allows the use of simpler (and hence more efficient as described above) hazard circuitry for the shadow registers than for the store buffer (which in a typical implementation can be where each entry stores a memory address) as it is not necessary to compare the address of an incoming load against the address associated with the data in each individual shadow register. Instead, a load specifying an address falling within the stack frame address range can be considered to satisfy the data hazard condition when there is at least one shadow register for which state has not yet been stored to memory (even if the load in fact specifies an address for which state from the relevant shadow register has already been saved to memory).

[0041] Indicating the stack frame address range by a base address and an indication of a span can be compatible with similar MPU checks which in some examples are performed on all loads / stores. In such examples, the number of comparators in the MPU can be increased by 1 (a relatively small proportionate increase) to cater for the additional hazard performed here. Furthermore, in examples where multiple sets of shadow registers are provided (for example to cater for multiple levels of interrupt nesting), a single MPU region can be extended for the hazard.

[0042] In one example, prior to completing the provision of the captured state to memory and in response to receiving a data processing request indicating a memory address within the stack frame address range, the processing circuitry is configured to perform a data hazard mitigation action for the received data processing request. The data hazard mitigation action can be performed in response to a determination of a data hazard as described above, for example a request to load data from a memory address within the stack frame address range described above. The data hazard mitigation action can comprise delaying processing of the received data processing request until the captured state has been stored in memory. Whilst this does delay processing of the particular data processing request, as described above, data processing requests following a state saving trigger operation such as an interrupt can be relatively unlikely to require data stored coincidentally in the register prior to the state saving trigger operation. The increased efficiency associated with not storing individual memory addresses for each shadow register and not performing hazard comparisons against individual memory addresses can therefore outweigh the delay associated with data hazard mitigation for data processing data processing requests for data in process of being stored from the shadow registers.

[0043] In one example, prior to completing the provision of the captured state to memory, and in response to receiving a stack pointer relative memory access request for which a target memory address is to be determined relative to the stack pointer, the processing circuitry is configured to perform a data risk mitigation action for the received data processing request. For example, the processing circuitry can be configured to determine whether a data risk mitigation action is to be performed for stack pointer relative memory access requests that are independent of the target memory address. This provides an even simpler hazard scheme that avoids the need for any address comparison between the address of the load and the address to which the state from the shadow register is to be stored. In this scheme, during the period in which the state has been captured in the shadow register but the saving of this state to memory has not yet been completed, any stack pointer relative memory access request can be considered to involve a data risk condition, regardless of the actual address accessed by the stack pointer relative memory access request. In practice, interrupt handlers do not tend to include stack pointer relative loads, so it is relatively unlikely that such a stack pointer relative memory access request will occur during the period between capturing the state in the shadow register and completing the saving of this state to memory. Thus, by using a hazard scheme that considers all stack pointer relative requests to be hazardous without comparing the addresses, this greatly reduces the amount of circuitry required for the risk check without significantly impacting performance.

[0044] As noted above, the state save trigger operation can be an interrupt operation. As other examples, the state save trigger operation can be an exception operation or a function call operation. All of these examples can trigger the saving of a register state that will be restored once the operation has completed execution. For example, the function call operation can be a function call operation that includes a transition from a high security operation state to a lower security operation state. In this example, the registers can contain secure data when a request to perform the function call operation is received. By preventing access to the secure data while operating in the lower security state, performing the state save can thus provide improved security.

[0045] It is not necessary for all registers to be captured in the shadow registers in response to the state save trigger operation. In some examples, only a subset of the registers can need to be saved at the time of an interrupt, exception, or function call. In some cases, the number of registers that need to be saved can depend on the specific type of transition that is being made (e.g., based on the operating state of the processing circuitry prior to and / or after the state save trigger operation).

[0046] Examples of the present disclosure will now be described with reference to the accompanying drawings.

[0047] Figure 1A processing apparatus 100 implementing a processing pipeline is schematically depicted according to an example. The apparatus 100 comprises a series of stages, each stage being implemented by circuitry. It will be appreciated that this is an example, and that other implementations can comprise additional or fewer stages than those shown.

[0048] The apparatus comprises a fetch stage 105 configured to fetch instructions to be executed from an instruction cache or memory. The fetched instructions are sent by the fetch unit to a decode stage 110 which decodes the received instructions and sends them to an issue stage 115. The issue stage maintains a queue of received instructions and issues them to an execution stage 120. The issue can be based on an issue policy, for example such that an instruction can be issued as soon as all source operands of that instruction are available (the source operands being produced in earlier instructions).

[0049] The execution stage comprises execution circuitry modules, for example arithmetic logic units (ALUs) and load / store (LD / ST) units, for performing processing operations. Data on which processing operations are to be performed is loaded (in response to load commands from the LD / ST units) from a memory 125 (which can be external to the apparatus 100) into a set of registers 130 accessible to the execution stage 120. Conversely, data in a given one of the registers 130 can be stored in the memory 125 in response to a store command from the LD / ST units.

[0050] In order to store data in the memory 125, the data is first provided to a store buffer 135 which buffers the data to be stored along with an associated memory address. The data is then provided from the store buffer 135 to the memory 125. As explained above, the latency associated with providing data to the store buffer 135 is lower than the latency associated with providing data to the memory 125. Using the store buffer 135 in this way therefore allows data to be stored to be provided from the registers to the store buffer 135 quickly, after which the execution units 120 are free to continue performing processing operations (the registers from which the data was stored to the store buffer are now available for reuse with other data), while the (relatively slow) storage of the data in the memory 125 is performed in the background. As explained above, the store buffer 135 is relatively complex to implement and so for performance reasons can have a limited number of entries, for example in some cases fewer entries than the number of registers. It is therefore possible that the store buffer 135 will become full, for example if data from a large number of registers is to be stored at the same time. In this situation, the LD / ST units will not be able to perform more store operations until the buffer 135 has space.

[0051] The apparatus 100 includes shadow registers 140 associated with the registers 130. In this example, one shadow register 140 is provided for each register 130. When a state save trigger operation is to be performed, such as an interrupt or a function call, the contents of the registers 130 are copied to the shadow registers 140. The state of the registers 130 is thereby captured at the initiation of the state save trigger operation, and the registers 130 are then available for use in the processing of the state save trigger operation. The captured register state, i.e., the contents of the captured registers 130 stored in the shadow registers 140, is then stored in memory 125 in the background while the state save trigger operation is processed. The execution of the state save trigger operation can thereby be performed in parallel with the relatively time-consuming process of storing the captured state in memory 125, without filling up the store buffer 135. As explained above, a given shadow register 140 is implemented with simpler circuitry than a store buffer entry, since no memory address is stored for the shadow register 140, and the shadow register is not subject to the same optimization constraints as the store buffer 135, which is optimized for load hits in the store buffer 135. It is therefore less expensive in terms of cost, resources, and processing capacity to implement the shadow registers 140 than to expand the number of store buffer 135 entries.

[0052] A comparison system that does not implement the present disclosure will now be described with reference to Figure 2A and Figure 2B Some differences between the processing of a state save trigger operation in a system according to the present disclosure and a comparison system that does not implement the present disclosure will now be described.

[0053] Figure 2A The processing of a state save trigger operation in a comparison system that does not implement the present disclosure is illustrated over time. In this comparison system, no shadow registers are provided and all storage of data in memory is performed via the store buffer.

[0054] At time tO, the system is executing processing instructions associated with an initial process (indicated by the horizontal line in Figure 2A ).

[0055] At time tl, an interrupt INT1 is received. The interrupt INT1 is a state save trigger operation, since the register state must be saved (for later restoration after the processing of INT1 is completed) in order to free the registers for processing INT1. This saving is performed by storing the register contents in a first stack frame in memory, which can be referred to as "stacking" the registers. Stacking the registers takes an amount of time, and is completed at time t2a.

[0056] INT1 can be processed. During the processing of INT1 at time t3a, another interrupt INT2 is received. As with INT1, the register state must be saved in order to free the registers for processing INT2. The registers are therefore stacked into a second stack frame in memory. This second stacking step is completed at time t4a.

[0057] INT2 is processed. At a later time t5a, the processing of INT2 is completed. The registers are restored from the second stack frame to their state at time t3a, and the processing of INT1 is resumed.

[0058] Finally, at time t6a, the processing of INT1 is completed. The registers are restored from the first stack frame to their state at time t1, and the processing of the initial process continues.

[0059] Figure 2B The processing of the same state-saving triggered operations INT1 and INT2 over time is illustrated in a system according to the present disclosure in which shadow registers are provided.

[0060] As with Figure 2A At time t0, the system is executing processing instructions associated with an initial process.

[0061] At time t1, an interrupt INT1 is received. The register state is therefore to be saved (for later restoration after the processing of INT1 is completed) in order to make the registers available for processing INT1.

[0062] The register state is captured in the shadow registers, which is completed at time t2b. Because this capture is much faster than the process of stacking the registers, time t2b is earlier than time t2a. At time t2b, the processing of INT1 and the stacking of the shadow registers are started in parallel.

[0063] At time t3b, during the processing of INT1, another interrupt INT2 is received. The register state is therefore to be saved in order to free the registers for processing INT2. The register state is captured in the shadow registers, which is completed at time t2b. This capture is completed at time t4b. As with the case of the capture before the processing of INT1, this is much faster than the stacking of the registers, and therefore the delay before the processing of INT2 starts at time t4b is shorter than Figure 2A the corresponding delay between times t3a and t4a in. Once the capture is completed at time t4b, the processing of INT2 and the stacking of the shadow registers are started in parallel.

[0064] At a later time t5b, the processing of INT2 is completed (the stacking having been completed at Figure 2Bthe earlier time (not shown) is completed). As in Figure 2A the state of the registers at time t3b is recovered from the second stack frame, and processing of INT1 is continued.

[0065] Eventually, as in Figure 2A at time t6b, processing of INT1 is completed. The state of the registers at time t1 is recovered, and processing of the initial process is continued.

[0066] From Figure 2A and Figure 2B it can be seen that the time to capture the state of the registers in the shadow registers in Figure 2B is much less than the time to perform the register stacking in Figure 2A . This means that the processing of INT1 and INT2 can begin more expeditiously after their receipt, and thus complete more quickly. A system according to the present disclosure (as shown in Figure 2B thus provides a performance advantage over a comparative system (as shown in Figure 2A ) that does not provide shadow registers. While the time required to perform the register stacking in the system of Figure 2A may be reduced by increasing the size of the storage buffer (thus reducing or eliminating the bottleneck associated with stacking several registers at the same time), as explained above, this would require a greater circuit area than the system associated with providing shadow registers. One reason for this is that the storage buffer would typically implement a uniform hazard procedure for all of its entries, whereas a more efficient hazard procedure can be implemented for the shadow registers, as described in more detail below.

[0067] Figure 3 A method 300 for processing an operation according to an example of the present disclosure is shown.

[0068] The method 300 begins at block 305, where a request to perform an operation is received.

[0069] At block 310, it is determined whether the operation triggers state saving. If not, flow proceeds to block 315, where the operation is performed.

[0070] If it is determined that the operation is a state saving triggering operation, flow proceeds to block 320, where the state of the registers is captured in a shadow register.

[0071] After the state of the registers is captured, at block 325, the captured state is provided from the shadow register to memory.

[0072] In parallel with providing the captured state to memory, at block 330, the requested operation is performed.

[0073] After the requested operation is performed, the register state captured at block 335 is restored and processing continues from the point at which the state was saved.

[0074] Figure 4 A method 400 for mitigating data risk associated with memory requests in a system according to some aspects of the present disclosure is shown. Such risk can arise if data is accessed during the time it is being provided from a shadow register to memory: as explained above, if an attempt is made to access the data from memory before it has been updated from the shadow register, it can inadvertently retrieve outdated data.

[0075] At block 405, a memory access request is received. For example, the received request can identify a memory address from which data is to be loaded.

[0076] At block 410, it is determined whether the shadow register is in the process of being stored (e.g., as indicated between times ti and t2b in FIG. 4). If the shadow register is not in the process of being stored, there is no risk of inadvertently retrieving an outdated version of the requested data from memory because it has not been updated from the shadow register. Flow therefore proceeds to block 415, where the memory access request is processed. Figure 2B

[0077] If it is determined that the shadow register is in the process of being stored, flow proceeds to block 415, where it is determined whether the requested memory access is likely to involve an un-stored shadow register. For example, instead of storing an individual address for each shadow register, an address range associated with the shadow register can be stored (e.g., indicated by a base address and an indication of the span of the stack frame to which the register contents are being stored). In such a system, it can be possible to determine whether the requested memory access involves an address within the address range, but it can not be possible to determine whether the data associated with that particular memory address is still to be stored from the corresponding shadow register. In such a case, it can be determined that the requested memory access is likely to involve an un-stored shadow register.

[0078] If the requested memory access is not likely to involve an un-stored shadow register (e.g., because it involves a memory address outside of the above-described storage address range), it can be assumed that there is no data risk because the data has not been updated from the shadow register. Flow therefore proceeds to block 415, where the memory access request is processed.

[0079] ​If the requested memory access does indeed have the potential to involve an un-stored shadow register (e.g. because it involves a memory address within the above-mentioned storage address range, and / or because it expresses the memory address from which data is to be loaded in terms of the stack pointer), then flow proceeds to block 420, where the memory access request is identified as involving a data risk. Data risk mitigation action can then be taken. For example, servicing of the data access request can be delayed until storage of the contents of the shadow register is complete.

[0080] Thus there is provided apparatus and methods for handling state save trigger operations such as interrupts.

[0081] As will be appreciated from the foregoing description, the techniques described herein provide a number of significant benefits. In particular, the speed and efficiency of handling state save trigger operations is improved without incurring the costs and performance penalties that would be associated with expanding the size of the storage buffer.

[0082] In this application, the word "configured" is used to mean that an element of an apparatus has a configuration able to perform the defined operation. In this context, a "configuration" refers to an arrangement or interconnection of hardware or software. For example, a processor or other processing device can be programmed to perform functions by configuring its elements to perform the defined operation. "Configured" does not imply that the apparatus element must be changed in any way to perform the defined operation.

[0083] While the present application has been described herein with reference to the illustrative embodiments, it is understood that the application is not limited to the precise steps described, and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope of the application as defined by the appended claims.

Claims

1. An apparatus comprising: Register circuitry that implements multiple registers; A processing circuit is used to perform data processing operations on the data stored in the register; A storage buffer circuit is used to temporarily store the given data in response to a storage instruction for the given data before providing the given data to the memory; In response to receiving a request for an execution state save trigger operation at the processing circuit, the register circuit is configured as follows: The state of a subset of the plurality of registers is captured in the shadow register of the register circuit; and The captured state is provided from the shadow register to the memory.

2. The apparatus of claim 1, wherein the processing circuitry is configured to initiate the execution of a requested state saving trigger operation before completing the provision of the captured state from the register circuitry to the memory.

3. The apparatus of claim 1, wherein capturing the state of the subset of registers includes copying the contents of the subset of registers to the shadow register.

4. The apparatus of claim 3, wherein each shadow register corresponds to one of the subsets of registers, and capturing the state of a given register of the subset of registers includes storing the contents of the given register in the corresponding shadow register.

5. The apparatus of claim 1, wherein capturing the state of the subset of registers includes updating mapping information that identifies which of the plurality of registers are shadow registers.

6. The apparatus of claim 1, wherein the processing circuit performs a risk check in response to receiving a memory access request to detect whether the memory access request causes a data risk condition; The data risk condition occurs at least when the memory access request has the potential to access a memory address such that data from one of the shadow registers will still be stored in the memory before the captured state is provided to the memory.

7. The apparatus of claim 6, wherein the risk check allows for the detection of false positives for the data risk conditions.

8. The apparatus of claim 6, wherein the probability of a false positive detection for the data risk condition is higher for a risk check performed on the shadow register than for a risk check performed on the storage buffer.

9. The apparatus of claim 1, wherein capturing the state of the register subset includes storing an indication of a stack frame address range to which data from the register subset will be saved.

10. The apparatus of claim 9, wherein the indication of the stack frame address range includes a base address of the stack frame address range and an indication of the span of the stack frame address range.

11. The apparatus according to claim 9, wherein, Before completing the provision of the captured state to the memory and in response to receiving a data processing request indicating a memory address within the stack frame address range, the processing circuitry is configured to perform data risk mitigation actions on the received data processing request.

12. The apparatus of claim 11, wherein the data risk mitigation action includes delaying the processing of a received data processing request until the captured state is stored in the memory.

13. The apparatus according to claim 1, wherein, Before completing the provision of the captured state to the memory, and in response to receiving a stack pointer relative memory access request to determine the target memory address relative to the stack pointer, the processing circuitry is configured to perform data risk mitigation actions on the received data processing request.

14. The apparatus of claim 13, wherein the processing circuitry is configured to determine whether to perform the data risk mitigation action on the stack pointer relative memory access request independent of the target memory address.

15. The apparatus of claim 1, wherein the state saving trigger operation is one of the following: Interrupt operation; Abnormal operation; and Function call operation.

16. The apparatus of claim 15, wherein the state saving trigger operation is a function call operation, the function call operation including a transition from a higher security operation state to a lower security operation state.

17. The apparatus according to claim 1, wherein, After the processing circuit performs the state saving trigger operation, the register circuit is configured to restore the captured state in the register.

18. The apparatus of claim 17, wherein restoring the capture state includes restoring the capture state from the shadow register in response to determining that the shadow register has not been overwritten.

19. An apparatus comprising: A register device that implements multiple registers; A processing device for performing data processing operations on the data stored in the register; A storage buffer device for temporarily storing given data in response to a storage instruction for the given data before providing the given data to a memory; In response to receiving a request for an execution state save trigger operation at the processing device, the register device is configured to: The state of a subset of the registers is captured in the shadow register of the register device; and The captured state is provided from the shadow register to the memory.

20. A method comprising: Data is stored in registers associated with the processing circuitry; Receive a request to perform a state saving trigger operation on a given piece of data in the data; and In response to the request: The state of a subset of the registers is captured in the shadow register corresponding to the registers; and The captured state is provided from the shadow register to the memory.

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