Display device and method of manufacturing a display device

Abstract

A display device includes a base substrate including a display area and a non-display area surrounding the display area; a first interlayer insulating layer disposed on the base substrate; a second interlayer insulating layer disposed on the first interlayer insulating layer; a first semiconductor layer disposed on the second interlayer insulating layer and including an oxide; and a first gate insulating layer disposed on the first semiconductor layer, wherein a material of the first interlayer insulating layer and a material of the second interlayer insulating layer are different from each other. A method of manufacturing a display device is also disclosed.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0124475, filed on October 8, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The disclosure relates to a display device and a method of manufacturing a display device. BACKGROUND

[0004] With the development of multimedia, the importance of display devices is increasing. Accordingly, various display devices such as liquid crystal displays (LCDs) and organic light emitting diode (OLED) displays are being used. In display devices, OLED displays display an image using an organic light emitting element that generates light through the recombination of electrons and holes. OLED displays include a transistor that supplies a driving current to the organic light emitting element. SUMMARY

[0005] Embodiments of the present application provide a display device that prevents shorting of an oxide semiconductor.

[0006] Another embodiment of the present application provides a method of manufacturing a display device that prevents shorting of an oxide semiconductor.

[0007] It should be noted that the objects of the disclosure are not limited to the above-mentioned objects, and other objects of the disclosure will be apparent to those skilled in the art from the following description.

[0008] According to an embodiment, a display device can include a base substrate including a display area and a non-display area surrounding the display area; a first interlayer insulating layer disposed on the base substrate; a second interlayer insulating layer disposed on the first interlayer insulating layer; a first semiconductor layer disposed on the second interlayer insulating layer; a first gate insulating layer disposed on the first semiconductor layer; a first gate electrode disposed on the first gate insulating layer; a third interlayer insulating layer disposed on the first gate electrode; and a first source electrode and a first drain electrode disposed on the third interlayer insulating layer and electrically connected to the first semiconductor layer, wherein a material of the first interlayer insulating layer and a material of the second interlayer insulating layer are different from each other.

[0009] The display device can further include a second semiconductor layer disposed between the base substrate and the first interlayer insulating layer, a second gate insulating layer disposed between the second semiconductor layer and the first interlayer insulating layer, a second gate electrode disposed between the second gate insulating layer and the first interlayer insulating layer, a third gate insulating layer disposed between the second gate electrode and the first interlayer insulating layer, and a second source electrode and a second drain electrode disposed on the third gate insulating layer, wherein the second source electrode and the second drain electrode can be electrically connected to the second semiconductor layer.

[0010] The second interlayer insulating layer can include silicon oxide (SiO x ). The first interlayer insulating layer can include nitrogen, hydrogen, and silicon, wherein the nitrogen and the hydrogen are bonded by a first bond, the silicon and the hydrogen are bonded by a second bond, and a ratio of the first bond to the second bond is in a range of about 15 to about 30.

[0011] The first interlayer insulating layer can have a release amount (intensity (A)) of the hydrogen of at most about 2.0E-09 at a substrate temperature of at least about 350℃.

[0012] The nitrogen, the hydrogen, and the silicon included in the first interlayer insulating layer can be formed by ammonia (NH3), silane (SiH4), and nitrogen (N2), and a supply ratio of the ammonia (NH3) to the silane (SiH4) can be at least about 5.

[0013] The supply ratio of the nitrogen (N2) to the silane (SiH4) can be at least about 30.

[0014] The nitrogen, the hydrogen, and the silicon of the first interlayer insulating layer can be formed by ammonia (NH3), silane (SiH4), and nitrogen (N2), and the supply ratio of the ammonia (NH3) to the silane (SiH4) can be about 0.

[0015] The supply ratio of the nitrogen (N2) to the silane (SiH4) can be at least about 150.

[0016] The first semiconductor layer can include an oxide.

[0017] The second semiconductor layer can include crystalline silicon.

[0018] A width of the first gate insulating layer can be less than a width of the first semiconductor layer.

[0019] The first gate electrode can overlap the first gate insulating layer, and a width of the first gate electrode can be less than the width of the first semiconductor layer.

[0020] The display device can further include a fourth gate electrode between the base substrate and the first interlayer insulating layer, and the first gate electrode and the fourth gate electrode can be electrically connected.

[0021] The display device can further include a fourth gate electrode between the base substrate and the first interlayer insulating layer, wherein a width of the fourth gate electrode can be greater than a width of the first semiconductor layer, and the first source electrode or the first drain electrode can be electrically connected to the fourth gate electrode.

[0022] The display area can include a first area and a second area adjacent to the first area, the first semiconductor layer can be disposed in the first area, and the second semiconductor layer can be disposed in the second area.

[0023] The display device can further include a third gate electrode disposed between the third gate insulating layer and the second source electrode and the second drain electrode, and the second gate electrode and the third gate electrode can form a capacitor.

[0024] The display device can include a switching transistor including the first semiconductor layer, the first gate electrode, and the first source electrode and the first drain electrode. The display device can include a driving transistor including the second semiconductor layer, the second gate electrode, and the second source electrode and the second drain electrode.

[0025] According to another embodiment, a method of manufacturing a display device includes forming a first interlayer insulating layer on a base substrate; forming a second interlayer insulating layer including silicon oxide (SiO x ) on the first interlayer insulating layer; and forming a first semiconductor layer on the second interlayer insulating layer, wherein the first interlayer insulating layer includes nitrogen, hydrogen, and silicon, and wherein the nitrogen and the hydrogen are bonded by a first bond, the silicon and the hydrogen are bonded by a second bond, and a ratio of the first bond to the second bond is in a range of about 15 to about 30.

[0026] A release amount (intensity (A)) of the hydrogen of the first interlayer insulating layer can be at most about 2.0E-09 at a substrate temperature of at least about 350°C.

[0027] Forming the first interlayer insulating layer can include supplying ammonia (NH3), silane (SiH4), and nitrogen (N2), and a supply ratio of the ammonia (NH3) to the silane (SiH4) can be at least about 5.

[0028] Forming the first interlayer insulating layer can include supplying ammonia (NH3), silane (SiH4), and nitrogen (N2), and a supply ratio of the nitrogen (N2) to the silane (SiH4) can be at least about 30.

[0029] Forming the first interlayer insulating layer can include supplying ammonia (NH3), silane (SiH4), and nitrogen (N2), and a supply ratio of the ammonia (NH3) to the silane (SiH4) can be about 0.

[0030] Forming the first interlayer insulating layer can include supplying ammonia (NH3), silane (SiH4), and nitrogen (N2), and a supply ratio of the nitrogen (N2) to the silane (SiH4) can be at least about 150.

[0031] The features of the present application, however, are not limited to the features set forth in this disclosure. The above and other features of the present application will become more fully understood from the detailed description of the application given hereinafter, and the appended claims, by referring to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more fully understood from the detailed description of the embodiments of the present disclosure given hereinafter and the appended claims, by referring to the accompanying drawings, in which:

[0033] Figure 1 is a schematic block diagram illustrating a display device according to an embodiment;

[0034] Figure 2 is a schematic diagram illustrating an equivalent circuit of a pixel of a display device according to an embodiment;

[0035] Figure 3 is a planar layout of a display device according to an embodiment;

[0036] Figure 4 is a schematic cross-sectional view illustrating a curved display device according to an embodiment;

[0037] Figure 5 shows a schematic cross-sectional view taken along lines V-V' and lines VI-VI' of Figure 3

[0038] Figure 6 is a schematic diagram illustrating a flow of hydrogen molecules into a second semiconductor layer including an oxide;

[0039] Figure 7 is a list showing a film formation condition of silicon nitride releasing excess hydrogen, a thin film property, and a release amount of hydrogen;

[0040] Figure 8 ​is a list of film formation conditions, thin film properties, and hydrogen release amounts of silicon nitride which shows release of a low amount of hydrogen;

[0041] Figure 9 is a list of film formation conditions, thin film properties, and hydrogen release amounts of silicon nitride which shows release of a minimum amount of hydrogen;

[0042] Figure 10 is a graph showing the nitrogen and hydrogen combination ratio according to the annealing temperature;

[0043] Figure 11 is a graph showing the silicon and hydrogen combination ratio according to the annealing temperature;

[0044] Figure 12 is a graph showing the drive current according to the gate-source voltage when the first interlayer insulating layer is omitted;

[0045] Figure 13 is a graph showing the drive current according to the gate-source voltage when the first interlayer insulating layer and the second interlayer insulating layer are provided together;

[0046] Figure 14 is a graph showing the threshold voltage according to the annealing temperature when the first interlayer insulating layer is omitted and when the first interlayer insulating layer and the second interlayer insulating layer are provided together;

[0047] Figure 15 is a plan layout of one transistor provided in a first region according to another embodiment;

[0048] Figure 16 is a schematic cross-sectional view of a display device according to another embodiment;

[0049] Figure 17 is a plan layout of one transistor provided in a first region according to still another embodiment;

[0050] Figure 18 is a schematic cross-sectional view of a display device according to still another embodiment;

[0051] Figure 19 is a graph showing the threshold voltage when the first interlayer insulating layer is omitted and when the first interlayer insulating layer and the second interlayer insulating layer are provided together;

[0052] Figure 20 is a schematic cross-sectional view of a display device according to yet another embodiment; and

[0053] Figure 21 is a schematic cross-sectional view of a display device according to yet another embodiment. DETAILED DESCRIPTION

[0054] The advantages and features of the present disclosure and a method of achieving the same will be more clearly understood from the following embodiments described with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments and can be implemented in various ways. The embodiments are provided only to make the present disclosure complete and to fully provide the one of ordinary skill in the art to which the present disclosure pertains and the present disclosure will be defined by the claims.

[0055] It will be understood that when an element such as a layer, film, region, substrate, or area is referred to as being "on" or "over" another element, it can be directly on or over the other element or intervening elements can also be present. In addition, when an element such as a layer, film, region, substrate, or area is referred to as being "under" another element, it can be directly under the other element, or intervening elements can also be present. Like reference numerals refer to like elements throughout the specification.

[0056] The term "overlapped" or "overlapping" means that a first object can be above or below or beside a second object, or vice versa. In addition, the term "overlapped" can include laminated, stacked, faced or faced, extended above, covered or partially covered, or any other suitable term that one of ordinary skill in the art would recognize and understand. The terms "faced" and "faced" mean that a first element can be directly or indirectly opposite a second element. In the case where a third element is interposed between the first element and the second element, the first element and the second element can be understood to be indirectly opposite each other, although still facing each other. When an element is described as "not overlapped" or "not overlapping" with another element, this can include that the elements are spaced apart from each other, offset from each other, separated from each other, or any other suitable term that one of ordinary skill in the art would recognize and understand.

[0057] In the drawings, the size and thickness of the elements can be exaggerated for better understanding, clarity and ease of description. However, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thickness of layers, films, panels, regions, and other elements can be exaggerated for better understanding and ease of description, for the purpose of clarity.

[0058] It should be understood that although the terms such as "first" and "second" and the like can be used herein to describe various components, these components are not limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, the first component described below can be named the second component without departing from the spirit and scope of the present disclosure.

[0059] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “approximately” or “about” as used herein include the listed values ​​and are intended to refer to a range of acceptable deviations for a particular value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±20%, ±10%, or ±5% of the listed values.

[0060] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless expressly defined in this specification, terms (such as those defined in a commonly used dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted as having an ideal or overly formal meaning.

[0061] In the following description, embodiments will be illustrated with reference to the accompanying drawings. The display device will be described using an organic light-emitting display device as an example.

[0062] Figure 1 This is a schematic block diagram illustrating a display device according to an embodiment.

[0063] Reference Figure 1 The display device 1 includes a display area DA with pixels 10, a scan driver 20, and a data driver 30 (see [link]). Figure 3 The system includes a scan driver 20, a data driver 30, and a transmit control driver 40. The controller 50 controls the scan driver 20, the data driver 30, and the transmit control driver 40. The controller 50 can be configured to... Figure 3 Main circuit board (see) Figure 3 (500) on.

[0064] The display area DA of the display device 1 includes pixels 10, which are disposed on scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n and SL41 to SL4n (n is an integer of at least 2), data lines DL1 to DLm (m is an integer of at least 2) and transmission control lines EL1 to ELn or transmission control lines EML1 to EMLn (see [reference]). Figure 2 The intersections of the ) are arranged in a matrix.

[0065] The scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, and SL41 to SL4n and the emission control lines EL1 to ELn can extend in the row direction, and the data lines DL1 to DLm can extend in the column direction. The row direction and the column direction can be converted to each other. The supply line of the initialization voltage VINT can branch along the row and extend in the row direction, and the supply line of the first power supply voltage ELVDD can branch along the column and extend in the column direction. However, the present disclosure is not limited to this, and the extending direction of the supply line of the initialization voltage VINT and the extending direction of the supply line of the first power supply voltage ELVDD can be variously modified.

[0066] The four scan lines SL11, SL21, SL31, and SL41, the one data line DL1, the one emission control line EL1, the one supply line of the initialization voltage VINT, and the one supply line of the first power supply voltage ELVDD can pass through the pixel 10 in the first row and the first column. The same lines can pass through the other pixels 10.

[0067] The scan driver 20 can generate four scan signals and transmit the four scan signals to each pixel 10 through the scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, and SL41 to SL4n. For example, the scan driver 20 sequentially supplies the scan signals to the first scan lines SL11 to SL1n, the second scan lines SL21 to SL2n, the third scan lines SL31 to SL3n, or the fourth scan lines SL41 to SL4n.

[0068] The data driver 30 transmits data signals to the pixels 10 through the data lines DL1 to DLm. The data signals are supplied to the pixels 10 selected by the second scan signals each time the second scan signals are supplied to the second scan lines SL21 to SL2n.

[0069] The emission control driver 40 generates an emission control signal and transmits the emission control signal to the pixels 10 through the emission control lines EML1 to EMLn. The emission control signal controls the emission time of the pixels 10. When the scan driver 20 generates the emission control signal as well as the scan signals, or according to the internal structure of the pixels 10, the emission control driver 40 can be omitted.

[0070] The controller 50 converts the image signals R, G, and B transmitted from the outside into image data signals DR, DG, and DB, and transmits the converted image data signals DR, DG, and DB to the data driver 30. The controller 50 receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the clock signal MCLK, and generates control signals for controlling the driving of the scan driver 20, the data driver 30, and the emission control driver 40 to transmit the generated control signals to the scan driver 20, the data driver 30, and the emission control driver 40. For example, the controller 50 can generate and transmit a scan driving control signal SCS for controlling the scan driver 20, a data driving control signal DCS for controlling the data driver 30, and an emission driving control signal ECS for controlling the emission control driver 40, respectively.

[0071] Each pixel 10 receives a first power voltage ELVDD and a second power voltage ELVSS. The first power voltage ELVDD can be a certain high-level voltage, and the second power voltage ELVSS can be a voltage lower than the first power voltage ELVDD.

[0072] Based on each data signal transmitted through the data lines DL1 to DLm, each pixel 10 emits light having a certain brightness due to a driving current supplied to the light emitting element.

[0073] The first power voltage ELVDD, the second power voltage ELVSS, and the initialization voltage VINT, etc. can be supplied from an external voltage source.

[0074] Figure 2 is a schematic diagram showing an equivalent circuit of one pixel of a display device according to an embodiment.

[0075] Referring to Figure 2 The circuit of one pixel 10 of the display device 1 includes an organic light emitting diode OLED, transistors T1 to T7, and a storage capacitor Cst. A data signal DATA, a first scan signal GI_N[n], a second scan signal GW_P[n], a third scan signal GW_P[n+1], a fourth scan signal GW_N[n], an emission control signal EM, a first power voltage ELVDD, a second power voltage ELVSS, and an initialization voltage VINT are applied to the circuit of one pixel 10.

[0076] The organic light emitting diode OLED includes an anode electrode and a cathode electrode. The storage capacitor Cst includes a first electrode and a second electrode.

[0077] The transistors T1 to T7 can include a first transistor T1 to a seventh transistor T7. The transistors T1 to T7 each include a gate electrode, a first electrode, and a second electrode. One of the first electrode and the second electrode of each of the transistors T1 to T7 becomes a source electrode, and the other thereof becomes a drain electrode.

[0078] The transistors T1 to T7 can each be a thin film transistor.

[0079] The transistors T1 to T7 according to the embodiment include a semiconductor layer. The semiconductor layer of the transistors T1 to T7 can include an oxide or crystalline silicon. For example, the semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can each be made of crystalline silicon. The semiconductor layers of the third transistor T3 and the fourth transistor T4 can each be made of an oxide.

[0080] The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 made of crystalline silicon can be disposed to be coplanar with each other. The semiconductor layers of the third transistor T3 and the fourth transistor T4 made of an oxide can be disposed to be coplanar with each other. The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be disposed not to be coplanar with the semiconductor layers of the third transistor T3 and the fourth transistor T4.

[0081] The gate electrode of the first transistor T1 is connected to a first electrode of a storage capacitor Cst. The first electrode of the first transistor T1 is connected to a first power supply voltage supply line VDDL for applying a first power supply voltage ELVDD via the fifth transistor T5. The second electrode of the first transistor T1 is connected to an anode electrode of an organic light emitting diode OLED via the sixth transistor T6. The first transistor T1 receives a data signal DATA according to a switching operation of the second transistor T2, and supplies a drive current Id to the organic light emitting diode OLED. For example, the first transistor T1 can be a drive transistor.

[0082] The gate electrode of the second transistor T2 is connected to a second scan line SLn+1 for applying a second scan signal GW_P[n]. The first electrode of the second transistor T2 is connected to a data line DLm. The second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1, and is also connected to the first power supply voltage supply line VDDL via the fifth transistor T5. The second transistor T2 is turned on in response to the second scan signal GW_P[n] to perform a switching operation of transmitting the data signal DATA to the first electrode of the first transistor T1.

[0083] The gate electrode of the third transistor T3 is connected to a fourth scan line SLn+3 for applying a fourth scan signal GW_N[n], and the first electrode of the third transistor T3 is connected to the first electrode of the sixth transistor T6 and the second electrode of the first transistor T1. The second electrode of the third transistor T3 is connected to the first electrode of the fourth transistor T4, the first electrode of the storage capacitor Cst, and the gate electrode of the first transistor T1.

[0084] The gate electrode of the fourth transistor T4 is connected to a first scan line SLn for applying a first scan signal GI_N[n]. The second electrode of the fourth transistor T4 is connected to a supply line ViniL of an initialization voltage VINT and the first electrode of the seventh transistor T7. The first electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3, the gate electrode of the first transistor T1, and the first electrode of the storage capacitor Cst.

[0085] The gate electrode of the fifth transistor T5 is connected to an emission control line EMLn for applying an emission control signal EM. The first electrode of the fifth transistor T5 is connected to a first power supply voltage supply line VDDL of a first power supply voltage ELVDD. The second electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1 and the second electrode of the second transistor T2.

[0086] The gate electrode of the sixth transistor T6 is connected to the emission control line EMLn for applying the emission control signal EM. The first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1 and the first electrode of the third transistor T3. The second electrode of the sixth transistor T6 is connected to the anode electrode of the organic light emitting diode OLED and the second electrode of the seventh transistor T7.

[0087] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the emission control signal EM, thereby driving a current Id to flow into the organic light emitting diode OLED.

[0088] The gate electrode of the seventh transistor T7 is connected to a third scan line SLn+2 for applying a third scan signal GW_P[n+1]. The first electrode of the seventh transistor T7 is connected to the second electrode of the fourth transistor T4 and the supply line ViniL of the initialization voltage VINT, and the second electrode of the seventh transistor T7 is connected to the anode electrode of the organic light emitting diode OLED and the second electrode of the sixth transistor T6.

[0089] The second transistor T2 to the seventh transistor T7 can be a switching transistor.

[0090] A second electrode of the storage capacitor Cst is connected to a first power voltage supply line VDDL. A first electrode of the storage capacitor Cst is connected to a gate electrode of the first transistor T1, a second electrode of the third transistor T3, and a first electrode of the fourth transistor T4. A cathode electrode of the organic light emitting diode OLED is connected to a supply line VSSL of a second power voltage ELVSS. The organic light emitting diode OLED receives a driving current Id from the first transistor T1 and emits light to display an image.

[0091] Figure 3 FIG. 1 is a schematic perspective view illustrating a display device according to an embodiment. Figure 4 FIG. 2 is a schematic cross-sectional view illustrating a curved display device according to an embodiment. Figure 5 FIG. 3 illustrates a cross-sectional view taken along lines V-V' and lines VI-VI' of FIG. 1. Figure 3

[0092] Referring to FIG. 1, Figures 3 to 5 The display device 1 can include a display panel 100 displaying an image, a driving integrated circuit 900 attached to the display panel 100, and a main circuit board 500 connected to the display panel 100.

[0093] In an embodiment, the driving integrated circuit 900 can be applied as a chip on plastic (COP). However, the present disclosure is not limited thereto, and the driving integrated circuit 900 can be applied as a chip on glass (COG).

[0094] The display panel 100 can be an organic light emitting display panel. A case in which the display panel 100 is an organic light emitting display panel will be described in the following embodiments. However, the present disclosure is not limited thereto, and examples of the display panel 100 can include other types of display panels such as a liquid crystal display (LCD) panel, a quantum dot organic light emitting diode (QD-OLED) display panel, a quantum dot LCD (QD-LCD) panel, a quantum nano light emitting display (nano LED) panel, and a micro light emitting display (Micro LED) panel.

[0095] ​The display panel 100 includes a display region DA having a pixel region and a non-display region NA provided around the display region DA. The display region DA can have a rectangular shape whose corners are right angles in a plan view, or can have a rectangular shape whose corners are rounded in a plan view. The display region DA can have a short side and a long side. The short side of the display region DA can be a side extending in the first direction DR1. The long side of the display region DA can be a side extending in the second direction DR2. The planar shape of the display region DA is not limited to a rectangular shape, and the display region DA can have a circular shape, an elliptical shape, or other various shapes. The non-display region NA can be provided adjacent to both the short sides and the long sides of the display region DA. The non-display region NA can surround all sides of the display region DA and form edges of the display region DA. However, the present disclosure is not limited thereto, and the non-display region NA can be provided adjacent to only the short sides or the long sides of the display region DA.

[0096] The non-display region NA of the display panel 100 further includes a panel pad region P_PA. The panel pad region P_PA can be provided, for example, adjacent to one short side of the display region DA. However, the present disclosure is not limited thereto, and the panel pad region P_PA can be provided adjacent to both the short sides of the display region DA, or can be provided adjacent to both the short sides and the long sides of the display region DA.

[0097] The driving integrated circuit 900 described above can be provided in the panel pad region P_PA. The driving integrated circuit 900 can be directly provided in the panel pad region P_PA of the display panel 100.

[0098] The main circuit board 500 can be connected to (e.g., provided in) the panel pad region P_PA of the display panel 100. The panel pad region P_PA in which the main circuit board 500 is provided can be located at a lower level in the second direction DR2, as compared to the panel pad region P_PA in which the driving integrated circuit 900 is provided. The main circuit board 500 can be attached to pads provided in the panel pad region P_PA of the display panel 100 using an anisotropic conductive film. In some embodiments, the main circuit board 500 can be attached to one side of the display panel 100 by ultrasonic bonding. The controller 50 (see Figure 1 ) described above can be provided on the main circuit board 500.

[0099] The driving integrated circuit 900 outputs signals and voltages for driving the display panel 100 based on signals generated by the controller 50 provided on the main circuit board 500. The driving integrated circuit 900 can be formed as an integrated circuit, but the present disclosure is not limited thereto.

[0100] The non-display area NA of the display panel 100 may also include the curved area BA.

[0101] The substrate 101 of the display panel 100 (see...) Figure 5 The substrate 101 can be made of an insulating material such as a polymer resin. Examples of insulating materials may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. The substrate 101 can be a flexible substrate that is bendable, foldable, and rollable. Examples of materials constituting the flexible substrate may be PI, but this disclosure is not limited thereto.

[0102] The curved region BA can be positioned between the pixel array and the panel pad area P_PA. The curved region BA can be located within the non-display area NA. The display panel 100 can be curved in one direction relative to a curved line that serves as a reference line positioned within the curved region BA. The curved line can be a straight line parallel to the lower (or upper) side of the display panel 100. Figure 4 As shown, the curved area BA of the display panel 100 can be bent downwards on the third direction DR3.

[0103] The panel pad area P_PA of the display panel 100 can be located below the display area DA of the display panel 100. Therefore, the driver integrated circuit 900 and the main circuit board 500 attached to the panel pad area P_PA of the display panel 100 can be located below the display area DA of the display panel 100 together with the curved panel pad area P_PA of the display panel 100.

[0104] However, this disclosure is not limited thereto; the display area DA and the panel pad area P_PA can be connected to each other without the bending area BA. For example, without the bending area BA, both the display area DA and the non-display area NA of the display panel 100 can be flat.

[0105] Reference Figure 5 The display panel 100 includes a substrate 101, a conductive layer disposed on the substrate 101, and an insulating layer disposed between the conductive layers. Figure 5 The cross-sectional structure of one pixel of the display area DA and the non-display area NA of the display panel 100 is shown. Furthermore, Figure 5 The cross-sectional structure of the curved region BA in the non-display area NA is shown.

[0106] In the display panel 100, the base substrate 101, the buffer layer 102, the barrier layer 103, the first semiconductor layer 105 (or the second semiconductor layer), the first insulating layer 111, the first conductive layer 120, the second insulating layer 112, the second semiconductor layer 145 (or the first semiconductor layer), the third insulating layer 115, the second conductive layer 130, the third interlayer insulating layer 116, the curved via layer VIA0, the third conductive layer 150, the first via layer VIA1, the pixel electrode ANO, and the bank layer BANK can be sequentially provided. Each of the above layers can be formed as a single film, but can also be formed as a stacked film including a plurality of films. Other layers can be further provided between the respective layers.

[0107] The base substrate 101 supports the respective layers provided thereon. The display region DA, the non-display region NA, and the curved region BA of the non-display region NA can be defined in the base substrate 101. The display region DA can include a first region in which a transistor including a semiconductor layer made of an oxide is provided, and a second region provided adjacent to the first region and in which a transistor including a semiconductor layer made of crystalline silicon is provided. As described above, the third transistor T3 and the fourth transistor T4 including a semiconductor layer made of an oxide can be provided in the first region. As described above, the first transistor T1, the second transistor T2, and the fifth transistor T5 to the seventh transistor T7 including a semiconductor layer made of crystalline silicon can be provided in the second region.

[0108] When the organic light emitting display device is a bottom emission type or a dual emission type, a transparent substrate can be used. When the organic light emitting display device is a top emission type, a semi-transparent or non-transparent substrate as well as a transparent substrate can be applied.

[0109] The buffer layer 102 can be provided on the base substrate 101. The buffer layer 102 can prevent diffusion of impurity ions, prevent penetration of moisture or ambient air, and perform a surface planarization function. The buffer layer 102 can include silicon nitride, silicon oxide, or silicon oxynitride, or the like. The buffer layer 102 can be omitted depending on the type of the base substrate 101 and process conditions, or the like.

[0110] The barrier layer 103 can be provided on the buffer layer 102. The barrier layer 103 can be made of at least one selected from silicon nitride, silicon oxide, and silicon oxynitride. The barrier layer 103 can be omitted depending on the type of the base substrate 101 and process conditions, or the like.

[0111] The first semiconductor layer 105 can be provided on the barrier layer 103. The first semiconductor layer 105 can be provided in the second region of the base substrate 101.

[0112] The first semiconductor layer 105 can be made of amorphous silicon or polycrystalline silicon, or the like. Polycrystalline silicon can be formed by crystallizing amorphous silicon. Methods of crystallizing amorphous silicon can include various methods including rapid thermal annealing (RTA), solid phase crystallization (SPC), excimer laser annealing (ELA), metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), and sequential lateral solidification (SLS).

[0113] The first semiconductor layer 105 can include a channel region provided to overlap the second gate electrode 121 above it in a thickness direction thereof, and source and drain regions provided at one side and the other side of the channel region. The source and drain regions can contain majority carrier ions compared to the channel region, and thus, their electric resistance can be lower than that of the channel region.

[0114] The first semiconductor layer 105 can be a semiconductor layer of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 described above.

[0115] The first insulating layer 111 can be provided on the first semiconductor layer 105. The first insulating layer 111 can be a gate insulating film having a gate insulating function. For example, the first insulating layer 111 can be a first gate insulating film. The first insulating layer 111 can include a silicon compound or a metal oxide, or the like. For example, the first insulating layer 111 can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide, or the like. These can be used alone or in combination with each other. The first insulating layer 111 can be a single film or a multilayer film including stacked films of different materials.

[0116] The first conductive layer 120 is provided on the first insulating layer 111. The first conductive layer 120 can include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 120 can be a single film or a multilayer film.

[0117] The first conductive layer 120 can include the second gate electrode 121 provided in the second region. The second gate electrode 121 can overlap the channel region of the first semiconductor layer 105 in a thickness direction thereof. The planar size of the second gate electrode 121 can be the same as that of the channel region of the first semiconductor layer 105, but is not limited thereto.

[0118] A second insulating layer 112 or a second gate insulating layer can be provided on the first conductive layer 120. The second insulating layer 112 can be a gate insulating film having a gate insulating function. The second insulating layer 112 can include a silicon compound or a metal oxide, or the like. For example, the second insulating layer 112 can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide, or the like. These can be used alone or in combination with each other. The second insulating layer 112 can be a single film or a multilayer film including stacked films of different materials.

[0119] A second conductive layer 130 can be provided on the second insulating layer 112. The second conductive layer 130 can include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second conductive layer 130 can be a single film or a multilayer film.

[0120] The second conductive layer 130 can include a third gate electrode 131 provided in the second region. The third gate electrode 131 and the second gate electrode 121 can form a capacitor. For example, the third gate electrode 131 and the second gate electrode 121 can form a capacitor using the second insulating layer 112 as a dielectric.

[0121] An interlayer insulating layer can be provided on the second conductive layer 130. The interlayer insulating layer provided on the second conductive layer 130 can include a stacked film. In an embodiment, a first interlayer insulating layer 113 and a second interlayer insulating layer 114 provided on the first interlayer insulating layer 113 can be provided on the second conductive layer 130.

[0122] The first interlayer insulating layer 113 can be made of silicon nitride (SiN x ), or the like, and the second interlayer insulating layer 114 can be made of silicon oxide (SiO x ). The first interlayer insulating layer 113 can prevent hydrogen from flowing from below the first interlayer insulating layer 113 into a second semiconductor layer 145 to be described below. Because the first interlayer insulating layer 113 is made of silicon nitride (SiN x ) that releases a small amount of hydrogen, the first interlayer insulating layer 113 can reduce the amount of hydrogen that can flow into the second semiconductor layer 145.

[0123] The concentration of hydrogen in the second interlayer insulating layer 114 can be less than the concentration of hydrogen in the first interlayer insulating layer 113. Like the first interlayer insulating layer 113, the second interlayer insulating layer 114 can function to prevent hydrogen from flowing into the second semiconductor layer 145 from below the second interlayer insulating layer 114. However, the hydrogen flow-in property can be lower compared to the first interlayer insulating layer 113. In addition to the function of preventing hydrogen flow-in, the second interlayer insulating layer 114 can function to prevent moisture or ambient air from being introduced into the second semiconductor layer 145.

[0124] The second semiconductor layer 145 can be provided on the second interlayer insulating layer 114. The second semiconductor layer 145 can be provided in the first region of the base substrate 101. The second semiconductor layer 145 can be made of an oxide. For example, the second semiconductor layer 145 can be an oxide semiconductor layer. The oxide of the second semiconductor layer 145 can include at least one oxide selected from gallium indium zinc oxide (GIZO) and an oxide combined with zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), hafnium (Hf), or a combination thereof. The oxide of the second semiconductor layer 145 can include at least one selected from indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium tin oxide (ITO).

[0125] The second semiconductor layer 145 can include a channel region provided to overlap a first gate electrode 151 above it in a thickness direction thereof, and source and drain regions provided at one side and the other side of the channel region. Majority carrier ions can be included in the channel region and the source and drain regions of the second semiconductor layer 145. Annealing or a conductive process can be performed on the source and drain regions of the second semiconductor layer 145. When the annealing or the conductive process is performed on the source and drain regions of the second semiconductor layer 145, majority carrier ions can be included in the source and drain regions. The majority carrier ions included in the source and drain regions can migrate to an adjacent channel region of the second semiconductor layer 145. The majority carrier ions can be hydrogen ions. The source and drain regions can also include majority carrier ions compared to the channel region, and thus, their resistance can be lower than that of the channel region.

[0126] When the amount of majority carrier ions (e.g., hydrogen ions) in the channel region of the second semiconductor layer 145 is greater than a reference value, the threshold voltage Vth can decrease due to the decreased resistance, which can cause shorting of the channel.

[0127] Specifically, a short channel method in which the width of the channel region of the second semiconductor layer 145 according to an embodiment is less than the width of the source or drain region can be applied. Thus, when the channel of the second semiconductor layer 145 includes an amount of hydrogen ions greater than a reference value, shorting of the channel can occur.

[0128] The second semiconductor layer 145 can be a semiconductor layer of the third transistor T3 and the fourth transistor T4 described above.

[0129] The third insulating layer 115 can be provided on the second semiconductor layer 145. The third insulating layer 115 can be a gate insulating film having a gate insulating function. For example, the third insulating layer 115 can be a third gate insulating layer. The third insulating layer 115 can include a silicon compound or a metal oxide, or the like. For example, the third insulating layer 115 can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide, or the like. These can be used alone or in combination with each other. The third insulating layer 115 can be a single film or a multilayer film including stacked films of different materials.

[0130] The width of the third insulating layer 115 can be smaller than the width of the second semiconductor layer 145. For example, the third insulating layer 115 can be provided to overlap with the channel region of the second semiconductor layer 145, can further extend outward to overlap with a part of each of the source region and the drain region of the second semiconductor layer 145, and can expose other parts of each of the source region and the drain region.

[0131] Because the width of the third insulating layer 115 is smaller than the width of the second semiconductor layer 145 and the third insulating layer 115 exposes other parts of each of the source region and the drain region and covers the channel region during the annealing or conductive process of the second semiconductor layer 145, more heat can be applied to the source region and the drain region of the second semiconductor layer 145, thereby reducing the resistance. Because the channel region is covered with the third insulating layer 115 during the annealing process of the second semiconductor layer 145, generation of most of the carrier ions in the channel region can be suppressed, thereby preventing the resistance from being reduced.

[0132] The third conductive layer 150 can be provided on the third insulating layer 115. The third conductive layer 150 can include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer 150 can be a single film or a multilayer film.

[0133] The third conductive layer 150 can include a first gate electrode 151 provided in a first region.

[0134] A third interlayer insulating layer 116 can be provided on the third conductive layer 150. The third interlayer insulating layer 116 can be an interlayer insulating film having an interlayer insulating function. The third interlayer insulating layer 116 can include a silicon compound or a metal oxide, etc. For example, the third interlayer insulating layer 116 can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide, etc. These can be used alone or in combination with each other. The third interlayer insulating layer 116 can be a single film or a multilayer film including stacked films of different materials.

[0135] The thickness of the third interlayer insulating layer 116 can be greater than the thickness of the first insulating layer 111 described above. The first insulating layer 111 can be formed to have the same thickness across its entire surface and thus conformally reflect the lower stepped portion. However, unlike the first insulating layer 111, the third interlayer insulating layer 116 can not conformally reflect the stepped portion of the underlying structure. Accordingly, the third interlayer insulating layer 116 can serve to cause the fourth conductive layer 160 provided thereon to be provided flat.

[0136] On the other hand, the buffer layer 102, the barrier layer 103, the first insulating layer 111, the second insulating layer 112, the first interlayer insulating layer 113, the second interlayer insulating layer 114, and the third interlayer insulating layer 116 can not be provided in the bending area BA. Because the buffer layer 102, the barrier layer 103, the first insulating layer 111, the second insulating layer 112, the first interlayer insulating layer 113, the second interlayer insulating layer 114, and the third interlayer insulating layer 116 are not provided in the bending area BA, the upper surface of the base substrate 101 can be exposed. For example, the fifth contact hole CNT5 or the via hole can be further formed in the bending area BA to pass through the buffer layer 102, the barrier layer 103, the first insulating layer 111, the second insulating layer 112, the first interlayer insulating layer 113, the second interlayer insulating layer 114, and the third interlayer insulating layer 116. The side surfaces of the buffer layer 102, the barrier layer 103, the first insulating layer 111, the second insulating layer 112, the first interlayer insulating layer 113, the second interlayer insulating layer 114, and the third interlayer insulating layer 116 can be exposed in the bending area BA. The side surfaces of the buffer layer 102, the barrier layer 103, the first insulating layer 111, the second insulating layer 112, the first interlayer insulating layer 113, the second interlayer insulating layer 114, and the third interlayer insulating layer 116 can be arranged to be aligned with each other in the bending area BA, but the present disclosure is not limited thereto.

[0137] The fifth contact hole CNT5 or the via hole can be simultaneously formed in a process of forming the first to fourth contact holes CNT1 to CNT4 to be described below.

[0138] Accordingly, when the display device 1 described above is bent in the bending area BA, a possible bending stress can be prevented.

[0139] The bending via layer VIA0 can be disposed in the fifth contact hole CNT5 or the via hole. The bending via layer VIA0 can be disposed on the third interlayer insulating layer 116 in the non-display area NA and can be disposed on the exposed side surfaces of the buffer layer 102, the barrier layer 103, the first insulating layer 111, the second insulating layer 112, the first interlayer insulating layer 113, the second interlayer insulating layer 114, and the third interlayer insulating layer 116 in the bending area BA. The bending via layer VIA0 can be in direct contact with the exposed upper surface of the base substrate 101.

[0140] The bending via layer VIA0 can include an inorganic insulating material or an organic insulating material such as a polyacrylate-based resin, an epoxy resin, a phenol resin, a polyamide-based resin, a polyimide-based resin, an unsaturated polyester-based resin, a polyphenyl ether-based resin, a polyphenylene sulfide-based resin, or benzocyclobutene (BCB). The bending via layer VIA0 can be a single film or a multi-layer film including stacked films of different materials.

[0141] The fourth conductive layer 160 can be disposed on the third interlayer insulating layer 116. The fourth conductive layer 160 can include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fourth conductive layer 160 can be a single film or a multi-layer film.

[0142] The fourth conductive layer 160 can include a first source electrode 161 and a first drain electrode 163 disposed in the first area and a second source electrode 165 and a second drain electrode 167 disposed in the second area.

[0143] The first source electrode 161 and the first drain electrode 163 can be connected to a source region and a drain region of the second semiconductor layer 145, and the second source electrode 165 and the second drain electrode 167 can be connected to a source region and a drain region of the first semiconductor layer 105.

[0144] The first source electrode 161 and the first drain electrode 163 can be connected to a source region and a drain region of the second semiconductor layer 145 through a first contact hole CNT1 and a second contact hole CNT2. The first contact hole CNT1 and the second contact hole CNT2 can each be formed in the first area and can pass through the third interlayer insulating layer 116.

[0145] The second source electrode 165 and the second drain electrode 167 can be connected to the source region and the drain region of the first semiconductor layer 105 through a third contact hole CNT3 and a fourth contact hole CNT4. The third contact hole CNT3 and the fourth contact hole CNT4 can each be formed in the second region and can pass through the third interlayer insulating layer 116, the second interlayer insulating layer 114, and the first interlayer insulating layer 113 in the thickness direction thereof.

[0146] The fourth conductive layer 160 can further include a connection electrode 169 located in the non-display region NA and the bend region BA. The connection electrode 169 can be connected to the scan line, the data line, or the power voltage line of the pixel described above and can be connected to the panel pad region P_PA to form a pad of the display panel 100.

[0147] The connection electrode 169 can be formed in the same manner as the first source electrode 161 and the first drain electrode 163 and can be made of the same material as the first source electrode 161 and the first drain electrode 163.

[0148] A first via layer VIA1 can be disposed on the fourth conductive layer 160. The first via layer VIA1 can be disposed in the display region DA and the non-display region NA.

[0149] The first via layer VIA1 can include an inorganic insulating material or an organic insulating material such as an acrylate-based resin, an epoxy resin, a phenol resin, a polyamide-based resin, a polyimide-based resin, an unsaturated polyester-based resin, a polyphenyl ether-based resin, a polyphenylene sulfide-based resin, or BCB. The first via layer VIA1 can be a single film or a multi-layer film including a stack film of different materials.

[0150] A pixel electrode ANO can be disposed on the first via layer VIA1. The pixel electrode ANO can be an anode electrode. The pixel electrode ANO can be electrically connected to the second source electrode 165 or the second drain electrode 167 through a sixth contact hole CNT6 passing through the first via layer VIA1. The pixel electrode ANO can be directly connected to the second source electrode 165 or the second drain electrode 167 through the sixth contact hole CNT6 without passing through the connection electrode or the like.

[0151] For each pixel, the pixel electrode ANO can be individually disposed.

[0152] A bank layer BANK can be disposed on the pixel electrode ANO. The bank layer BANK can partially expose the pixel electrode ANO. The bank layer BANK can be made of an organic insulating material or an inorganic insulating material. For example, the bank layer BANK can be made of at least one selected from a photoresist, a polyimide-based resin, an acrylic-based resin, a silicon compound, and a polyacrylate-based resin.

[0153] The organic layer EL can be provided on the upper surface of the pixel electrode ANO and in the opening of the bank layer BANK. The cathode electrode CAT can be provided on the organic layer EL and the bank layer BANK. The cathode electrode CAT can be a common electrode provided on the pixels.

[0154] The pixel electrode ANO, the organic layer EL, and the cathode electrode CAT can constitute an organic light emitting element.

[0155] A thin film encapsulation layer 170 can be provided on the cathode electrode CAT. The thin film encapsulation layer 170 can cover the organic light emitting element (OLED). The thin film encapsulation layer 170 can be a stacked film in which inorganic films and organic films are alternately stacked. For example, the thin film encapsulation layer 170 can include a first encapsulation inorganic film 171, an encapsulation organic film 172, and a second encapsulation inorganic film 173, which are sequentially stacked.

[0156] Figure 6 is a schematic diagram illustrating inflow of hydrogen molecules into the second semiconductor layer including an oxide.

[0157] Referring to Figure 6 As described above, the second semiconductor layer 145 can include a channel region CH, a source region SR located at one side of the channel region CH, and a drain region DR located at the other side of the channel region CH.

[0158] Hydrogen ions can flow into the channel region CH. There can be several routes through which the hydrogen ions flow into the channel region CH. For example, as shown in Figure 6 As shown in, there can be a first route through which the hydrogen ions flow from below the first interlayer insulating layer 113, a second route through which the hydrogen ions are discharged from the first interlayer insulating layer 113 to flow into the channel region CH, and a third route through which the hydrogen ions flow from the source region SR and the drain region DR which are annealed.

[0159] Hydrogen can flow from the third insulating layer 115, and hydrogen can flow from above the third insulating layer 115.

[0160] As described above, when the amount of hydrogen greater than the reference value flows into the second semiconductor layer 145, a short circuit can occur in the channel region CH of the second semiconductor layer 145.

[0161] In the display device 1 according to the embodiment, the first interlayer insulating layer 113 including silicon nitride having excellent hydrogen inflow characteristics can be further provided below the second interlayer insulating layer 114, thereby greatly reducing the degree of inflow of hydrogen ions into the channel region CH.

[0162] To reduce the amount of hydrogen released from the first interlayer insulating layer 113, the first interlayer insulating layer 113 that releases a small amount of hydrogen can be formed by adjusting the input amounts of ammonia (NH3), nitrogen (N2), and silane (SiH4) in a thin film process. The amount of hydrogen released from the first interlayer insulating layer 113 can be the amount of hydrogen released during the annealing process of the second semiconductor layer 145.

[0163] Figure 7 is a list of film formation conditions, thin film properties, and the amount of hydrogen released from silicon nitride that releases a small amount of hydrogen. Figure 8 is a list of film formation conditions, thin film properties, and the amount of hydrogen released from silicon nitride that releases a small amount of hydrogen. Figure 9 is a list of film formation conditions, thin film properties, and the amount of hydrogen released from silicon nitride that releases a small amount of hydrogen. Figure 10 is a graph showing the binding rate of nitrogen and hydrogen according to the annealing temperature. Figure 11 is a graph showing the binding rate of silicon and hydrogen according to the annealing temperature.

[0164] In Figures 7 to 9 , the horizontal axis shows the substrate temperature (°C), and the vertical axis shows the intensity of hydrogen (A) according to the measurement amount. In Figure 10 and Figure 11 , the horizontal axis shows the annealing temperature (°C), and the vertical axis shows the intensity of the first bond I(N-H)Sir.(cm -1 ) and the intensity of the second bond I(Si-H)Sir.(cm -1 ) measured.

[0165] Referring to Figures 7 to 11 , the first interlayer insulating layer 113 can include silicon nitride that releases a small amount of hydrogen or silicon nitride that releases a minimum amount of hydrogen.

[0166] First, referring to Figures 7 to 9 , a method of manufacturing the first interlayer insulating layer 113 according to an embodiment will be described.

[0167] The first interlayer insulating layer 113 can be formed on the base substrate 101. As described above with reference to Figure 5 , the buffer layer 102, the barrier layer 103, the first insulating layer 111, and the second insulating layer 112 can be disposed between the first interlayer insulating layer 113 and the base substrate 101.

[0168] The first interlayer insulating layer 113 can include nitrogen, hydrogen, and silicon.

[0169] The first interlayer insulating layer 113 can be formed on the base substrate 101 by a film formation process.

[0170] The forming of the first interlayer insulating layer 113 can include supplying ammonia (NH3), nitrogen (N2), and silane (SiH4), and combining the supplied ammonia (NH3), nitrogen (N2), and silane (SiH4) with each other.

[0171] As shown in Figure 8 In the case of the silicon nitride releasing a small amount of hydrogen, the supply ratio NH3 / SiH4 of ammonia (NH3) to silane (SiH4) at the time of supplying ammonia (NH3), nitrogen (N2), and silane (SiH4) can be in the range of about 5 to about 30.

[0172] For example, in the case of the silicon nitride releasing a small amount of hydrogen, the supply ratio NH3 / SiH4 of ammonia (NH3) to silane (SiH4) at the time of supplying ammonia (NH3), nitrogen (N2), and silane (SiH4) can be about 10.

[0173] As shown in Figure 9 In the case of the silicon nitride releasing a minimum amount of hydrogen, the supply ratio NH3 / SiH4 of ammonia (NH3) to silane (SiH4) at the time of supplying ammonia (NH3), nitrogen (N2), and silane (SiH4) can be about 0. For example, ammonia (NH3) can not be supplied.

[0174] On the other hand, as shown in Figure 7 In the case of the silicon nitride releasing an excess amount of hydrogen, the supply ratio NH3 / SiH4 of ammonia (NH3) to silane (SiH4) can be less than about 5. For example, in the case of the silicon nitride releasing an excess amount of hydrogen, the supply ratio NH3 / SiH4 of ammonia (NH3) to silane (SiH4) can be about 4.

[0175] Referring to Figure 8 In the case of the silicon nitride releasing a small amount of hydrogen, the supply ratio N2 / SiH4 of nitrogen (N2) to silane (SiH4) at the time of supplying ammonia (NH3), nitrogen (N2), and silane (SiH4) can be in the range of about 30 to about 150.

[0176] For example, in the case of the silicon nitride releasing a small amount of hydrogen, the supply ratio N2 / SiH4 of nitrogen (N2) to silane (SiH4) at the time of supplying ammonia (NH3), nitrogen (N2), and silane (SiH4) can be about 60.

[0177] Referring to Figure 9 In the case of the silicon nitride releasing a minimum amount of hydrogen, the supply ratio N2 / SiH4 of nitrogen (N2) to silane (SiH4) at the time of supplying ammonia (NH3), nitrogen (N2), and silane (SiH4) can be in the range of about 150 to about 210.

[0178] For example, when supplying ammonia (NH3), nitrogen (N2), and silane (SiH4), in the case of silicon nitride with minimal hydrogen release, the supply ratio of nitrogen (N2) to silane (SiH4), N2 / SiH4, can be approximately 180.

[0179] On the other hand, such as Figure 7 As shown, in the case of silicon nitride releasing excess hydrogen, the nitrogen (N2) to silane (SiH4) supply ratio N2 / SiH4 can be in the range of about 5 to about 15. For example, in the case of silicon nitride releasing excess hydrogen, the nitrogen (N2) to silane (SiH4) supply ratio N2 / SiH4 can be about 10.

[0180] Reference Figure 8 The thin film characteristics of the first interlayer insulating layer 113 are described, in which nitrogen and hydrogen are bonded by a first bond, and silicon and hydrogen are bonded by a second bond. For example... Figure 8 As shown, in the case of silicon nitride that releases a small amount of hydrogen, the ratio of the first bond to the second bond [NH] / [Si-H] can be in the range of approximately 15 to approximately 30. For example, the ratio of the first bond to the second bond [NH] / [Si-H] can be approximately 22.

[0181] like Figure 9 As shown, in the case of silicon nitride that releases a minimum amount of hydrogen, the ratio of the first bond to the second bond [NH] / [Si-H] can be in the range of approximately 15 to approximately 30. For example, the ratio of the first bond to the second bond [NH] / [Si-H] can be approximately 18.

[0182] On the other hand, such as Figure 7 As shown, in the case of silicon nitride that releases excess hydrogen, the ratio of the first bond to the second bond, [NH] / [Si-H], can be less than about 14. For example, the ratio of the first bond to the second bond, [NH] / [Si-H], can be about 0.6.

[0183] Describe the hydrogen content of the first interlayer insulation layer 113, such as Figure 8 As shown, in the case of silicon nitride that releases a small amount of hydrogen, the hydrogen content is approximately 22 at%. Figure 9 As shown, in the case of silicon nitride that releases the minimum amount of hydrogen, the hydrogen content is approximately 14 at%; and, as Figure 7 As shown, in the case of silicon nitride that releases excess hydrogen, the hydrogen content is approximately 19 at%.

[0184] The ratio of the first bond between nitrogen and hydrogen to the second bond between silicon and hydrogen, [NH] / [Si-H], can be related to the hydrogen release characteristics of the first interlayer insulating layer 113.

[0185] Referring to Figure 10 and Figure 11 As the annealing temperature increases, the second bond between silicon and hydrogen is more easily broken than the first bond between nitrogen and hydrogen.

[0186] For example, in the case of the silicon nitride that releases a small amount of hydrogen or the silicon nitride that releases a minimal amount of hydrogen, in which the proportion of the first bond is relatively greater than the proportion of the second bond in the first interlayer insulating layer 113, the bond is easily broken, and thus, more hydrogen that can be released to the outside of the film is generated.

[0187] Referring to Figures 7 to 9 In the case of the silicon nitride that releases a small amount of hydrogen and the silicon nitride that releases a minimal amount of hydrogen, the measured intensity of the amount of hydrogen released and measured at a substrate temperature in a range of about 50°C to about 550°C can be at most about 2.0E-09. However, in the case of the silicon nitride that releases an excess amount of hydrogen, the measured intensity of the amount of hydrogen released and measured at a substrate temperature in a range of about 50°C to about 350°C can be at most about 2.0E-09, but the measured intensity of the amount of hydrogen released and measured at a substrate temperature in a range of about 350°C to about 550°C can be at least about 2.0E-09.

[0188] As described above, in the case of the silicon nitride that releases a small amount of hydrogen, the hydrogen content is about 22 at%; in the case of the silicon nitride that releases a minimal amount of hydrogen, the hydrogen content is about 14 at%; and in the case of the silicon nitride that releases an excess amount of hydrogen, the hydrogen content is about 19 at%. Thus, the hydrogen content of the silicon nitride that releases a small amount of hydrogen is greater than the hydrogen content of the silicon nitride that releases an excess amount of hydrogen, but the amount of hydrogen released at a substrate temperature of at least about 350°C is relatively smaller in the silicon nitride that releases a small amount of hydrogen than in the silicon nitride that releases an excess amount of hydrogen.

[0189] Figure 12 is a graph showing a driving current according to a gate-source voltage when the first interlayer insulating layer is omitted. Figure 13 is a graph showing a driving current according to a gate-source voltage when the first interlayer insulating layer and the second interlayer insulating layer are provided together. Figure 14 is a graph showing a threshold voltage according to an annealing temperature when the first interlayer insulating layer is omitted and when the first interlayer insulating layer and the second interlayer insulating layer are provided together. In Figure 12 and Figure 13 , the horizontal axis shows a gate-source voltage VGS (V), and the vertical axis shows a driving current IDS (A). In Figure 14 , the horizontal axis shows an annealing temperature (°C), and the vertical axis shows a threshold voltage Vth (V).

[0190] Referring toFigures 12 to 14 When the first interlayer insulating layer 113 is omitted and only the second interlayer insulating layer 114 is provided under the second semiconductor layer 145, the threshold voltage Vth(V) is shifted in the negative direction, as compared to when the first and second interlayer insulating layers 113 and 114 are provided together under the second semiconductor layer 145. In other words, when the first and second interlayer insulating layers 113 and 114 are provided together under the second semiconductor layer 145, the threshold voltage Vth(V) is shifted in the positive direction, as compared to when the first interlayer insulating layer 113 is omitted and only the second interlayer insulating layer 114 is provided under the second semiconductor layer 145.

[0191] When the first interlayer insulating layer 113 is omitted and only the second interlayer insulating layer 114 is provided under the second semiconductor layer 145, and when the threshold voltage Vth(V) is shifted in the negative direction and lowered to a level less than or equal to a certain voltage, a short circuit in which a drive current IDS(A) flows continuously occurs.

[0192] As shown in FIG. 6, under the conditions that the channel region CH has a length L of about 3 μm, the annealing temperature is about 320°C, and the total thickness of the interlayer insulating layers is about 1,000 A, the threshold voltage Vth(V) can be about 0.6 V when the first interlayer insulating layer 113 is omitted and only the second interlayer insulating layer 114 is provided, and the threshold voltage Vth(V) can be about 2.94 V when the first and second interlayer insulating layers 113 and 114 are provided together. Figure 14 As shown in FIG. 6, under the conditions that the channel region CH has a length L of about 3 μm, the annealing temperature is about 320°C, and the total thickness of the interlayer insulating layers is about 1,000 A, the threshold voltage Vth(V) can be about 0.6 V when the first interlayer insulating layer 113 is omitted and only the second interlayer insulating layer 114 is provided, and the threshold voltage Vth(V) can be about 2.94 V when the first and second interlayer insulating layers 113 and 114 are provided together.

[0193] As shown in FIG. 6, under the conditions that the channel region CH has a length L of about 3 μm, the annealing temperature is about 320°C, and the total thickness of the interlayer insulating layers is about 1,000 A, the threshold voltage Vth(V) can be about 0.6 V when the first interlayer insulating layer 113 is omitted and only the second interlayer insulating layer 114 is provided, and the threshold voltage Vth(V) can be about 2.94 V when the first and second interlayer insulating layers 113 and 114 are provided together. As shown in FIG. 6, under the conditions that the channel region CH has a length L of about 3 μm, the annealing temperature is about 320°C, and the total thickness of the interlayer insulating layers is about 1,000 A, the threshold voltage Vth(V) can be about 0.6 V when the first interlayer insulating layer 113 is omitted and only the second interlayer insulating layer 114 is provided, and the threshold voltage Vth(V) can be about 2.94 V when the first and second interlayer insulating layers 113 and 114 are provided together.

[0194] As shown in FIG. 6, under the conditions that the channel region CH has a length L of about 3 μm, the annealing temperature is about 320°C, and the total thickness of the interlayer insulating layers is about 1,000 A, the threshold voltage Vth(V) can be about 0.6 V when the first interlayer insulating layer 113 is omitted and only the second interlayer insulating layer 114 is provided, and the threshold voltage Vth(V) can be about 2.94 V when the first and second interlayer insulating layers 113 and 114 are provided together.

[0195] As shown in FIG. 6, under the conditions that the channel region CH has a length L of about 3 μm, the annealing temperature is about 320°C, and the total thickness of the interlayer insulating layers is about 1,000 A, the threshold voltage Vth(V) can be about 0.6 V when the first interlayer insulating layer 113 is omitted and only the second interlayer insulating layer 114 is provided, and the threshold voltage Vth(V) can be about 2.94 V when the first and second interlayer insulating layers 113 and 114 are provided together.​​ Under the conditions described above, when the first interlayer insulating layer 113 is omitted and only the second interlayer insulating layer 114 is provided, the threshold voltage Vth(V) can be approximately -5.75 V on average, and when the first interlayer insulating layer 113 and the second interlayer insulating layer 114 are provided together, the threshold voltage Vth(V) can be approximately -0.02 V on average.

[0196] In the display device 1 according to the embodiment, the first interlayer insulating layer 113 including silicon nitride having excellent hydrogen flow-in characteristics can be further provided below the second semiconductor layer 145 and the second interlayer insulating layer 114, thereby greatly reducing the degree of flow of hydrogen ions into the channel region CH.

[0197] As described above, in the process of forming the first interlayer insulating layer 113, the input amounts of ammonia (NH3), nitrogen (N2), and silane (SiH4) can be adjusted to adjust the ratio of the first bond between nitrogen and hydrogen to the second bond between silicon and hydrogen, thereby reducing the amount of hydrogen released.

[0198] Accordingly, the degree of flow of hydrogen ions into the channel region CH can be reduced to shift the overall threshold voltage Vth(V) of the transistor in the positive direction, thereby ensuring the margin of the threshold voltage Vth(V). The shift of the threshold voltage in the negative direction can be suppressed to prevent the amount of hydrogen ions greater than the reference value from flowing into the second semiconductor layer 145, thereby preventing defects in the switching characteristics of the transistor.

[0199] Hereinafter, display devices according to other embodiments will be described. In the following embodiments, the same reference numerals will be assigned to the same components as those of the above-described embodiments, and the description thereof will be omitted or simplified.

[0200] Figure 15 is a plan view showing one transistor provided in a first region according to another embodiment. Figure 16 is a schematic cross-sectional view showing a display device according to another embodiment. Figure 17 is a plan view showing one transistor provided in a first region according to still another embodiment. Figure 18 is a schematic cross-sectional view showing a display device according to still another embodiment. Figure 19 is a graph showing the threshold voltage when the first interlayer insulating layer is omitted and when the first interlayer insulating layer and the second interlayer insulating layer are provided together, in which SiO(ref.) indicates the case corresponding to the omission of the first interlayer insulating layer, and SiN / SiO indicates the case corresponding to the provision of the first interlayer insulating layer and the second interlayer insulating layer together.

[0201] Figure 15 、 Figure 16 、 Figure 17 and Figure 18A modified example of a transistor of a display device is shown.

[0202] Referring to Figure 15 and Figure 16 A display device 2 according to another embodiment is different from the display device 1 of Figure 5 in that the display device 2 further includes a fourth gate electrode 133 positioned between the second insulating layer 112 and the first interlayer insulating layer 113.

[0203] The fourth gate electrode 133 can include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fourth gate electrode 133 can be a single film or a multi-layer film.

[0204] The fourth gate electrode 133 can be disposed in the second conductive layer 130_1. In other words, the second conductive layer 130_1 can further include the fourth gate electrode 133. However, the disclosure is not limited thereto, and the fourth gate electrode 133 can be disposed in the second conductive layer 130_1 and can also be disposed in other layers.

[0205] The fourth gate electrode 133 can be electrically connected to the first gate electrode 151 through a seventh contact hole CNT7. The same scan signal can be applied to the fourth gate electrode 133 and the first gate electrode 151, and the fourth gate electrode 133 and the first gate electrode 151 can adjust the on / off of the channel of the transistor based on the same scan signal. The transistor structure in which the fourth gate electrode 133 is electrically connected to the first gate electrode 151 through the seventh contact hole CNT7 can be a switching transistor structure.

[0206] The seventh contact hole CNT7 can pass through the third insulating layer 115, the second interlayer insulating layer 114, and the first interlayer insulating layer 113 disposed below the first gate electrode 151.

[0207] The first gate electrode 151 can be disposed to overlap the fourth gate electrode 133 in a thickness direction thereof in a plan view. The planar size of the fourth gate electrode 133 can be substantially the same as the planar size of the first gate electrode 151, but the disclosure is not limited thereto.

[0208] The fourth gate electrode 133 and the first gate electrode 151 can be disposed to further extend to the upper side and the lower side of the second semiconductor layer 145. The seventh contact hole CNT7 can be formed in a portion of the fourth gate electrode 133 and the first gate electrode 151 that further extends compared to the second semiconductor layer 145.

[0209] Referring to Figure 19In the display device 2, even in a structure in which the fourth gate electrode 133 is electrically connected to the first gate electrode 151 through the seventh contact hole CNT7, the first interlayer insulating layer 113 including silicon nitride having excellent hydrogen flow-in characteristics can be further provided below the second semiconductor layer 145 and the second interlayer insulating layer 114, thereby greatly reducing the degree of flow of hydrogen ions into the channel region CH.

[0210] As described above, in the process of forming the first interlayer insulating layer 113, the input amounts of ammonia (NH3), nitrogen (N2), and silane (SiH4) can be adjusted to adjust the ratio of the first bond between nitrogen and hydrogen to the second bond between silicon and hydrogen, thereby reducing the amount of hydrogen released.

[0211] Accordingly, the degree of flow of hydrogen ions into the channel region CH can be reduced to shift the overall threshold voltage Vth(V) of the transistor in the positive direction, thereby ensuring the margin of the threshold voltage Vth(V). The shift of the threshold voltage in the negative direction can be suppressed to prevent the amount of hydrogen ions greater than the reference value from flowing into the second semiconductor layer 145, thereby preventing defects in the switching characteristics of the transistor.

[0212] Referring to Figure 17 and Figure 18 , the display device 3 according to yet another embodiment differs from the display device 1 of Figure 5 in that the display device 3 further includes a fourth gate electrode 133_1 located between the second insulating layer 112 and the first interlayer insulating layer 113, and the first source electrode 161_1 or the first drain electrode 163 additionally contacts the fourth gate electrode 133_1 (wherein the case in which the first drain electrode 163 described hereinafter contacts the fourth gate electrode 133_1 is an alternative example, not shown).

[0213] The fourth gate electrode 133_1 can include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fourth gate electrode 133_1 can be a single film or a multilayer film.

[0214] The fourth gate electrode 133_1 can be provided in the second conductive layer 130_2, but as described above with reference to Figure 15 and Figure 16 , the present disclosure is of course not limited thereto.

[0215] The fourth gate electrode 133_1 can be electrically connected to the first source electrode 161_1 or the first drain electrode 163 through the eighth contact hole CNT8. Among them, the transistor structure in which the fourth gate electrode 133_1 is electrically connected to the first source electrode 161_1 or the first drain electrode 163 through the eighth contact hole CNT8 can be a driving transistor structure.

[0216] The eighth contact hole CNT8 can pass through the third interlayer insulating layer 116, the second interlayer insulating layer 114, and the first interlayer insulating layer 113 disposed below the first source electrode 161_1 or the first drain electrode 163. The fourth gate electrode 133_1 can further extend outward from the second semiconductor layer 145. In the region in which the fourth gate electrode 133_1 further extends outward from the second semiconductor layer 145, the fourth gate electrode 133_1 can be electrically connected to the first source electrode 161_1 or the first drain electrode 163 through the eighth contact hole CNT8.

[0217] The fourth gate electrode 133_1 can be disposed to overlap the first gate electrode 151 in a thickness direction thereof in a plan view, and a planar size thereof can be greater than a planar size of the first gate electrode 151.

[0218] Referring again to Figure 19 , in the display device 3, even in the structure in which the fourth gate electrode 133_1 is electrically connected to the first source electrode 161_1 or the first drain electrode 163 through the eighth contact hole CNT8, the first interlayer insulating layer 113 including silicon nitride having excellent hydrogen flow-in characteristics can be further disposed below the second semiconductor layer 145 and the second interlayer insulating layer 114, thereby greatly reducing the degree of flow of hydrogen ions into the channel region CH.

[0219] As described above, in the process of forming the first interlayer insulating layer 113, the input amounts of ammonia (NH3), nitrogen (N2), and silane (SiH4) can be adjusted to adjust the ratio of the first bond between nitrogen and hydrogen to the second bond between silicon and hydrogen, thereby reducing the amount of hydrogen released.

[0220] Figure 20 is a cross-sectional view illustrating a display device according to still another embodiment.

[0221] Referring again to Figure 20 , the display device 4 according to this embodiment is different from the display device 1 of Figure 5 in that the first interlayer insulating layer 113_1 includes a stacked film.

[0222] More specifically, the first interlayer insulating layer 113_1 includes a stacked film having a first sub-insulating layer 113a and a second sub-insulating layer 113b. The first sub-insulating layer 113a can include the silicon nitride that releases a small amount of hydrogen described above, and the second sub-insulating layer 113b disposed between the first sub-insulating layer 113a and the second interlayer insulating layer 114 can include the silicon nitride that releases a minimum amount of hydrogen described above.

[0223] Figure 21 is a cross-sectional view illustrating a display device according to still another embodiment.

[0224] Referring to Figure 21 , the display device 5 according to this embodiment differs from the display device 1 of Figure 5 in that the first interlayer insulating layer includes a stacked film, and the second interlayer insulating layer includes a stacked film.

[0225] More specifically, the first sub-insulating layer 113c of the first interlayer insulating layer is disposed between the second insulating layer 112 and the second semiconductor layer 145. The first sub-insulating layer 114a of the second interlayer insulating layer can be disposed between the first sub-insulating layer 113c of the first interlayer insulating layer and the second semiconductor layer 145. The second sub-insulating layer 113d of the first interlayer insulating layer can be disposed between the first sub-insulating layer 114a of the second interlayer insulating layer and the second semiconductor layer 145. The second sub-insulating layer 114b of the second interlayer insulating layer can be disposed between the second sub-insulating layer 113d of the first interlayer insulating layer and the second semiconductor layer 145.

[0226] The first sub-insulating layer 114a and the second sub-insulating layer 114b of the second interlayer insulating layer can be made of the same material.

[0227] The first sub-insulating layer 113c of the first interlayer insulating layer can include the silicon nitride that releases a small amount of hydrogen described above, and the second sub-insulating layer 113d of the first interlayer insulating layer can include the silicon nitride that releases a minimum amount of hydrogen described above.

[0228] According to the display device and the method of manufacturing the display device according to the embodiments, short-circuiting of the oxide semiconductor can be prevented.

[0229] Effects of the present disclosure are not limited to the embodiments set forth herein and include more diverse effects in the present specification.

[0230] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that the present disclosure can be implemented in other detailed forms without changing the technical spirit and essential characteristics of the present disclosure. Therefore, it should be understood that the embodiments described herein are illustrative in all aspects and are not restrictive.

Claims

1. A display device, wherein, The display device includes: a base substrate including a display area and a non-display area surrounding the display area; a first interlayer insulating layer disposed on the base substrate; a second interlayer insulating layer disposed on the first interlayer insulating layer; a first semiconductor layer disposed on the second interlayer insulating layer; a first gate insulating layer disposed on the first semiconductor layer; a first gate electrode disposed on the first gate insulating layer; a third interlayer insulating layer disposed on the first gate electrode; a first source electrode and a first drain electrode disposed on the third interlayer insulating layer and electrically connected to the first semiconductor layer; a second semiconductor layer disposed between the base substrate and the first interlayer insulating layer; a second gate insulating layer disposed between the second semiconductor layer and the first interlayer insulating layer; a second gate electrode disposed between the second gate insulating layer and the first interlayer insulating layer; a third gate insulating layer disposed between the second gate electrode and the first interlayer insulating layer; and a second source electrode and a second drain electrode disposed on the third gate insulating layer and electrically connected to the second semiconductor layer, wherein a material of the first interlayer insulating layer and a material of the second interlayer insulating layer are different from each other, and the first interlayer insulating layer does not contact the second gate electrode.

2. The display device according to claim 1, wherein: the second interlayer insulating layer includes silicon oxide; the first interlayer insulating layer includes nitrogen, hydrogen, and silicon; and in the first interlayer insulating layer, the nitrogen and the hydrogen are bonded by first bonds, the silicon and the hydrogen are bonded by second bonds, and a ratio of the first bonds to the second bonds is in a range of 15 to 30.

3. The display device according to claim 2, wherein a release amount of the hydrogen of the first interlayer insulating layer is at most 2.0E-09 at a substrate temperature of at least 350 °C.

4. The display device according to claim 3, wherein: the nitrogen, the hydrogen, and the silicon included in the first interlayer insulating layer are formed by ammonia gas, silane, and nitrogen gas; a supply ratio of the ammonia gas to the silane is at least 5; and a supply ratio of the nitrogen gas to the silane is at least 30.

5. The display device according to claim 3, wherein: the nitrogen, the hydrogen, and the silicon included in the first interlayer insulating layer are formed by ammonia gas, silane, and nitrogen gas; a supply ratio of the ammonia gas to the silane is 0; and a supply ratio of the nitrogen gas to the silane is at least 150.

6. The display device according to claim 1, wherein the first semiconductor layer includes an oxide.

7. The display device according to claim 1, wherein the second semiconductor layer includes crystalline silicon.

8. The display device according to claim 1, wherein a width of the first gate insulating layer is smaller than a width of the first semiconductor layer.

9. The display device according to claim 8, wherein: the first gate electrode overlaps the first gate insulating layer; and a width of the first gate electrode is smaller than the width of the first semiconductor layer.

10. The display device according to claim 1, wherein the display device further includes a fourth gate electrode between the base substrate and the first interlayer insulating layer, wherein the first gate electrode and the fourth gate electrode are electrically connected.

11. The display device according to claim 1, wherein the display device further includes a fourth gate electrode between the base substrate and the first interlayer insulating layer, The fourth gate electrode has a width greater than a width of the first semiconductor layer. The first source electrode or the first drain electrode is electrically connected to the fourth gate electrode.

12. The display device according to claim 1, wherein: the display region includes a first region and a second region adjacent to the first region; the first semiconductor layer is provided in the first region; and the second semiconductor layer is provided in the second region.

13. The display device of claim 12, wherein, The display device further includes a third gate electrode provided between the third gate insulating layer and the second source electrode and the second drain electrode, wherein the second gate electrode and the third gate electrode form a capacitor.

14. The display device of claim 12, wherein, The display device further includes: a switching transistor including the first semiconductor layer, the first gate electrode, and the first source electrode and the first drain electrode; and a driver transistor including the second semiconductor layer, the second gate electrode, and the second source electrode and the second drain electrode.

15. A method of manufacturing a display device, wherein, The method includes: forming a first interlayer insulating layer on a base substrate; forming a second interlayer insulating layer including silicon oxide on the first interlayer insulating layer; and forming a first semiconductor layer on the second interlayer insulating layer, wherein the first interlayer insulating layer includes nitrogen, hydrogen, and silicon, wherein, in the first interlayer insulating layer, the nitrogen and the hydrogen are bonded by a first bond, the silicon and the hydrogen are bonded by a second bond, and a ratio of the first bond to the second bond is in a range of 15 to 30.

16. The method of claim 15, wherein, The first interlayer insulating layer has a release amount of the hydrogen of at most 2.0E-09 at a substrate temperature of at least 350 °C.

17. The method according to claim 16, wherein: forming the first interlayer insulating layer includes supplying ammonia gas, silane, and nitrogen gas; and a supply ratio of the ammonia gas to the silane is at least 5.

18. The method according to claim 17, wherein, a supply ratio of the nitrogen gas to the silane is at least 30.

19. The method according to claim 16, wherein: forming the first interlayer insulating layer includes supplying ammonia gas, silane, and nitrogen gas; and a supply ratio of the ammonia gas to the silane is 0.

20. The method according to claim 19, wherein, a supply ratio of the nitrogen gas to the silane is at least 150.

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