Semiconductor integrated circuit for driving a display device

Abstract

The present invention relates to a semiconductor integrated circuit for driving a display device, and more particularly to a semiconductor integrated circuit for driving a display to supply a gamma voltage to each DAC via a gamma bus to which a plurality of gamma voltage circuits are connected.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit for driving a display device. Background Art

[0002] As society becomes more information-oriented, the demand for products requiring display devices has increased. In recent years, various display devices such as liquid crystal display devices, plasma display devices, or organic light emitting diode display devices are used.

[0003] Therefore, various technologies for improving the image quality of display devices are being developed. One of these technologies is a technology for high-speed driving of display panels. As the number of pixels arranged on a display panel increases to improve image quality, a technology for high-speed driving of a display panel is required to drive all of the numerous pixels in the same period of time as before or in a shorter period of time than before.

[0004] The display panel may be driven by a data driving device called a source driver or a column driver, and the above-mentioned high-speed driving technology is related to the data driving device. The data driving device generally receives image data representing the grayscale of each pixel, converts the image data into a data voltage in an analog form, and supplies the data voltage to each pixel to drive the display panel. In order to drive the display panel at high speed, the above process needs to be performed at high speed. Summary of the invention

[0005] In this context, one aspect of the present invention provides a technique for high-speed driving a display panel. Another aspect of the present invention provides a technique for high-speed processing of signals in a data driver. Yet another aspect of the present invention provides a technique for high-speed processing of signals in a data driver implemented in the form of a semiconductor integrated circuit (IC).

[0006] To this end, an embodiment of the present invention provides a semiconductor integrated circuit including a plurality of channel circuits, a gamma bus, and a plurality of gamma voltage circuits.

[0007] The semiconductor integrated circuit for display driving may be formed of a single semiconductor package or one integrated circuit.

[0008] Each channel circuit may include a digital-to-analog converter (DAC) for selecting one of a plurality of gamma voltages according to pixel image data and generating a data voltage, and each channel circuit supplies the data voltage to a data line connected to a sub-pixel.

[0009] The gamma bus may provide a path through which the plurality of gamma voltages are transmitted to a DAC of each channel circuit.

[0010] Each gamma voltage circuit may generate the plurality of gamma voltages by dividing a reference voltage, and is connected to the gamma bus at a voltage division point.

[0011] The plurality of channel circuits may be arranged along a first direction, and the plurality of gamma voltage circuits may be arranged in a manner of being spaced apart from each other along the first direction.

[0012] Each pixel may include a plurality of sub-pixels, and the gamma bus may include a plurality of sub-gamma buses. A channel circuit for driving a first sub-pixel of the plurality of sub-pixels and a channel circuit for driving a second sub-pixel may be connected to a first sub-gamma bus, and a channel circuit for driving a third sub-pixel may be connected to a second sub-gamma bus. Here, the number of gamma voltage circuits connected to the first sub-gamma bus may be greater than the number of gamma voltage circuits connected to the second sub-gamma bus.

[0013] Each gamma voltage circuit may include: a first resistor string for dividing the reference voltage; a decoder for selecting a plurality of intermediate voltages from the first resistor string; a gamma buffer for buffering the intermediate voltages; and a second resistor string for generating the plurality of gamma voltages by dividing the voltage output from the gamma buffer. Here, the decoder may receive a decoded signal and select the plurality of intermediate voltages according to the decoded signal.

[0014] Each sub-pixel may include a red (R), green (G) or blue (B) organic light emitting diode (OLED), and the plurality of gamma voltages may have different gamma curves for each RGB OLED. The semiconductor integrated circuit may include separate gamma voltage circuits for each color sub-pixel to form different gamma curves for each RGB OLED.

[0015] Each DAC may include a switch array including a plurality of switches, and one of the plurality of gamma voltages is selected by turning on one of the plurality of switches.

[0016] The reference voltage may be supplied to the plurality of gamma voltage circuits from a same source.

[0017] Another embodiment provides a semiconductor integrated circuit including a timing control circuit, a plurality of channel circuits, a gamma bus, and a plurality of gamma voltage circuits.

[0018] The semiconductor integrated circuit for display driving may be a single semiconductor package or an integrated circuit (IC).

[0019] The timing control circuit may supply pixel image data and a synchronization signal for a display period to a data driving circuit including the plurality of channel circuits.

[0020] Each channel circuit may include a digital-to-analog converter (DAC) for selecting one of a plurality of gamma voltages according to the pixel image data and generating a data voltage, and each channel circuit supplies the data voltage to a data line connected to a sub-pixel.

[0021] The gamma bus may provide a path through which the plurality of gamma voltages are transmitted to a DAC of each channel circuit.

[0022] Each gamma voltage circuit may generate the plurality of gamma voltages by dividing a reference voltage, and is connected to the gamma bus at a voltage division point.

[0023] The semiconductor integrated circuit may further include a data bus for transmitting the pixel image data. Each channel circuit may further include a latch circuit for latching the pixel image data from the data bus.

[0024] The semiconductor integrated circuit may further include a gate driving circuit for generating a gate driving signal of a thin film transistor (TFT) arranged in each sub-pixel according to a control signal received from the timing control circuit.

[0025] The semiconductor integrated circuit may further include a plurality of output pads respectively connected to the data lines. The plurality of channel circuits may be arranged in parallel with the plurality of output pads, and the plurality of gamma voltage circuits may be arranged between the plurality of channel circuits at fixed intervals.

[0026] The plurality of channel circuits may be divided into a plurality of channel circuit blocks by the plurality of gamma voltage circuits. A size of an outermost channel circuit block may be smaller than a size of an inner channel circuit block.

[0027] The gamma voltage circuit may receive a decoded signal and adjust the plurality of gamma voltages according to the decoded signal. The timing control circuit may send the decoded signal to a corresponding gamma voltage circuit.

[0028] As described above, according to the present invention, a display panel can be driven at high speed, and a signal in a data driving device can be processed at high speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a structural diagram of a display device according to an embodiment;

[0030] Figure 2 is a structural diagram of a data driving device according to an embodiment;

[0031] Figure 3is a diagram showing a configuration of a gamma voltage circuit and a DAC according to an embodiment;

[0032] Figure 4 is a diagram showing a configuration of a gamma voltage circuit and a channel circuit according to an embodiment;

[0033] Figure 5 is a diagram of an example of a configuration of a gamma voltage circuit for each sub-pixel;

[0034] Figure 6 is a diagram showing a configuration of a semiconductor integrated circuit according to an embodiment;

[0035] Figure 7 is a structural diagram of a first example of a gamma voltage circuit according to an embodiment;

[0036] Figure 8 is a structural diagram of a second example of a gamma voltage circuit according to the embodiment; and

[0037] Fig. 9 is a diagram illustrating a process of generating a data voltage using a gamma voltage in a data driving device. DETAILED DESCRIPTION

[0038] Figure 1 is a structural diagram of a display device according to an embodiment.

[0039] refer to Figure 1 , the display device 100 may include a panel 110 , a data driving device 120 , a gate driving device 130 , and a timing control device 140 .

[0040] On the panel 110, a plurality of data lines DL and a plurality of gate lines GL may be arranged, and a plurality of sub-pixels may be arranged in a matrix. Each sub-pixel may be connected to the data line DL according to a scanning signal supplied via the gate line GL. In addition, the brightness of each sub-pixel may be adjusted according to a data voltage supplied via the data line DL.

[0041] The panel 110 may be a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) panel, or other types of panels. If the panel 110 is an OLED panel, an OLED and a plurality of transistors connected to the OLED may be arranged in each sub-pixel. The gate line GL and the data line DL may be connected to a plurality of transistors of each sub-pixel. When a scan signal indicating switching on is supplied via the gate line GL, one of the plurality of transistors may be switched on, and the data line DL may be connected to the gate of another transistor. According to the level of the data voltage supplied via the data line DL, the level of the current flowing to the another transistor is adjusted to adjust the brightness of the OLED. Hereinafter, for ease of description, an embodiment in which the panel 110 is an OLED panel will be described, but the present invention is not limited thereto.

[0042] The gate driving device 130 may supply a scan signal via the gate line GL, and the data driving device 120 may supply a data voltage via the data line DL. The gate driving device 130 and the data driving device 120 may receive a control signal or a synchronization signal from the timing control device 140, and determine the driving timing of each sub-pixel according to the control signal or the synchronization signal.

[0043] The timing control device 140 may send the image data RGB representing the grayscale of each sub-pixel to the data driving device 120. The timing control device 140 may receive the image data RGB from an external device, convert the image data RGB into data suitable for the data driving device 120, and send the converted image data to the data driving device 120. When the panel 110 is an OLED panel, the timing control device 140 may detect a change in the characteristics of each sub-pixel of the OLED panel, convert the image data RGB so as to compensate for the change in the characteristics, and send the converted image data to the data driving device 120.

[0044] The data driving device 120 may extract pixel image data of each sub-pixel from the image data RGB, generate a data voltage according to the pixel image data, and supply the generated data voltage through the data line DL connected to each sub-pixel.

[0045] The data driving device 120 may be implemented in the form of a semiconductor integrated circuit. When the data driving device 120 is implemented in the form of a semiconductor integrated circuit, the circuit forming the data driving device 120 may be implemented in the form of an integrated circuit and surrounded by a semiconductor package. The data driving device 120, the gate driving device 130, and the timing control device 140 may each be implemented in the form of a separate semiconductor integrated circuit, or all may be implemented in the form of a single semiconductor integrated circuit. For example, the data driving device 120, the gate driving device 130, and the timing control device 140 may all be included in a single semiconductor package.

[0046] Figure 2 is a structural diagram of a data driving device according to an embodiment.

[0047] refer to Figure 2 The data driving device 120 may include a plurality of channel circuits CH, a plurality of gamma voltage circuits 210 a and 210 b , a data bus Dbus, and a gamma bus Gbus.

[0048] The data driving device 120 may receive image data from a data processing circuit (not shown), extract pixel image data pRGB from the image data, and transmit the pixel image data pRGB to a data bus Dbus.

[0049] The data bus Dbus as a parallel communication bus may include as many bus lines as the number of bits of the pixel image data pRGB. For example, when the pixel image data pRGB includes P (P is a natural number) bits, the data bus Dbus may include P bus lines.

[0050] The pixel image data pRGB sent to the data bus Dbus may be distributed to the corresponding channel circuits CH sequentially or non-sequentially by the shift register.

[0051] The channel circuit CH may include a shift register SR, a latch LT, a digital-to-analog converter (DAC), and an output buffer BR. The pixel image data pRGB sent to the data bus Dbus may be temporarily stored in the latch LT by the shift register SR, and then may be converted into a data voltage Vdata in analog form in the DAC. The data voltage Vdata may be output to the data line by the output buffer BF.

[0052] The data driving device 120 may include two buses: one bus is a data bus Dbus through which the pixel image data pRGB is transmitted, and the other bus is a gamma bus Gbus through which the gamma voltage is transmitted.

[0053] A plurality of gamma voltages may be provided to the DAC via a gamma bus Gbus. Then, the DAC may select one of the plurality of gamma voltages according to the pixel image data pRGB and generate a data voltage Vdata.

[0054] The gamma voltages may be generated by the gamma voltage circuits 210a and 210b. The gamma voltage circuits 210a and 210b may generate the gamma voltages and supply the gamma voltages to the DAC via the gamma bus Gbus.

[0055] A plurality of gamma voltage circuits 210a, 210b may be connected to a gamma bus Gbus. In the case of using only one gamma voltage circuit, when the channel circuit is located far from the gamma voltage circuit, the RC delay increases, and this may result in a restriction on the driving speed of the channel circuit. The designer may increase the driving current or bias current of the gamma voltage circuit to relax the restriction, however, this may result in an increase in the size (particularly its height) of the gamma voltage circuit.

[0056] According to an embodiment, the data driving device 120 may improve the gamma voltage supply capability and minimize the above-mentioned RC delay by connecting the plurality of gamma voltage circuits 210 a , 210 b to the gamma bus Gbus.

[0057] The channel circuit CH may be connected to the gamma voltage circuits 210a and 210b via the gamma bus Gbus. Such an embodiment has the following advantages: compared with the case where the channel circuit is connected to the gamma voltage circuit in a 1:1 manner, the wiring is simpler.

[0058] The gamma bus Gbus may include a plurality of bus lines. The gamma bus Gbus may include Q (Q is a natural number) bus lines. Here, in the case where the pixel image data pRGB includes P bits, the relationship between P and Q (which is the number of bus lines of the gamma bus Gbus) may be Q≤2^P.

[0059] Preferably, the plurality of gamma voltage circuits 210a, 210b are arranged spaced apart from each other along the gamma bus Gbus. When the gamma voltage circuits 210a, 210b are respectively assigned to predetermined areas to supply gamma voltages along the gamma bus Gbus, all channel circuits CH may be uniformly provided with gamma voltages.

[0060] Figure 3 is a diagram showing a configuration of a gamma voltage circuit and a DAC according to an embodiment.

[0061] refer to Figure 3 , a plurality of gamma voltage circuits 310 a , 310 b , . . . , 310 n and a plurality of DACs may be connected to a gamma bus Gbus.

[0062] A plurality of gamma voltage circuits 310a, 310b, ..., 310n may be arranged in a spaced manner along the gamma bus. Here, each distance between two adjacent gamma voltage circuits may be almost the same. Alternatively, each number of DACs arranged between two adjacent gamma voltage circuits may be almost the same.

[0063] Each gamma voltage circuit may output an s gamma voltage, and the s gamma voltages output from each gamma voltage circuit may be different. For example, the first s gamma voltage sGMAa output from the first gamma voltage circuit 310a, the second s gamma voltage sGMAb output from the second gamma voltage circuit 310b, and the Nth s gamma voltage sGMAn output from the Nth gamma voltage circuit 310n may be different from each other. In the case where the gamma voltages used by two adjacent DACs are very different, there may be defects in the image quality such as vertical lines on the panel. However, the data driving device using the structure using the gamma bus Gbus according to the embodiment can allow the possibility of such defects in image quality to be reduced.

[0064] For example, in an embodiment, the adjacent first DAC 320a and the second DAC 320b are not greatly affected by the voltage difference between the gamma voltage circuits 310a, 310b, ..., 310n. The adjacent first DAC 320a and the second DAC 320b may actually be affected by the voltage of the connection nodes n1 and n2 in the gamma bus Gbus. However, if the adjacent first DAC 320a and the second DAC 320b are respectively connected to the nodes n1 and n2 that are close enough to each other, the difference between the voltages of the respective nodes n1 and n2 is not large, and therefore the difference between the r gamma voltages rGMAa and rGMAb respectively received by the nodes n1 and n2 is not large.

[0065] Figure 4 is a diagram showing a configuration of a gamma voltage circuit and a channel circuit according to an embodiment.

[0066] refer to Figure 4 , the plurality of channel circuits CH may be divided into a plurality of channel circuit blocks CHBa, CHBb, CHBc, CHBd, and the gamma voltage circuits 410a, 410b, 410c may each be disposed between two adjacent channel circuit blocks.

[0067] A plurality of channel circuits CH and a plurality of channel circuit blocks CHBa, CHBb, CHBc, CHBd may be arranged along a first direction X (eg, along a transverse direction of the panel), and a plurality of gamma voltage circuits 410a, 410b, 410c may be arranged along the first direction X in a manner spaced apart from each other.

[0068] The loads of the channel circuits carried by the gamma voltage circuits 410a, 410b, and 410c may be almost equal. For such an equal distribution of the load, the size of the outermost channel circuit blocks CHBa and CHBd may be smaller than the size of the inner channel circuit blocks CHBb and CHBc. For example, the size of the outermost channel circuit blocks CHBa and CHBd may be about half the size of the inner channel circuit blocks CHBb and CHBc. Here, the size may refer to the area of ​​the circuit or the number of channel circuits included in the channel circuit block.

[0069] The gamma bus Gbus may be arranged to pass through the plurality of channel circuits CH and the plurality of channel circuit blocks CHBa, CHBb, CHBc, CHBd along the first direction X. The plurality of gamma voltage circuits 410a, 410b, 410c may be arranged on one side of a plane bisected by the gamma bus Gbus.

[0070] In the panel, a pixel may include a plurality of sub-pixels. The data driving device may include a gamma voltage circuit for each sub-pixel to supply different gamma voltages to each different type of sub-pixel.

[0071] Figure 5 is a diagram showing an example of a configuration of a gamma voltage circuit for each sub-pixel.

[0072] refer to Figure 5 In the panel 110, each pixel PX may include a plurality of sub-pixels (R: red, G: green, B: blue, G: green). Each sub-pixel may have a different color, but some of these sub-pixels may have the same color. For example, the pixel PX may include a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and another green sub-pixel G. For another example, the pixel PX may include a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W.

[0073] The data driving device may have at least one gamma voltage circuit for each sub-pixel included in the pixel PX. For example, in the case where the pixel PX includes four sub-pixels, the data driving device may include a gamma voltage circuit for the first sub-pixel, a gamma voltage circuit for the second sub-pixel, a gamma voltage circuit for the third sub-pixel, and a gamma voltage circuit for the fourth sub-pixel. In addition, the data driving device may include a plurality of gamma voltage circuits for each sub-pixel. For example, the data driving device may include a plurality of gamma voltage circuits for the first sub-pixel and a plurality of gamma voltage circuits for the second sub-pixel.

[0074] The data driving device may include at least one gamma voltage circuit for each type of sub-pixel. For example, the data driving device may include at least one R gamma voltage circuit 510a for supplying a gamma voltage to a red sub-pixel, at least one G gamma voltage circuit 510b for supplying a gamma voltage to a green sub-pixel, and at least one B gamma voltage circuit 510c for supplying a gamma voltage to a blue sub-pixel.

[0075] The gamma bus may include a plurality of sub-gamma buses GbusR, GbusG, and GbusB. Each pixel PX may include a plurality of sub-pixels RGBG. A channel circuit for driving a first sub-pixel (e.g., a green sub-pixel) of the plurality of sub-pixels and a channel circuit for driving a second pixel (e.g., another green sub-pixel) may be connected to the first sub-gamma bus GbusG. A channel circuit for driving a third sub-pixel (e.g., a red sub-pixel) may be connected to the second sub-gamma bus GbusR, and a channel circuit for driving a fourth sub-pixel (e.g., a blue sub-pixel) may be connected to the third sub-gamma bus GbusB.

[0076] Here, the number of gamma voltage circuits (e.g., G gamma voltage circuit 510b) connected to the first sub-gamma bus GbusG may be greater than the number of gamma voltage circuits (e.g., R gamma voltage circuit 510a) connected to the second sub-gamma bus GbusR, or the number of gamma voltage circuits (e.g., B gamma voltage circuit 510c) connected to the third sub-gamma bus GbusB.

[0077] For another example, a channel circuit for driving a first sub-pixel (e.g., a green sub-pixel) among a plurality of sub-pixels and a channel circuit for driving a second sub-pixel (e.g., another green sub-pixel) may be connected to a sub-gamma bus (not shown), while a channel circuit for driving a third sub-pixel (e.g., a red sub-pixel) and a channel circuit for driving a fourth sub-pixel (e.g., a blue sub-pixel) may be connected to another sub-gamma bus (not shown). Here, the gamma bus may include two sub-gamma buses.

[0078] Figure 6 is a diagram showing a configuration of a semiconductor integrated circuit according to an embodiment.

[0079] refer to Figure 6 , on the semiconductor integrated circuit 600 , a plurality of channel circuit blocks CHBa, CHBb, CHBc, a plurality of gamma voltage circuits 610 , other circuit blocks 620 , a plurality of output pads 630 , and a plurality of input pads 640 may be arranged.

[0080] Each channel circuit block CHBa, CHBb, CHBc may include a plurality of channel circuits, and these channel circuits may respectively include a DAC sharing a gamma bus. Each gamma voltage circuit 610 may be arranged between two adjacent channel circuit blocks CHBa, CHBb, CHBc. Here, the area of ​​the outermost channel circuit blocks CHBa, CHBc may be smaller than the area of ​​the inner channel circuit block CHBb.

[0081] The channel circuits included in the channel circuit blocks CHBa, CHBb, CHBc may be respectively connected to the output pads 630. The output pads 630 may be respectively connected to the data lines.

[0082] The plurality of channel circuits may be arranged in parallel with the direction in which the output pads 630 are arranged, and the plurality of gamma voltage circuits 610 may be arranged in a manner of being spaced apart from each other along the direction in which the output pads 630 are arranged.

[0083] The channel circuit blocks CHBa, CHBb, CHBc and the gamma voltage circuit 610 may be arranged at positions close to the output pads 630 , and the other circuit blocks 620 may be arranged at positions close to the input pads 640 .

[0084] Other circuit blocks 620 may include a gate driver and a timing control device. The gate driver may receive a synchronization signal from the timing control device, generate a gate control signal, and then send the gate control signal to a panel gate (GIP) circuit. The timing control device may receive image data from an external device, process the image data, and send the image data to a data driver including channel circuit blocks CHBa, CHBb, and CHBc. Other circuit blocks 620 may also include a random access memory (RAM), a communication circuit, and a DC-DC converter.

[0085] The timing control device may send a signal (e.g., a decoded signal) for controlling the gamma voltage circuit 610 to the data driving device. The gamma voltage circuit 610 may use such a signal to adjust the gamma curve or perform other controls. In the case where the semiconductor integrated circuit 600 includes a timing control device and a plurality of gamma voltage circuits 610, it is easier for the timing control device to control each gamma voltage circuit 610 using a separate signal. In the case where a plurality of gamma voltage circuits 610 are arranged in the semiconductor integrated circuit, there may be differences between the gamma voltage circuits 610. However, in the above structure, the timing control device can minimize these differences by controlling each gamma voltage circuit 610 individually.

[0086] Figure 7 is a structural diagram of a first example of a gamma voltage circuit according to an embodiment.

[0087] refer to Figure 7 , the gamma voltage circuit 700 may include a first resistor string 710 , a decoder 720 , a gamma buffer 730 , and a second resistor string 740 .

[0088] The first resistor string 710 may include a plurality of resistors connected in series, and these resistors are used to divide the reference voltages VH and VL. The first resistor string 710 may be connected to a reference high voltage VH at one end thereof, and to a reference low voltage at the other end thereof. In some of the plurality of resistors constituting the first resistor string 710, a node may be formed and a divided voltage may be output via such a node. Here, the resistors constituting the first resistor string 710 may have almost the same resistance value.

[0089] In the data driving device, a plurality of gamma voltage circuits 700 may be arranged, and the reference voltages VH, VL may be provided to the plurality of gamma voltage circuits 700 through the same source. The plurality of gamma voltage circuits 700 may use the same source to minimize the difference between the gamma voltages.

[0090] The decoder 720 may include a plurality of decoding blocks PDEC, and use the plurality of decoding blocks PDEC to select a plurality of intermediate voltages Vc1-Vc5 from the first resistor string 710. For example, each decoding block PDEC may receive a plurality of divided voltages from the first resistor string 710, select one of the plurality of divided voltages, and output the selected voltage as the intermediate voltages Vc1-Vc5.

[0091] The decoder 720 may receive a decoding signal SDEC and select a plurality of intermediate voltages Vc1 to Vc5 according to the decoding signal SDEC. For example, each decoding block PDEC may receive a decoding signal SDEC individually, or the decoding blocks PDEC may receive a decoding signal SDEC in common and select one of a plurality of divided voltages according to a value indicated by the decoding signal SDEC to output the selected voltage as the intermediate voltages Vc1 to Vc5.

[0092] Such a process may be referred to as programmable decoding. According to such programmable decoding, the gamma curve may be finely adjusted and the differences that may exist between multiple gamma voltage circuits may be minimized.

[0093] The intermediate voltages Vc1 ˜ Vc5 output from the decoder 720 may be transmitted to the gamma buffer 730 . The gamma buffer 730 may buffer the intermediate voltages Vc1 ˜ Vc5 and then output the intermediate voltages Vc1 ˜ Vc5 to the second resistor string 740 .

[0094] The second resistor string 740 may include a plurality of resistors connected in series, and divide the reference voltages VH, VL and the intermediate voltages Vc1 ˜ Vc5 using the resistors to generate a plurality of gamma voltages Vgm0 ˜ Vgm1023 .

[0095] The second resistor string 740 may receive reference voltages VH, VL, and a voltage output from the gamma buffer 730. The reference high voltage VH may be connected to one end of the second resistor string 740, and the reference low voltage VL may be connected to the other end of the second resistor string 740. The voltage output from the gamma buffer 730 may be connected to nodes formed in some of the plurality of resistors constituting the second resistor string 740.

[0096] The second resistor string 740 may output the gamma voltages Vgm0 ˜ Vgm1023 generated in this manner to the gamma bus.

[0097] Figure 8 is a structural diagram of a second example of a gamma voltage circuit according to the embodiment.

[0098] refer to Figure 8 , the gamma voltage circuit 800 may include a first resistor string 810 , a gamma buffer 830 , and a second resistor string 840 .

[0099] The first resistor string 810 may include a plurality of resistors connected in series, and these resistors are used to divide the reference voltages VH and VL. The first resistor string 810 may be connected to a reference high voltage VH at one end and to a reference low voltage VL at the other end. In some of the plurality of resistors constituting the first resistor string 810, nodes may be formed and intermediate voltages Vc1 to Vc5 may be output via these nodes. Here, the resistors constituting the first resistor string 810 may have almost the same resistance value.

[0100] The gamma buffer 830 may buffer the intermediate voltages Vc1 ˜ Vc5 and then output the intermediate voltages Vc1 ˜ Vc5 to the second resistor string 840 .

[0101] The second resistor string 840 may include a plurality of resistors connected in series, and divide the reference voltages VH, VL and the intermediate voltages Vc1 ˜ Vc5 using the resistors to generate a plurality of gamma voltages Vgm0 ˜ Vgm1023 .

[0102] The second resistor string 840 may receive reference voltages VH, VL, and a voltage output from the gamma buffer 830. The reference high voltage VH may be connected to one end of the second resistor string 840, and the reference low voltage VL may be connected to the other end of the second resistor string 840. The voltage output from the gamma buffer 830 may be connected to nodes formed in some of the plurality of resistors constituting the second resistor string 840.

[0103] The second resistor string 840 may output the gamma voltages Vgm0 ˜ Vgm1023 generated in this manner to the gamma bus Gbus.

[0104] Fig. 9 is a diagram illustrating a process of generating a data voltage using a gamma voltage in a data driving device.

[0105] refer to Fig. 9 The data driving device 900 may include a plurality of channel circuits CH, and each channel circuit CH may include a switch array SA and an output buffer BF.

[0106] The gamma bus Gbus may be arranged to pass through each channel circuit CH and be connected to a switch array of each channel circuit CH.

[0107] Each switch array SA may include a plurality of switches. Each switch may be connected to each bus line constituting the gamma bus Gbus. Gamma voltages Vgm0 to Vgm1023 are supplied via each bus line, and the switch array SA may select one of the bus lines so that the gamma voltage of the selected bus line may be output as a data voltage.

[0108] The output buffer BF may buffer the data voltage and output the data voltage.

[0109] The switch array SA may select one of the plurality of gamma voltages Vgm0 to Vgm1023 according to the grayscale of the pixel image data pRGB. The switch array SA may be included in the above-mentioned DAC.

[0110] CROSS-REFERENCE TO RELATED APPLICATIONS

[0111] This application claims priority to Korean Patent Application No. 10-2019-0128479, filed on October 16, 2019, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor integrated circuit for driving a display, the semiconductor integrated circuit comprising: a data bus that receives and sends pixel image data; a plurality of channel circuits, the plurality of channel circuits being connected to the corresponding data bus, each of the plurality of channel circuits comprising a shift register, a latch, a digital-to-analog converter DAC and an output buffer connected to the data bus, the DAC being used to select one of a plurality of gamma voltages according to pixel image data and generate a data voltage, and each of the channel circuits supplying the data voltage via a data line connected to a sub-pixel; a gamma bus for providing a path through which the plurality of gamma voltages are sent to the DACs of the corresponding channel circuits; as well as a plurality of gamma voltage circuits, each of which generates the plurality of gamma voltages by dividing a reference voltage and is connected to the gamma bus at a voltage division point, Each pixel includes a first sub-pixel having a first color, The gamma bus includes a first sub-gamma bus, and the channel circuit for driving the first sub-pixel is connected to the first sub-gamma bus. wherein the plurality of gamma voltage circuits include gamma voltage circuits connected to the first sub-gamma bus at points spaced apart from each other, wherein the plurality of channel circuits are divided into a plurality of channel circuit blocks by the plurality of gamma voltage circuits, and each of the plurality of gamma voltage circuits is arranged between two adjacent channel circuit blocks, and The gamma bus is arranged to pass through the plurality of channel circuits from a portion between the latch and the DAC of the plurality of channel circuits along a first direction, and the plurality of gamma voltage circuits are arranged on one side of a plane divided into two by the gamma bus.

2. The semiconductor integrated circuit according to claim 1, wherein: The plurality of channel circuits are arranged along the first direction, and the plurality of gamma voltage circuits are arranged in a manner of being spaced apart from each other along the first direction.

3. The semiconductor integrated circuit according to claim 1, wherein: Each pixel includes a plurality of sub-pixels, the gamma bus includes a plurality of sub-gamma buses, the channel circuit for driving the first sub-pixel and the channel circuit for driving the second sub-pixel among the plurality of sub-pixels are connected to the first sub-gamma bus, and the channel circuit for driving the third sub-pixel is connected to the second sub-gamma bus, wherein the number of gamma voltage circuits connected to the first sub-gamma bus is greater than the number of gamma voltage circuits connected to the second sub-gamma bus, and The first sub-pixel and the second sub-pixel have the same color, and the first sub-pixel and the third sub-pixel have different colors.

4. The semiconductor integrated circuit according to claim 1, wherein: Each gamma voltage circuit includes: a first resistor string for dividing the reference voltage; a decoder for selecting multiple intermediate voltages from the first resistor string; a gamma buffer for buffering the intermediate voltages; and a second resistor string for dividing the voltage output from the gamma buffer to generate the multiple gamma voltages.

5. The semiconductor integrated circuit according to claim 4, wherein: The decoder receives a decoded signal and selects the plurality of intermediate voltages according to the decoded signal.

6. The semiconductor integrated circuit according to claim 1, wherein: Each sub-pixel includes a red R organic light emitting diode OLED, a green G organic light emitting diode OLED, or a blue B organic light emitting diode OLED, and the plurality of gamma voltages have different gamma curves for the respective RGB OLEDs.

7. The semiconductor integrated circuit according to claim 1, wherein: The DAC includes a switch array including a plurality of switches, and one of the plurality of gamma voltages is selected by turning on one of the plurality of switches.

8. The semiconductor integrated circuit according to claim 1, wherein: The reference voltage is provided to the plurality of gamma voltage circuits through a same source.

9. A semiconductor integrated circuit for driving a display, the semiconductor integrated circuit comprising: A timing control circuit for supplying pixel image data and a synchronization signal for displaying a time period; a data bus, the data bus receiving and sending the pixel image data; a plurality of channel circuits, the plurality of channel circuits being connected to the corresponding data bus, each of the plurality of channel circuits comprising a shift register, a latch, a digital-to-analog converter DAC and an output buffer connected to the data bus, the DAC being used to select one of a plurality of gamma voltages according to the pixel image data and generate a data voltage, and each of the channel circuits supplying the data voltage via a data line connected to a sub-pixel; a gamma bus for providing a path through which the plurality of gamma voltages are sent to the DACs of the corresponding channel circuits; a plurality of gamma voltage circuits, each of which generates the plurality of gamma voltages by dividing a reference voltage and is connected to the gamma bus at a voltage division point; as well as A plurality of output pads connected to the data lines respectively, wherein the plurality of channel circuits are arranged in parallel with the plurality of output pads, wherein the plurality of channel circuits are divided into a plurality of channel circuit blocks by the plurality of gamma voltage circuits, and each of the plurality of gamma voltage circuits is arranged between two adjacent channel circuit blocks, and The gamma bus is arranged to pass through the plurality of channel circuits from a portion between the latch and the DAC of the plurality of channel circuits along a first direction, and the plurality of gamma voltage circuits are arranged on one side of a plane divided into two by the gamma bus.

10. The semiconductor integrated circuit according to claim 9, wherein: The latch is used for latching the pixel image data from the shift register.

11. The semiconductor integrated circuit according to claim 9, further comprising a gate driving circuit for generating a gate driving signal of a thin film transistor TFT arranged in each sub-pixel according to a control signal received from the timing control circuit.

12. The semiconductor integrated circuit according to claim 9, wherein: The size of the outermost channel circuit block is smaller than the size of the inner channel circuit block.

13. The semiconductor integrated circuit according to claim 9, wherein: The gamma voltage circuit receives a decoded signal and adjusts the plurality of gamma voltages according to the decoded signal.

14. The semiconductor integrated circuit according to claim 13, wherein: The timing control circuit sends the decoded signal to a corresponding gamma voltage circuit.

Images