Pixel circuit and display device having the same

Abstract

The present invention relates to a pixel circuit and a display device having the pixel circuit. The pixel circuit includes: a first switching element including a control electrode connected to a first node, an input electrode receiving a first power voltage, and an output electrode connected to a third node; a second switching element including a control electrode receiving a compensation gate signal, an input electrode connected to a second node, and an output electrode connected to the third node; a third switching element including a control electrode receiving a write gate signal, an input electrode connected to the first node, and an output electrode connected to the second node; a storage capacitor including a first electrode receiving an initialization voltage and a second electrode connected to the first node; a programming capacitor receiving a data voltage and connected to the second node; and an organic light-emitting element connected to the third node and receiving a second power voltage.

Description

Technical Field

[0001] Exemplary embodiments of the present invention relate to a pixel circuit and a display device including the pixel circuit. More specifically, exemplary embodiments of the present invention relate to a pixel circuit for high resolution and a display device including the pixel circuit. Background Art

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel typically includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. The display panel driver typically includes a gate driver, a data driver, and a driving controller. The gate driver outputs a gate signal to the gate lines. The data driver outputs a data voltage to the data lines. The driving controller controls the gate driver and the data driver. Summary of the Invention

[0003] Conventional pixel circuits typically include a large number of transistors, such that due to the excessive number of transistors, conventional pixel circuits may not be effectively used for high-resolution display panels. In addition, when the number of transistors is reduced for high resolution, color difference between the upper and lower parts and crosstalk may occur.

[0004] Exemplary embodiments of the present invention provide a pixel circuit that includes a reduced number of transistors and is used to enhance the image quality of a display panel.

[0005] Exemplary embodiments of the present invention also provide a display device including the pixel circuit.

[0006] In an exemplary embodiment according to the present invention, a pixel circuit includes: a first switching element including a control electrode connected to a first node, an input electrode receiving a first power voltage, and an output electrode connected to a third node; a second switching element including a control electrode receiving a compensation gate signal, an input electrode connected to a second node, and an output electrode connected to the third node; a third switching element including a control electrode receiving a write gate signal, an input electrode connected to the first node, and an output electrode connected to the second node; a storage capacitor including a first electrode receiving an initialization voltage and a second electrode connected to the first node; a programming capacitor including a first electrode receiving a data voltage and a second electrode connected to the second node; and an organic light-emitting element including a first electrode connected to the third node and a second electrode receiving a second power voltage.

[0007] In the exemplary embodiment, the first switching element, the second switching element, and the third switching element may be P-type transistors.

[0008] In an exemplary embodiment, during the conduction bias period, the first switching element may be turned on, the second switching element may be turned off, the third switching element may be turned off, the first power voltage may be at a high level, the second power voltage may be at a high level, and the initialization voltage may be at a low level.

[0009] In an exemplary embodiment, during the initialization period after the conduction bias period, the first switching element may be turned on, the second switching element may be turned on, the third switching element may be turned on, the first power voltage may be at a low level, the second power voltage may be at a high level, and the initialization voltage may be at a low level.

[0010] In an exemplary embodiment, during the threshold voltage compensation period after the initialization period, the first switching element may be turned on, the second switching element may be turned on, the third switching element may be turned on, the first power voltage may be at a high level, the second power voltage may be at a high level, and the initialization voltage may be at a high level.

[0011] In an exemplary embodiment, during the programming period after the threshold voltage compensation period, the first switching element may be turned on, the second switching element may be turned off, the third switching element may be turned on, the first power voltage may be at a low level, the second power voltage may be at a high level, and the initialization voltage may be at a high level.

[0012] In an exemplary embodiment, during the pre-emission anode initialization period after the programming period, the first switching element may be turned on, the second switching element may be turned off, the third switching element may be turned off, the first power voltage may be at a low level, the second power voltage may be at a high level, and the initialization voltage may be at a low level.

[0013] In an exemplary embodiment, during the emission period after the pre-emission anode initialization period, the first switching element may be turned on, the second switching element may be turned off, the third switching element may be turned off, the first power voltage may be at a high level, the second power voltage may be at a low level, and the initialization voltage may be at a high level.

[0014] In an exemplary embodiment, during the first initialization period after the conduction bias period, the first switching element may be turned on, the second switching element may be turned on, the third switching element may be turned off, the first power voltage may be at a low level, the second power voltage may be at a high level, and the initialization voltage may be at a low level. In such an embodiment, during the second initialization period after the first initialization period, the first switching element may be turned on, the second switching element may be turned on, the third switching element may be turned on, the first power voltage may be at a low level, the second power voltage may be at a high level, and the initialization voltage may be at a low level.

[0015] In an exemplary embodiment, during an initialization period after a turn-on bias period, a first switching element may be turned on, a second switching element may be turned on, a third switching element may be turned on, a first power voltage may have a low level, a second power voltage may have a high level, and an initialization voltage may have a low level. In such an embodiment, the initialization voltage may temporarily have a high level at a boundary between the turn-on bias period and the initialization period.

[0016] In an exemplary embodiment, during a first initialization period after a turn-on bias period, a first switching element may be turned on, a second switching element may be turned on, a third switching element may be turned off, a first power voltage may have a low level, a second power voltage may have a high level, and an initialization voltage may have a low level. In such an embodiment, during a second initialization period after the first initialization period, a first switching element may be turned on, a second switching element may be turned on, a third switching element may be turned on, a first power voltage may have a low level, a second power voltage may have a high level, and an initialization voltage may have a low level. In such an embodiment, the initialization voltage may temporarily have a high level at a boundary between the turn-on bias period and the first initialization period.

[0017] In an exemplary embodiment, a compensation gate signal may be a write gate signal of different pixels.

[0018] In an exemplary embodiment, the first switching element, the second switching element, and the third switching element may be N-type transistors.

[0019] In an exemplary embodiment, during the initialization period, a first switching element may be turned on, a second switching element may be turned on, a third switching element may be turned on, and a first power voltage may have an intermediate level between a high level and a low level.

[0020] In an exemplary embodiment, during a threshold voltage compensation period after the initialization period, a first switching element may be turned on, a second switching element may be turned on, a third switching element may be turned on, a first power voltage may have a low level, and an initialization voltage may have a low level.

[0021] In an exemplary embodiment, during a programming period after the threshold voltage compensation period, a first switching element may be turned on, a second switching element may be turned off, a third switching element may be turned on, a first power voltage may have a high level, and an initialization voltage may have a low level.

[0022] In an exemplary embodiment, during a emission period after a programming period, the first switching element may be turned on, the second switching element may be turned off, the third switching element may be turned off, the first power voltage may have a high level, and the initialization voltage may have a high level.

[0023] In an exemplary embodiment, the compensation gate signal may be a write gate signal for different pixels.

[0024] In an exemplary embodiment, the first switching element may be a P-type transistor, and the second and third switching elements may be N-type transistors.

[0025] In an exemplary embodiment of a display device according to the present invention, the display device includes: a display panel, a gate driver, and a data driver. In such an embodiment, the display panel includes a plurality of pixels. In such an embodiment, the gate driver outputs a write gate signal to the plurality of pixels. In such an embodiment, the data driver outputs a data voltage to the plurality of pixels. In such an embodiment, each pixel among the plurality of pixels includes: a first switching element including a control electrode connected to a first node, an input electrode receiving a first power voltage, and an output electrode connected to a third node; a second switching element including a control electrode receiving a compensation gate signal, an input electrode connected to a second node, and an output electrode connected to the third node; a third switching element including a control electrode receiving a write gate signal, an input electrode connected to the first node, and an output electrode connected to the second node; a storage capacitor including a first electrode receiving an initialization voltage and a second electrode connected to the first node; a programming capacitor including a first electrode receiving a data voltage and a second electrode connected to the second node; and an organic light-emitting element including a first electrode connected to the third node and a second electrode receiving a second power voltage.

[0026] According to an exemplary embodiment of a pixel circuit, a display device includes a pixel circuit having three transistors and two capacitors, so that the display panel can have a high resolution.

[0027] In these embodiments, drive signals of the pixel circuit including three transistors and two capacitors can be controlled so that color difference and crosstalk between the upper and lower parts can be reduced or prevented without increasing the number of transistors in the pixel circuit. Therefore, the display quality of the display panel can be enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features of the present invention will become more apparent by referring to the exemplary embodiments of the present invention described in detail with reference to the drawings, in which:

[0029] Figure 1is a block diagram showing a display device according to an exemplary embodiment of the present invention;

[0030] Figure 2 is a diagram showing Figure 1 the circuit diagram of a pixel of a display panel;

[0031] Figure 3 is a timing diagram showing an input signal applied to Figure 2 the pixel;

[0032] Figure 4 is a diagram showing Figure 3 during the initialization period of Figure 2 the circuit diagram of the pixel;

[0033] Figure 5 is a diagram showing Figure 3 during the threshold voltage compensation period of Figure 2 the circuit diagram of the pixel;

[0034] Figure 6 is a diagram showing Figure 3 during the programming period of Figure 2 the circuit diagram of the pixel;

[0035] Figure 7 is a diagram showing Figure 3 during the anode initialization period of Figure 2 the circuit diagram of the pixel;

[0036] Figure 8 is a diagram showing Figure 3 during the emission period of Figure 2 the circuit diagram of the pixel;

[0037] Figure 9 is a timing diagram showing an input signal applied to a pixel of a display device according to an alternative exemplary embodiment of the present invention;

[0038] Figure 10 is a timing diagram showing an input signal applied to a pixel of a display device according to another alternative exemplary embodiment of the present invention;

[0039] Figure 11 is a timing diagram showing an input signal applied to a pixel of a display device according to another alternative exemplary embodiment of the present invention;

[0040] Figure 12 is a circuit diagram showing a pixel of a display panel according to an alternative exemplary embodiment of the present invention;

[0041] Figure 13 is a diagram showing an input signal applied to Figure 12 the pixel;

[0042] Figure 14 shows the Figure 13 pixel in the initialization period and the threshold voltage compensation period of Figure 12 circuit diagram;

[0043] Figure 15 shows the Figure 13 pixel in the programming period of Figure 12 circuit diagram;

[0044] Figure 16 shows the Figure 13 pixel in the emission period of Figure 12 circuit diagram;

[0045] Figure 17 shows the circuit diagram of the pixel of the display panel according to another alternative exemplary embodiment of the present invention;

[0046] Figure 18 shows the circuit diagram of the pixel of the display panel according to another alternative exemplary embodiment of the present invention; and

[0047] Figure 19 shows the circuit diagram of the pixel of the display panel according to another alternative exemplary embodiment of the present invention. Detailed Description

[0048] The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which various embodiments are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals throughout the figures indicate like elements.

[0049] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0050] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, without departing from the teachings herein, the first "element", "component", "region", "layer" or "section" discussed below could be referred to as the second "element", "component", "region", "layer" or "section".

[0051] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a" and "the" are intended to include the plural forms, and the plural forms include "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that the term "comprises", when used in this specification, specifies the presence of the stated features, regions, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0052] In addition, relational terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another as shown in the figures. It will be understood that the relational terms are intended to cover different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is flipped, an element described as on the "lower" side of other elements will be oriented on the "upper" side of the other elements. Thus, depending on the specific orientation of the figure, the exemplary term "lower" can cover both the "lower" and "upper" orientations. Similarly, if the device in one figure is flipped, an element described as "below" or "beneath" other elements will be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can cover both the above and below orientations.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure, and not in an idealized or overly formal sense, unless expressly so defined herein.

[0054] Exemplary embodiments are described herein with reference to cross-sections that are schematic illustrations of idealized embodiments. As such, variations in the shape of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but will include shape deviations resulting from, for example, manufacturing. For example, typically, regions shown or described as flat may have rough and / or non-linear features. Additionally, sharp corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the exact shape of the regions and are not intended to limit the scope of the claims.

[0055] Hereinafter, exemplary embodiments of the present invention will be explained in detail with reference to the accompanying drawings.

[0056] Figure 1 is a block diagram showing a display device according to an exemplary embodiment of the present invention.

[0057] Referring to Figure 1 , an exemplary embodiment of the display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0058] The display panel 100 has a display area on which an image is displayed and a peripheral area adjacent to the display area.

[0059] The display panel 100 includes multiple sets of gate lines GWL and GCL, multiple data lines DL, and multiple pixels electrically connected to the multiple sets of gate lines GWL and GCL and the multiple data lines DL. The multiple sets of gate lines GWL and GCL extend in a first direction D1, and the multiple data lines DL extend in a second direction D2 intersecting the first direction D1.

[0060] The driving controller 200 receives input image data IMG and an input control signal CONT from an external device (not shown). In one exemplary embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0061] The driving controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0062] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0063] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0064] The driving controller 200 generates a data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.

[0065] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0066] The gate driver 300 generates gate signals for driving multiple sets of gate lines GWL and GCL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may sequentially output the gate signals to the multiple sets of gate lines GWL and GCL. In one exemplary embodiment, for example, the gate driver 300 may be integrated on the display panel 100. In one exemplary embodiment, for example, the gate driver 300 may be mounted on the display panel 100.

[0067] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0068] In an exemplary embodiment, the gamma reference voltage generator 400 may be provided in the driving controller 200 or in the data driver 500.

[0069] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into a data voltage of an analog type by using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0070] Figure 2 is a circuit diagram of a pixel of the display panel 100 showing Figure 1 of. Figure 3 is a timing diagram of an input signal applied to a pixel of Figure 2 showing. Figure 4shows the Figure 3 in the initialization period INITIAL of Figure 2 circuit diagram of the pixel. Figure 5 shows the Figure 3 in the threshold voltage compensation period VTH COMP of Figure 2 circuit diagram of the pixel. Figure 6 shows the Figure 3 in the programming period PROGRAMMING of Figure 2 circuit diagram of the pixel. Figure 7 shows the Figure 3 in the anode initialization period BCB of Figure 2 circuit diagram of the pixel. Figure 8 shows the Figure 3 in the emission period EMISSION of Figure 2 circuit diagram of the pixel.

[0071] Referring to Figures 1 to 8 , the display panel 100 includes a plurality of pixels. Each pixel includes an organic light emitting element OLED.

[0072] The pixel receives a write gate signal GW[n], a compensation gate signal GC, a data voltage VDATA, and an initialization voltage VINIT, a first power voltage ELVDD, and a second power voltage ELVSS, and the organic light emitting element OLED of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0073] In such an embodiment, the write gate signal GW[n] may be a local signal having a predetermined phase for a corresponding pixel row (e.g., the nth pixel row). Here, n is a natural number. In such an embodiment, the compensation gate signal GC may be a common signal commonly applied to all pixel rows.

[0074] In an exemplary embodiment, as described above, each pixel among the plurality of pixels, for example, a pixel in the nth row, may include a first switching element T1, a second switching element T2, and a third switching element T3, a storage capacitor CST, a programming capacitor CPR, and an organic light emitting element OLED.

[0075] In an exemplary embodiment, as Figure 2 shown in, the first switching element T1, the second switching element T2, and the third switching element T3 may be P-type transistors. In one exemplary embodiment, for example, the first switching element T1, the second switching element T2, and the third switching element T3 may be polysilicon thin film transistors.

[0076] The first switching element T1 may include a control electrode connected to the first node N1, an input electrode receiving the first power supply voltage ELVDD, and an output electrode connected to the third node N3. The control electrode of the first switching element T1 may be a gate electrode, the input electrode of the first switching element T1 may be a source electrode, and the output electrode of the first switching element T1 may be a drain electrode.

[0077] The second switching element T2 may include a control electrode receiving the compensation gate signal GC, an input electrode connected to the second node N2, and an output electrode connected to the third node N3. The control electrode of the second switching element T2 may be a gate electrode, the input electrode of the second switching element T2 may be a source electrode, and the output electrode of the second switching element T2 may be a drain electrode.

[0078] The third switching element T3 may include a control electrode receiving the write gate signal GW[n], an input electrode connected to the first node N1, and an output electrode connected to the second node N2. The control electrode of the third switching element T3 may be a gate electrode, the input electrode of the third switching element T3 may be a source electrode, and the output electrode of the third switching element T3 may be a drain electrode.

[0079] The storage capacitor CST may include a first electrode receiving the initialization voltage VINIT and a second electrode connected to the first node N1.

[0080] The programming capacitor CPR may include a first electrode receiving the data voltage VDATA and a second electrode connected to the second node N2.

[0081] The organic light-emitting element OLED may include a first electrode connected to the third node N3 and a second electrode receiving the second power supply voltage ELVSS. The first electrode of the organic light-emitting element OLED may be an anode electrode. The second electrode of the organic light-emitting element OLED may be a cathode electrode.

[0082] In an exemplary embodiment, as Figure 2 and Figure 3 shown, during the conduction bias period ON BIAS, the first switching element T1 may be turned on, the second switching element T2 may be turned off, the third switching element T3 may be turned off, the first power supply voltage ELVDD may be at a high level, the second power supply voltage ELVSS may be at a high level, and the initialization voltage VINIT may be at a low level.

[0083] During the conduction bias period ON BIAS, the write gate signal GW[n] may be at a high level and the compensation gate signal GC may be at a high level.

[0084] During an ON BIAS period, an ON bias may be applied to the first switching element T1 to enhance hysteresis. Further, during the ON BIAS period, a second power voltage ELVSS may be at a high level to prevent emission of the organic light emitting element OLED due to conduction of the first switching element T1.

[0085] In an exemplary embodiment, as Figure 3 and Figure 4 shown, during an INITIAL period following the ON BIAS period, the first switching element T1 may conduct, the second switching element T2 may conduct, the third switching element T3 may conduct, a first power voltage ELVDD may be at a low level, a second power voltage ELVSS may be at a high level, and an initialization voltage VINIT may be at a low level.

[0086] During the INITIAL period, a write gate signal GW[n] may be at a low level and a compensation gate signal GC may be at a low level.

[0087] During the INITIAL period, a first node N1 connected to a control electrode of the first switching element T1 may be initialized by using the initialization voltage VINIT. During the INITIAL period, the voltage at the first node N1 may be ELVDD_L + a, where ELVDD_L represents the low level of the first power voltage ELVDD, and a represents a voltage generated by charge sharing when the write gate signal GW[n] is activated at a low level.

[0088] In an exemplary embodiment, as Figure 3 and Figure 5 shown, during a VTH COMP period following the INITIAL period, the first switching element T1 may conduct, the second switching element T2 may conduct, the third switching element T3 may conduct, a first power voltage ELVDD may be at a high level, a second power voltage ELVSS may be at a high level, and an initialization voltage VINIT may be at a high level.

[0089] During the VTH COMP period, a write gate signal GW[n] may be at a low level and a compensation gate signal GC may be at a low level.

[0090] During a threshold voltage compensation period VTH COMP, a first power supply voltage ELVDD has a high level so that a threshold voltage (represented by |VTH|) of a first switching element T1 can be compensated by using a diode connection of the first switching element T1. During the threshold voltage compensation period VTH COMP, a voltage at a first node N1 may be ELVDD_H - |VTH|. Here, ELVDD_H represents the high level of the first power supply voltage ELVDD.

[0091] In an exemplary embodiment, as Figure 3 and Figure 6 shown in, during a programming period PROGRAMMING after the threshold voltage compensation period VTH COMP, the first switching element T1 may be turned on, the second switching element T2 may be turned off, the third switching element T3 may be turned on, the first power supply voltage ELVDD may have a low level, the second power supply voltage ELVSS may have a high level, and an initialization voltage VINIT may have a high level.

[0092] During the programming period PROGRAMMING, a write gate signal GW[n] may sequentially have a low level according to scanning of pixels in a pixel row in the display panel 100, and a compensation gate signal GC may have a high level. In Figure 3 which, the write gate signal GW[n] is represented as a scan signal SCAN of the n-th pixel row <n>。

[0093] During PROGRAMMING, a data voltage VDATA is applied to a pixel through a data line DL. In Figure 3 , the number of pixel rows may be m (where m is a natural number greater than 1) such that the data voltage VDATA may include a first gray-scale voltage DATA<1> to an m-th gray-scale voltage DATA <m>。

[0094] During the PROGRAMMING period, the third switching element T3 can be turned on so that due to the charge sharing between the first node N1 and the second node N2 and the coupling of the programming capacitor CPR, the voltage at the first node N1 can be ELVDD_L - |VTH| + a' * VDATA. Here, a' is CPR / (CST + CPR), where CPR and CST represent the capacitances of the programming capacitor and the storage capacitor, respectively.

[0095] In an exemplary embodiment, as Figure 3 and Figure 7 shown, during the pre-emission anode initialization period BCB after the PROGRAMMING period, the first switching element T1 can be turned on, the second switching element T2 can be turned off, the third switching element T3 can be turned off, the first power voltage ELVDD can have a low level, the second power voltage ELVSS can have a high level, and the initialization voltage VINIT can have a low level.

[0096] During the pre-emission anode initialization period BCB, the write gate signal GW[n] can have a high level and the compensation gate signal GC can have a high level.

[0097] During the pre-emission anode initialization period BCB, the anode electrode of the organic light-emitting element OLED can be initialized before emission so that the afterimage of a display image with a low gray value can be enhanced. In addition, during the pre-emission anode initialization period BCB, the first power voltage ELVDD has a low level so that the anode electrode of the organic light-emitting element OLED can be stably initialized.

[0098] In an exemplary embodiment, as Figure 3 and Figure 8 shown, during the emission period EMISSION after the pre-emission anode initialization period BCB, the first switching element T1 can be turned on, the second switching element T2 can be turned off, the third switching element T3 can be turned off, the first power voltage ELVDD can have a high level, the second power voltage ELVSS can have a low level, and the initialization voltage VINIT can have a high level.

[0099] During the emission period EMISSION, the write gate signal GW[n] can have a high level and the compensation gate signal GC can have a high level.

[0100] During an emission period EMISSION, a first switching element T1 is turned on, a first power voltage ELVDD has a high level, and a second power voltage ELVSS has a low level, so that a current path through the first switching element T1 can be generated. During the emission period EMISSION, the organic light-emitting element OLED can emit light due to the current flowing through the first switching element T1.

[0101] According to an exemplary embodiment, as mentioned above, the pixel circuit includes three transistors T1, T2, and T3 and two capacitors CST and CPR, so that the display panel 100 including the pixel circuit can have a high resolution.

[0102] In such an embodiment, drive signals of the pixel circuit including three transistors T1, T2, and T3 and two capacitors CST and CPR can be controlled so that color difference and crosstalk between the upper and lower parts can be reduced or effectively prevented without increasing the number of transistors in the pixel circuit. Accordingly, the display quality of the display panel 100 can be enhanced.

[0103] Figure 9 is a timing diagram showing input signals applied to pixels of a display device according to an alternative exemplary embodiment of the present invention.

[0104] Except for the timing of the write gate signal GW[n], Figure 9 the pixel circuit and the exemplary embodiment of the display device of Figures 1 to 8 are substantially the same as the pixel circuit and the exemplary embodiment of the display device described above with reference to Figures 1 to 8 Accordingly, the same or similar elements as those of the embodiment of

[0105] are referred to Figure 1 , Figure 2 and Figures 4 to 9 , and any repetitive detailed description thereof will be omitted.

[0106] In such an embodiment, as described above, each of the plurality of pixels may include a first switching element T1, a second switching element T2, and a third switching element T3, a storage capacitor CST, a programming capacitor CPR, and an organic light-emitting element OLED, as shown in Figure 2 .

[0107] In an exemplary embodiment, the first switching element T1, the second switching element T2, and the third switching element T3 may be P-type transistors. In one exemplary embodiment, for example, the first switching element T1, the second switching element T2, and the third switching element T3 may be polysilicon thin film transistors.

[0108] In such an embodiment, as Figure 9 shown, during the ON BIAS period, the first switching element T1 may be turned on, the second switching element T2 may be turned off, the third switching element T3 may be turned off, the first power voltage ELVDD may have a high level, the second power voltage ELVSS may have a high level, and the initialization voltage VINIT may have a low level.

[0109] During the first initialization period (the first part of INITIAL) after the ON BIAS period, the first switching element T1 may be turned on, the second switching element T2 may be turned on, the third switching element T3 may be turned off, the first power voltage ELVDD may have a low level, the second power voltage ELVSS may have a high level, and the initialization voltage VINIT may have a low level.

[0110] During the second initialization period (the second part of INITIAL) after the first initialization period, the first switching element T1 may be turned on, the second switching element T2 may be turned on, the third switching element T3 may be turned on, the first power voltage ELVDD may have a low level, the second power voltage ELVSS may have a high level, and the initialization voltage VINIT may have a low level.

[0111] In an exemplary embodiment, as Figure 9 shown, during the first initialization period (the first part of INITIAL), the write gate signal GW[n] may have a high level and the compensation gate signal GC may have a low level. In such an embodiment, during the second initialization period (the second part of INITIAL), the write gate signal GW[n] may have a low level and the compensation gate signal GC may have a low level.

[0112] During the first initialization period (the first part of INITIAL), the first switching element T1 is turned on and the second switching element T2 is turned on so that the second node N2 and the third node N3 can be initialized. During the second initialization period (the second part of INITIAL), the first switching element T1 is turned on, the second switching element T2 is turned on, and the third switching element T3 is turned on so that the first node N1, the second node N2, the third node N3, and the storage capacitor CST can be initialized.

[0113] According to an exemplary embodiment, a pixel circuit includes three transistors T1, T2, and T3 and two capacitors CST and CPR such that a display panel 100 including the pixel circuit can have a high resolution.

[0114] In such an embodiment, drive signals of the pixel circuit including three transistors T1, T2, and T3 and two capacitors CST and CPR can be controlled such that color difference and crosstalk between the upper and lower portions can be reduced or effectively prevented without increasing the number of transistors in the pixel circuit. Accordingly, the display quality of the display panel 100 can be enhanced.

[0115] Figure 10 is a timing diagram showing input signals applied to pixels of a display device according to an exemplary embodiment of the present invention.

[0116] Except for the timing of an initialization voltage VINIT, Figure 10 the exemplary embodiments of the pixel circuit and the display device Figures 1 to 8 are substantially the same as the exemplary embodiments of the pixel circuit and the display device described above with reference to Figures 1 to 8 Accordingly, elements that are the same as or similar to those of the

[0117] Referring to Figure 1 , Figure 2 , Figures 4 to 8 and Figure 10 , an exemplary embodiment of the display panel 100 includes a plurality of pixels. Each pixel includes an organic light emitting element OLED.

[0118] In such an embodiment, as described above, each of the plurality of pixels may include a first switching element T1, a second switching element T2, and a third switching element T3, a storage capacitor CST, a programming capacitor CPR, and an organic light emitting element OLED.

[0119] In an exemplary embodiment, the first switching element T1, the second switching element T2, and the third switching element T3 may be P-type transistors. In one exemplary embodiment, for example, the first switching element T1, the second switching element T2, and the third switching element T3 may be polysilicon thin film transistors.

[0120] In such an embodiment, as Figure 10 As shown, during the ON BIAS period, the first switching element T1 can be turned on, the second switching element T2 can be turned off, the third switching element T3 can be turned off, the first power voltage ELVDD can be at a high level, the second power voltage ELVSS can be at a high level, and the initialization voltage VINIT can be at a low level.

[0121] During the INITIAL period after the ON BIAS period, the first switching element T1 can be turned on, the second switching element T2 can be turned on, the third switching element T3 can be turned on, the first power voltage ELVDD can be at a low level, the second power voltage ELVSS can be at a high level, and the initialization voltage VINIT can be at a low level.

[0122] In an exemplary embodiment, as Figure 10 shown, the initialization voltage VINIT can temporarily be at a high level at the boundary between the ON BIAS period and the INITIAL period.

[0123] Therefore, in such an embodiment, the voltage at the first node N1 can be further instantaneously decreased. Thus, the first node N1 can be further stably initialized.

[0124] According to an exemplary embodiment, as described above, the pixel circuit includes three transistors T1, T2, and T3 and two capacitors CST and CPR such that the display panel 100 including the pixel circuit can have a high resolution.

[0125] In such an embodiment, the driving signals of the pixel circuit including the three transistors T1, T2, and T3 and the two capacitors CST and CPR can be controlled such that the color difference and crosstalk between the upper and lower parts can be reduced or effectively prevented without increasing the number of transistors. Therefore, the display quality of the display panel 100 can be enhanced.

[0126] Figure 11 is a timing diagram showing input signals applied to pixels of a display device according to an exemplary embodiment of the present invention.

[0127] Except for the timing of the write gate signal GW[n], Figure 11 the exemplary embodiments of the pixel circuit and the display device of Figure 10 are substantially the same as the exemplary embodiments of the pixel circuit and the display device described above with reference to Figure 10 Therefore, the same or similar elements to those of the

[0128] Refer to Figure 1 , Figure 2 , Figures 4 to 8 and Figure 11 , exemplary embodiments of the display panel 100 include a plurality of pixels. Each pixel includes an organic light emitting element OLED.

[0129] In such an embodiment, as described above, each pixel of the plurality of pixels may include a first switching element T1, a second switching element T2, and a third switching element T3, a storage capacitor CST, a programming capacitor CPR, and an organic light emitting element OLED.

[0130] In an exemplary embodiment, the first switching element T1, the second switching element T2, and the third switching element T3 may be P-type transistors. In one exemplary embodiment, for example, the first switching element T1, the second switching element T2, and the third switching element T3 may be polysilicon thin film transistors.

[0131] In such an embodiment, as Figure 11 shown, during the on bias period ON BIAS, the first switching element T1 may be turned on, the second switching element T2 may be turned off, the third switching element T3 may be turned off, the first power voltage ELVDD may have a high level, the second power voltage ELVSS may have a high level, and the initialization voltage VINIT may have a low level.

[0132] During a first initialization period (the first part of INITIAL) after the on bias period ON BIAS, the first switching element T1 may be turned on, the second switching element T2 may be turned on, the third switching element T3 may be turned off, the first power voltage ELVDD may have a low level, the second power voltage ELVSS may have a high level, and the initialization voltage VINIT may have a low level.

[0133] During a second initialization period (the second part of INITIAL) after the first initialization period, the first switching element T1 may be turned on, the second switching element T2 may be turned on, the third switching element T3 may be turned on, the first power voltage ELVDD may have a low level, the second power voltage ELVSS may have a high level, and the initialization voltage VINIT may have a low level.

[0134] In an exemplary embodiment, as Figure 11 As shown, during the first initialization period (the first part of INITIAL), the write gate signal GW[n] may be at a high level and the compensation gate signal GC may be at a low level. In such an embodiment, during the second initialization period (the second part of INITIAL), the write gate signal GW[n] may be at a low level and the compensation gate signal GC may be at a low level.

[0135] During the first initialization period (the first part of INITIAL), the first switching element T1 is turned on and the second switching element T2 is turned on so that the second node N2 and the third node N3 can be initialized. During the second initialization period (the second part of INITIAL), the first switching element T1 is turned on, the second switching element T2 is turned on, and the third switching element T3 is turned on so that the first node N1, the second node N2, the third node N3, and the storage capacitor CST can be initialized.

[0136] In an exemplary embodiment, as described above, the initialization voltage VINIT may temporarily be at a high level at the boundary between the conduction bias period ONBIAS and the first initialization period (the first part of INITIAL).

[0137] Therefore, in such an embodiment, the voltage at the first node N1 may further instantaneously decrease. Therefore, the first node N1 can be more stably initialized.

[0138] According to an exemplary embodiment, the pixel circuit includes three transistors T1, T2, and T3 and two capacitors CST and CPR so that the display panel 100 including the pixel circuit can have a high resolution.

[0139] In such an embodiment, the drive signals of the pixel circuit including the three transistors T1, T2, and T3 and the two capacitors CST and CPR can be controlled so that color difference and crosstalk between the upper and lower parts can be reduced or effectively prevented without increasing the number of transistors. Therefore, the display quality of the display panel 100 can be enhanced.

[0140] Figure 12 is a circuit diagram showing a pixel of the display panel 100 according to an alternative exemplary embodiment of the present invention. Figure 13 is a diagram showing the application to Figure 12 the input signal timing diagram of the pixel. Figure 14 is a diagram showing at Figure 13 the initialization period INITIAL and the threshold voltage compensation period COMP of Figure 12 the circuit diagram of the pixel. Figure 15 is a diagram showing at Figure 13 the programming period PROGRAMMING of Figure 12 The circuit diagram of the pixel. Figure 16 is a diagram showing Figure 13 during the emission period EMISSION of Figure 12 The circuit diagram of the pixel.

[0141] Except that the first switching element T1 to the third switching element T3 are N-type transistors and except for the timing of the input signal, Figures 12 to 16 The exemplary embodiments of the pixel circuit and the display device are substantially the same as the exemplary embodiments of the pixel circuit and the display device described above with reference to Figures 1 to 8 Therefore, the same or similar reference numerals will be used to denote the same or similar elements as those in the Figures 1 to 8 embodiment, and any repetitive detailed description thereof will be omitted.

[0142] Referring to Figure 1 and Figures 12 to 16 , an exemplary embodiment of the display panel 100 includes a plurality of pixels. Each pixel includes an organic light-emitting element OLED.

[0143] In such an embodiment, as shown in Figure 12 and Figure 13 , the pixel receives a write gate signal GW[n], a compensation gate signal GC, a data voltage VDATA, an initialization voltage VEM, a first power voltage ELVDD, and a second power voltage ELVSS, and the organic light-emitting element OLED of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0144] In the exemplary embodiment, the write gate signal GW[n] may be a local signal having a predetermined phase for a corresponding pixel row (e.g., the nth pixel row). In such an embodiment, the compensation gate signal GC may be a common signal commonly applied to all pixel rows.

[0145] In such an embodiment, as described above, each of the plurality of pixels may include a first switching element T1, a second switching element T2, and a third switching element T3, a storage capacitor CST, a programming capacitor CPR, and an organic light-emitting element OLED.

[0146] In the present exemplary embodiment, the first switching element T1, the second switching element T2, and the third switching element T3 may be N-type transistors. In one exemplary embodiment, for example, the first switching element T1, the second switching element T2, and the third switching element T3 may be oxide thin film transistors.

[0147] The first switching element T1 may include a control electrode connected to the first node N1, an input electrode receiving the first power voltage ELVDD, and an output electrode connected to the third node N3. The control electrode of the first switching element T1 may be a gate electrode, the input electrode of the first switching element T1 may be a source electrode, and the output electrode of the first switching element T1 may be a drain electrode.

[0148] The second switching element T2 may include a control electrode receiving the compensation gate signal GC, an input electrode connected to the second node N2, and an output electrode connected to the third node N3. The control electrode of the second switching element T2 may be a gate electrode, the input electrode of the second switching element T2 may be a source electrode, and the output electrode of the second switching element T2 may be a drain electrode.

[0149] The third switching element T3 may include a control electrode receiving the write gate signal GW[n], an input electrode connected to the first node N1, and an output electrode connected to the second node N2. The control electrode of the third switching element T3 may be a gate electrode, the input electrode of the third switching element T3 may be a source electrode, and the output electrode of the third switching element T3 may be a drain electrode.

[0150] The storage capacitor CST may include a first electrode receiving the initialization voltage VEM and a second electrode connected to the first node N1.

[0151] The programming capacitor CPR may include a first electrode receiving the data voltage VDATA and a second electrode connected to the second node N2.

[0152] The organic light emitting element OLED may include a first electrode connected to the third node N3 and a second electrode receiving the second power voltage ELVSS. The first electrode of the organic light emitting element OLED may be an anode electrode. The second electrode of the organic light emitting element OLED may be a cathode electrode.

[0153] In an exemplary embodiment, the second power voltage ELVSS may be a direct current (DC) voltage. In one exemplary embodiment, for example, the second power voltage ELVSS may have a low level.

[0154] In such an embodiment, as Figure 13 and Figure 14 shown, during the initialization period INITIAL, the first switching element T1 may be turned on, the second switching element T2 may be turned on, the third switching element T3 may be turned on, and the first power voltage ELVDD may have an intermediate level between a high level and a low level.

[0155] During the INITIAL initialization period, the initialization voltage VEM can drop from a high level to a low level. During the INITIAL initialization period, the write gate signal GW[n] can have a high level and the compensation gate signal GC can have a high level.

[0156] During the INITIAL initialization period, the first node N1 connected to the control electrode of the first switching element T1 can be initialized by using the intermediate level of the first power supply voltage ELVDD. During the INITIAL initialization period, the voltage at the first node N1 can be ELVDD_INT + |VTH|. Here, ELVDD_INT represents the intermediate level of the first power supply voltage ELVDD.

[0157] In such an embodiment, as Figure 13 and Figure 14 shown, during the COMP threshold voltage compensation period after the INITIAL initialization period, the first switching element T1 can be turned on, the second switching element T2 can be turned on, the third switching element T3 can be turned on, the first power supply voltage ELVDD can have a low level, and the initialization voltage VEM can have a low level.

[0158] During the COMP threshold voltage compensation period, the write gate signal GW[n] can have a high level and the compensation gate signal GC can have a high level.

[0159] During the COMP threshold voltage compensation period, the first power supply voltage ELVDD drops from the intermediate level to the low level so that the threshold voltage of the first switching element T1 (represented by |VTH|) can be compensated by using the diode connection of the first switching element T1. During the COMP threshold voltage compensation period, the voltage at the first node N1 can be ELVDD_L + |VTH|. Here, ELVDD_L represents the low level of the first power supply voltage ELVDD.

[0160] In such an embodiment, as Figure 13 and Figure 15 shown, during the PROGRAMMING programming period after the COMP threshold voltage compensation period, the first switching element T1 can be turned on, the second switching element T2 can be turned off, the third switching element T3 can be turned on, the first power supply voltage ELVDD can have a high level, and the initialization voltage VEM can have a low level.

[0161] During the PROGRAMMING programming period, the write gate signal GW[n] can sequentially have a high level according to the scanning of the pixels in the pixel rows of the display panel 100 and the compensation gate signal GC can have a low level.

[0162] During the PROGRAMMING period, a data voltage VDATA is applied to the pixel through a data line DL.

[0163] During the PROGRAMMING period, a third switching element T3 may be turned on so that due to charge sharing between a first node N1 and a second node N2 and coupling of a programming capacitor CPR, the voltage at the first node N1 may be ELVDD_L + |VTH| + a'*VDATA, where a' is CPR / (CST + CPR).

[0164] A HOLD period may be set between a threshold voltage compensation period COMP and the PROGRAMMING period.

[0165] During the HOLD period, a first power voltage ELVDD may have a high level and an initialization voltage VEM may have a low level.

[0166] During the HOLD period, a write gate signal GW[n] may have a low level and a compensation gate signal GC may have a low level.

[0167] In such an embodiment, as Figure 13 and Figure 16 shown, during an EMISSION period after the PROGRAMMING period, a first switching element T1 may be turned on, a second switching element T2 may be turned off, a third switching element T3 may be turned off, a first power voltage ELVDD may have a high level, and an initialization voltage VEM may have a high level.

[0168] During the EMISSION period, a write gate signal GW[n] may have a low level and a compensation gate signal GC may have a low level.

[0169] During the EMISSION period, the first switching element T1 is turned on, the first power voltage ELVDD has a high level and the second power voltage ELVSS has a low level so that a current path through the first switching element T1 may be generated. During the EMISSION period, the organic light emitting element OLED may emit light due to the current flowing through the first switching element T1.

[0170] According to an exemplary embodiment, as described above, the pixel circuit includes three transistors T1, T2, and T3 and two capacitors CST and CPR so that a display panel 100 including the pixel circuit may have a high resolution.

[0171] In such an embodiment, drive signals of a pixel circuit including three transistors T1, T2, and T3 and two capacitors CST and CPR can be controlled so that color difference and crosstalk between the upper and lower portions can be reduced or effectively prevented without increasing the number of transistors in the pixel circuit. Accordingly, the display quality of the display panel 100 can be enhanced.

[0172] Figure 17 is a circuit diagram showing a pixel of a display device according to an exemplary embodiment of the present invention.

[0173] Except that the first switch element T1 to the third switch element T3 are N-type transistors, Figure 17 the pixel circuit and the exemplary embodiment of the display device are substantially the same as the exemplary embodiment of the pixel circuit and the display device described above with reference to Figures 1 to 8 Therefore, the same or similar elements as those of the Figures 1 to 8 embodiment will be denoted by the same or similar reference numerals, and any repetitive detailed description thereof will be omitted.

[0174] Referring to Figure 1 , Figures 3 to 8 and Figure 17 , an exemplary embodiment of the display panel 100 includes a plurality of pixels. Each pixel includes an organic light emitting element OLED.

[0175] The pixel receives a write gate signal GW[n], a compensation gate signal GC, a data voltage VDATA, an initialization voltage VEM, a first power voltage ELVDD, and a second power voltage ELVSS, and the organic light emitting element OLED of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0176] In the exemplary embodiment, the write gate signal GW[n] may be a local signal having a predetermined phase for a corresponding pixel row (e.g., the n-th pixel row). In such an embodiment, the compensation gate signal GC may be a common signal commonly applied to all pixel rows.

[0177] In such an embodiment, as described above, each of the plurality of pixels may include a first switch element T1, a second switch element T2, and a third switch element T3, a storage capacitor CST, a programming capacitor CPR, and an organic light emitting element OLED.

[0178] In an exemplary embodiment, the first switching element T1 may be a P-type transistor. In one exemplary embodiment, for example, the first switching element T1 may be a polysilicon thin film transistor. In the present exemplary embodiment, the second switching element T2 and the third switching element T3 may be N-type transistors. In one exemplary embodiment, for example, the second switching element T2 and the third switching element T3 may be oxide thin film transistors.

[0179] The first switching element T1 is a P-type transistor so that pre-emission anode initialization can be operated and luminance variation at high temperatures can be effectively prevented.

[0180] The second switching element T2 and the third switching element T3 are N-type transistors so that current leakage at the second switching element T2 and the third switching element T3 can be effectively prevented.

[0181] According to an exemplary embodiment, the pixel circuit includes three transistors T1, T2, and T3 and two capacitors CST and CPR so that the display panel 100 including the pixel circuit can have a high resolution.

[0182] In such an embodiment, the driving signals of the pixel circuit including three transistors T1, T2, and T3 and two capacitors CST and CPR can be controlled so that color difference and crosstalk between the upper and lower parts can be reduced or effectively prevented without increasing the number of transistors in the pixel circuit. Accordingly, the display quality of the display panel 100 can be enhanced.

[0183] Figure 18 is a circuit diagram showing a pixel of a display device according to an exemplary embodiment of the present invention.

[0184] In addition to compensating the gate signal GC, Figure 18 the exemplary embodiments of the pixel circuit and the display device Figures 1 to 8 are substantially the same as the exemplary embodiments of the pixel circuit and the display device described above with reference to Figures 1 to 8 Accordingly, the same or similar elements to those of the

[0185] Referring to Figure 1 、 Figures 3 to 8 and Figure 18 the exemplary embodiment of the display panel 100 includes a plurality of pixels. Each pixel includes an organic light emitting element OLED.

[0186] The pixel receives a write gate signal GW[n], a compensation gate signal GC, a data voltage VDATA, an initialization voltage VINIT, a first power voltage ELVDD, and a second power voltage ELVSS, and an organic light-emitting diode OLED of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0187] In an exemplary embodiment, the write gate signal GW[n] may be a local signal having a predetermined phase for a corresponding pixel row (e.g., the n-th pixel row). In such an embodiment, the compensation gate signal GC may be a local signal having a predetermined phase for a corresponding pixel row (e.g., the n-th pixel row).

[0188] In one exemplary embodiment, the compensation gate signal GC may be a write gate signal of a different pixel or another pixel. In one exemplary embodiment, for example, the write gate signal GW[n + 1] of a pixel provided in the (n + 1)-th pixel row may be used as the compensation gate signal GC of a pixel provided in the n-th pixel row. Alternatively, the write gate signal GW[n] of a pixel provided in the n-th pixel row may be used as the compensation gate signal GC of a pixel provided in the n-th pixel row. Alternatively, one of a plurality of write gate signals GW of the pixel may be used as the compensation gate signal GC of a pixel provided in the n-th pixel row.

[0189] In such an embodiment, as described above, each pixel of the plurality of pixels may include a first switching element T1, a second switching element T2, and a third switching element T3, a storage capacitor CST, a programming capacitor CPR, and an organic light-emitting diode OLED.

[0190] In an exemplary embodiment, the first switching element T1, the second switching element T2, and the third switching element T3 may be P-type transistors. In one exemplary embodiment, for example, the first switching element T1, the second switching element T2, and the third switching element T3 may be polysilicon thin-film transistors.

[0191] According to an exemplary embodiment, as mentioned above, the pixel circuit includes three transistors T1, T2, and T3 and two capacitors CST and CPR, such that a display panel 100 including the pixel circuit may have a high resolution.

[0192] In such an embodiment, drive signals of the pixel circuit including three transistors T1, T2, and T3 and two capacitors CST and CPR may be controlled such that color difference and crosstalk between the upper and lower portions may be reduced or effectively prevented without increasing the number of transistors in the pixel circuit. Accordingly, the display quality of the display panel 100 may be enhanced.

[0193] Figure 19 It is a circuit diagram showing a pixel of a display device according to an exemplary embodiment of the present invention.

[0194] Except for compensating the gate signal GC, Figure 19 the pixel circuit and the exemplary embodiment of the display device are substantially the same as the exemplary embodiment of the pixel circuit and the display device described above with reference to Figures 12 to 16 Therefore, the same or similar reference numerals will be used to denote the same or similar elements as those in the Figures 12 to 16 embodiment, and any repetitive detailed description thereof will be omitted.

[0195] Referring to Figure 1 , Figures 13 to 16 and Figure 19 , an exemplary embodiment of the display panel 100 includes a plurality of pixels. Each pixel includes an organic light emitting element OLED.

[0196] The pixel receives a write gate signal GW[n], a compensation gate signal GC, a data voltage VDATA, an initialization voltage VEM, a first power voltage ELVDD, and a second power voltage ELVSS, and the organic light emitting element OLED of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0197] In an exemplary embodiment, the write gate signal GW[n] may be a local signal having a predetermined phase for a corresponding pixel row (e.g., the nth pixel row). In such an embodiment, the compensation gate signal GC may be a local signal having a predetermined phase for a corresponding pixel row (e.g., the nth pixel row).

[0198] In one exemplary embodiment, the compensation gate signal GC may be the write gate signal of a different pixel or another pixel. In one exemplary embodiment, for example, the write gate signal GW[n + 1] of a pixel provided in the (n + 1)th pixel row may be used as the compensation gate signal GC of a pixel provided in the nth pixel row. Alternatively, the write gate signal GW[n] of a pixel provided in the nth pixel row may be used as the compensation gate signal GC of a pixel provided in the nth pixel row. Alternatively, one of the plurality of write gate signals GW of the pixel may be used as the compensation gate signal GC of a pixel provided in the nth pixel row.

[0199] In such an embodiment, as described above, each of the plurality of pixels may include a first switching element T1, a second switching element T2, and a third switching element T3, a storage capacitor CST, a programming capacitor CPR, and an organic light emitting element OLED.

[0200] In an exemplary embodiment, the first switching element T1, the second switching element T2, and the third switching element T3 may be N-type transistors. In one exemplary embodiment, for example, the first switching element T1, the second switching element T2, and the third switching element T3 may be oxide thin film transistors.

[0201] According to an exemplary embodiment, as mentioned above, the pixel circuit includes three transistors T1, T2, and T3 and two capacitors CST and CPR, such that the display panel 100 including the pixel circuit may have a high resolution.

[0202] In such an embodiment, the driving signals of the pixel circuit including three transistors T1, T2, and T3 and two capacitors CST and CPR may be controlled such that color difference and crosstalk between the upper and lower portions may be reduced or effectively prevented without increasing the number of transistors in the pixel circuit. Accordingly, the display quality of the display panel 100 may be enhanced.

[0203] According to an exemplary embodiment of the present invention as described herein, a display panel in which the pixel circuit includes three transistors and two capacitors may have a high resolution and may enhance the display quality of the display panel.

[0204] The present invention should not be construed as being limited to the exemplary embodiments set forth herein. On the contrary, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0205] Although the present invention has been specifically shown and described with reference to exemplary embodiments thereof, those of ordinary skill in the art will understand that various modifications in form and detail may be made therein without departing from the spirit or scope of the present invention as defined by the appended claims.< / m> < / n>

Claims

1. A pixel circuit, comprising: A first switching element, including a control electrode connected to a first node, an input electrode receiving a first power voltage, and an output electrode connected to a third node; A second switching element, including a control electrode receiving a compensation gate signal, an input electrode connected to a second node, and an output electrode connected to the third node; A third switching element, including a control electrode receiving a write gate signal, an input electrode connected to the first node, and an output electrode connected to the second node; A storage capacitor, including a first electrode receiving an initialization voltage and a second electrode connected to the first node; A programming capacitor, including a first electrode receiving a data voltage and a second electrode connected to the second node; And An organic light-emitting element, including a first electrode connected to the third node and a second electrode receiving a second power voltage, Wherein, the first switching element, the second switching element, and the third switching element are P-type transistors, Wherein, during a conduction bias period, the first switching element is turned on, the second switching element is turned off, the third switching element is turned off, the first power voltage has a high level, the second power voltage has a high level, and the initialization voltage has a low level, Wherein, during an initialization period after the conduction bias period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned on, the first power voltage has a low level, the second power voltage has a high level, and the initialization voltage has a low level, and Wherein, the initialization voltage temporarily has a high level at the boundary between the conduction bias period and the initialization period.

2. The pixel circuit according to claim 1, wherein, During a threshold voltage compensation period after the initialization period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned on, the first power voltage has a high level, the second power voltage has a high level, and the initialization voltage has a high level.

3. The pixel circuit according to claim 2, wherein, During a programming period after the threshold voltage compensation period, the first switching element is turned on, the second switching element is turned off, the third switching element is turned on, the first power voltage has a low level, the second power voltage has a high level, and the initialization voltage has a high level.

4. The pixel circuit according to claim 3, wherein, During a pre-emission anode initialization period after the programming period, the first switching element is turned on, the second switching element is turned off, the third switching element is turned off, the first power voltage has a low level, the second power voltage has a high level, and the initialization voltage has a low level.

5. The pixel circuit according to claim 4, wherein, During an emission period after the pre-emission anode initialization period, the first switching element is turned on, the second switching element is turned off, the third switching element is turned off, the first power voltage has a high level, the second power voltage has a low level, and the initialization voltage has a high level.

6. The pixel circuit according to claim 1, wherein, The compensation gate signal is the write gate signal of different pixels.

7. A display device, comprising: A display panel, including a plurality of pixels; A gate driver that outputs a write gate signal to the plurality of pixels; and A data driver that outputs a data voltage to the plurality of pixels, wherein each of the plurality of pixels includes: A first switching element including a control electrode connected to a first node, an input electrode receiving a first power voltage, and an output electrode connected to a third node; A second switching element including a control electrode receiving a compensation gate signal, an input electrode connected to a second node, and an output electrode connected to the third node; A third switching element including a control electrode receiving the write gate signal, an input electrode connected to the first node, and an output electrode connected to the second node; A storage capacitor including a first electrode receiving an initialization voltage and a second electrode connected to the first node; A programming capacitor including a first electrode receiving the data voltage and a second electrode connected to the second node; and An organic light emitting element including a first electrode connected to the third node and a second electrode receiving a second power voltage, wherein the first switching element, the second switching element, and the third switching element are P-type transistors, wherein during a conduction bias period, the first switching element is turned on, the second switching element is turned off, the third switching element is turned off, the first power voltage has a high level, the second power voltage has a high level, and the initialization voltage has a low level, wherein during an initialization period after the conduction bias period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned on, the first power voltage has a low level, the second power voltage has a high level, and the initialization voltage has a low level, and wherein the initialization voltage temporarily has a high level at a boundary between the conduction bias period and the initialization period.

8. A pixel circuit, comprising: A first switching element including a control electrode connected to a first node, an input electrode receiving a first power voltage, and an output electrode connected to a third node; A second switching element including a control electrode receiving a compensation gate signal, an input electrode connected to a second node, and an output electrode connected to the third node; A third switching element including a control electrode receiving the write gate signal, an input electrode connected to the first node, and an output electrode connected to the second node; A storage capacitor including a first electrode receiving an initialization voltage and a second electrode connected to the first node; A programming capacitor including a first electrode receiving the data voltage and a second electrode connected to the second node; and An organic light emitting element including a first electrode connected to the third node and a second electrode receiving a second power voltage, wherein the first switching element, the second switching element, and the third switching element are P-type transistors, wherein during a conduction bias period, the first switching element is turned on, the second switching element is turned off, the third switching element is turned off, the first power voltage has a high level, the second power voltage has a high level, and the initialization voltage has a low level, Among them, during a first initialization period after the conduction bias period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned off, the first power voltage has a low level, the second power voltage has a high level, and the initialization voltage has a low level, and Among them, during a second initialization period after the first initialization period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned on, the first power voltage has a low level, the second power voltage has a high level, and the initialization voltage has a low level.

9. A pixel circuit, comprising: A first switching element, comprising a control electrode connected to a first node, an input electrode receiving a first power voltage, and an output electrode connected to a third node; A second switching element, comprising a control electrode receiving a compensation gate signal, an input electrode connected to a second node, and an output electrode connected to the third node; A third switching element, comprising a control electrode receiving a write gate signal, an input electrode connected to the first node, and an output electrode connected to the second node; A storage capacitor, comprising a first electrode receiving an initialization voltage and a second electrode connected to the first node; A programming capacitor, comprising a first electrode receiving a data voltage and a second electrode connected to the second node; And An organic light-emitting element, comprising a first electrode connected to the third node and a second electrode receiving a second power voltage, Among them, the first switching element, the second switching element, and the third switching element are P-type transistors, Among them, during the conduction bias period, the first switching element is turned on, the second switching element is turned off, the third switching element is turned off, the first power voltage has a high level, the second power voltage has a high level, and the initialization voltage has a low level, Among them, during a first initialization period after the conduction bias period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned off, the first power voltage has a low level, the second power voltage has a high level, and the initialization voltage has a low level, Among them, during a second initialization period after the first initialization period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned on, the first power voltage has a low level, the second power voltage has a high level, and the initialization voltage has a low level, and Among them, the initialization voltage temporarily has a high level at the boundary between the conduction bias period and the first initialization period.

10. The pixel circuit according to claim 8 or 9, wherein, The compensation gate signal is the write gate signal of different pixels.

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