Pixels of display device and organic light emitting diode display device

Abstract

The present invention relates to a pixel of a display device and an organic light emitting diode display device. The pixel of the display device includes a capacitor; a light emitting diode; and a first transistor, a second transistor, a third transistor and a fourth transistor. The display device has a normal frequency mode and a low frequency mode. The two electrodes of the capacitor are respectively connected to a first voltage source and a gate node. The gate electrode of the first transistor is connected to the gate node. In the holding period in the low frequency mode, both the second transistor and the third transistor receive a scan signal, the third transistor diode-connects the first transistor, the fourth transistor receives an initialization signal and transmits the initialization voltage to the gate node, the scan signal is at a first cut-off voltage level, and the initialization signal is at a second cut-off voltage level that is not equal to the first cut-off voltage level. The cathode of the light emitting diode is connected to the second voltage source.

Description

[0001] The technical field relates to pixels of an organic light emitting diode display device and an organic light emitting diode display device. Background Art

[0002] In an organic light emitting diode (OLED) display device used in a portable device such as a smart phone or a tablet computer, a reduction in power consumption can be expected. In order to reduce the power consumption of the OLED display device, the OLED display device can be operated by relatively low frequency driving when displaying a static image. When performing low frequency driving, the OLED display device can display an image based on a stored data signal, thereby reducing power consumption.

[0003] When the OLED display device displays an image based on the stored data signal, the stored data signal may be distorted due to leakage current of a transistor included in a pixel of the OLED display device. As a result, the quality of the image displayed by the OLED display device may be unsatisfactory. Summary of the invention

[0004] Some embodiments may relate to pixels and related organic light emitting diode (OLED) display devices. OLED display devices can display images with satisfactory quality under low-frequency driving.

[0005] According to an embodiment, a pixel of an organic light emitting diode display device includes the following elements: a capacitor including a first electrode coupled to a line of a first power supply voltage and a second electrode coupled to a gate node, a first transistor including a gate electrode coupled to the gate node, a second transistor configured to transmit a data signal to a source of the first transistor in response to a scan signal, a third transistor configured to diode-connect the first transistor in response to the scan signal, a fourth transistor configured to transmit an initialization voltage to the gate node in response to an initialization signal, and an organic light emitting diode including an anode and a cathode coupled to a line of a second power supply voltage. In a low frequency holding period, the scan signal applied to the third transistor has a first cut-off voltage level, and the initialization signal applied to the fourth transistor has a second cut-off voltage level different from the first cut-off voltage level.

[0006] In an embodiment, in a low frequency driving mode of driving a display panel of an organic light emitting diode display device at a low frequency lower than a normal driving frequency, at least one frame period of a plurality of consecutive frame periods may be set as a low frequency maintaining period.

[0007] In an embodiment, in a normal driving period in which a display panel of an organic light emitting diode display device is driven, a scan signal and an initialization signal may have a turn-on voltage level at different times, and each of the scan signal and the initialization signal may be changed to a third turn-off voltage level after the turn-on voltage level. In a low-frequency holding period in which the display panel is not driven, a scan signal applied to the third transistor may have a first turn-off voltage level substantially the same as the third turn-off voltage level, and an initialization signal applied to the fourth transistor may be increased from the third turn-off voltage level to a second turn-off voltage level higher than the third turn-off voltage level.

[0008] In an embodiment, in the low frequency holding period, a drain current of the fourth transistor of the line from the gate node to the initialization voltage may increase based on the initialization signal having the second cut-off voltage level higher than the third cut-off voltage level.

[0009] In an embodiment, the difference between the second cut-off voltage level and the third cut-off voltage level may be determined according to a driving frequency for the display panel.

[0010] In an embodiment, in a normal driving period of a display panel in which the organic light emitting diode display device is driven, a scan signal and an initialization signal may have a turn-on voltage level at different times, and each of the scan signal and the initialization signal may be changed to a third turn-off voltage level after the turn-on voltage level. In a low-frequency holding period in which the display panel is not driven, a scan signal applied to the third transistor may be increased from the third turn-off voltage level to a first turn-off voltage level higher than the third turn-off voltage level, and an initialization signal applied to the fourth transistor may have a second turn-off voltage level substantially the same as the third turn-off voltage level.

[0011] In an embodiment, in the low frequency holding period, a leakage current of the third transistor from the gate node to the drain of the first transistor may increase based on the scan signal having the first cut-off voltage level higher than the third cut-off voltage level.

[0012] In an embodiment, in a normal driving period in which a display panel of an organic light emitting diode display device is driven, a scan signal and an initialization signal may have a turn-on voltage level at different times, and each of the scan signal and the initialization signal may be changed to a third turn-off voltage level after the turn-on voltage level. In a low-frequency holding period in which the display panel is not driven, a scan signal applied to the third transistor may have a first turn-off voltage level substantially the same as the third turn-off voltage level, and an initialization signal applied to the fourth transistor may be reduced from the third turn-off voltage level to a second turn-off voltage level lower than the third turn-off voltage level.

[0013] In an embodiment, in the low frequency holding period, a leakage current of the fourth transistor from the gate node may be reduced based on the initialization signal having the second cut-off voltage level lower than the third cut-off voltage level.

[0014] In an embodiment, in a normal driving period in which a display panel of an organic light emitting diode display device is driven, a scan signal and an initialization signal may have a turn-on voltage level at different times, and each of the scan signal and the initialization signal may be changed to a third turn-off voltage level after the turn-on voltage level. In a low-frequency holding period in which the display panel is not driven, a scan signal applied to the third transistor may be reduced from the third turn-off voltage level to a second turn-off voltage level lower than the third turn-off voltage level, and an initialization signal applied to the fourth transistor may have a first turn-off voltage level substantially the same as the third turn-off voltage level.

[0015] In an embodiment, in the low frequency maintaining period, a leakage current of the third transistor from the gate node may be reduced based on the scan signal having the second cut-off voltage level lower than the third cut-off voltage level.

[0016] In an embodiment, the third transistor may include a first sub-transistor and a second sub-transistor coupled in series between the gate node and the drain of the first transistor, and the fourth transistor may include a third sub-transistor and a fourth sub-transistor coupled in series between the gate node and a line of an initialization voltage.

[0017] In an embodiment, the pixel may further include: a fifth transistor, including a gate electrode receiving an emission signal, a source coupled to a line of a first power supply voltage, and a drain coupled to the source of the first transistor; a sixth transistor, including a gate electrode receiving an emission signal, a source coupled to the drain of the first transistor, and a drain coupled to an anode of an organic light emitting diode; and a seventh transistor, including a gate electrode receiving an initialization signal, a source coupled to the anode of the organic light emitting diode, and a drain coupled to a line of an initialization voltage.

[0018] According to an embodiment, a pixel of an organic light emitting diode display device includes the following elements: a capacitor including a first electrode coupled to a line of a first power supply voltage and a second electrode coupled to a gate node, a first transistor including a gate electrode coupled to the gate node, a second transistor configured to transmit a data signal to a source of the first transistor in response to a scan signal, a third transistor configured to diode-connect the first transistor in response to the scan signal, a fourth transistor configured to transmit an initialization voltage to the gate node in response to an initialization signal, and an organic light emitting diode including an anode and a cathode coupled to a line of a second power supply voltage. In a low frequency holding period, at least one of a scan signal applied to the third transistor and an initialization signal applied to the fourth transistor is changed from a first cut-off voltage level to a second cut-off voltage level different from the first cut-off voltage level.

[0019] According to an embodiment, an organic light emitting diode (OLED) display device includes the following elements: a display panel including a plurality of pixels; a data driver configured to provide a data signal to the plurality of pixels; a power management circuit configured to generate a gate-on voltage and a gate-off voltage; a scan driver including an initialization stage group configured to sequentially provide an initialization signal to the plurality of pixels based on the gate-on voltage and the gate-off voltage and a scan stage group configured to sequentially provide a scan signal to the plurality of pixels based on the gate-on voltage and the gate-off voltage; and a controller configured to control the data driver, the power management circuit, and the scan driver. In a normal driving period, the power management circuit provides a first gate-off voltage as a gate-off voltage to the initialization stage group and the scan stage group. In a low-frequency holding period, the power management circuit provides the first gate-off voltage as a gate-off voltage to a first stage group of the initialization stage group and the scan stage group, and provides a second gate-off voltage different from the first gate-off voltage as a gate-off voltage to a second stage group of the initialization stage group and the scan stage group.

[0020] In an embodiment, the power management circuit may include a switch block configured to receive a hold flag signal indicating a low-frequency hold period from a controller, and selectively provide the first gate-off voltage or the second gate-off voltage as the gate-off voltage to the second stage group in response to the hold flag signal.

[0021] In an embodiment, the switch block may include a first switch configured to provide the first gate-off voltage as the gate-off voltage to the second stage group in response to the hold flag signal and a second switch configured to provide the second gate-off voltage as the gate-off voltage to the second stage group in response to the hold flag signal.

[0022] In an embodiment, the controller may include a static image detector configured to receive input image data at an input frame frequency and determine whether the input image data represents a static image. In the case where the input image data represents a static image, the controller may set at least one frame period of a plurality of consecutive frame periods as a low-frequency holding period so that the display panel is driven at a low frequency lower than the input frame frequency.

[0023] In an embodiment, the display panel may be divided into a plurality of panel areas. The controller may include a static image detector configured to receive input image data at an input frame frequency, divide the input image data for the display panel into a plurality of partial image data respectively for the plurality of panel areas, and determine whether each of the plurality of partial image data represents a static image. In the case where at least one partial image data among the plurality of partial image data represents a static image, the controller may set at least one frame period among the plurality of continuous frame periods as a low-frequency holding period with respect to a corresponding panel area among the plurality of panel areas corresponding to the at least one partial image data, so that the corresponding panel area among the plurality of panel areas is driven at a low frequency lower than the input frame frequency.

[0024] In an embodiment, the second stage group may include a plurality of stage subgroups respectively coupled to the plurality of panel regions. The power management circuit may include a plurality of switch blocks configured to selectively provide the first gate-off voltage or the second gate-off voltage as the gate-off voltage to the plurality of stage subgroups, respectively.

[0025] Embodiments may relate to pixels of a display device. The display device may have a first mode and a second mode (i.e., may operate in the first mode and the second mode). The driving frequency of the display device in the second mode may be lower than the driving frequency of the display device in the first mode. The pixel may include a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, and an organic light emitting diode. The first electrode of the capacitor may receive a first power supply voltage. The second electrode of the capacitor may be electrically connected to a gate node. The gate electrode of the first transistor may be electrically connected to the gate node. The drain electrode of the second transistor may be electrically connected to the source electrode of the first transistor. The gate electrode of the second transistor may receive a first instance of a scan signal in a holding period in the second mode. The third transistor may diode-connect the first transistor in response to a second instance of the scan signal in the holding period in the second mode. The fourth transistor may transmit an initialization voltage to the gate node in response to a first instance of an initialization signal in the holding period in the second mode. The organic light emitting diode may include an anode and a cathode. The cathode may receive a second power supply voltage different from the first power supply voltage. In the holding period in the second mode, the scan signal and the initialization signal may have different cut-off voltage levels.

[0026] In the second mode, the holding period may include one frame period among the continuous frame periods.

[0027] In a frame period in the first mode, the scan signal may be changed from the on-voltage level to the first off-voltage level at a first moment, and the initialization signal may be changed from the on-voltage level to the first off-voltage level at a second moment different from the first moment. In a hold period in the second mode, the initialization signal may be increased from the first off-voltage level to a second off-voltage level higher than the first off-voltage level.

[0028] In the holding period in the second mode, a drain current of the fourth transistor may increase based on a difference between the second cut-off voltage level and the first cut-off voltage level.

[0029] The difference between the second cut-off voltage level and the first cut-off voltage level may depend on the driving frequency of the second mode.

[0030] In a frame period in the first mode, the scan signal may be changed from the on-voltage level to the first off-voltage level at a first moment, and the initialization signal may be changed from the on-voltage level to the first off-voltage level at a second moment different from the first moment. In a hold period in the second mode, the scan signal may be increased from the first off-voltage level to a second off-voltage level higher than the first off-voltage level.

[0031] In the holding period in the second mode, a leakage current of the third transistor from the gate node to the drain electrode of the first transistor may increase based on a difference between the first cut-off voltage level and the second cut-off voltage level.

[0032] In a frame period in the first mode, the scan signal may be changed from the on-voltage level to the first off-voltage level at a first moment, and the initialization signal may be changed from the on-voltage level to the first off-voltage level at a second moment different from the first moment. In a hold period in the second mode, the initialization signal may be reduced from the first off-voltage level to a second off-voltage level lower than the first off-voltage level.

[0033] In the holding period in the second mode, a leakage current of the fourth transistor may be reduced based on a difference between the second cut-off voltage level and the first cut-off voltage level.

[0034] In a frame period in the first mode, the scan signal may be changed from the on-voltage level to the first off-voltage level at a first moment, and the initialization signal may be changed from the on-voltage level to the first off-voltage level at a second moment different from the first moment. In a hold period in the second mode, the scan signal may be reduced from the first off-voltage level to a second off-voltage level lower than the first off-voltage level.

[0035] In the holding period in the second mode, a leakage current of the third transistor may be reduced based on a difference between the first cut-off voltage level and the second cut-off voltage level.

[0036] The third transistor may include a first sub-transistor and a second sub-transistor electrically connected in series between the gate node and the drain electrode of the first transistor. The fourth transistor may include a third sub-transistor and a fourth sub-transistor electrically connected in series between the gate node and a line of an initialization voltage.

[0037] The pixel may further include a fifth transistor, a sixth transistor, and a seventh transistor. The gate electrode of the fifth transistor may be electrically connected to the emission signal source. The source electrode of the fifth transistor may receive a first power supply voltage. The drain electrode of the fifth transistor may be electrically connected to the source electrode of the first transistor. The gate electrode of the sixth transistor may be electrically connected to the emission signal source. The source electrode of the sixth transistor may be electrically connected to the drain electrode of the first transistor. The drain electrode of the sixth transistor may be electrically connected to the anode of the organic light emitting diode. The gate electrode of the seventh transistor may receive a second instance of the initialization signal. The source electrode of the seventh transistor may be electrically connected to the anode of the organic light emitting diode. The drain electrode of the seventh transistor may be electrically connected to the line of the initialization voltage.

[0038] Embodiments may relate to pixels of a display device. The display device may have a first mode and a second mode (i.e., may operate in the first mode and the second mode). The driving frequency of the display device in the second mode may be lower than the driving frequency of the display device in the first mode. The pixel may include a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, and an organic light emitting diode. The first electrode of the capacitor may receive a first power supply voltage. The second electrode of the capacitor may be electrically connected to a gate node. The gate electrode of the first transistor may be electrically connected to the gate node. The drain electrode of the second transistor may be electrically connected to the source electrode of the first transistor. The gate electrode of the second transistor may receive a first instance of a scan signal in a holding period in the second mode. The third transistor may diode-connect the first transistor in response to a second instance of the scan signal in the holding period in the second mode. The fourth transistor may transmit an initialization voltage to the gate node in response to a first instance of an initialization signal in the holding period in the second mode. The organic light emitting diode may include an anode and a cathode. The cathode may receive a second power supply voltage different from the first power supply voltage. At the end of a frame period in the first mode, each of the scan signal and the initialization signal may be at a first cut-off voltage level. In the sustain period in the second mode, at least one of the scan signal and the initialization signal may be at a second off voltage level that is unequal to the first off voltage level.

[0039] Embodiments may relate to an organic light emitting diode (OLED) display device. The OLED display device may include the following elements: a display panel including pixels; a data driver electrically connected to the display panel and configured to provide data signals to the pixels; a power management circuit; a scan driver electrically connected to the power management circuit, electrically connected to the display panel, and including an initialization stage group configured to sequentially provide initialization signals to the pixels and a scanning stage group configured to sequentially provide scan signals to the pixels; and a controller configured to control the data driver, the power management circuit, and the scan driver. In a frame period in a first mode of the OLED display device, the power management circuit may provide a first gate-off voltage to each of the initialization stage group and the scanning stage group. In a holding period in a second mode of the OLED display device, the power management circuit may provide a first gate-off voltage to a first stage group in the initialization stage group and the scanning stage group, and may provide a second gate-off voltage unequal to the first gate-off voltage to a second stage group in the initialization stage group and the scanning stage group.

[0040] The power management circuit may include a switch block. The switch block may receive a hold flag signal from the controller. The switch block may selectively provide the first gate-off voltage or the second gate-off voltage to a second stage group of the initialization stage group and the scan stage group in response to the hold flag signal.

[0041] The switch block may include a first switch and a second switch. The first switch may provide a first gate-off voltage to a second stage group among the initialization stage group and the scanning stage group in response to a hold flag signal. The second switch may provide a second gate-off voltage to a second stage group among the initialization stage group and the scanning stage group in response to the hold flag signal.

[0042] The controller may include a static image detector. The static image detector may receive input image data at an input frame frequency. When the static image detector determines that the input image data represents a static image, the controller may set at least one frame period in the continuous frame periods as a holding period in the second mode so that the display panel may operate at a frequency lower than the input frame frequency in the second mode.

[0043] The display panel may be divided into panel areas. The controller may include a static image detector. The static image detector may receive input image data for the display panel at an input frame frequency, and may divide the input image data into local image data sets respectively for the panel areas. When the static image detector determines that the identified local image data set in the local image data set represents a static image, the controller may, in a second mode, set at least one frame period in the continuous frame period as a holding period for a corresponding panel area in the panel area corresponding to the identified local image data set, so that the corresponding panel area may operate at a frequency lower than the input frame frequency in the second mode.

[0044] The second stage group of the initialization stage group and the scanning stage group may include stage subgroups electrically connected to the panel areas, respectively. The power management circuit may include a switch block electrically connected to the stage subgroups, respectively, and configured to selectively provide a first gate-off voltage or a second gate-off voltage to each of the stage subgroups.

[0045] In an embodiment, in the low-frequency holding period, the cut-off voltage level of at least one of the scanning signal applied to the third transistor (e.g., the threshold voltage compensation transistor) and the initialization signal applied to the fourth transistor (e.g., the gate initialization transistor) may be unequal to the voltage level in the normal frequency frame period. Advantageously, the voltage distortion of the gate node of the first transistor (e.g., the driving transistor) under low-frequency driving can be compensated, and satisfactory image quality of the organic light emitting diode display device can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a circuit diagram illustrating a pixel of an organic light emitting diode display device according to an embodiment.

[0047] Figure 2 is a timing diagram for describing an operation of a pixel of an organic light emitting diode display device in a normal driving mode according to an embodiment.

[0048] Figure 3 is a timing diagram for describing an operation of a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0049] Figure 4 is a circuit diagram illustrating a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0050] Figure 5 is a graph illustrating voltage-current characteristics of a transistor included in a pixel of an organic light emitting diode display device according to an embodiment.

[0051] Figure 6is a timing diagram for describing an operation of a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0052] Figure 7 is a timing diagram for describing an operation of a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0053] Figure 8 is a circuit diagram illustrating a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0054] Fig. 9 is a timing diagram for describing an operation of a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0055] Fig.10 is a circuit diagram illustrating a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0056] Fig.11 is a graph illustrating voltage-current characteristics of a transistor included in a pixel of an organic light emitting diode display device according to an embodiment.

[0057] Fig.12 is a timing diagram for describing an operation of a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0058] Fig.13 is a circuit diagram illustrating a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0059] Fig.14 is a timing diagram for describing an operation of a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0060] Fig.15 is a circuit diagram illustrating a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0061] Fig.16 is a timing diagram for describing an operation of a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0062] Fig.17 is a circuit diagram illustrating a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0063] Fig.18 is a block diagram illustrating an organic light emitting diode display device according to an embodiment.

[0064] Fig.19is a circuit diagram illustrating a switching block included in a power management circuit of an organic light emitting diode display device according to an embodiment.

[0065] Fig. 20 is a block diagram illustrating a scan driver included in an organic light emitting diode display device according to an embodiment.

[0066] Fig.21 is a circuit diagram illustrating stages included in a scan driver according to an embodiment.

[0067] Fig. 22 is a timing diagram for describing the operation of the organic light emitting diode display device according to the embodiment.

[0068] Fig.23 is a block diagram illustrating an organic light emitting diode display device according to an embodiment.

[0069] Fig.24 is a diagram for describing a panel area of ​​a display panel of an organic light emitting diode display device driven at different driving frequencies according to an embodiment.

[0070] Fig.25 is a timing diagram for describing the operation of the organic light emitting diode display device according to the embodiment.

[0071] Fig.26 An electronic device including an organic light emitting diode display device according to an embodiment. DETAILED DESCRIPTION

[0072] Embodiments are described with reference to the accompanying drawings. Although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another element. The first element can be referred to as the second element without departing from the teaching of one or more embodiments. The description of an element such as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can be used to distinguish different categories or sets of elements. For simplicity, the terms "first", "second", etc. can respectively represent "first type (or first set)", "second type (or second set)", etc. The term "connection" or the term "coupling" can mean "electrical connection" or "not electrically connected through an intermediate transistor". The term "insulation" can mean "electrical insulation" or "electrical isolation". The term "drive" can mean "operation" or "control". The "source" of a transistor can mean the "source electrode" of a transistor. The "drain" of a transistor can mean the "drain electrode" of a transistor. The "gate" of a transistor can mean the "gate electrode" of a transistor. The term "different" can mean "unequal". The term “different from” may mean “not equal to”. The term “same as” may mean “equal to”. A statement that a signal has a voltage level may mean that the signal is at the voltage level; for example, “a scanning signal having a voltage level of the second gate-off voltage” may mean “a scanning signal at the voltage level of the second gate-off voltage” or “a scanning signal at the second gate-off voltage”.

[0073] Figure 1 is a circuit diagram illustrating a pixel of an organic light emitting diode display device according to an embodiment.

[0074] refer to Figure 1 The pixel 100 of the organic light emitting diode display device may include a capacitor CST, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and an organic light emitting diode EL. The pixel 100 may further include a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0075] The capacitor CST may store the data signal DS transmitted through the second transistor T2 and the (diode-connected) first transistor T1. The capacitor CST may be referred to as a storage capacitor. The capacitor CST may include a first electrode coupled to a line of the first power supply voltage ELVDD and may include a second electrode coupled to the gate node NG.

[0076] The first transistor T1 may generate a driving current based on a data signal DS stored in the capacitor CST or based on a voltage of a gate node NG. The first transistor T1 may be referred to as a driving transistor for driving the organic light emitting diode EL. The first transistor T1 may include a gate electrode coupled to a second electrode of the capacitor CST (through a gate node NG), a source electrode coupled to a line of a first power supply voltage ELVDD (through a fifth transistor T5), and a drain electrode coupled to the organic light emitting diode EL (through a sixth transistor T6).

[0077] The second transistor T2 may transmit the data signal DS toward / toward the source of the first transistor T1 in response to (the first instance of) the scan signal SS. The second transistor T2 may be referred to as a switching transistor or a scan transistor for transmitting the data signal DS of the data line. The second transistor T2 may include a gate electrode receiving the scan signal SS, a source receiving the data signal DS, and a drain coupled to the source of the first transistor T1.

[0078] The third transistor T3 may diode-connect the first transistor T1 (by electrically connecting the drain of the first transistor T1 to the gate of the first transistor T1) in response to (the second instance of) the scan signal SS. The third transistor T3 may be referred to as a threshold voltage compensation transistor for compensating the threshold voltage of the first transistor T1. The third transistor T3 may include a gate electrode receiving the scan signal SS, a drain coupled to the drain of the first transistor T1, and a source coupled to the gate electrode of the first transistor T1 (through a gate node NG). When the scan signal SS is applied, the data signal DS transmitted by the second transistor T2 may be provided to the capacitor CST through the first transistor T1 diode-connected by the third transistor T3. Therefore, the capacitor CST may store the data signal DS when the threshold voltage of the first transistor T1 is compensated.

[0079] The fourth transistor T4 may transmit the initialization voltage VINIT to the gate node NG in response to (the first instance of) the initialization signal SI. The fourth transistor T4 may be referred to as a gate initialization transistor for initializing the gate node NG. The fourth transistor T4 may include a gate electrode receiving the initialization signal SI, a source / drain coupled to the gate node NG, and a drain / source coupled to a line of the initialization voltage VINIT. When the initialization signal SI is applied, the fourth transistor T4 may use the initialization voltage VINIT to initialize the gate node NG, the capacitor CST, and / or the gate electrode of the first transistor T1.

[0080] The fifth transistor T5 may couple the line of the first power supply voltage ELVDD to the source of the first transistor T1 in response to an emission signal SEM from an emission signal source, and the sixth transistor T6 may couple the drain of the first transistor T1 to the anode of the organic light emitting diode EL in response to the emission signal SEM. The fifth transistor T5 and the sixth transistor T6 may be referred to as emission transistors for allowing the organic light emitting diode EL to emit light. The fifth transistor T5 may include a gate electrode receiving the emission signal SEM, a source coupled to the line of the first power supply voltage ELVDD, and a drain coupled to the source of the first transistor T1. The sixth transistor T6 may include a gate electrode receiving the emission signal SEM, a source coupled to the drain of the first transistor T1, and a drain coupled to the anode of the organic light emitting diode EL. When the emission signal SEM is applied, the fifth transistor T5 and the sixth transistor T6 may be turned on, and a path of a drive current from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS may be formed.

[0081] The seventh transistor T7 may transmit the initialization voltage VINIT to the anode of the organic light emitting diode EL in response to (the second instance of) the initialization signal SI. The seventh transistor T7 may be referred to as a diode initialization transistor for initializing the organic light emitting diode EL. The seventh transistor T7 may include a gate electrode receiving the initialization signal SI, a source / drain coupled to the anode of the organic light emitting diode EL, and a drain / source coupled to a line of the initialization voltage VINIT. When the initialization signal SI is applied, the seventh transistor T7 may initialize the organic light emitting diode EL using the initialization voltage VINIT.

[0082] The organic light emitting diode EL may emit light based on the driving current generated / provided by the first transistor T1. The organic light emitting diode EL may include an anode coupled to the drain of the sixth transistor T6 and a cathode coupled to the line of the second power supply voltage ELVSS. When the emission signal SEM is applied, the driving current generated by the first transistor T1 may be provided to the organic light emitting diode EL, and the organic light emitting diode EL may emit light based on the driving current.

[0083] In order to reduce power consumption, the organic light emitting diode display device including the pixel 100 may perform low-frequency driving, for example, when displaying a static image. When the low-frequency driving is performed, each pixel 100 may not receive the initialization signal SI, the scan signal SS, and the data signal DS in at least some frame periods or in the low-frequency holding period, and may emit light based on the data signal DS that has been stored in the capacitor CST in the previous frame period. Due to the leakage current of the transistors T1 to T7 of the pixel 100, especially due to the leakage current of the third transistor T3 and the fourth transistor T4 coupled to the second electrode of the capacitor (through the gate node NG), the data signal DS stored in the capacitor CST (i.e., the voltage of the gate node NG) may be distorted, and therefore the image quality of the organic light emitting diode display device may be unsatisfactory.

[0084] In order to reduce the leakage current of the third transistor T3 and the fourth transistor T4, as Figure 1 As illustrated in , each of the third transistor T3 and the fourth transistor T4 may have a dual transistor structure. For example, the third transistor T3 may include a first sub-transistor T3-1 and a second sub-transistor T3-2 coupled in series between the gate node NG and the drain of the first transistor T1; the fourth transistor T4 may include a third sub-transistor T4-1 and a fourth sub-transistor T4-2 coupled in series between the gate node NG and the line of the initialization voltage VINIT. Since the third transistor T3 includes the first sub-transistor T3-1 and the second sub-transistor T3-2, the leakage current of the third transistor T3 between the drain of the first transistor T1 and the gate node NG can be reduced. Since the fourth transistor T4 includes the third sub-transistor T4-1 and the fourth sub-transistor T4-2, the leakage current of the fourth transistor T4 between the line of the initialization voltage VINIT and the gate node NG can be reduced.

[0085] However, a parasitic capacitor may be formed between the node NT3 of the third transistor T3 and the scan line transmitting the scan signal SS, and a leakage current of the first sub-transistor T3-1 from the node NT3 of the third transistor T3 to the gate node NG may occur. In addition, a parasitic capacitor may be formed between the node NT4 of the fourth transistor T4 and the initialization line transmitting the initialization signal SI, and a leakage current of the third sub-transistor T4-1 from the node NT4 of the fourth transistor T4 to the gate node NG may occur. Therefore, the voltage of the gate node NG may increase, so that the driving current of the first transistor T1 may be reduced, and thus the brightness of the organic light emitting diode EL may be reduced.

[0086] In the pixel 100 of the organic light emitting diode display device, in order to compensate for the voltage distortion of the gate node NG caused by the leakage current of the third transistor T3, the fourth transistor T4, the first sub-transistor T3-1 and / or the third sub-transistor T4-1, in the low frequency holding period, the cut-off voltage level (e.g., high voltage level) of at least one of the scan signal SS applied to the third transistor T3 and the initialization signal SI applied to the fourth transistor T4 can be adjusted. In the low frequency holding period, the scan signal SS applied to the third transistor T3 and the initialization signal SI applied to the fourth transistor T4 can have different / unequal cut-off voltage levels. Therefore, the leakage current to the gate node NG can be compensated or reduced, and thus the voltage distortion of the gate node NG can be compensated.

[0087] Figure 2 is a timing diagram for describing the operation of a pixel of an organic light emitting diode display device in a normal driving mode according to an embodiment, Figure 3 is a timing diagram for describing the operation of a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment, Figure 4 is a circuit diagram illustrating a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment, Figure 5 is a graph illustrating voltage-current characteristics of a transistor included in a pixel of an organic light emitting diode display device according to an embodiment, and Figure 6 is a timing diagram for describing an operation of a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0088] refer to Figure 1 and Figure 2 In the normal driving mode, a plurality of frame periods FP1, FP2, FP3, and FP4 may be set as a normal driving period NDP, and the display panel of the organic light emitting diode display device may be driven at a normal driving frequency. For example, the normal driving frequency may be about 60 Hz or about 120 Hz.

[0089] In each frame period FP1, FP2, FP3, and FP4 of the normal driving period NDP, the scan signal SS and the initialization signal SI may be asynchronous (i.e., have a turn-on voltage level at different times) and may be applied to each pixel PX, and the data voltage VD may be applied to each pixel PX as the data signal DS. A gate turn-on voltage VGL (e.g., a low gate voltage) may be applied as a turn-on voltage level for each of the scan signal SS and the initialization signal SI. For example, Figure 2As illustrated in , the initialization signal SI having the on voltage level and the scan signal SS having the on voltage level may be sequentially applied to the pixel 100. When the initialization signal SI having the on voltage level is applied, the fourth transistor T4 may be turned on, the initialization voltage VINIT may be applied to the gate node NG through the turned-on fourth transistor T4, and the gate node NG may have the initialization voltage VINIT as the gate node voltage V_NG. Thereafter, when the scan signal SS having the on voltage level is applied, the second transistor T2 and the third transistor T3 may be turned on, the first transistor T1 may be diode-connected by the turned-on third transistor T3, and the data voltage VD may be applied to the second electrode (or gate node NG) of the capacitor CST through the turned-on second transistor T2 and the diode-connected first transistor T1 as the data signal DS. Therefore, the gate node voltage V_NG at the gate node NG may be equal to the voltage VD-VTH (i.e., VD minus VTH), i.e., the threshold voltage VTH of the first transistor T1 is subtracted from the data voltage VD.

[0090] Each of the scan signal SS and the initialization signal SI may be changed from the on voltage level to the off voltage level, and the emission signal SEM may be changed to the on voltage level. A first gate off voltage VGH1 (e.g., a first high gate voltage) may be applied as the off voltage level for each of the scan signal SS and the initialization signal SI. When the emission signal SEM having the on voltage level is applied to the pixel 100, the fifth transistor T5 and the sixth transistor T6 may be turned on, the driving current generated by the first transistor T1 may be provided to the organic light emitting diode EL, and the organic light emitting diode EL may emit light based on the driving current. When the organic light emitting diode EL emits light, the leakage current of the third transistor T3 and / or the fourth transistor T4 may flow to the gate node NG, and thus the gate node voltage V_NG may be distorted, or may gradually increase. However, in the normal driving mode or in the normal driving period NDP, since each pixel 100 is driven in each frame period FP1, FP2, FP3 and FP4, or since the scan signal SS, the initialization signal SI and the data signal DS are applied to each pixel 100 in each frame period FP1, FP2, FP3 and FP4, the gate node voltage V_NG may be initialized or refreshed in each frame period FP1, FP2, FP3 and FP4. Therefore, the voltage difference between the gate node voltage V_NG at the emission start time point in each frame period (e.g., FP2) and the gate node voltage V_NG at the emission end time point in the previous frame period (e.g., FP1) may be within an allowable or tolerable voltage difference, the brightness difference between the brightness of the pixel 100 at the emission start time point in each frame period (e.g., FP2) and the brightness of the pixel 100 at the emission end time point in the previous frame period (e.g., FP1) may be within an allowable or tolerable brightness difference, and therefore the flicker caused by the distortion of the gate node voltage V_NG may not significantly affect the image display quality. However, in a conventional organic light emitting diode display device, significant flickering may occur in a low-frequency driving mode.

[0091] refer to Figure 1 and Figure 3, in the low-frequency driving mode, at least one (e.g., FP2) of the continuous frame periods (e.g., FP1, FP2) can be set as the low-frequency holding period LHP, the remaining frame periods (e.g., FP1) can be set as the normal driving period NDP, and thus the display panel can be driven at a low frequency lower than the normal driving frequency. The number of frame periods (e.g., FP2) set as the low-frequency holding period LHP among the continuous frame periods (e.g., FP1, FP2) can be determined according to the low frequency. For example, if the normal driving frequency is NHz, and if the low frequency is M Hz, where M is an integer less than N, then M frame periods among the N continuous frame periods can be set as the low-frequency holding period LHP. Although Figure 3 It is illustrated that the normal driving frequency is about 60 Hz and the low frequency is about 30 Hz, and the low frequency in the low-frequency driving mode may be a frequency lower than the normal driving frequency and not equal to 30 Hz.

[0092] In each of the frame periods FP1 and FP3, in the normal driving period NDP in which the display panel is driven, the scan signal SS and the initialization signal SI may be applied to each pixel PX, the data voltage VD may be applied to each pixel PX as the data signal DS, and each pixel PX may emit light based on the applied data voltage VD. In each low frequency holding period LHP, the display panel may not be driven. The display panel not being driven may mean that the on-voltage level of the scan signal SS, the on-voltage level of the initialization signal SI, and the data voltage VD are not applied to the pixel 100 of the display panel. In the low frequency holding period LHP, each pixel 100 may not receive the on-voltage level of the scan signal SS, the on-voltage level of the initialization signal SI, and the data voltage VD, and may emit light based on the data signal DS that has been stored in the capacitor CST in the previous frame period.

[0093] In the conventional organic light emitting diode display device, in the low frequency holding period LHP, the on-voltage level of the scan signal SS, the on-voltage level of the initialization signal SI, and the data voltage VD are not applied to any pixel 100. Figure 3210 in, the leakage current of the third transistor T3 and / or the fourth transistor T4 may flow to the gate node NG, and thus the gate node voltage V_NG may be distorted, or may gradually increase. Therefore, the voltage difference between the gate node voltage V_NG at the emission start time point in the normal driving period NDP directly after the low-frequency holding period LHP and the gate node voltage V_NG at the emission end time point in the low-frequency holding period LHP may be greater than the allowable or tolerable voltage difference, the brightness difference between the brightness of the pixel 100 at the emission start time point in the normal driving period NDP directly after the low-frequency holding period LHP and the brightness difference between the brightness of the pixel 100 at the emission end time point in the low-frequency holding period LHP may be greater than the allowable or tolerable brightness difference, and thus significant flicker of the image may occur due to the brightness difference. That is, in a conventional organic light emitting diode display device, significant flicker may be caused by the distortion 210 of the gate node voltage V_NG in the low-frequency driving mode.

[0094] In order to reduce or prevent flickering, in the organic light emitting diode display device according to the embodiment, in the low frequency holding period LHP, the scan signal SS applied to the third transistor T3 may have a first cut-off voltage level, and the initialization signal SI applied to the fourth transistor T4 may have a second cut-off voltage level different from the first cut-off voltage level. Figure 3 As illustrated in FIG. 1 , in the low frequency holding period LHP, the initialization signal SI may increase to a second cut-off voltage level higher than the first cut-off voltage level.

[0095] For example, Figure 3As illustrated in FIG. 1 , in the normal driving period NDP in which the display panel is driven, the scan signal SS and the initialization signal SI may have an on-voltage level at different moments, and each of the scan signal SS and the initialization signal SI may be changed to a third off-voltage level after the on-voltage level. The on-voltage level of the scan signal SS and the initialization signal SI in the normal driving period NDP may be a voltage level of the gate on voltage VGL (e.g., a low gate voltage), and the third off-voltage level of the scan signal SS and the initialization signal SI in the normal driving period NDP may be a voltage level of the first gate off voltage VGH1 (e.g., a first high gate voltage). In the low frequency holding period LHP, the scan signal SS applied to the third transistor T3 may have a first off-voltage level substantially the same as the third off-voltage level. That is, the first off-voltage level of the scan signal SS in the low frequency holding period LHP may be a voltage level of the first gate off voltage VGH1. In addition, in the low frequency holding period LHP, the initialization signal SI applied to the fourth transistor T4 may increase from the third off-voltage level to a second off-voltage level higher than the third off-voltage level. The second turn-off voltage level of the initialization signal SI in the low frequency holding period LHP may be a voltage level of a second gate-off voltage VGH2 (eg, a second high gate voltage) that is higher than the first gate-off voltage VGH1 .

[0096] Therefore, in the low frequency holding period LHP, if Figure 4 As illustrated in FIG. 1 , according to an embodiment, a scan signal SS having a voltage level of a first gate-off voltage VGH1 and an initialization signal SI having a voltage level of a second gate-off voltage VGH2 higher than the first gate-off voltage VGH1 may be applied to a pixel 100a of an organic light emitting diode display device. Figure 5 As shown in the figure, Figure 51 shows the voltage-current (Vgs-Ids) characteristics of the fourth transistor T4 in the on-state (ON-STATE) and the off-state (OFF-STATE). If the initialization signal SI applied to the fourth transistor T4 is changed from the first gate-off voltage VGH1 to the second gate-off voltage VGH2 higher than the first gate-off voltage VGH1, the voltage-current characteristics of the fourth transistor T4 can be changed from the first operating point 310 to the second operating point 330. Therefore, the leakage current ILT4 of the fourth transistor T4 from the gate node NG to the line of the initialization voltage VINIT can be increased based on the second cut-off voltage level higher than the third cut-off voltage level or the voltage level of the second gate-off voltage VGH2 higher than the first gate-off voltage VGH1. In the low-frequency holding period LHP, since the leakage current ILT4 of the fourth transistor T4 from the gate node NG to the line of the initialization voltage VINIT increases, the distortion 210 of the gate node voltage V_NG can be as shown by Figure 3 is compensated as indicated by 220 in FIG. Figure 3 As shown in 220 in FIG. 1 , the gate node voltage V_NG may not increase or may decrease in the low-frequency holding period LHP. Therefore, the voltage difference between the gate node voltage V_NG at the emission start time point in the normal driving period NDP directly after the low-frequency holding period LHP and the gate node voltage V_NG at the emission end time point in the low-frequency holding period LHP may be within an allowable or tolerable voltage difference, and the brightness difference between the brightness of the pixel 100a at the emission start time point in the normal driving period NDP directly after the low-frequency holding period LHP and the brightness of the pixel 100a at the emission end time point in the low-frequency holding period LHP may be within an allowable or tolerable brightness difference, and thus flickering in the low-frequency driving mode may be minimized or prevented.

[0097] The difference between the second cut-off voltage level and the third cut-off voltage level or the voltage level difference between the second gate cut-off voltage VGH2 and the first gate cut-off voltage VGH1 can be determined according to the driving frequency or low frequency of the display panel. The lower the driving frequency in the low frequency driving mode, the greater the voltage level difference between the second gate cut-off voltage VGH2 and the first gate cut-off voltage VGH1. For example, Figure 3 and Figure 6As illustrated in , the second gate-off voltage VGH2′ in the low-frequency holding period LHP in the low-frequency driving mode of the display panel driven at about 20 Hz may be higher than the second gate-off voltage VGH2 in the low-frequency holding period LHP in the low-frequency driving mode of the display panel driven at about 30 Hz. Therefore, although the distortion of the gate node voltage V_NG at the low frequency of about 20 Hz may be greater than the distortion of the gate node voltage V_NG at the low frequency of about 30 Hz, the second gate-off voltage VGH2′ at the low frequency of about 20 Hz may be higher than the second gate-off voltage VGH2 at the low frequency of about 30 Hz, and therefore, the distortion 210 of the gate node voltage V_NG at the low frequency of about 20 Hz may be as shown by Figure 6 The ground indicated by 230 is fully compensated.

[0098] refer to Figure 3 , Figure 4 , Figure 5 and Figure 6 In the pixel 100a of the organic light emitting diode display device according to the embodiment, in the low frequency holding period LHP, the cut-off voltage level of the initialization signal SI applied to the fourth transistor T4 can be increased. Therefore, the leakage current ILT4 of the fourth transistor T4 from the gate node NG can be increased, the distortion 210 of the gate node voltage V_NG under the low frequency driving can be compensated, and thus the satisfactory image quality of the organic light emitting diode display device can be obtained.

[0099] Figure 7 is a timing diagram for describing the operation of a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment, and Figure 8 is a circuit diagram illustrating a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0100] refer to Figure 7 and Figure 8 , in the low frequency holding period LHP, a scan signal SS having a voltage level of a second gate-off voltage VGH2 higher than the first gate-off voltage VGH1 and an initialization signal SI having a voltage level of the first gate-off voltage VGH1 may be applied to the pixel 100b of the organic light emitting diode display device. In the low frequency holding period LHP, a leakage current ILT3 of the third transistor T3 from the gate node NG to the drain of the first transistor T1 may be increased based on the scan signal SS having a voltage level of the second gate-off voltage VGH2 higher than the first gate-off voltage VGH1. Therefore, in the low frequency holding period LHP, since the leakage current ILT3 of the third transistor T3 from the gate node NG to the drain of the first transistor T1 increases, the distortion 210 of the gate node voltage V_NG may be as shown by Figure 7 is compensated as indicated by 240 in FIG. Figure 7 As illustrated in FIG. 240 , in the low frequency holding period LHP, the gate node voltage V_NG may not increase, or may decrease, and thus flickering in the low frequency driving mode may be minimized or prevented.

[0101] In the pixel 100b, in the low frequency holding period LHP, the cut-off voltage level of the scan signal SS applied to the third transistor T3 can be increased. Therefore, the leakage current ILT3 of the third transistor T3 from the gate node NG can be increased, the distortion 210 of the gate node voltage V_NG under the low frequency driving can be compensated, and thus the satisfactory image quality of the organic light emitting diode display device can be obtained.

[0102] Fig. 9 is a timing diagram for describing the operation of a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment, Fig.10 is a circuit diagram illustrating a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment, and Fig.11 is a graph illustrating voltage-current characteristics of a transistor included in a pixel of an organic light emitting diode display device according to an embodiment.

[0103] refer to Fig. 9 and Fig.10 , in the low frequency holding period LHP, according to an embodiment, the scan signal SS having a voltage level of the first gate-off voltage VGH1 and the initialization signal SI having a voltage level of the second gate-off voltage VGH2″ lower than the first gate-off voltage VGH1 may be applied to the pixel 100c of the organic light emitting diode display device. If the initialization signal SI applied to the fourth transistor T4 is changed from the first gate-off voltage VGH1 to the second gate-off voltage VGH2″ lower than the first gate-off voltage VGH1, as shown Fig.11 As illustrated in , the voltage-current characteristics of the fourth transistor T4 or the voltage-current characteristics of the third sub-transistor T4-1 and the fourth sub-transistor T4-2 can be changed from the first operating point 310 to the second operating point 350. Therefore, the leakage current ILT4-1 of the fourth transistor T4 from the node NT4 of the fourth transistor T4 to the gate node NG (or specifically the leakage current ILT4-1 of the third sub-transistor T4-1) can be reduced based on the initialization signal SI having a voltage level of the second gate-off voltage VGH2″ lower than the first gate-off voltage VGH1. Therefore, in the low-frequency holding period LHP, since the leakage current ILT4-1 of the fourth transistor T4 to the gate node NG (or specifically the leakage current ILT4-1 of the third sub-transistor T4-1) is reduced, the distortion 210 of the gate node voltage V_NG can be as shown by Fig. 9 That is, as indicated by Fig. 9 As indicated by 250 in FIG. 1 , the increment of the gate node voltage V_NG in the low frequency holding period LHP can be reduced, and thus the flicker in the low frequency driving mode can be minimized or prevented.

[0104] In the pixel 100c, in the low frequency holding period LHP, the cut-off voltage level of the initialization signal SI applied to the fourth transistor T4 can be reduced. Therefore, the leakage current ILT4-1 of the fourth transistor T4 to the gate node NG can be reduced, the distortion 210 of the gate node voltage V_NG under the low frequency driving can be compensated, and thus the satisfactory image quality of the organic light emitting diode display device can be obtained.

[0105] Fig.12 is a timing diagram for describing the operation of a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment, and Fig.13 is a circuit diagram illustrating a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0106] refer to Fig.12 and Fig.13 , in the low frequency holding period LHP, a scan signal SS having a voltage level of a second gate-off voltage VGH2″ lower than the first gate-off voltage VGH1 and an initialization signal SI having a voltage level of the first gate-off voltage VGH1 may be applied to the pixel 100d of the organic light emitting diode display device. The leakage current ILT3-1 of the first sub-transistor T3-1 from the node NT3 of the third transistor T3 to the gate node NG may be reduced based on the scan signal SS having a voltage level of the second gate-off voltage VGH2″ lower than the first gate-off voltage VGH1. Therefore, in the low frequency holding period LHP, since the leakage current ILT3-1 of the first sub-transistor T3-1 to the gate node NG is reduced, the distortion 210 of the gate node voltage V_NG may be as shown by Fig.12 That is, as indicated by 260 in Fig.12 As indicated by 260 in FIG. 1 , the gate node voltage V_NG in the low frequency holding period LHP may not increase significantly, and thus flickering in the low frequency driving mode may be minimized or prevented.

[0107] In the pixel 100d, in the low frequency holding period LHP, the off voltage level of the scan signal SS applied to the third transistor T3 can be reduced. Therefore, the leakage current ILT3-1 of the third transistor T3 to the gate node NG can be reduced, the distortion 210 of the gate node voltage V_NG under the low frequency driving can be compensated, and thus the satisfactory image quality of the organic light emitting diode display device can be obtained.

[0108] Fig.14 is a timing diagram for describing the operation of a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment, and Fig.15 is a circuit diagram illustrating a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0109] refer to Fig.14 and Fig.15 , in the low frequency holding period LHP, a scan signal SS having a voltage level of a second gate-off voltage VGH2 higher than the first gate-off voltage VGH1 and an initialization signal SI having a voltage level of a second gate-off voltage VGH2 higher than the first gate-off voltage VGH1 may be applied to the pixel 100e of the organic light emitting diode display device. In the low frequency holding period LHP, a leakage current ILT3 of the third transistor T3 from the gate node NG to the drain of the first transistor T1 may be increased based on the scan signal SS having a voltage level of the second gate-off voltage VGH2 higher than the first gate-off voltage VGH1, and a leakage current ILT4 of the fourth transistor T4 from the gate node NG to the line of the initialization voltage VINIT may be increased based on the initialization signal SI having a voltage level of the second gate-off voltage VGH2 higher than the first gate-off voltage VGH1. Therefore, in the low frequency holding period LHP, since the leakage current ILT3 of the third transistor T3 and the leakage current ILT4 of the fourth transistor T4 from the gate node NG are increased, the distortion 210 of the gate node voltage V_NG may be as shown by Fig.14 is compensated as indicated by 270 in FIG. Fig.14 As indicated by 270 in FIG. 1 , in the low frequency holding period LHP, the gate node voltage V_NG may not increase, or may decrease, and thus flickering in the low frequency driving mode may be minimized or prevented.

[0110] In the pixel 100e, in the low frequency holding period LHP, the cut-off voltage level of the scan signal SS applied to the third transistor T3 and the cut-off voltage level of the initialization signal SI applied to the fourth transistor T4 can be increased. Therefore, the leakage current ILT3 of the third transistor T3 and the leakage current ILT4 of the fourth transistor T4 from the gate node NG can be increased, the distortion 210 of the gate node voltage V_NG under the low frequency driving can be compensated, and thus the satisfactory image quality of the organic light emitting diode display device can be obtained.

[0111] Fig.16 is a timing diagram for describing the operation of a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment, and Fig.17 is a circuit diagram illustrating a pixel of an organic light emitting diode display device in a low frequency driving mode according to an embodiment.

[0112] refer to Fig.16 and Fig.17 , in the low frequency holding period LHP, a scan signal SS having a voltage level of a second gate-off voltage VGH2” lower than the first gate-off voltage VGH1 and an initialization signal SI having a voltage level of a second gate-off voltage VGH2” lower than the first gate-off voltage VGH1 may be applied to the pixel 100f of the organic light emitting diode display device. A leakage current ILT3-1 of the first sub-transistor T3-1 from the node NT3 of the third transistor T3 to the gate node NG may be reduced based on the scan signal SS having a voltage level of the second gate-off voltage VGH2” lower than the first gate-off voltage VGH1, and a leakage current ILT4-1 of the third sub-transistor T4-1 from the node NT4 of the fourth transistor T4 to the gate node NG may be reduced based on the initialization signal SI having a voltage level of the second gate-off voltage VGH2” lower than the first gate-off voltage VGH1. Therefore, in the low frequency holding period LHP, since the leakage current ILT3-1 of the first sub-transistor T3-1 and the leakage current ILT4-1 of the third sub-transistor T4-1 to the gate node NG are reduced, the distortion 210 of the gate node voltage V_NG may be as shown by Fig.16 That is, as indicated by 280 in Fig.16 As indicated by 280 in FIG. 1 , the increment of the gate node voltage V_NG in the low frequency holding period LHP may be reduced, and thus flickering in the low frequency driving mode may be minimized or prevented.

[0113] In the pixel 100f, in the low frequency holding period LHP, the cut-off voltage level of the scan signal SS applied to the third transistor T3 and the cut-off voltage level of the initialization signal SI applied to the fourth transistor T4 can be reduced. Therefore, the leakage current ILT3-1 of the first sub-transistor T3-1 and the leakage current ILT4-1 of the third sub-transistor T4-1 to the gate node NG can be reduced, the distortion 210 of the gate node voltage V_NG under the low frequency driving can be compensated, and thus the satisfactory image quality of the organic light emitting diode display device can be obtained.

[0114] Fig.18 is a block diagram illustrating an organic light emitting diode display device according to an embodiment, Fig.19 is a circuit diagram illustrating a switch block included in a power management circuit of an organic light emitting diode display device according to an embodiment, Fig. 20 is a block diagram illustrating a scan driver included in an organic light emitting diode display device according to an embodiment, Fig.21 It is shown in Fig. 20 A circuit diagram of a stage included in a scan driver, and Fig. 22 is a timing diagram for describing the operation of the organic light emitting diode display device according to the embodiment.

[0115] refer to Fig.18 According to an embodiment, the organic light emitting diode display device 400 may include: a display panel 410 including a plurality of pixels PX, a data driver 420 that provides a data signal DS to the plurality of pixels PX, a power management circuit 430 that generates a gate-on voltage VGL and a gate-off voltage VGH, a scan driver 440 that provides a scan signal SS and an initialization signal SI to the plurality of pixels PX based on the gate-on voltage VGL and the gate-off voltage VGH, an emission driver 470 that provides an emission signal SEM to the plurality of pixels PX, and a controller 480 that controls the operation of the organic light emitting diode display device 400.

[0116] The display panel 410 may include a plurality of data signal lines, a plurality of scan signal lines, a plurality of initialization signal lines, a plurality of emission signal lines, and a plurality of pixels PX coupled to the signal lines. According to an embodiment, each pixel PX may be Figure 1 100 pixels, Figure 4 Pixel 100a, Figure 8 Pixel 100b, Fig.10 Pixel 100c, Fig.13 Pixel 100d, Fig.15 Pixel 100e or Fig.17The pixel 100f, etc. The turn-off voltage levels of the scan signal SS applied to the third transistor of each pixel PX and the initialization signal SI applied to the fourth transistor may be adjusted in the low-frequency holding period.

[0117] The data driver 420 may generate a data signal DS based on a data control signal DCTRL and output image data ODAT received from the controller 480, and may provide the data signal DS to a plurality of pixels PX through a plurality of data signal lines. The data control signal DCTRL may include an output data enable signal ODE, a horizontal start signal, and a load signal. The data driver 420 may receive the output image data ODAT from the controller 480 at an output frame frequency OFF. The data driver 420 may receive the output image data ODAT at an output frame frequency OFF substantially the same as the input frame frequency IFF when displaying a moving image, and may receive the output image data ODAT at an output frame frequency OFF lower than the input frame frequency IFF when displaying a static image. In addition, the data driver 420 may receive the output data enable signal ODE synchronously with the output image data ODAT. The data driver 420 and the controller 480 may be implemented with a signal integrated circuit, and the signal integrated circuit may be referred to as a timing controller embedded data driver (TED). The data driver 420 and the controller 480 may be implemented with separate integrated circuits.

[0118] The power management circuit 430 may generate a gate-on voltage VGL and a gate-off voltage VGH provided to the scan driver 440. The gate-on voltage VGL may be a low gate voltage, and the gate-off voltage VGH may be a high gate voltage. The power management circuit 430 may be implemented with an integrated circuit (e.g., a power management integrated circuit (PMIC)). The power management circuit 430 may be included in the data driver 420 or the controller 480.

[0119] In the normal driving period, the power management circuit 430 may provide the first gate-off voltage VGH1 as the gate-off voltage VGH to the initialization stage group 450 and the scanning stage group 460 of the scanning driver 440. In the low-frequency holding period, the power management circuit 430 may provide the first gate-off voltage VGH1 as the gate-off voltage VGH to the first stage group of the initialization stage group 450 and the scanning stage group 460, and may provide the second gate-off voltage VGH2 or VGH2″ different from the first gate-off voltage VGH1 as the gate-off voltage VGH to the second stage group of the initialization stage group 450 and the scanning stage group 460. Although Fig.18The power management circuit 430 is illustrated as selectively providing the first gate-off voltage VGH1 or the second gate-off voltage VGH2 or VGH2 ″ to the initialization stage group 450 , but the first gate-off voltage VGH1 or the second gate-off voltage VGH2 or VGH2 ″ may be selectively provided to the scan stage group 460 and / or the initialization stage group 450 .

[0120] During the low frequency hold period, in order to Figure 3 As illustrated in FIG. 4 , the initialization signal SI having a voltage level of a second gate-off voltage VGH2 higher than the first gate-off voltage VGH1 is provided to each pixel PX, and the power management circuit 430 may provide the second gate-off voltage VGH2 higher than the first gate-off voltage VGH1 as the gate-off voltage VGH to the initialization stage group 450 .

[0121] During the low frequency hold period, in order to Figure 7 As illustrated in FIG. 4 , the scan signal SS having a voltage level of a second gate-off voltage VGH2 higher than the first gate-off voltage VGH1 is provided to each pixel PX, and the power management circuit 430 may provide the second gate-off voltage VGH2 higher than the first gate-off voltage VGH1 as the gate-off voltage VGH to the scan stage group 460 .

[0122] During the low frequency hold period, in order to Fig. 9 As shown in the figure, the initialization signal SI having a voltage level of a second gate-off voltage VGH2” lower than the first gate-off voltage VGH1 is provided to each pixel PX, and the power management circuit 430 can provide the second gate-off voltage VGH2” lower than the first gate-off voltage VGH1 as the gate-off voltage VGH to the initialization stage group 450.

[0123] During the low frequency hold period, in order to Fig.12 As illustrated in the figure, the scan signal SS having a voltage level of a second gate-off voltage VGH2” lower than the first gate-off voltage VGH1 is provided to each pixel PX, and the power management circuit 430 can provide the second gate-off voltage VGH2” lower than the first gate-off voltage VGH1 as the gate-off voltage VGH to the scan stage group 460.

[0124] During the low frequency hold period, in order to Fig.14 As illustrated in the figure, an initialization signal SI and a scan signal SS having a voltage level of a second gate-off voltage VGH2 higher than the first gate-off voltage VGH1 are provided to each pixel PX, and the power management circuit 430 can provide the second gate-off voltage VGH2 higher than the first gate-off voltage VGH1 as the gate-off voltage VGH to the initialization level group 450 and the scan level group 460.

[0125] During the low frequency hold period, in order to Fig.16 As shown in the figure, an initialization signal SI and a scan signal SS having a voltage level of a second gate-off voltage VGH2” lower than the first gate-off voltage VGH1 are provided to each pixel PX, and the power management circuit 430 can provide the second gate-off voltage VGH2” lower than the first gate-off voltage VGH1 as the gate-off voltage VGH to the initialization level group 450 and the scan level group 460.

[0126] In order to selectively provide the first gate-off voltage VGH1 or the second gate-off voltage VGH2 or VGH2″ to at least one of the initialization stage group 450 and the scanning stage group 460, the power management circuit 430 may include a switch block 435. The switch block 435 may receive a hold flag signal HFS indicating a low-frequency hold period from the controller 480, and may selectively provide the first gate-off voltage VGH1 or the second gate-off voltage VGH2 or VGH2″ as the gate-off voltage VGH to the at least one stage group in response to the hold flag signal HFS.

[0127] like Fig.19 As shown in FIG. 4 , the switch block 435 may include providing the first gate-off voltage VHG1 as the gate-off voltage VGH to the at least one group of first switches SWS1 in response to the hold flag signal HFS and providing the second gate-off voltage VGH2 or VGH2″ as the gate-off voltage VGH to the at least one group of second switches SWS2 in response to the hold flag signal HFS. For example, Fig.19 As illustrated in FIG. 1 , the first switch SWS1 may be implemented with an NMOS transistor, and the second switch SWS2 may be implemented with a PMOS transistor.

[0128] The scan driver 440 may receive a gate-on voltage VGL and a gate-off voltage VGH from the power management circuit 430, may receive a scan control signal from the controller 480, and may generate a scan signal SS and an initialization signal SI based on the gate-on voltage VGL, the gate-off voltage VGH, and the scan control signal. The scan driver 440 may sequentially provide the initialization signal SI to a plurality of pixels PX row by row through a plurality of initialization signal lines, and may sequentially provide the scan signal SS to a plurality of pixels PX row by row through a plurality of scan signal lines. The scan control signal may include an initialization start signal SI_FLM, an initialization clock signal SI_CLK, a scan start signal SS_FLM, and a scan clock signal SS_CLK. The scan driver 440 may be integrated or formed in a peripheral portion of the display panel 410. The scan driver 440 may be implemented with one or more integrated circuits.

[0129] like Fig.18 and Fig. 20 As shown in FIG. 1 , the scan driver 440 may include an initialization stage group 450 that sequentially provides an initialization signal SI to a plurality of pixels PX based on a gate-on voltage VGL and a gate-off voltage VGH, and a scan stage group 460 that sequentially provides a scan signal SS to a plurality of pixels PX based on a gate-on voltage VGL and a gate-off voltage VGH. For example, Fig. 20 As illustrated in the figure, the initialization level group 450 may include a plurality of serially connected initialization levels SI_STG1, SI_STG2, SI_STG3, ... receiving an initialization start signal SI_FLM, a first initialization clock signal SI_CLK1 and a second initialization clock signal SI_CLK2; the scanning level group 460 may include a plurality of serially connected scanning levels SS_STG1, SS_STG2, SS_STG3, ... receiving a scanning start signal SS_FLM, a first scanning clock signal SS_CLK1 and a second scanning clock signal SS_CLK2.

[0130] like Fig.21As illustrated in the figure, each stage STG of the plurality of initialization stages SI_STG1, SI_STG2, SI_STG3, ... and the plurality of scanning stages SS_STG1, SS_STG2, SS_STG3, ... may include a first transistor M1 to a seventh transistor M7 and a first capacitor C1 and a second capacitor C2. In each stage STG, the first transistor M1 may transmit a start signal FLM (e.g., an initialization start signal SI_FLM or a scanning start signal SS_FLM) or a previous output signal POUT to a first node N1 in response to a first clock signal CLK1 (e.g., a first initialization clock signal SI_CLK1 or a first scanning clock signal SS_CLK1), the second transistor M2 may transmit a gate-off voltage VGH to a third node N3 in response to a voltage of a second node N2, and the third transistor M3 may transmit a gate-off voltage VGH to a third node N3 in response to a second clock signal CLK2 (e.g., a second initialization clock signal SI_CLK2 or a second scanning clock signal SS_CLK1). The first transistor C1 may be coupled between the line of the gate-off voltage VGH and the second node N2, and the second capacitor C2 may be coupled between the first node N1 and the output node NO. Therefore, when the stage STG receives the first gate-off voltage VGH1 as the gate-off voltage VGH in the low-frequency holding period, the stage STG may output the first gate-off voltage VGH1 as the output signal OUT (for example, the initialization signal SI or the scan signal SS) in the low-frequency holding period. When stage STG receives the second gate-off voltage VGH2 or VGH2″ as the gate-off voltage VGH in the low-frequency holding period, stage STG can output the second gate-off voltage VGH2 or VGH2″ as the output signal OUT (e.g., initialization signal SI or scan signal SS) in the low-frequency holding period.

[0131] The organic light emitting diode display device 400 may include an initialization stage group 450 generating an initialization signal SI, and may include a scan stage group 460 generating a scan signal SS. Therefore, since the scan signal SS and the initialization signal SI are generated by different stage groups 450 and 460, the scan signal SS and the initialization signal SI may be adjusted to have different cutoff voltage levels in the low frequency holding period.

[0132] The emission driver 470 may generate an emission signal SEM based on an emission control signal EMCTRL received from the controller 480, and may provide the emission signal SEM to a plurality of pixels PX through a plurality of emission signal lines. The emission signal SEM may be sequentially provided to a plurality of pixels PX row by row. The emission signal SEM may be a global signal provided to a plurality of pixels PX substantially simultaneously. The emission driver 470 may be integrated or formed in a peripheral portion of the display panel 410. The emission driver 470 may be implemented with one or more integrated circuits.

[0133] The controller (e.g., timing controller (TCON)) 480 may receive input image data IDAT and a control signal CTRL from an external host such as an application processor (AP), a graphics processing unit (GPU), or a graphics card. The control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal IDE, a main clock signal, etc. The controller 480 may generate output image data ODAT, a data control signal DCTRL, a scan control signal, an emission control signal EMCTRL, and a hold flag signal HFS based on the input image data IDAT and the control signal CTRL. The controller 480 may control the operation of the data driver 420 by providing the output image data ODAT and the data control signal DCTRL to the data driver 420, may control the operation of the scan driver 440 by providing the scan control signal to the scan driver 440, may control the operation of the emission driver 470 by providing the emission control signal EMCTRL to the emission driver 470, and may control the operation of the power management circuit 430 by providing the hold flag signal HFS to the power management circuit 430.

[0134] The organic light emitting diode display device 400 may detect whether the input image data IDAT represents a static image, may set at least one frame period in the continuous frame periods as a low-frequency holding period when the input image data IDAT represents a static image, and may perform low-frequency driving of driving the display panel 410 at a low frequency lower than the input frame frequency IFF in the low-frequency holding period. In order to perform the low-frequency driving, the controller 480 of the organic light emitting diode display device 400 may include a static image detector 490.

[0135] The static image detector 490 may receive input image data IDAT at an input frame frequency IFF, and may determine whether the input image data IDAT represents a static image. The static image detector 490 may determine whether the input image data IDAT represents a static image by comparing the input image data IDAT in a previous frame period with the input image data IDAT in a current frame period. For example, the static image detector 490 may store a representative value (e.g., an average value, a checksum, etc.) of the input image data IDAT in a previous frame period, may calculate a representative value of the input image data IDAT in a current frame period, and may determine whether the input image data IDAT represents a static image by comparing the stored representative value with the calculated representative value.

[0136] When the input image data IDAT represents a static image, in order to drive the display panel 410 at a low frequency or an output frame frequency OFF lower than the input frame frequency IFF, the controller 480 may set at least one frame period in the continuous frame periods as a low frequency holding period, and the data voltage VD may not be provided to the display panel 410 during the low frequency holding period. The controller 480 may control the data driver 420 not to provide the data signal DS (or the data voltage VD) to the plurality of pixels PX during the low frequency holding period. The controller 480 may control the scan driver 440 to provide the adjusted scan signal SS or not to provide the scan signal SS to the plurality of pixels PX during the low frequency holding period, and to provide the adjusted initialization signal SI or not to provide the initialization signal SI to the plurality of pixels PX. During the low frequency holding period, the emission driver 470 may provide the emission signal SEM to the plurality of pixels PX at the input frame frequency IFF, so that the display panel 410 may periodically emit light. In the low-frequency holding period, the power management circuit 430 may provide a second gate-off voltage VGH2 or VGH2″ different from the first gate-off voltage VGH1 as the gate-off voltage VGH to at least one of the initialization stage group 450 and the scanning stage group 460. The initialization stage group 450 and / or the scanning stage group 460 receiving the second gate-off voltage VGH2 or VGH2″ may apply the second gate-off voltage VGH2 or VGH2″ as the initialization signal SI and / or the scanning signal SS to the corresponding pixel PX in the low-frequency holding period. Therefore, the distortion of the gate node voltage in the corresponding pixel PX may be compensated, and satisfactory image quality of the organic light emitting diode display device 400 may be obtained.

[0137] refer to Fig. 22, the controller 480 may receive the input image data IDAT at a normal driving frequency or an input frame frequency IFF of about 60 Hz, and may receive the input data enable signal IDE in synchronization with the input image data IDAT. For example, the controller 480 may receive sixty frame data FDAT as the input image data IDAT in about one second. In the first frame period FP1 and the second frame period FP2, when the input image data IDAT does not represent a static image or the input image data IDAT represents a moving image, the controller 480 may provide the output image data ODAT to the data driver 420 at an output frame frequency OFF of about 60 Hz substantially the same as the input frame frequency IFF, and may further provide the data driver 420 with an output data enable signal ODE synchronized with the output image data ODAT. Therefore, the display panel 110 may be driven at a normal driving frequency or an output frame frequency OFF of about 60 Hz.

[0138] When the static image detector 490 determines that the input image data IDAT represents a static image, the controller 480 may determine the driving frequency or output frame frequency OFF of the display panel 410 to be a low frequency lower than the normal driving frequency or input frame frequency IFF. The controller 480 may determine a flicker value (indicating a level of flicker perceived by a user) corresponding to the grayscale level or brightness of the input image data IDAT, and may determine the driving frequency of the display panel 410 based on the flicker value. Fig. 22 , the input frame frequency IFF is about 60 Hz, the low frequency or output frame frequency OFF is determined to be about 20 Hz, and the controller 480 can set two frame periods (e.g., FP4 and FP5) of three consecutive frame periods (e.g., FP3, FP4, and FP5) as the low frequency holding period LHP. The controller 480 can set the fourth frame period FP4 and the fifth frame period FP5 of the third to fifth frame periods FP3, FP4, and FP5 as the low frequency holding period LHP, and can set the seventh frame period FP7 and the eighth frame period FP8 of the sixth to eighth frame periods FP6, FP7, and FP8 as the low frequency holding period LHP.

[0139] In the low frequency holding period LHP, the controller 480 may control the data driver 420 not to provide the data signal DS (or the data voltage VD) to the plurality of pixels PX. For example, in the third frame period FP3, the controller 480 may provide the frame data FDAT as the output image data ODAT and the output data enable signal ODE synchronized with the output image data ODAT to the data driver 420. In the low frequency holding period LHP, for example, in the fourth frame period FP4 and the fifth frame period FP5, the controller 480 may not provide the output image data ODAT and the output data enable signal ODE to the data driver 420. That is, the controller 480 may provide only one frame data FDAT to the data driver 420 in the three frame periods FP3, FP4, and FP5, and thus the data driver 420 may drive the display panel 410 at a low frequency or output frame frequency OFF of about 20 Hz, which is one-third of the input frame frequency IFF of about 60 Hz.

[0140] In the low frequency holding period LHP, the controller 480 may provide a holding flag signal HFS indicating the low frequency holding period LHP, and the switch block 435 of the power management circuit 430 may provide a second gate-off voltage VGH2 or VGH2″ different from the first gate-off voltage VGH1 in the normal driving period NDP as the gate-off voltage VGH to at least one of the initialization stage group 450 and the scanning stage group 460. Therefore, the at least one stage group may apply the second gate-off voltage VGH2 or VGH2″ as the initialization signal SI and / or the scanning signal SS to the corresponding pixel PX in the low frequency holding period LHP. Therefore, the distortion of the gate node voltage in the corresponding pixel PX may be compensated, and satisfactory image quality of the organic light emitting diode display device 400 may be obtained.

[0141] The organic light emitting diode display device 400 may perform low-frequency driving by detecting a static image, and may set at least one frame period as a low-frequency holding period LHP when performing the low-frequency driving. In the low-frequency holding period LHP, the organic light emitting diode display device 400 may provide a second gate-off voltage VGH2 or VGH2″ different from the first gate-off voltage VGH1 in the normal driving period NDP as an initialization signal SI and / or a scan signal SS to the pixel PX. Therefore, the distortion of the gate node voltage in the corresponding pixel PX may be compensated, and satisfactory image quality of the organic light emitting diode display device 400 may be obtained.

[0142] Fig.23 is a block diagram illustrating an organic light emitting diode display device according to an embodiment, Fig.24 It is used to describe the drive at different drive frequencies. Fig.23A diagram of a panel area of ​​a display panel of an organic light emitting diode display device, and Fig.25 is a timing diagram for describing the operation of the organic light emitting diode display device according to the embodiment.

[0143] refer to Fig.23 , the organic light emitting diode display device 500 may include a display panel 510 , a data driver 520 , a power management circuit 530 , a scan driver 540 , an emission driver 570 , and a controller 580 . Fig.23 The organic light emitting diode display device 500 may have Fig.18 The organic light emitting diode display device 400 has similar features to those of the display panel 510, except that the display panel 510 may be divided into a plurality of panel regions PR1, PR2, and PR3, and the power management circuit 530 may include a plurality of switching blocks SB1, SB2, and SB3 that selectively provide a first gate-off voltage VGH1 or a second gate-off voltage VGH2 or VGH2" to the stage sub-groups SG1, SG2, and SG3 respectively coupled to the panel regions PR1, PR2, and PR3.

[0144] The organic light emitting diode display device 500 may perform multi-frequency driving (MFD) for driving the panel regions PR1, PR2, and PR3 at different driving frequencies. Therefore, different low-frequency holding periods may be set with respect to the panel regions PR1, PR2, and PR3, and the cut-off voltage levels of the initialization signal SI and / or the scan signal SS of the panel regions PR1, PR2, and PR3 may be independently controlled.

[0145] To perform these operations, the static image detector 590 of the controller 580 may receive the input image data IDAT at the input frame frequency IFF, and may divide the input image data IDAT for the display panel 510 into partial image data for the panel regions PR1, PR2, and PR3. The static image detector 590 may determine whether each partial image data represents a static image. When at least one partial image data among the plurality of partial image data represents a static image, in order to drive at least one of the panel regions PR1, PR2, and PR3 corresponding to the at least one partial image data at a low frequency lower than the input frame frequency IFF, the controller 580 may set at least one frame period among the continuous frame periods as a low frequency holding period with respect to the at least one of the panel regions PR1, PR2, and PR3.

[0146] refer to Figure 23 to Figure 25, the static image detector 590 may divide the input image data IDAT or the frame data FDAT for the display panel 510 into the first to third partial image data PD1, PD2, and PD3 for the first to third panel regions PR1, PR2, and PR3, respectively. When the first partial image data PD1 for the first panel region PR1 represents a motion image, and when the third partial image data PD3 for the third panel region PR3 represents a motion image, the driving frequency of the first panel region PR1 and the third panel region PR3 may be determined as a normal driving frequency, for example, about 60 Hz. Therefore, the first partial image data PD1 and the third partial image data PD3 for the first panel region PR1 and the third panel region PR3, respectively, may be provided to the data driver 520 at an output frame frequency OFF of about 60 Hz, and the first panel region PR1 and the third panel region PR3 may be driven at a normal driving frequency of about 60 Hz. The controller 580 may provide the first hold flag signal HFS1 and the third hold flag signal HFS3 having a high level to the first switch block SB1 and the third switch block SB3 of the power management circuit 530, respectively, and the first switch block SB1 and the third switch block SB3 may provide the first gate-off voltage VGH1 as the gate-off voltage VGH_SG1 of the first stage subgroup SG1 and the gate-off voltage VGH_SG3 of the third stage subgroup SG3 of the initialization stage group 550, respectively, in response to the first hold flag signal HFS1 and the third hold flag signal HFS3 having a high level, respectively, and the first stage subgroup SG1 and the third stage subgroup SG3 may apply the first gate-off voltage VGH1 as the initialization signal SI having a cutoff voltage level to the first panel region PR1 and the third panel region PR3, respectively. Although Fig.23 The diagram shows that the initialization level group 550 includes level sub-groups SG1, SG2 and SG3 that receive different gate cut-off voltages VGH_SG1, VGH_SG2 and VGH_SG3, respectively, but the scanning level group 560 instead of the initialization level group 550 or the scanning level group 560 together with the initialization level group 550 may include level sub-groups SG1, SG2 and SG3 that receive different gate cut-off voltages VGH_SG1, VGH_SG2 and VGH_SG3, respectively.

[0147] When the second partial image data PD2 for the second panel area PR2 represents a static image, the driving frequency for the second panel area PR2 may be determined as a low frequency lower than the normal driving frequency, for example, determined to be about 20 Hz. In order to drive the second panel area PR2 at a low frequency of about 20 Hz, two frame periods FP2 and FP3 of three consecutive frame periods FP1, FP2, and FP3 may be set as a low frequency holding period LHP with respect to the second panel area PR2. In the low frequency holding period LHP for the second panel area PR2, the controller 580 may not provide the second partial image data PD2 to the data driver 520, so that no data signal DS may be provided to the second panel area PR2.

[0148] In the low frequency holding period LHP, the controller 580 may provide a second holding flag signal HFS2 having a low level to the second switching block SB2 of the power management circuit 530, and the second switching block SB2 may provide a second gate-off voltage VGH2 or VGH2″ different from the first gate-off voltage VGH1 as a gate-off voltage VGH_SG2 for the second level sub-group SG2 of the initialization level group 550 in response to the second holding flag signal HFS2 having a low level, and the second level sub-group SG2 may apply the second gate-off voltage VGH2 or VGH2″ as an initialization signal SI having a cut-off voltage level to the second panel region PR2. Therefore, the distortion of the gate node voltage at the second panel region PR2 may be compensated, and satisfactory image quality of the organic light emitting diode display device 500 may be obtained.

[0149] The organic light emitting diode display device 500 may perform MFD to drive the panel areas PR1, PR2, and PR3 at different driving frequencies. When the panel area is driven at a low frequency, at least one frame period for the panel area may be set as a low frequency holding period LHP. In the low frequency holding period LHP for the panel area, the organic light emitting diode display device 500 may provide a second gate cut-off voltage VGH2 or VGH2″ different from the first gate cut-off voltage VGH1 in the normal driving period NDP as an initialization signal SI and / or a scan signal SS to each pixel PX in the panel area. Therefore, the distortion of the gate node voltage in the corresponding pixel PX in the panel area may be compensated, and satisfactory image quality of the organic light emitting diode display device 500 may be obtained.

[0150] Fig.26 An electronic device including an organic light emitting diode display device according to an embodiment.

[0151] refer to Fig.26, the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and an organic light emitting diode (OLED) display device 1160. The electronic device 1100 may further include a port for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0152] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, etc. The processor 1110 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0153] The memory device 1120 may store data used for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc. and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

[0154] The storage device 1130 may be or include at least one of a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1140 may include at least one input device (such as one of a keyboard, a keypad, a mouse, and a touch screen) and an output device (such as one of a printer and a speaker). The power supply 1150 may supply power for the operation of the electronic device 1100. The organic light emitting diode display device 1160 may be coupled to other components via a bus or other communication link.

[0155] In each pixel of the organic light emitting diode display device 1160, the cut-off voltage level of at least one of the scanning signal applied to the third transistor (e.g., the threshold voltage compensation transistor) and the initialization signal applied to the fourth transistor (e.g., the gate initialization transistor) can be changed in the low-frequency holding period. Therefore, the voltage distortion of the gate node of the first transistor (e.g., the driving transistor) under low-frequency driving can be compensated, and satisfactory image quality of the organic light emitting diode display device 1160 can be obtained.

[0156] The embodiments may be applied to an organic light emitting diode display device 1160 and / or an electronic device 1100 including the organic light emitting diode display device 1160. For example, the embodiments may be applied to mobile phones, smart phones, wearable electronic devices, tablet computers, televisions (TVs), digital TVs, 3D TVs, personal computers (PCs), home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, and the like.

[0157] The foregoing is illustrative and not restrictive. Although embodiments have been described, many modifications are possible in the embodiments. All modifications are intended to be included within the scope defined in the claims.

Claims

1. A pixel of a display device, the display device having a first mode and a second mode, the driving frequency of the second mode being lower than the driving frequency of the first mode, the pixel comprising: a capacitor, wherein a first electrode of the capacitor receives a first supply voltage, and wherein a second electrode of the capacitor is electrically connected to a gate node; a first transistor, wherein a gate electrode of the first transistor is electrically connected to the gate node; a second transistor, wherein a drain electrode of the second transistor is electrically connected to a source electrode of the first transistor, and wherein a gate electrode of the second transistor receives a first instance of a scan signal in a holding period in the second mode; a third transistor diode-connecting the first transistor in response to a second instance of the scan signal during the hold period in the second mode; a fourth transistor that transmits an initialization voltage to the gate node in response to a first instance of an initialization signal during the retention period in the second mode; as well as An organic light emitting diode includes an anode and a cathode, wherein the cathode receives a second power supply voltage different from the first power supply voltage, wherein in the holding period in the second mode, the scan signal and the initialization signal have different cut-off voltage levels.

2. The pixel according to claim 1, wherein: In the second mode, the holding period includes one frame period among consecutive frame periods.

3. The pixel according to claim 1, wherein: In a frame period in the first mode, the scan signal changes from an on voltage level to a first off voltage level at a first time, and the initialization signal changes from the on voltage level to the first off voltage level at a second time different from the first time, and In the holding period in the second mode, the initialization signal increases from the first cut-off voltage level to a second cut-off voltage level higher than the first cut-off voltage level.

4. The pixel according to claim 3, wherein: In the holding period in the second mode, a drain current of the fourth transistor increases based on a difference between the second cut-off voltage level and the first cut-off voltage level.

5. The pixel according to claim 3, wherein: A difference between the second cut-off voltage level and the first cut-off voltage level depends on the driving frequency of the second mode.

6. The pixel according to claim 1, wherein: In a frame period in the first mode, the scan signal changes from an on voltage level to a first off voltage level at a first time, and the initialization signal changes from the on voltage level to the first off voltage level at a second time different from the first time, and In the holding period in the second mode, the scan signal increases from the first cut-off voltage level to a second cut-off voltage level higher than the first cut-off voltage level.

7. The pixel according to claim 6, wherein: In the holding period in the second mode, a drain current of the third transistor increases based on a difference between the first cut-off voltage level and the second cut-off voltage level.

8. The pixel according to claim 1, wherein: In a frame period in the first mode, the scan signal changes from an on voltage level to a first off voltage level at a first time, and the initialization signal changes from the on voltage level to the first off voltage level at a second time different from the first time, and In the holding period in the second mode, the initialization signal decreases from the first cut-off voltage level to a second cut-off voltage level lower than the first cut-off voltage level.

9. The pixel according to claim 8, wherein: In the holding period in the second mode, a drain current of the fourth transistor decreases based on a difference between the second cut-off voltage level and the first cut-off voltage level.

10. The pixel according to claim 1, wherein: In a frame period in the first mode, the scan signal changes from an on voltage level to a first off voltage level at a first time, and the initialization signal changes from the on voltage level to the first off voltage level at a second time different from the first time, and In the holding period in the second mode, the scan signal decreases from the first cut-off voltage level to a second cut-off voltage level lower than the first cut-off voltage level.

11. The pixel according to claim 10, wherein: In the holding period in the second mode, a drain current of the third transistor decreases based on a difference between the first cut-off voltage level and the second cut-off voltage level.

12. The pixel according to claim 1, wherein: The third transistor includes a first sub-transistor and a second sub-transistor electrically connected in series between the gate node and a drain electrode of the first transistor, and The fourth transistor includes a third sub-transistor and a fourth sub-transistor electrically connected in series between the gate node and the line of the initialization voltage.

13. The pixel of claim 1, further comprising: a fifth transistor, wherein a gate electrode of the fifth transistor is electrically connected to an emission signal source, wherein a source electrode of the fifth transistor receives the first power supply voltage, and wherein a drain electrode of the fifth transistor is electrically connected to the source electrode of the first transistor; a sixth transistor, wherein a gate electrode of the sixth transistor is electrically connected to the emission signal source, wherein a source electrode of the sixth transistor is electrically connected to a drain electrode of the first transistor, and wherein a drain electrode of the sixth transistor is electrically connected to the anode of the organic light emitting diode; as well as a seventh transistor, wherein a gate electrode of the seventh transistor receives a second instance of the initialization signal, wherein a source electrode of the seventh transistor is electrically connected to the anode of the organic light emitting diode, and wherein a drain electrode of the seventh transistor is electrically connected to a line of the initialization voltage.

14. A pixel of a display device, the display device having a first mode and a second mode, the driving frequency of the second mode being lower than the driving frequency of the first mode, the pixel comprising: a capacitor, wherein a first electrode of the capacitor receives a first supply voltage, and wherein a second electrode of the capacitor is electrically connected to a gate node; a first transistor, wherein a gate electrode of the first transistor is electrically connected to the gate node; a second transistor, wherein a drain electrode of the second transistor is electrically connected to a source electrode of the first transistor, and wherein a gate electrode of the second transistor receives a first instance of a scan signal in a holding period in the second mode; a third transistor diode-connecting the first transistor in response to a second instance of the scan signal during the hold period in the second mode; a fourth transistor that transmits an initialization voltage to the gate node in response to a first instance of an initialization signal during the retention period in the second mode; as well as an organic light emitting diode comprising an anode and a cathode, wherein the cathode receives a second power supply voltage different from the first power supply voltage, wherein at the end of a frame period in the first mode, each of the scan signal and the initialization signal is at a first cut-off voltage level, and In the holding period in the second mode, at least one of the scan signal and the initialization signal is at a second cut-off voltage level that is not equal to the first cut-off voltage level.

15. An organic light emitting diode display device, comprising: Display panel, including pixels; a data driver electrically connected to the display panel and configured to provide data signals to the pixels; Power management circuits; a scan driver electrically connected to the power management circuit, electrically connected to the display panel, and comprising an initialization stage group configured to sequentially provide initialization signals to the pixels and a scan stage group configured to sequentially provide scan signals to the pixels; as well as a controller configured to control the data driver, the power management circuit and the scan driver, wherein in a frame period in the first mode of the organic light emitting diode display device, the power management circuit provides a first gate-off voltage to each of the initialization stage group and the scanning stage group, and Wherein, during the holding period in the second mode of the organic light emitting diode display device, the power management circuit provides the first gate cut-off voltage to the first level group among the initialization level group and the scanning level group, and provides a second gate cut-off voltage that is not equal to the first gate cut-off voltage to the second level group among the initialization level group and the scanning level group.

16. The organic light emitting diode display device according to claim 15, wherein: The power management circuit comprises: A switch block is configured to receive a hold flag signal from the controller and to selectively provide the first gate-off voltage or the second gate-off voltage to the second stage group of the initialization stage group and the scan stage group in response to the hold flag signal.

17. The organic light emitting diode display device according to claim 16, wherein: The switch block comprises: a first switch configured to provide the first gate-off voltage to the second stage group of the initialization stage group and the scan stage group in response to the hold flag signal; and A second switch is configured to provide the second gate-off voltage to the second stage group of the initialization stage group and the scan stage group in response to the hold flag signal.

18. The organic light emitting diode display device according to claim 15, wherein: The controller comprises: a still image detector configured to receive input image data at an input frame frequency, and Wherein, when the static image detector determines that the input image data represents a static image, the controller sets at least one frame period in continuous frame periods as the holding period in the second mode, so that the display panel operates at a frequency lower than the input frame frequency in the second mode.

19. The organic light emitting diode display device according to claim 15, wherein: The display panel is divided into panel areas, The controller comprises: a static image detector configured to receive input image data for the display panel at an input frame frequency and to divide the input image data into local image data sets respectively for the panel regions, and Wherein, when the static image detector determines that the identified local image data set in the local image data set represents a static image, the controller, in the second mode, sets at least one frame period in the continuous frame periods as the holding period for a corresponding panel area in the panel area corresponding to the identified local image data set, so that the corresponding panel area operates at a frequency lower than the input frame frequency in the second mode.

20. The organic light emitting diode display device according to claim 19, wherein: The second stage group of the initialization stage group and the scanning stage group includes stage sub-groups electrically connected to the panel regions, respectively, and The power management circuit comprises: The switch blocks are electrically connected to the stage sub-groups, respectively, and are configured to selectively provide the first gate-off voltage or the second gate-off voltage to each of the stage sub-groups.

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