Display device

Abstract

A display device is disclosed. The display device includes a first power supply voltage line, a second power supply voltage line, a first dam portion, a second dam portion, and a third dam portion. The first power supply voltage line is in a non-display area and includes a first conductive layer, a first organic layer on the first conductive layer, and a second conductive layer on the first organic layer. The second power supply voltage line is in the non-display area and includes a third conductive layer spaced apart from the first conductive layer and a fourth conductive layer located on the first organic layer. The first organic layer is located on the third conductive layer. The first dam portion is adjacent to the first power supply voltage line. The second dam portion is adjacent to the first dam portion. The third dam portion is between the first power supply voltage line and the first dam portion. The fourth conductive layer includes an opening exposing the upper surface of the first organic layer between the first power supply voltage line and the second dam portion.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2019 - 0136897, filed with the Korean Intellectual Property Office on October 30, 2019, the entire content of which is incorporated herein by reference. Technical field

[0003] One or more embodiments relate to a display device. Background art

[0004] A display device is a device for visually displaying data. Recently, display devices have become diversified in terms of their applicability to various uses. As display devices become thinner and lighter in weight, they are used more widely.

[0005] Such a display device may include a substrate, which is divided into a display area and a non - display area outside the display area. The non - display area is a dead zone where an image cannot be realized, and non - display elements such as pad portions, wirings, and driving circuits may be arranged in the non - display area. Therefore, there is an increasing need to further reduce the dead zone of the display device.

[0006] It will be understood that this background of the technical part is intended in part to provide a useful background for understanding the technology. However, this background of the technical part may also include ideas, concepts, or understandings that are not part of what was known or appreciated by those skilled in the relevant art before the effective filing date of the corresponding application of the subject matter disclosed herein. Summary of the invention

[0007] One or more embodiments are provided to prevent the occurrence of pixel defects caused by outgassing emitted from an organic layer disposed or provided between two layers when a power line is applied in a two - layer structure to reduce the dead zone. However, this is only an example, and the scope of the present disclosure is not limited thereby.

[0008] Additional aspects will be partially set forth in the description below, and will be partially apparent from the description, or may be learned by practicing the embodiments of the present disclosure set forth herein.

[0009] According to one or more embodiments, a display device may include a substrate, a display area, a non-display area, a first power supply voltage line, a second power supply voltage line, a first dam, a second dam, and a third dam. The display area is disposed on the substrate and includes a plurality of pixels. The non-display area is adjacent to the display area. The first power supply voltage line is disposed in the non-display area and includes a first conductive layer, a first organic layer disposed on the first conductive layer, and a second conductive layer disposed on the first organic layer. The second power supply voltage line is disposed in the non-display area and includes a third conductive layer spaced apart from the first conductive layer and a fourth conductive layer disposed on the first organic layer, wherein the first organic layer may be disposed on the third conductive layer. The first dam surrounds the display area and is disposed adjacent to the first power supply voltage line. The second dam is disposed adjacent to the first dam. The third dam is disposed between the first power supply voltage line and the first dam. Wherein, the fourth conductive layer includes an opening exposing the upper surface of the first organic layer between the first power supply voltage line and the second dam.

[0010] The display device may further include a second organic layer and a pixel defining layer. The second organic layer is disposed on the first organic layer. The pixel defining layer is disposed on the second organic layer. Wherein, the first dam may include: a first layer including a part of the second organic layer and a second layer including a part of the pixel defining layer. The second dam may include: a first layer including a part of the second organic layer and a second layer including a part of the pixel defining layer. And the third dam may include: a first layer including a part of the second organic layer and a second layer including a part of the pixel defining layer.

[0011] The fourth conductive layer may include an opening disposed between the third dam and the second dam along the extending direction of the third dam and the second dam.

[0012] The opening may be disposed to overlap with the first dam.

[0013] The fourth conductive layer may include a first part and a second part spaced apart from each other through the opening. The third dam may overlap with an end of the first part adjacent to the opening, and the second dam may overlap with an end of the second part adjacent to the opening.

[0014] The second dam may overlap with an end of the second part at a predetermined distance from the opening.

[0015] The fourth conductive layer may include a plurality of openings disposed between the third dam and the second dam.

[0016] The fourth conductive layer may include an opening disposed between the first power supply voltage line and the third dam along the extending direction of the third dam.

[0017] The fourth conductive layer may include a plurality of openings disposed between the first power supply voltage line and the third dam.

[0018] A pixel may include a first electrode, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer. The second electrode may be commonly disposed in a plurality of pixels, and the second electrode may extend toward a non-display area to overlap with a part of a third dam part.

[0019] The display device may further include a spacer disposed on a pixel defining layer. Wherein, the second dam part may include a third layer located on a second layer of the second dam part including a part of the pixel defining layer, and the third layer and the spacer may include the same material.

[0020] The height of the second dam part may be greater than the height of the first dam part and the height of the third dam part.

[0021] The third dam part, the first dam part, and the second dam part may be disposed to overlap with a second power supply voltage line.

[0022] The first conductive layer and the third conductive layer may include the same material, and the second conductive layer and the fourth conductive layer may include the same material.

[0023] The display device may further include a thin film encapsulation layer including a first inorganic encapsulation layer overlapping with a display area, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer. Wherein, the thin film encapsulation layer may overlap with the third dam part and the first dam part.

[0024] The first inorganic encapsulation layer and the second inorganic encapsulation layer may be in direct contact with an edge of the second dam part.

[0025] The first conductive layer may be electrically connected to the second conductive layer through a first contact hole disposed in a first organic layer.

[0026] The third conductive layer may be electrically connected to the fourth conductive layer through a second contact hole disposed in the first organic layer.

[0027] According to one or more embodiments, a display device may include a substrate, a display area, a non-display area, a first power supply voltage line, a second power supply voltage line, a first dam part, a second dam part, and a third dam part. The display area is disposed on the substrate and includes a plurality of pixels. The non-display area is adjacent to the display area. The first power supply voltage line is disposed in the non-display area and includes a first conductive layer, a first organic layer disposed on the first conductive layer, and a second conductive layer disposed on the first organic layer. The second power supply voltage line is disposed in the non-display area, and the second power supply voltage line and the second conductive layer include the same material. The first dam part surrounds the display area and is disposed adjacent to the first power supply voltage line. The second dam part is disposed adjacent to the first dam part. The third dam part is disposed between the first power supply voltage line and the first dam part. Wherein, the first organic layer may have a substantially concave-convex pattern including at least one opening between the first power supply voltage line and the second dam part.

[0028] The second power supply voltage line may be disposed on the first organic layer along a substantially uneven pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects, features, and advantages of the embodiments will become more apparent from the following description taken in conjunction with the drawings, in which:

[0030] Figure 1 is a schematic plan view of a display device according to an embodiment;

[0031] Figure 2A and Figure 2B is an equivalent circuit diagram of a pixel included in the display device according to an embodiment;

[0032] Figure 3 is Figure 1 a schematic plan view of Region III of

[0033] Figure 4 is Figure 3 a schematic cross-sectional view of a pixel included in the display device taken along line IVA-IVB of Figure 1 ;

[0034] Figure 5 is Figure 1 a schematic cross-sectional view of the display device taken along line VA-VB of

[0035] Figure 6 is Figure 5 a schematic cross-sectional view of Region VI of

[0036] Figure 7 showing Figure 6 a plan view of the fourth conductive layer and the first to third dam parts of

[0037] Figure 8 is a schematic cross-sectional view of a display device according to a comparative example;

[0038] Figure 9 is a schematic plan view of a display device according to an embodiment;

[0039] Figure 10 is a schematic plan view of a display device according to an embodiment;

[0040] Figure 11 is a schematic plan view of a display device according to an embodiment; and

[0041] Figure 12 is a schematic cross-sectional view of a display device according to an embodiment. DETAILED DESCRIPTION

[0042] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the embodiments are described only by way of example with reference to the accompanying drawings to explain aspects of the description.

[0043] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. When describing the embodiments with reference to the accompanying drawings, the same or corresponding elements may be denoted by the same reference numerals, and redundant descriptions thereof will be omitted.

[0044] To describe the embodiments of the present disclosure, some parts not relevant to the description may not be provided, and throughout the specification, like reference numerals refer to like elements.

[0045] It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first element discussed below could be termed the second element without departing from the teachings of the present disclosure. Similarly, the second element could also be termed the first element.

[0046] Unless the context clearly indicates otherwise, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well.

[0047] It will be understood that the terms such as “comprise,” “comprises,” “comprising,” “include,” “includes,” and “including” and “have” and “having” used herein specifically specify the presence of the recited features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0048] When a layer, film, region, substrate, or area is referred to as being "on" another layer, film, region, substrate, or area, it can be directly on the other layer, film, region, substrate, or area, or there can be intervening layers, films, regions, substrates, or areas therebetween. In contrast, when a layer, film, region, substrate, or area is referred to as being "directly" "on" another layer, film, region, substrate, or area, there can be no intervening layers, films, regions, substrates, or areas therebetween. Additionally, when a layer, film, region, substrate, or area is referred to as being "under" another layer, film, region, substrate, or area, it can be directly under the other layer, film, region, substrate, or area, or there can be intervening layers, films, regions, substrates, or areas therebetween. In contrast, when a layer, film, region, substrate, or area is referred to as being "directly" "under" another layer, film, region, substrate, or area, there can be no intervening layers, films, regions, substrates, or areas therebetween. Further, "above" or "on" can include being positioned above or below an object and does not necessarily imply a gravity-based direction.

[0049] For convenience of description, the spatial relative terms "under", "beneath", "lower", "above", "upper", or similar words may be used herein to describe the relationship between one element or component and another element or component as shown in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, in the case where the device shown in the figures is flipped, a device positioned "under" or "beneath" another device can be placed "above" the other device. Thus, the illustrative term "under" can include both the lower and upper positions. The device can also be oriented in other directions and, accordingly, the spatial relative terms can be interpreted differently depending on the orientation.

[0050] For clarity and convenience of description, the dimensions of the components in the figures may be exaggerated. In other words, since the dimensions and thicknesses of the elements in the figures may be arbitrarily shown for convenience of description, the following embodiments are not limited thereto.

[0051] In addition, in the specification, the phrase "in a plan view" means when observing the object portion from above, while the phrase "in a schematic cross-sectional view" means when observing a schematic cross-section taken by vertically cutting the object portion from the side.

[0052] Additionally, the terms "overlap" or "overlapping" mean that the first object can be above or below the second object or on the side of the second object, and vice versa. Additionally, the term "overlap" can include layering, stacking, facing or being oriented, extending over, covering or partially covering, or any other suitable terms that one of ordinary skill in the art would appreciate and understand. The terms "face" and "be oriented" mean that the first element can be directly or indirectly opposite the second element. In the case where a third element is between the first element and the second element, the first element and the second element can be understood as being indirectly opposite each other even though they still face each other. When an element is described as "not overlapping" or "will not overlap" with another element, this can include these elements being spaced apart from each other, offset from each other or separated from each other or any other suitable terms that one of ordinary skill in the art would appreciate and understand.

[0053] Taking into account the measurements being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0054] For purposes of its meaning and interpretation, in the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a conjunctive or disjunctive sense and can be understood to be equivalent to "and / or". For purposes of its meaning and interpretation, in the specification and claims, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0055] When embodiments can be implemented differently, a particular processing order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0056] In the following embodiments, it will be understood that when a film, layer, region, element, or component is referred to as being "connected to" or "coupled to" another film, layer, region, element, or component, it can be directly or indirectly connected or coupled to the other film, layer, region, element, or component. That is, for example, there can be intermediate films, regions, or components. In the following embodiments, it will be understood that when a film, layer, region, element, or component is referred to as being "electrically connected to" or "electrically coupled to" another film, layer, region, element, or component, it can be directly or indirectly electrically connected or coupled to the other film, layer, region, element, or component. That is, for example, there can be intermediate films, layers, regions, elements, or components.

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong. Additionally, it will be further understood that unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly rigid sense.

[0058] The display device can be a device for displaying one or more images and can be a liquid crystal display, an electrophoretic display, an organic light-emitting display, an inorganic light-emitting display, a field emission display, a surface-conduction electron-emission display, a plasma display, a cathode-ray display, or other displays within the spirit and scope of the present disclosure.

[0059] Although the organic light-emitting display device will be described below as an example of the display device according to the embodiments, the display device according to the embodiments is not limited thereto. Within the spirit and scope of the present disclosure, various types of display devices can be used.

[0060] Figure 1 is a schematic plan view of a display device 1 according to an embodiment. Figure 2A and Figure 2B is an equivalent circuit diagram showing an example of a pixel included in the display device 1 according to an embodiment. Figure 3 is Figure 1 a schematic plan view of region III of Figure 4 is along Figure 3 a schematic cross-sectional view taken along line IVA-IVB of Figure 5 is along Figure 1 a schematic cross-sectional view taken along line VA-VB of

[0061] Refer to Figure 1, the display device 1 may include a display area DA disposed or provided on a substrate 100. The display area DA may include pixels P electrically connected to data lines DL extending in a first direction and scan lines SL extending in a second direction. The second direction may intersect the first direction. Each pixel P may be electrically connected to a driving voltage line PL extending in the first direction.

[0062] One pixel P may emit, for example, red light, green light, blue light, or white light, and may include, for example, an organic light-emitting diode OLED. Each pixel P may include devices such as a thin-film transistor (TFT) and a capacitor.

[0063] The display area DA may provide a certain image (or images) through light emitted from the pixels P, and a non-display area NDA may be disposed or provided outside the display area DA. For example, the non-display area NDA may surround the display area DA.

[0064] The non-display area NDA may be an area where no pixel P is disposed or provided, and the non-display area NDA may not provide an image (or images). A first power supply voltage line 10 may be disposed or provided in the non-display area NDA. A second power supply voltage line 20 may provide a voltage different from the voltage of the first power supply voltage line 10, and the second power supply voltage line 20 may be disposed or provided in the non-display area NDA.

[0065] The first power supply voltage line 10 may include a first main voltage line 11 and a first connection line 12, and the first main voltage line 11 and the first connection line 12 may be disposed or provided on the sides of the display area DA. For example, when the display area DA is rectangular, the first main voltage line 11 may be disposed or provided corresponding to the sides of the display area DA. The first connection line 12 may extend in the first direction from the first main voltage line 11. In an embodiment, the first direction may be understood as the direction from the display area DA toward a terminal portion 30 located or provided near an end of the substrate 100. The first connection line 12 may be electrically connected to a first terminal 32 of the terminal portion 30.

[0066] The second power supply voltage line 20 may include a second main voltage line 21 and a second connection line 22, the second main voltage line 21 may partially surround two ends of the first main voltage line 11 and the display area DA, and the second connection line 22 extends in the first direction from the second main voltage line 21. For example, when the display area DA is rectangular, the second main voltage line 21 may extend along two ends of the first main voltage line 11 and the remaining sides of the display area DA except for the side adjacent to the first main voltage line 11. The second connection line 22 may extend in a first direction substantially parallel to the first connection line 12, and may be electrically connected to a second terminal 33 of the terminal portion 30. The second power supply voltage line 20 may be bent to surround an end of the first power supply voltage line 10.

[0067] The terminal portion 30 can be arranged or disposed at an end of the substrate 100 and can include terminals 31, 32, and 33. The terminal portion 30 can be exposed without being covered or overlapped by an insulating layer and can be electrically connected to a flexible printed circuit board or a controller (not shown), such as a driver IC chip.

[0068] The controller can convert an image signal transmitted from the outside into an image data signal and can transmit the image data signal to the display area DA through the third terminal 31. The controller can receive a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, can generate a control signal for controlling the driving of a first gate driver and a second gate driver (not shown), and can transmit the control signal through a terminal (not shown).

[0069] The controller can transmit different voltages to the first power supply voltage line 10 and the second power supply voltage line 20 through the first terminal 32 and the second terminal 33, respectively.

[0070] The first power supply voltage line 10 can supply a first power supply voltage ELVDD to each pixel P (see Figure 2A and Figure 2B ), and the second power supply voltage line 20 can supply a second power supply voltage ELVSS to each pixel P (see Figure 2A and Figure 2B ).

[0071] For example, the first power supply voltage ELVDD can be supplied to each pixel P through a driving voltage line PL electrically connected to the first power supply voltage line 10. The second power supply voltage ELVSS can be supplied to the cathode of an organic light emitting diode OLED provided in each pixel P (see Figure 2A and Figure 2B ). In this case, the second main voltage line 21 of the second power supply voltage line 20 can be electrically connected to the cathode of the organic light emitting diode OLED in the non-display area NDA.

[0072] Although not shown, a scan driver that can supply a scan signal to a scan line SL of each pixel P, a data driver that can supply a data signal to a data line DL, and the like can be arranged or disposed in the non-display area NDA.

[0073] In the non-display area NDA, a first dam portion 110, a second dam portion 120, and a third dam portion 130 surrounding the display area DA can be spaced apart from each other.

[0074] When forming Figure 4 of the thin film encapsulation layer 400 Figure 4When the organic encapsulation layer 420 including an organic material such as a monomer is formed by applying an inkjet process, the first dam part 110 and the second dam part 120 can be used as dams, and the dams can prevent the organic material from flowing to the edge of the substrate 100 and can prevent the formation of edge tails at the edge of the substrate 100 through the organic encapsulation layer 420.

[0075] Although the first dam part 110 and the second dam part 120 are arranged, the organic encapsulation layer 420 can flow over the first dam part 110 and the second dam part 120 to the edge of the substrate 100. For example, when the position of the second dam part 120 is arranged or set to be closer to the first dam part 110 from the edge of the substrate 100 to reduce the dead zone area recognizable externally, or when the position of the first dam part 110 is arranged or set to be closer to the second dam part 120 to expand the display area DA, the interval between the first dam part 110 and the second dam part 120 will be reduced, and thus, the organic encapsulation layer 420 can flow over the second dam part 120. The edge tails formed due to the overflow of the organic material can be used as an input path for external impurities, resulting in defects in the organic light-emitting diode OLED. As the dead zone decreases, the need to reduce the overflow of the organic material and control the amount of the overflowed organic material becomes more important. The third dam part 130 arranged or set between the display area DA and the first dam part 110 can reduce the amount of the organic material flowing over the first dam part by reducing the reflux speed of the organic material.

[0076] Referring to Figure 2A , each pixel P can include a pixel circuit PC electrically connected to a scan line SL and a data line DL and an organic light-emitting diode OLED electrically connected to the pixel circuit PC.

[0077] The pixel circuit PC can include a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2 can transmit the data signal Dm input through the data line DL to the driving thin film transistor T1 according to the scan signal Sn input through the scan line SL.

[0078] The storage capacitor Cst can be electrically connected to the switching thin film transistor T2 and the driving voltage line PL, and can store a voltage corresponding to the difference between the voltage received from the switching thin film transistor T2 and the first power supply voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0079] The driving thin film transistor T1 can be electrically connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the organic light-emitting diode OLED according to the voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED can emit light with a certain brightness according to the driving current.

[0080] Having referred to Figure 2AA case where the pixel circuit PC may include two thin film transistors and a storage capacitor is described, but the embodiments are not limited thereto.

[0081] Referring Figure 2B , the pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, a compensating thin film transistor T3, a first initialization thin film transistor T4, a first emission control thin film transistor T5, a second emission control thin film transistor T6, and a second initialization thin film transistor T7.

[0082] Figure 2B A case where signal lines SLn, SLn-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL may be provided for each pixel P is shown, but the embodiments are not limited thereto. In an embodiment, at least one of the signal lines SLn, SLn-1, EL, and DL and / or the initialization voltage line VL may be shared by adjacent pixels.

[0083] The drain electrode of the driving thin film transistor T1 may be electrically connected to the organic light emitting diode OLED through the second emission control thin film transistor T6. The driving thin film transistor T1 may receive a data signal Dm according to the switching operation of the switching thin film transistor T2 and supply a driving current to the organic light emitting diode OLED.

[0084] The gate electrode of the switching thin film transistor T2 may be electrically connected to the first scan line SLn, and the source electrode of the switching thin film transistor T2 may be electrically connected to the data line DL. The drain electrode of the switching thin film transistor T2 may be electrically connected to the source electrode of the driving thin film transistor T1 and electrically connected to the driving voltage line PL through the first emission control thin film transistor T5.

[0085] The switching thin film transistor T2 may be turned on according to the first scan signal Sn received through the first scan line SLn to perform a switching operation to transfer the data signal Dm received through the data line DL to the source electrode of the driving thin film transistor T1.

[0086] The gate electrode of the compensating thin film transistor T3 may be electrically connected to the first scan line SLn. The source electrode of the compensating thin film transistor T3 may be electrically connected to the drain electrode of the driving thin film transistor T1 and electrically connected to the pixel electrode of the organic light emitting diode OLED through the second emission control thin film transistor T6. The drain electrode of the compensating thin film transistor T3 may be electrically connected to any one electrode of the storage capacitor Cst, the source electrode of the first initialization thin film transistor T4, and the gate electrode of the driving thin film transistor T1. The compensating thin film transistor T3 may be turned on according to the first scan signal Sn received through the first scan line SLn to electrically connect the gate electrode and the drain electrode of the driving thin film transistor T1 to each other, so that the driving thin film transistor T1 may be diode-connected.

[0087] The gate electrode of the first initialization thin film transistor T4 can be electrically connected to the second scan line (previous scan line) SLn-1. The drain electrode of the first initialization thin film transistor T4 can be electrically connected to the initialization voltage line VL. The source electrode of the first initialization thin film transistor T4 can be electrically connected to any one of the electrodes of the storage capacitor Cst, the drain electrode of the compensation thin film transistor T3, and the gate electrode of the driving thin film transistor T1. The first initialization thin film transistor T4 can be turned on according to the second scan signal Sn-1 received through the second scan line SLn-1 to perform an initialization operation to transmit the initialization voltage VINT to the gate electrode of the driving thin film transistor T1, thereby initializing the voltage of the gate electrode of the driving thin film transistor T1.

[0088] The gate electrode of the first emission control thin film transistor T5 can be electrically connected to the emission control line EL. The source electrode of the first emission control thin film transistor T5 can be electrically connected to the driving voltage line PL. The drain electrode of the first emission control thin film transistor T5 can be electrically connected to the source electrode of the driving thin film transistor T1 and the drain electrode of the switching thin film transistor T2.

[0089] The gate electrode of the second emission control thin film transistor T6 can be electrically connected to the emission control line EL. The source electrode of the second emission control thin film transistor T6 can be electrically connected to the drain electrode of the driving thin film transistor T1 and the source electrode of the compensation thin film transistor T3. The drain electrode of the second emission control thin film transistor T6 can be electrically connected to the pixel electrode of the organic light emitting diode OLED. The first emission control thin film transistor T5 and the second emission control thin film transistor T6 can be turned on simultaneously according to the emission control signal En received through the emission control line EL to transmit the first power supply voltage ELVDD to the organic light emitting diode OLED, so that a driving current can flow through the organic light emitting diode OLED.

[0090] The gate electrode of the second initialization thin film transistor T7 can be electrically connected to the second scan line SLn-1. The source electrode of the second initialization thin film transistor T7 can be electrically connected to the pixel electrode of the organic light emitting diode OLED. The drain electrode of the second initialization thin film transistor T7 can be electrically connected to the initialization voltage line VL. The second initialization thin film transistor T7 can be turned on according to the second scan signal Sn-1 received through the second scan line SLn-1 to initialize the pixel electrode of the organic light emitting diode OLED.

[0091] Figure 2BIllustrated is a case where the first initialization thin film transistor T4 and the second initialization thin film transistor T7 can be electrically connected to the second scan line SLn-1, but the embodiment is not limited thereto. In the embodiment, the first initialization thin film transistor T4 can be electrically connected to the previous scan line, for example, the second scan line SLn-1, and can be driven according to the second scan signal Sn-1, and the second initialization thin film transistor T7 can be electrically connected to a separate signal line (for example, the next scan line), and can be driven according to the signal received through the corresponding scan line.

[0092] The other electrode of the storage capacitor Cst can be electrically connected to the driving voltage line PL. Any one of the electrodes of the storage capacitor Cst can be electrically connected to the gate electrode of the driving thin film transistor T1, the drain electrode of the compensation thin film transistor T3, and the source electrode of the first initialization thin film transistor T4.

[0093] The opposite electrode (for example, the cathode) of the organic light emitting diode OLED can receive the second power supply voltage ELVSS (or the common power supply voltage). The organic light emitting diode OLED can receive the driving current from the driving thin film transistor T1 and can emit light.

[0094] The pixel circuit PC is not limited to the number and circuit design of the thin film transistors and storage capacitors described above with reference to Figure 2A and Figure 2B and various changes can be made to the number and circuit design of the thin film transistors and storage capacitors within the spirit and scope of the present disclosure.

[0095] Reference will be made to Figure 3 and Figure 4 for a more detailed description of Figure 1 Region III of Figure 2A and Figure 2B the first thin film transistor (driving thin film transistor) T1, the second thin film transistor (switching thin film transistor) T2, and the storage capacitor Cst in the pixel circuit PC of each pixel P described above with reference to

[0096] Referring to Figure 3 , the pixel P can be arranged or disposed in Figure 1 Region III of

[0097] The pixel P Figure 3 is shown in

[0098] The spacer 115 may be disposed or arranged between some (or a predetermined number) of the plurality of pixels P. During the process of depositing the intermediate layer 320 including the emission layer by the application of a mask, the spacer 115 may maintain the spacing between the mask and the substrate 100 to prevent the intermediate layer 320 from being perforated or otherwise damaged during the deposition process.

[0099] The spacer 115 may include a material that is the same as or similar to the material of the pixel defining layer 113. When the pixel defining layer 113 is formed by the application of a halftone mask, the spacer 115 may be formed of a material that is the same as or similar to the material of the pixel defining layer 113 at a height different from the height of the pixel defining layer 113.

[0100] Referring Figure 4 , the buffer layer 101 may be disposed or arranged on the substrate 100, and the driving thin film transistor T1, the switching thin film transistor T2, and the storage capacitor Cst may be disposed or arranged on the buffer layer 101.

[0101] The substrate 100 may include various materials such as glass, metal, or plastic. For example, the substrate 100 may be a flexible substrate including polymer resins such as polyethersulfone (PES), polyacrylate (PA), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

[0102] The buffer layer 101 formed of silicon oxide (SiO x ) and / or silicon nitride (SiN x ) may be provided or arranged on the substrate 100 and may prevent the penetration of impurities.

[0103] The driving thin film transistor T1 may include a driving semiconductor layer A1 and a driving gate electrode G1, and the switching thin film transistor T2 may include a switching semiconductor layer A2 and a switching gate electrode G2. The first gate insulating layer 103 may be disposed or arranged between the driving semiconductor layer A1 and the driving gate electrode G1 and between the switching semiconductor layer A2 and the switching gate electrode G2. The first gate insulating layer 103 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON).

[0104] The driving semiconductor layer A1 and the switching semiconductor layer A2 may include amorphous silicon or polycrystalline silicon. In an embodiment, both the driving semiconductor layer A1 and the switching semiconductor layer A2 may include an oxide of at least one selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn).

[0105] The driving semiconductor layer A1 may include a driving channel region that overlaps with the driving gate electrode G1 and is not doped with impurities, and a driving source region and a driving drain region that are disposed or arranged on both sides of the driving channel region and are doped with impurities. The driving source electrode S1 and the driving drain electrode D1 may be electrically connected to the driving source region and the driving drain region, respectively.

[0106] The switching semiconductor layer A2 may include a switching channel region that overlaps with the switching gate electrode G2 and is not doped with impurities, and a switching source region and a switching drain region that are disposed or arranged on both sides of the switching channel region and are doped with impurities. The switching source electrode S2 and the switching drain electrode D2 may be electrically connected to the switching source region and the switching drain region, respectively.

[0107] Both the driving gate electrode G1 and the switching gate electrode G2 may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be a single layer or a multi-layer.

[0108] In one or more embodiments, the storage capacitor Cst may be disposed or arranged to overlap with the driving thin film transistor T1. In this case, the area of the storage capacitor Cst and the area of the driving thin film transistor T1 may be increased, and high-quality images may be provided. For example, the driving gate electrode G1 may be the first storage capacitor plate CE1 of the storage capacitor Cst. The second storage capacitor plate CE2 may overlap with the first storage capacitor plate CE1, wherein the second gate insulating layer 105 is interposed between the first storage capacitor plate CE1 and the second storage capacitor plate CE2. The second gate insulating layer 105 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON).

[0109] The driving thin film transistor T1, the switching thin film transistor T2, and the storage capacitor Cst may be covered or overlapped by the interlayer insulating layer 107.

[0110] The interlayer insulating layer 107 may be an inorganic layer such as silicon oxynitride (SiON), silicon oxide (SiO x ), and / or silicon nitride (SiN x ).

[0111] The data line DL may be disposed or provided on the interlayer insulating layer 107. The data line DL may be electrically connected to the switching semiconductor layer A2 of the switching thin film transistor T2 through a contact hole penetrating the interlayer insulating layer 107. The data line DL may be used as the switching source electrode S2.

[0112] The driving source electrode S1, the driving drain electrode D1, the switching source electrode S2, and the switching drain electrode D2 may be disposed or provided on the interlayer insulating layer 107 and may be electrically connected to the driving semiconductor layer A1 or the switching semiconductor layer A2 through contact holes penetrating the interlayer insulating layer 107.

[0113] The data line DL, the driving source electrode S1, the driving drain electrode D1, the switching source electrode S2, and the switching drain electrode D2 may be covered or overlapped by an inorganic protective layer (not shown).

[0114] The inorganic protective layer (not shown) may be a single-layer film or a multi-layer film of silicon nitride (SiN x ) and silicon oxide (SiO x ). The inorganic protective layer (not shown) may prevent some of the lines exposed in the non-display area NDA from being damaged by the etchant used during the patterning of the pixel electrode 310. The lines exposed in the non-display area NDA may be, for example, the lines formed together with the data line DL in the same process.

[0115] The driving voltage line PL may be disposed or provided on a layer different from the data line DL. As used herein, the expression “A and B are disposed or provided on different layers” may refer to a case where at least one insulating layer may be disposed or provided between A and B such that one of A and B may be disposed or provided below the at least one insulating layer and the other of them may be disposed or provided above the at least one insulating layer. The first organic layer 109 may be disposed or provided between the driving voltage line PL and the data line DL, and the driving voltage line PL may be covered or overlapped by the second organic layer 111.

[0116] The driving voltage line PL may be a single-layer film or a multi-layer film including at least one of aluminum (Al), copper (Cu), titanium (Ti), and any alloy thereof. In an embodiment, the driving voltage line PL may be a three-layer film of Ti / Al / Ti.

[0117] Figure 4 A configuration in which the driving voltage line PL may be disposed or provided on the first organic layer 109 is shown, but the embodiment is not limited thereto. In an embodiment, the driving voltage line PL may be electrically connected to a lower additional voltage line (not shown) that may be formed or provided on the same layer as the layer of the data line DL through a through hole (not shown) that may be formed in the first organic layer 109, thereby reducing the resistance.

[0118] Both the first organic layer 109 and the second organic layer 111 may be a single-layer film or a multi-layer film.

[0119] Both the first organic layer 109 and the second organic layer 111 may include an organic insulating material. For example, the organic insulating material may include general polymers (imide polymers, polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, vinyl alcohol polymers, and other materials within the spirit and scope of the present disclosure.

[0120] An organic light-emitting diode (OLED) including a pixel electrode 310, a counter electrode 330, and an intermediate layer 320 disposed or arranged therebetween and including an emission layer may be located or disposed on the second organic layer 111.

[0121] The pixel electrode 310 may be electrically connected to a connection line CL formed or disposed on the first organic layer 109, and the connection line CL may be electrically connected to a driving drain electrode D1 of a driving thin-film transistor T1.

[0122] The pixel electrode 310 may be a transparent electrode or a reflective electrode.

[0123] When the pixel electrode 310 is a transparent electrode, the pixel electrode 310 may include a transparent conductive layer. The transparent conductive layer may include at least one selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). As a further example of the transparent conductive layer, the pixel electrode 310 may include a semi-transmissive layer to improve light efficiency. The semi-transmissive layer may be a thin film having a thickness in the range of several micrometers (μm) to several tens of micrometers (μm), and may include at least one selected from Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, and Yb.

[0124] When the pixel electrode 310 is a reflective electrode, the pixel electrode 310 may include a reflective layer and a transparent conductive layer disposed or arranged above and / or below the reflective layer. The reflective layer may include one selected from Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and any of their compounds. The transparent conductive layer may include at least one selected from ITO, IZO, ZnO, In2O3, IGO, and AZO.

[0125] However, the embodiments are not limited thereto. The pixel electrode 310 may include various materials and may be variously modified. For example, the pixel electrode 310 may have a single-layer structure or a multi-layer structure.

[0126] The pixel defining layer 113 may be disposed or arranged on the pixel electrode 310.

[0127] The pixel defining layer 113 may have an opening exposing the pixel electrode 310 to define the pixel P. The pixel defining layer 113 may increase the distance between the edge of the pixel electrode 310 and the counter electrode 330, thereby preventing an arc or the like from occurring at the end of the pixel electrode. The pixel defining layer 113 may include, for example, an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

[0128] The intermediate layer 320 may include a low molecular weight material or a high molecular weight material.

[0129] When the intermediate layer 320 includes a low molecular weight material, the intermediate layer 320 may have a structure in which a hole injection layer, a hole transport layer, an emission layer, an electron transport layer, and an electron injection layer are stacked in a single-layer structure or a multi-layer structure. The intermediate layer 320 may include various organic materials such as copper phthalocyanine (CuPc), N-N'-di(naphthalen-1-yl)-N,N'-diphenyl-benzidine (NPB), and tris(8-hydroxyquinoline)aluminum (Alq3). The intermediate layer 320 may be formed by various methods such as vacuum deposition. However, the present disclosure is not limited thereto.

[0130] When the intermediate layer 320 includes a high molecular weight material, the intermediate layer 320 may have a structure including a hole transport layer and an emission layer. In this case, the hole transport layer may include poly(3,4-ethylenedioxythiophene) (PEDOT), and the emission layer may include high molecular weight materials such as poly(phenylene vinylene) (PPV)-type polymers and polyfluorene-type polymers. The intermediate layer 320 may be formed by various methods, for example, such as screen printing, inkjet printing, or laser-induced thermal imaging.

[0131] The intermediate layer 320 may be an integral layer on the pixel electrode 310, or may be a patterned layer corresponding to each pixel electrode 310.

[0132] The counter electrode 330 may be disposed or arranged on the display area DA, and may be disposed or arranged to cover the display area DA or overlap with the display area DA. For example, the counter electrode 330 may be integrally formed in the organic light emitting diode OLED and correspond to the pixel electrode 310. The counter electrode 330 may be electrically connected to the second power supply voltage line 20 to be described below.

[0133] The counter electrode 330 may be a transparent electrode or a reflective electrode. When the counter electrode 330 is a transparent electrode, the counter electrode 330 may include one or more selected from Ag, Al, Mg, Li, Ca, Cu, LiF / Ca, LiF / Al, MgAg, and CaAg. The counter electrode 330 may be a thin film having a thickness in the range of several nanometers (nm) to dozens of nanometers (nm).

[0134] When the counter electrode 330 is a reflective electrode, the counter electrode 330 may include at least one selected from Ag, Al, Mg, Li, Ca, Cu, LiF / Ca, LiF / Al, MgAg, and CaAg. The structure and material of the counter electrode 330 are not limited thereto, and various modifications can be made thereto.

[0135] The spacer 115 may be disposed or provided on the pixel defining layer 113. The spacer 115 may protrude from the pixel defining layer 113 toward the thin film encapsulation layer 400. During the process of depositing the intermediate layer 320 including the emission layer by the application of a mask, the spacer 115 may maintain the interval between the mask and the substrate 100 to prevent the intermediate layer 320 from being perforated or otherwise damaged during the deposition process.

[0136] The spacer 115 may include an organic material such as polyimide or hexamethyldisiloxane (HMDSO). The spacer 115 may be disposed or provided on at least one of the first dam portion 110, the second dam portion 120, and the third dam portion 130 to be described later, and may prevent moisture penetration and the formation of a height difference in the dam portion.

[0137] Since the organic light-emitting diode OLED can be easily damaged by external moisture or oxygen, the organic light-emitting diode OLED can be covered or overlapped and protected by the thin film encapsulation layer 400.

[0138] The thin film encapsulation layer 400 may cover or overlap the display area DA and may extend to the outside of the display area DA. The thin film encapsulation layer 400 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. In an embodiment, the thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

[0139] The first inorganic encapsulation layer 410 may cover or overlap the entire counter electrode 330 and may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0140] Other layers such as a cover layer (not shown) may be disposed or provided between the first inorganic encapsulation layer 410 and the counter electrode 330. For example, the cover layer (not shown) may include one or more organic materials or inorganic materials to improve light efficiency, and the organic material or inorganic material is selected from silicon oxide (SiO2), silicon nitride (SiN x) Zinc oxide (ZnO2), titanium dioxide (TiO2), zirconium dioxide (ZrO2), indium tin oxide (ITO), indium zinc oxide (IZO), Alq3, CuPc, CBP, and a-NPB. In an embodiment, a cover layer (not shown) can cause a plasma resonance with respect to the light generated by the organic light-emitting diode OLED. For example, the cover layer (not shown) can include nanoparticles. The cover layer (not shown) can prevent the organic light-emitting diode OLED from being damaged by heat, plasma, or the like generated in the chemical vapor deposition process or sputtering process for forming the thin film encapsulation layer 400. For example, the cover layer (not shown) can include at least one epoxy material selected from bisphenol epoxy resin, epoxy butadiene resin, fluorine epoxy resin, and novolac epoxy resin.

[0141] A layer (not shown) including LiF can be disposed or provided between the first inorganic encapsulation layer 410 and the cover layer (not shown).

[0142] Since the first inorganic encapsulation layer 410 can be formed or provided along the underlying structure, the upper surface of the first inorganic encapsulation layer 410 can be uneven. The organic encapsulation layer 420 can cover or overlap the first inorganic encapsulation layer 410 to achieve planarization. The organic encapsulation layer 420 can have a substantially flat upper surface in a portion corresponding to the display area DA.

[0143] The organic encapsulation layer 420 can include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, an acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, or the like), or any combination thereof.

[0144] The second inorganic encapsulation layer 430 can cover or overlap the organic encapsulation layer 420 and can include silicon oxide, silicon nitride, and / or silicon oxynitride. Although not shown, the second inorganic encapsulation layer 430 can be disposed or provided to directly contact the first inorganic encapsulation layer 410 at the edge region of the display device 1, thereby preventing the organic encapsulation layer 420 from being exposed to the outside of the display device 1.

[0145] Figure 5 The structure of the pixel P is shown on the left side of Figure 4 and Figure 5 The right side of Figure 1 shows a schematic cross-section taken along the line VA-VB of

[0146] A buffer layer 101, a first gate insulating layer 103, a second gate insulating layer 105, an interlayer insulating layer 107, and a first organic layer 109 that can extend on a substrate 100 in a display area DA can be arranged or disposed in a VA-VB region. A spiderline SPL can be arranged or disposed between the second gate insulating layer 105 and the interlayer insulating layer 107, a first conductive layer 10a and a third conductive layer 20a can be arranged or disposed on the interlayer insulating layer 107, and a second conductive layer 10b and a fourth conductive layer 20b can be arranged or disposed on the first organic layer 109.

[0147] The first conductive layer 10a and the second conductive layer 10b can be electrically connected through a first contact hole CNT1 formed in the first organic layer 109 to constitute a first power supply voltage line 10 that can supply a first power supply voltage ELVDD (see Figure 2A and Figure 2B ) to each pixel P. Since the first power supply voltage line 10 can be formed as a two-layer conductive layer, the width of the first power supply voltage line 10 can be reduced, thereby reducing the dead zone. In Figure 5 two first contact holes CNT1 can be shown, but this is an example. Within the spirit and scope of the present disclosure, the number of the first contact holes CNT1 can be one or three or more.

[0148] The third conductive layer 20a and the fourth conductive layer 20b can be electrically connected through a second contact hole CNT2 and a third contact hole CNT3 formed in the first organic layer 109 respectively to constitute a second power supply voltage line 20 that can supply a second power supply voltage ELVSS (see Figure 2A and Figure 2B ) to each pixel P.

[0149] In an embodiment, the fourth conductive layer 20b can include an opening OP that exposes the upper surface of the first organic layer 109. Since the second power supply voltage line 20 can be formed as a two-layer conductive layer of the third conductive layer 20a and the fourth conductive layer 20b, the width of the second power supply voltage line 20 can be reduced, thereby reducing the dead zone. However, when the fourth conductive layer 20b blocks the upper part of the first organic layer 109, during the process of forming an organic light-emitting diode OLED, the escape gas discharged from the first organic layer 109 can remain in the organic light-emitting diode OLED. This can cause damage to the organic light-emitting diode OLED. However, in the embodiment, the opening OP can be formed in the fourth conductive layer 20b to expose the upper surface of the first organic layer 109, thereby facilitating the discharge of the escape gas discharged from the first organic layer 109 during the process of manufacturing the organic light-emitting diode OLED.

[0150] Regarding the fourth conductive layer 20b, the following will describe based on the proximity of the opening OP to the display area DA (see Figure 1a first portion 20b1 and a second portion 20b2 away from the display area DA. The first portion 20b1 of the fourth conductive layer 20b can be electrically connected to the third conductive layer 20a through the second contact hole CNT2, and the second portion 20b2 of the fourth conductive layer 20b can be electrically connected to the third conductive layer 20a through the third contact hole CNT3. In Figure 5 it, one second contact hole CNT2 and one third contact hole CNT3 are shown, but this is an example. The number of the second contact holes CNT2 and the number of the third contact holes CNT3 can be one or more that conform to the spirit and scope of the present disclosure.

[0151] The first conductive layer 10a and the third conductive layer 20a can be formed of the same or similar material as that of the data line DL, and the second conductive layer 10b and the fourth conductive layer 20b can be formed of the same or similar material as that of the driving voltage line PL.

[0152] The second organic layer 111 and the pixel defining layer 113 can be located or disposed on the second conductive layer 10b at positions overlapping with the first power supply voltage line 10, respectively. The counter electrode 330 formed or disposed in the display area DA can extend on the pixel defining layer 113.

[0153] The third dam part 130, the first dam part 110, and the second dam part 120 can be sequentially arranged or disposed at positions overlapping with the second power supply voltage line 20 in the direction from the display area DA to the end of the substrate 100.

[0154] The third dam part 130 can include a first layer 111c formed of the same or similar material as that of the second organic layer 111 and a second layer 113c formed of the same or similar material as that of the pixel defining layer 113. The second layer 113c of the third dam part 130 can cover the upper surface and the side surface of the first layer 111c to stably ensure the process margin during the patterning of the second layer 113c in the photolithography process, thereby stably ensuring the height of the second layer 113c.

[0155] A part of the third dam part 130 can overlap with the counter electrode 330 extending in the display area DA. The end of the counter electrode 330 can extend to the second power supply voltage line 20, thereby blocking the noise caused by the line that may affect the touch sensing layer (not shown) formed or disposed on the thin film encapsulation layer 400.

[0156] The first dam portion 110 may include a first layer 111a formed of a material the same as or similar to that of the second organic layer 111 and a second layer 113a formed of a material the same as or similar to that of the pixel defining layer 113. The second layer 113a of the first dam portion 110 may cover the upper surface and the side surfaces of the first layer 111a to stably ensure a processing margin during patterning of the second layer 113a in a photolithography process, thereby stably ensuring the height of the second layer 113a.

[0157] The second dam portion 120 may include a first layer 111b formed of a material the same as or similar to that of the second organic layer 111, a second layer 113b formed of a material the same as or similar to that of the pixel defining layer 113, and a third layer 115b formed of a material the same as or similar to that of the spacer 115. The second layer 113b of the second dam portion 120 may cover the upper surface and the side surfaces of the first layer 111b to stably ensure a processing margin during patterning of the second layer 113b in a photolithography process, thereby stably ensuring the height of the second layer 113b.

[0158] Figure 5 A structure in which the third layer 115b of the second dam portion 120 covers the upper surface and the side surfaces of the second layer 113b is shown, but the embodiment is not limited thereto. Since it is feasible to form the second layer 113b and the third layer 115b of the second dam portion 120 by a process of applying the same mask, the width of the upper surface of the second layer 113b and the width of the lower surface of the third layer 115b may be formed to be substantially the same as each other.

[0159] Since the height of the second dam portion 120 may be formed to be greater than the height of the first dam portion 110 and the height of the third dam portion 130, it is possible to prevent the organic encapsulation layer 420 from forming beyond the edge tails of the second dam portion 120. During the deposition of the intermediate layer 320 by applying a mask, the interval between the mask and the substrate 100 may be maintained to prevent the intermediate layer 320 from being perforated or otherwise damaged by the mask during deposition.

[0160] Figure 6 is Figure 5 a schematic cross-sectional view of region VI of Figure 7 which the thin film encapsulation layer 400 may be omitted, and Figure 6 is a plan view showing the fourth conductive layer 20b and the first dam portion 110, the second dam portion 120, and the third dam portion 130 of

[0161] Referring to Figure 6 and Figure 7, the fourth conductive layer 20b of the second power supply voltage line 20 may be located or disposed on the first organic layer 109, and a single opening OP exposing the upper surface of the first organic layer 109 may be formed in the fourth conductive layer 20b. The opening OP may be described as a single opening in the embodiment. However, the present disclosure is not limited thereto. For example, within the spirit and scope of the present disclosure, the opening OP may be one opening or multiple openings.

[0162] The single opening OP may be formed between the third dam portion 130 and the second dam portion 120 in a direction in which the third dam portion 130 and the second dam portion 120 may extend. The first dam portion 110 located or disposed between the third dam portion 130 and the second dam portion 120 may be arranged or disposed at a position overlapping the single opening OP formed in the fourth conductive layer 20b. The opening OP may be described as a single opening in the embodiment. However, the present disclosure is not limited thereto. For example, within the spirit and scope of the present disclosure, the opening OP may be one opening or multiple openings.

[0163] The third dam portion 130 and the first dam portion 110 may be spaced apart from each other, and a first hole H1 may be formed between the third dam portion 130 and the first dam portion 110. The first dam portion 110 and the second dam portion 120 may be spaced apart from each other, and a second hole H2 may be formed between the first dam portion 110 and the second dam portion 120. The size of the opening OP formed between the third dam portion 130 and the second dam portion 120 may be greater than the sum of the sizes of the first hole H1 and the second hole H2. However, the present disclosure is not limited thereto.

[0164] A part of the opening OP formed in the fourth conductive layer 20b may be covered or overlapped by the first dam portion 110, but another part of the opening OP may be exposed in the first hole H1 and the second hole H2. Therefore, the escaping gas discharged from the first organic layer 109 during the process of forming the organic light-emitting diode OLED may be discharged to the outside through the first hole H1 and the second hole H2.

[0165] The third dam portion 130 may cover the first end portion ES1 of the first part 20b1 of the fourth conductive layer 20b, and the second dam portion 120 may cover the second end portion ES2 and the third end portion ES3 of the second part 20b2 of the fourth conductive layer 20b, thereby preventing damage to the first end portion ES1, the second end portion ES2, and the third end portion ES3 of the fourth conductive layer 20b when etching the pattern of the fourth conductive layer 20b.

[0166] The fourth conductive layer 20b may be made of the same material as the driving voltage line PL (see Figure 5) is formed of the same or similar materials. In an embodiment, the fourth conductive layer 20b may be a single-layer film or a multi-layer film including at least one of aluminum (Al), copper (Cu), titanium (Ti), and any alloys thereof. For example, the fourth conductive layer 20b may have a stacked structure including a first layer including titanium (Ti), a second layer including aluminum (Al), and a third layer including titanium (Ti).

[0167] Figure 8 is a schematic cross-sectional view of the display device 1' according to the comparative example. The main differences from the display device 1 Figure 5 according to the embodiment will be described.

[0168] Figure 8 The left side of Figure 5 may be the same as the IVA-IVB region of Figure 8 and the right side of Figure 5 may be similar to the VA-VB region of

[0169] Referring to the VA-VB region, a buffer layer 101, a first gate insulating layer 103, a second gate insulating layer 105, an interlayer insulating layer 107, and a first organic layer 109 that can extend in the display area DA may be arranged or provided on the substrate 100. The grid line SPL may be arranged or provided between the second gate insulating layer 105 and the interlayer insulating layer 107, the first conductive layer 10a and the third conductive layer 20a may be arranged or provided on the interlayer insulating layer 107, and the second conductive layer 10b and the fourth conductive layer 20b may be arranged or provided on the first organic layer 109.

[0170] The first conductive layer 10a and the second conductive layer 10b may be electrically connected through a first contact hole CNT1 formed in the first organic layer 109 to constitute a first power supply voltage line 10. The third conductive layer 20a and the fourth conductive layer 20b may be electrically connected through a second contact hole CNT2 formed in the first organic layer 109 to constitute a second power supply voltage line 20.

[0171] Different from Figure 5 the above embodiment of

[0172] Figure 9 is a schematic plan view of the display device according to the embodiment.

[0173] Referring toFigure 9 An opening OP exposing the upper surface of the first organic layer 109 may be formed in the fourth conductive layer 20b.

[0174] The third dam portion 130 and the first dam portion 110 may be spaced apart from each other, and a first hole H1 may be formed between the third dam portion 130 and the first dam portion 110. The first dam portion 110 and the second dam portion 120 may be spaced apart from each other, and a second hole H2 may be formed between the first dam portion 110 and the second dam portion 120. Some (or a predetermined amount) of the openings OP formed between the third dam portion 130 and the second dam portion 120 may be arranged or disposed to overlap with the first hole H1 and the second hole H2.

[0175] When Figure 7 the embodiment of Figure 9 is compared with Figure 7 the embodiment of Figure 7 as in the embodiment of

[0176] the position where the opening OP can be formed may be arranged or disposed between the third dam portion 130 and the second dam portion 120. However, different from the embodiment of Figure 7 the fourth conductive layer 20b may not be divided into a first portion 20b1 (see Figure 7 ) and a second portion 20b2 (see Figure 7 ), and connections may be made between the openings OP. In the embodiment, the outgassing gas can be effectively discharged by forming the opening OP in the fourth conductive layer 20b, and the lower surfaces of the first dam portion 110, the second dam portion 120, and the third dam portion 130 may be in direct contact with the upper surface of the first organic layer 109 through the opening OP, thereby improving the bonding strength between the first dam portion 110, the second dam portion 120, and the third dam portion 130 and the first organic layer 109.

[0177] The opening OP is shown in Figure 9 as having substantially the same size, but this is only an example. Various modifications can be made to the size and shape of the opening OP.

[0178] The second dam portion 120 may cover the third end portion ES3 of the fourth conductive layer 20b, thereby preventing damage to the third end portion ES3 of the fourth conductive layer 20b when etching the pattern of the fourth conductive layer 20b.

[0179] Figure 10 is a schematic plan view of a display device according to an embodiment.

[0180] Referring to Figure 10, a single opening OP exposing the upper surface of the first organic layer 109 may be formed in the fourth conductive layer 20b. The opening OP may be described as a single opening in the embodiment. However, the present disclosure is not limited thereto. For example, within the spirit and scope of the present disclosure, the opening OP may be one opening or multiple openings.

[0181] The single opening OP may be formed between the first power supply voltage line 10 (see Figure 5 ) and the third dam portion 130 in a direction in which the first power supply voltage line 10 and the third dam portion 130 may extend. In the embodiment, the opening OP may be described as a single opening. However, the present disclosure is not limited thereto. For example, within the spirit and scope of the present disclosure, the opening OP may be one opening or multiple openings.

[0182] The third dam portion 130 and the first dam portion 110 may be spaced apart from each other, and a first hole H1 may be formed between the third dam portion 130 and the first dam portion 110. The first dam portion 110 and the second dam portion 120 may be spaced apart from each other, and a second hole H2 may be formed between the first dam portion 110 and the second dam portion 120. In the embodiment, the opening OP may not overlap with the first hole H1 and the second hole H2.

[0183] When comparing the embodiment of Figure 7 with the embodiment of Figure 10 , as in the embodiment of Figure 7 , the number of the openings OP may be one, but different from the embodiment of Figure 7 , the opening OP may be formed between the first power supply voltage line 10 and the third dam portion 130.

[0184] As in the above-mentioned Figure 7 embodiment, the fourth conductive layer 20b may include a first portion 20b1 and a second portion 20b2, and the first portion 20b1 and the second portion 20b2 may be spaced apart from each other through the opening OP.

[0185] The third dam portion 130 may cover the second end portion ES2 of the second portion 20b2 of the fourth conductive layer 20b, and the second dam portion 120 may cover the third end portion ES3 of the second portion 20b2 of the fourth conductive layer 20b, thereby preventing damage to the second end portion ES2 and the third end portion ES3 of the fourth conductive layer 20b when etching the pattern of the fourth conductive layer 20b.

[0186] Figure 11 is a schematic plan view of a display device according to an embodiment.

[0187] Referring to Figure 11 , an opening OP exposing the upper surface of the first organic layer 109 (see Figure 5 ) may be formed in the first power supply voltage line 10 (see Figure 5) is formed in the fourth conductive layer 20b between the third dam portion 130.

[0188] The third dam portion 130 and the first dam portion 110 may be spaced apart from each other, and the first hole H1 may be formed between the third dam portion 130 and the first dam portion 110. The first dam portion 110 and the second dam portion 120 may be spaced apart from each other, and the second hole H2 may be formed between the first dam portion 110 and the second dam portion 120. In an embodiment, the opening OP may not overlap with the first hole H1 and the second hole H2.

[0189] When Figure 10 the embodiment of Figure 11 is compared with Figure 10 the embodiment of

[0190] as in Figure 10 the embodiment of Figure 10 the position where the opening OP can be formed may be formed between the first power supply voltage line 10 and the third dam portion 130, but the number of the opening OP may increase and the size of the opening OP may decrease. Figure 10 ) and the second part 20b2 (see

[0191] Different from the above embodiment of Figure 11 the fourth conductive layer 20b may not be divided into the first part 20b1 (see

[0192] The second dam portion 120 may cover the third end portion ES3 of the fourth conductive layer 20b, thereby preventing damage to the third end portion ES3 of the fourth conductive layer 20b when etching the pattern of the fourth conductive layer 20b.

[0193] Figure 12 is a schematic cross-sectional view of the display device 2 according to an embodiment.

[0194] Figure 12 The left side of Figure 4 shows the structure of the pixel P of Figure 12 and the right side of Figure 1 shows a schematic cross-section taken along the line VA-VB of

[0195] A buffer layer 101, a first gate insulating layer 103, a second gate insulating layer 105, an interlayer insulating layer 107, and a first organic layer 109 that can extend on a substrate 100 in a display area DA can be arranged or disposed in a VA-VB area. A grid line SPL can be arranged or disposed between the second gate insulating layer 105 and the interlayer insulating layer 107, a part of a first conductive layer 10a and a second power supply voltage line 20 can be arranged or disposed on the interlayer insulating layer 107, and other parts of a second conductive layer 10b and the second power supply voltage line 20 can be arranged or disposed on the first organic layer 109.

[0196] The first conductive layer 10a and the second conductive layer 10b can be electrically connected through a first contact hole CNT1 formed in the first organic layer 109 to constitute a first power supply voltage line 10. Since the first power supply voltage line 10 is formed as a two-layer conductive layer, the width of the first power supply voltage line 10 can be reduced, thereby reducing the dead zone. In Figure 5 Two first contact holes CNT1 are shown, but this is an example. Within the spirit and scope of the present disclosure, the number of the first contact holes CNT1 can be one or three or more.

[0197] In an embodiment, different from the Figure 5 embodiment, the second power supply voltage line 20 can be a single-layer conductive layer instead of a two-layer conductive layer. In an area where the second power supply voltage line 20 can be arranged or disposed, openings OP1 and OP2 can be formed in the first organic layer 109 to form a substantially concave-convex pattern. The second power supply voltage line 20 can be formed or disposed along the substantially concave-convex pattern on the first organic layer 109.

[0198] Different from the first power supply voltage line 10, the second power supply voltage line 20 formed as a substantially concave-convex pattern instead of a two-layer conductive layer can have a wider effective line width, thereby reducing the resistance. The openings OP1 and OP2 can be formed to reduce the amount occupied by the first organic layer 109, thereby reducing the amount of outgassing gas discharged from the first organic layer 109.

[0199] The first conductive layer 10a can be formed of a material the same as or similar to that of a data line DL, and the second conductive layer 10b and the second power supply voltage line 20 can be formed of a material the same as or similar to that of a driving voltage line PL.

[0200] A second organic layer 111 and a pixel defining layer 113 can be located or disposed on the second conductive layer 10b and the second organic layer 111 at positions overlapping with the first power supply voltage line 10, respectively. A counter electrode 330 formed or disposed in the display area DA can extend on the pixel defining layer 113. The counter electrode 330 can extend to cover a part of or overlap with a part of a third dam portion 130.

[0201] The thin film encapsulation layer 400 disposed or provided on the opposing electrode 330 may cover or overlap with the display area DA and may extend outside the display area DA. The thin film encapsulation layer 400 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. The structure, material, etc. of the thin film encapsulation layer 400 may be applied in the same or similar manner as in Figure 5 the embodiments.

[0202] The third dam portion 130, the first dam portion 110, and the second dam portion 120 may be sequentially disposed or provided at positions overlapping with the second power supply voltage line 20 in the direction from the display area DA to the end of the substrate 100.

[0203] The third dam portion 130 may include a first layer 111c formed of a material the same as or similar to that of the second organic layer 111 and a second layer 113c formed of a material the same as or similar to that of the pixel defining layer 113.

[0204] The first dam portion 110 may include a first layer 111a formed of a material the same as or similar to that of the second organic layer 111 and a second layer 113a formed of a material the same as or similar to that of the pixel defining layer 113.

[0205] The second dam portion 120 may include a first layer 111b formed of a material the same as or similar to that of the second organic layer 111, a second layer 113b formed of a material the same as or similar to that of the pixel defining layer 113, and a third layer 115b formed of a material the same as or similar to that of the spacer 115.

[0206] To maintain the appropriate heights of the first dam portion 110, the second dam portion 120, and the third dam portion 130, the first dam portion 110, the second dam portion 120, and the third dam portion 130 may be disposed or provided in the convex regions of the second power supply voltage line forming a substantially uneven pattern.

[0207] According to one or more embodiments, when the second power supply voltage line is formed of two conductive layers, the amount of exhaust gas or outgassing gas discharged from the organic layer disposed or provided between the two conductive layers may be reduced, thereby preventing the occurrence of defective pixels in the display device due to the exhaust gas or outgassing gas. However, the scope of the present disclosure is not limited by these effects.

[0208] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. The description of a feature or aspect within each embodiment is generally to be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the figures, those of ordinary skill in the art will understand that various changes in form and detail may be made in the embodiments without departing from the spirit and scope defined by the following claims.

Claims

1. A display device, comprising: a substrate; a display area disposed on the substrate and including a plurality of pixels; a non-display area adjacent to the display area; a first power supply voltage line disposed in the non-display area and including: a first conductive layer; a first organic layer disposed on the first conductive layer; and a second conductive layer disposed on the first organic layer; a second power supply voltage line disposed in the non-display area and including: a third conductive layer spaced apart from the first conductive layer; and a fourth conductive layer disposed on the first organic layer, wherein the first organic layer is disposed on the third conductive layer; a first dam portion surrounding the display area and disposed adjacent to the first power supply voltage line; a second dam portion disposed adjacent to the first dam portion; and a third dam portion disposed between the first power supply voltage line and the first dam portion, wherein the fourth conductive layer includes an opening exposing an upper surface of the first organic layer between the first power supply voltage line and the second dam portion.

2. The display device according to claim 1, further comprising: a second organic layer disposed on the first organic layer; and a pixel defining layer disposed on the second organic layer, wherein, the first dam portion includes: a first layer including a part of the second organic layer; and a second layer including a part of the pixel defining layer, the second dam portion includes: a first layer including a part of the second organic layer; and a second layer including a part of the pixel defining layer, and the third dam portion includes: a first layer including a part of the second organic layer; and a second layer including a part of the pixel defining layer.

3. The display device according to claim 2, wherein, The fourth conductive layer includes an opening disposed between the third dam portion and the second dam portion along an extending direction of the third dam portion and the second dam portion.

4. The display device according to claim 3, wherein, The opening is disposed to overlap with the first dam portion.

5. The display device according to claim 3, wherein, the fourth conductive layer includes a first part and a second part spaced apart from each other through the opening, the third dam portion and an end portion of the first part adjacent to the opening overlap, and the second dam portion and an end portion of the second part adjacent to the opening overlap.

6. The display device according to claim 5, wherein, The second dam portion overlaps with an end portion of the second part at a predetermined distance from the opening.

7. The display device according to claim 2, wherein, The fourth conductive layer includes a plurality of openings disposed between the third dam portion and the second dam portion.

8. The display device according to claim 2, wherein, The fourth conductive layer includes an opening disposed between the first power supply voltage line and the third dam portion along an extending direction of the third dam portion.

9. The display device according to claim 2, wherein, The fourth conductive layer includes a plurality of openings disposed between the first power supply voltage line and the third dam portion.

10. The display device according to claim 2, wherein, the pixel includes: a first electrode; an emission layer disposed on the first electrode; and a second electrode disposed on the emission layer, the second electrode is commonly disposed in a plurality of the pixels, and the second electrode extends toward the non-display area to overlap with a part of the third dam portion.

11. The display device according to claim 10 further includes spacers disposed on the pixel defining layer, wherein, the second dam portion includes a third layer located on the second layer of the second dam portion that includes the portion of the pixel defining layer, and the third layer and the spacers are made of the same material.

12. The display device according to claim 11, wherein, The height of the second dam portion is greater than the height of the first dam portion and the height of the third dam portion.

13. The display device according to claim 2, wherein The third dam portion, the first dam portion, and the second dam portion overlap the second power supply voltage line.

14. The display device according to claim 1, wherein, the first conductive layer and the third conductive layer are made of the same material, and the second conductive layer and the fourth conductive layer are made of the same material.

15. The display device according to claim 1 further includes a thin film encapsulation layer, which includes: a first inorganic encapsulation layer overlapping with the display area; an organic encapsulation layer located on the first inorganic encapsulation layer; and and a second inorganic encapsulation layer located on the organic encapsulation layer, wherein the thin film encapsulation layer overlaps the third dam portion and the first dam portion.

16. The display device according to claim 15, wherein, The first inorganic encapsulation layer and the second inorganic encapsulation layer are in direct contact with the edge of the second dam portion.

17. The display device according to claim 1, wherein, The first conductive layer is electrically connected to the second conductive layer through a first contact hole provided in the first organic layer.

18. The display device according to claim 1, wherein, The third conductive layer is electrically connected to the fourth conductive layer through a second contact hole provided in the first organic layer.

19. A display device includes: a substrate; a display area provided on the substrate and including a plurality of pixels; a non-display area adjacent to the display area; a first power supply voltage line provided in the non-display area and including: a first conductive layer; a first organic layer provided on the first conductive layer; and a second conductive layer provided on the first organic layer; a second power supply voltage line provided in the non-display area, the second power supply voltage line and the second conductive layer being made of the same material; a first dam portion surrounding the display area and disposed adjacent to the first power supply voltage line; a second dam portion disposed adjacent to the first dam portion; and a third dam portion disposed between the first power supply voltage line and the first dam portion, wherein the first organic layer has a concavo-convex pattern including at least one opening between the first power supply voltage line and the second dam portion.

20. The display device according to claim 19, wherein, The second power supply voltage line is disposed on the first organic layer along the concavo-convex pattern.

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