Semiconductor device

Abstract

A semiconductor device capable of being used as a memory device is disclosed. The memory device includes a plurality of memory cells, and each memory cell includes a first transistor and a second transistor. The first transistor is provided on a substrate including a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. A gate electrode of the first transistor and one of a source electrode and a drain electrode of the second transistor are electrically connected to each other. The extremely low off-state current of the second transistor allows data stored in the memory cell to be held for a long time even when power supply is not performed.

Description

[0001] This application is a divisional application filed again with respect to divisional application 201610082458.5. Divisional application 201610082458.5 is a divisional application of PCT international application number PCT / JP2010 / 068103, international application date October 7, 2010, application number 201080049673.6 which entered the Chinese national phase, and is entitled "Semiconductor Device". Technical Field

[0002] The invention disclosed herein relates to semiconductor devices using semiconductor elements, and methods for manufacturing semiconductor devices. Background Technology

[0003] Memory devices using semiconductor elements are broadly classified into two categories: volatile devices that lose stored data when power is cut off, and non-volatile devices that retain stored data even when power is not supplied.

[0004] A typical example of a volatile memory element is DRAM (Dynamic Random Access Memory). DRAM stores data by selecting transistors included in the memory element and storing charge in capacitors.

[0005] When data is read from DRAM, the charge in the capacitor is lost according to the principles described above; therefore, another write operation is required every time data is read. Furthermore, the transistors included in the storage element have leakage current, and charge flows into or out of the capacitor even when the transistor is not selected, resulting in a short data retention time. Therefore, another write operation (refresh operation) is necessary at predetermined intervals, making it difficult to sufficiently reduce power consumption. Moreover, since the stored data is lost when power is cut off, additional storage elements made of magnetic or optical materials are required to maintain data for a longer period.

[0006] Another example of volatile storage elements is SRAM (Static Random Access Memory). SRAM retains stored data using circuitry such as flip-flops, thus eliminating the need for refresh operations. This means SRAM has advantages over DRAM. However, the cost per unit storage capacity increases due to the use of circuitry such as flip-flops. Furthermore, as in DRAM, the data stored in SRAM is lost when power is cut off.

[0007] A typical example of a non-volatile memory element is flash memory. Flash memory includes a floating gate between the gate electrode and the channel formation region in a transistor, and stores data by holding the charge in the floating gate. Therefore, the advantage of flash memory is that the data retention time is extremely long (almost permanent), and it does not require the refresh operation that is necessary in volatile memory devices (see, for example, Patent Document 1).

[0008] However, the gate insulation layer included in the memory element degrades due to the tunneling current generated during writing, causing the memory element to cease functioning after multiple write operations. To avoid this problem, methods such as compensating for the number of write operations on the memory element are employed. However, this requires additional complex auxiliary circuitry to implement. Furthermore, this method does not address the fundamental issue of lifespan. In other words, flash memory is unsuitable for applications where data is frequently rewritten.

[0009] In addition, high voltage is necessary for injecting or removing charge into the floating gate. Furthermore, it takes a relatively long time to inject or remove charge, and it is not easy to perform write and erase operations at higher speeds.

[0010] [References]

[0011] Patent Document 1: Japanese Patent Application Publication No. S57-105889 Summary of the Invention

[0012] In view of the above problems, an embodiment of the invention disclosed herein aims to provide a semiconductor device with a novel structure in which stored data can be retained even when no power is supplied, and in which there is no limit to the number of writes.

[0013] One embodiment of the present invention is a semiconductor device having a layered structure of transistors formed using oxide semiconductors and transistors formed using non-oxide semiconductor materials. For example, the following structure may be adopted.

[0014] An embodiment of the present invention is a semiconductor device comprising: a first line (source line); a second line (bit line); a third line (first signal line); a fourth line (second signal line); a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is disposed on a substrate comprising a semiconductor material. The second transistor comprises an oxide semiconductor layer. The first gate electrode is electrically connected to one of the second source electrode and the second drain electrode. The first line (source line) is electrically connected to the first source electrode. The second line (bit line) is electrically connected to the first drain electrode. The third line (first signal line) is electrically connected to the other of the second source electrode and the second drain electrode. The fourth line (second signal line) is electrically connected to the second gate electrode.

[0015] In the above structure, the first transistor includes a channel forming region disposed on a substrate containing semiconductor material; an impurity region disposed to clamp the channel forming region; a first gate insulating layer on the channel forming region; a first gate electrode on the first gate insulating layer; and a first source electrode and a first drain electrode electrically connected to the impurity region.

[0016] In the above structure, the second transistor includes a second gate electrode on a substrate containing a semiconductor material; a second gate insulating layer on the second gate electrode; an oxide semiconductor layer on the second gate insulating layer; and a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer.

[0017] In the above structure, the substrate containing the semiconductor material is preferably a single-crystal semiconductor substrate or an SOI substrate. Specifically, the semiconductor material is preferably silicon.

[0018] In the above structure, the oxide semiconductor layer preferably comprises an In-Ga-Zn-O based oxide semiconductor material. Specifically, the oxide semiconductor layer preferably comprises In2Ga2ZnO7 crystal. Furthermore, the hydrogen concentration of the oxide semiconductor layer is preferably less than or equal to 5 × 10⁻⁶. 19 atoms / cm 3 The cutoff current of the second transistor is preferably less than or equal to 1 × 10⁻⁶. -13 A, more preferably, is less than or equal to 1×10 -20 A.

[0019] In the above structure, the second transistor can be disposed in the region overlapping with the first transistor.

[0020] Note that in this specification, terms such as "above" or "below" do not necessarily mean that a component is placed directly on or below another component. For example, the statement "first gate electrode on the gate insulating layer" does not exclude the possibility that a component is placed between the gate insulating layer and the gate electrode. Furthermore, terms such as "above" and "below" are used for convenience only and may include cases where the positional relationship of the components is reversed, unless otherwise specified.

[0021] Additionally, in this specification, terms such as “electrode” or “wire” do not limit the function of the components. For example, “electrode” is sometimes used as part of a “wire”, and vice versa. Furthermore, the terms “electrode” or “wire” can include cases where multiple “electrodes” or “wires” are formed in an integrated manner.

[0022] For example, when using transistors of opposite polarity, or when changing the direction of current flow during circuit operation, the functions of "source" and "drain" can sometimes be substituted for each other. Therefore, in this specification and other documents, the terms "source" and "drain" are used interchangeably.

[0023] It should be noted that in this specification, the term "electrical connection" includes the case where components are connected through an object having any electrical function. There is no specific limitation on the object having any electrical function, as long as it is possible to transmit and receive electrical signals between the components connected through that object.

[0024] Examples of objects with any electrical function are switching elements such as transistors, resistors, inductors, capacitors, and elements with various functions, as well as electrodes and wires.

[0025] Generally, the term "SOI substrate" refers to a substrate in which a silicon semiconductor layer is disposed on an insulating surface. In this specification, the term "SOI substrate" also includes substrates in which a semiconductor layer formed using materials other than silicon is disposed on an insulating surface. That is, the semiconductor layer included in "SOI substrate" is not limited to a silicon semiconductor layer. The substrate in "SOI substrate" is not limited to semiconductor substrates such as silicon wafers, and can be a non-semiconductor substrate such as a glass substrate, quartz substrate, sapphire substrate, or metal substrate. In other words, "SOI substrate" also includes conductive substrates with insulating surfaces or insulating substrates with layers formed of semiconductor materials. Furthermore, in this specification, the term "semiconductor substrate" refers not only to substrates formed using only semiconductor materials, but also to all substrates containing semiconductor materials. That is, in this specification, "SOI substrate" is also included within the scope of "semiconductor substrate."

[0026] One embodiment of the present invention provides a semiconductor device in which transistors made of materials other than oxide semiconductors are disposed at the bottom and transistors made of oxide semiconductors are disposed at the top.

[0027] Because transistors containing oxide semiconductors have extremely low cutoff current, stored data can be retained for a very long time. In other words, power consumption can be significantly reduced because refresh operations become unnecessary or can be performed at a very low frequency. Furthermore, stored data can be retained for extended periods even when no power is supplied.

[0028] Furthermore, no high voltage is required to write data, and component degradation is negligible. Additionally, data is written by switching between the transistor's on and off states, making high-speed operation easily achievable. Moreover, since data can be rewritten by controlling the transistor's potential input, there is no need for data erasure operations, which is another advantage.

[0029] Since transistors containing materials other than oxide semiconductors can operate at higher speeds than transistors containing oxide semiconductors, stored data can be read out at high speeds by using such transistors.

[0030] Semiconductor devices with novel features can be realized by including both transistors containing materials other than oxide semiconductors and transistors containing oxide semiconductors. Brief description of the attached diagram

[0031] In the attached diagram:

[0032] Figure 1 It is a circuit diagram of a semiconductor device;

[0033] Figure 2A and 2B These are cross-sectional and planar views used to illustrate semiconductor devices;

[0034] Figures 3A to 3H This is a cross-sectional view showing the steps involved in manufacturing a semiconductor device;

[0035] Figure 4A to 4G This is a cross-sectional view showing the steps involved in manufacturing a semiconductor device;

[0036] Figures 5A to 5D This is a cross-sectional view showing the steps involved in manufacturing a semiconductor device;

[0037] Figure 6 It is a cross-sectional view of a semiconductor device;

[0038] Figure 7A and 7B Each shows a cross-sectional view of a semiconductor device;

[0039] Figure 8A and 8B Each shows a cross-sectional view of a semiconductor device;

[0040] Figure 9A and 9B Each shows a cross-sectional view of a semiconductor device;

[0041] Figures 10A to 10F Each device is shown;

[0042] Figure 11 It is a cross-sectional view of an inverted interleaved transistor containing oxide semiconductors;

[0043] Figure 12A and 12B yes Figure 11 The band structure diagram (schematic diagram) of section A-A' in the middle;

[0044] Figure 13A Showing a positive potential (+V) G The state is applied to the gate (GE1), and Figure 13B Showing negative potential (-V) G The state of being applied to the gate (GE1); and

[0045] Figure 14 Showing the work function of vacuum energy levels and metals And the relationship between electron affinity (χ) of oxide semiconductors;

[0046] Figure 15A and 15BIt is a circuit diagram of a semiconductor device;

[0047] Figure 16 It is a circuit diagram of a semiconductor device;

[0048] Figure 17A and 17B It is a circuit diagram of a semiconductor device;

[0049] Figures 18A to 18C It is a circuit diagram of a semiconductor device;

[0050] Figure 19 It is a circuit diagram of a semiconductor device;

[0051] Figure 20 It is a timing diagram used to illustrate the relationship between potentials;

[0052] Figure 21 It is a circuit diagram of a semiconductor device;

[0053] Figure 22A and 22B These are cross-sectional and planar views used to illustrate semiconductor devices;

[0054] Figures 23A to 23D This is a cross-sectional view showing a semiconductor device;

[0055] Figures 24A to 24C This is a cross-sectional view showing a semiconductor device;

[0056] Figure 25 It is a graph showing the characteristics of a transistor containing an oxide semiconductor;

[0057] Figure 26 It is a circuit diagram used to evaluate the characteristics of transistors containing oxide semiconductors;

[0058] Figure 27 It is a timing diagram used to evaluate the characteristics of transistors containing oxide semiconductors;

[0059] Figure 28 It is a graph showing the characteristics of a transistor containing an oxide semiconductor;

[0060] Figure 29 It is a graph showing the characteristics of a transistor containing an oxide semiconductor; and

[0061] Figure 30 It is a graph showing the characteristics of a transistor containing an oxide semiconductor.

[0062] Figure 31 This is a graph showing the evaluation results of the memory window width.

[0063] Explanation of reference numerals in the attached figures

[0064] 100: Substrate, 102: Protective layer, 104: Semiconductor region, 106: Device isolation insulating layer, 108: Gate insulating layer, 110: Gate electrode, 112: Insulating layer, 114: Impurity region, 116: Channel formation region, 118: Sidewall insulating layer, 120: High-concentration impurity region, 122: Metal layer, 124: Metal compound region, 126: Interlayer insulating layer, 128: Interlayer insulating layer, 130a: Source / drain electrode, 130b: Source / drain electrode, 130c: Electrode, 132: Insulating layer, 134: Conductive layer, 136a: Electrode, 136b: Electrode, 136c: Electrode, 136d: Gate electrode, 138: Gate insulating layer, 140: Oxide semiconductor layer, 142a: Source Electrode / drain electrode, 142b: source electrode / drain electrode, 144: protective insulating layer, 146: interlayer insulating layer, 148: conductive layer, 150a: electrode, 150b: electrode, 150c: electrode, 150d: electrode, 150e: electrode, 152: insulating layer, 154a: electrode, 154b: electrode, 154c: electrode, 154d: electrode, 160: transistor, 162: transistor, 164: capacitor, 200: substrate, 206: device isolation insulating layer, 208: gate insulating layer, 210: gate electrode, 216: channel formation region, 220: high concentration impurity region, 224: metal compound region, 225: interlayer insulating layer, 226: interlayer insulating layer, 228: interlayer insulating layer, 24 2a: Drain electrode, 242b: Drain electrode, 243a: Insulating layer, 243b: Insulating layer, 244: Oxide semiconductor layer, 246: Gate insulating layer, 248a: Gate electrode, 248b: Electrode, 250: Interlayer insulating layer, 252: Interlayer insulating layer, 254: Drain electrode, 256: Line, 260: Transistor, 262: Transistor, 264: Capacitor, 301: Main body, 302: Housing, 303: Display section, 304: Keyboard, 311: Main body, 312: Stylus, 313: Display section, 314: Operation button, 315: External interface, 320: E-book reader, 321: Housing, 323: Housing, 325: Display section, 327: Display section, 332: Power supply Switch step 333: Operation key, 335: Speaker, 337: Chain link, 340: Housing, 341: Housing, 342: Display panel, 343: Speaker, 344: Microphone, 345: Operation key, 346: Pointing device, 347: Camera lens, 348: External connection terminal, 349: Solar cell unit, 350: External storage slot, 361: Main body, 363: Eyepiece, 364: Operation switch, 365: Display part (8), 366: Battery, 367: Display part (A), 370: Television, 371: Housing, 373: Display part, 375: Stand, 377: Display part, 379: Operation key, 380: Remote control, 400: Storage unit, 800: Measurement system802: Capacitor, 802a: Capacitor, 802b: Capacitor, 802c: Capacitor, 804: Transistor, 805: Transistor, 806: Transistor, 808: Transistor, 1100: Memory cell, 1111: First driving circuit, 1112: Second driving circuit, 1113: Third driving circuit, 1114: Fourth driving circuit, 1200: Memory cell, 1211: First driving circuit, 1212: Second driving circuit, 1213: Third driving circuit, and 1214: Fourth driving circuit. Detailed Implementation

[0065] Examples of embodiments of the present invention will now be described with reference to the accompanying drawings. It should be noted that the present invention is not limited to the following description, and those skilled in the art will readily understand that the patterns and details disclosed herein can be modified in various ways without departing from the scope and spirit of the invention. Therefore, the present invention is not to be construed as limited to the embodiments included herein.

[0066] Note that, for ease of understanding, the positions, dimensions, and extents of the various structures shown in the accompanying drawings are not precisely represented in some cases. Therefore, embodiments of the present invention are not necessarily limited to the positions, dimensions, and extents disclosed in the accompanying drawings.

[0067] In this specification, ordinal numbers such as “first,” “second,” and “third” are used to avoid confusion between components, and these terms do not imply a limitation on the number of components.

[0068] (Example 1)

[0069] In this embodiment, reference will be made to Figure 1 , Figure 2A and 2B , Figures 3A to 3H , Figure 4A to 4G , Figures 5A to 5D , Figure 6 , Figure 7A and 7B , Figure 8A and 8B as well as Figure 9A and 9B This describes the structure and manufacturing method of a semiconductor device according to an embodiment of the invention disclosed herein.

[0070] <Circuit Structure of Semiconductor Devices>

[0071] Figure 1 An example of the circuit construction of a semiconductor device is shown. The semiconductor device includes a transistor 160 formed using a material other than oxide semiconductor (e.g., silicon) and a transistor 162 formed using oxide semiconductor. Note that in the following description, in some cases... Figure 1 The semiconductor device shown is called a memory cell.

[0072] Here, the gate electrode of transistor 160 is electrically connected to one of the source and drain electrodes of transistor 162. A first line (also called the source line SL) is electrically connected to the source electrode of transistor 160. A second line (also called the bit line BL) is electrically connected to the drain electrode of transistor 160. A third line (also called the first signal line) is electrically connected to the other of the source and drain electrodes of transistor 162. A fourth line (also called the second signal line) is electrically connected to the gate electrode of transistor 162.

[0073] Since the transistor 160, which incorporates materials other than oxide semiconductors, can operate at a higher speed than transistors containing oxide semiconductors, stored data can be read out at high speed using this transistor 160. Furthermore, the transistor 162, which incorporates oxide semiconductors, has an ultra-low cutoff current. For these reasons, the potential of the gate electrode of the transistor 160 can be maintained for an extremely long time by turning off the transistor 162. Additionally, short-channel effects do not occur in the transistor 162, which is another advantage.

[0074] Taking advantage of the ability to maintain the potential of the gate electrode, data can be written, held, and read in the following ways.

[0075] First, the description data is written and held. First, the potential of the fourth line is set to the potential that turns on transistor 162, and transistor 162 is turned on. Therefore, the potential of the third line is supplied to the gate electrode of transistor 160 (writing). Then, the potential of the fourth line is set to the potential that turns off transistor 162, and transistor 162 is turned off, thereby holding the potential of the gate electrode of transistor 160 (holding).

[0076] Because the cutoff current of transistor 162 is extremely low, the potential of the gate electrode of transistor 160 is maintained for a relatively long time. For example, when the potential of the gate electrode of transistor 160 is the potential that turns transistor 160 on, the on state of transistor 160 is maintained for a relatively long time. Furthermore, when the potential of the gate electrode of transistor 160 is the potential that turns transistor 160 off, the off state of transistor 160 is maintained for a relatively long time.

[0077] Next, the reading of the description data will be described. When a predetermined potential (low potential) is supplied to the first line while the transistor 160 is in the on or off state as described above, the potential of the second line changes depending on the on or off state of the transistor 160. For example, when the transistor 160 is on, the potential of the second line becomes lower under the influence of the potential of the first line. Conversely, when the transistor 160 is off, the potential of the second line does not change.

[0078] In this way, the potential of the second line is compared with a predetermined potential while the data is being held, and the data can be read from this point.

[0079] Next, the described data is rewritten. Data rewriting is performed in a similar manner to data writing and retention. That is, the potential of the fourth line is set to the potential that turns on transistor 162, and transistor 162 is turned on. This supplies the potential of the third line (the potential for the new data) to the gate electrode of transistor 160. Then, the potential of the fourth line is set to the potential that turns off transistor 162, and transistor 162 is turned off, thereby storing the new data.

[0080] In the semiconductor device according to the invention disclosed herein, data can be directly rewritten via another data write operation as described above. For this reason, the necessary erase operation on flash memory is eliminated, thereby preventing a decrease in operating speed caused by the erase operation. In other words, high-speed operation of the semiconductor device can be achieved.

[0081] Because the cutoff current of the oxide semiconductor transistor 162 used for writing is extremely low, the potential of the gate electrode of transistor 160 is maintained for a relatively long time. Therefore, for example, the refresh operation required by conventional DRAM may be unnecessary, or the frequency of refresh operations may be quite low (e.g., about once a month or once a year). Thus, the semiconductor device according to the disclosed invention essentially has the characteristics of a non-volatile memory device.

[0082] Furthermore, unlike conventional DRAM, data is not lost during data reading in the semiconductor device disclosed in this invention; therefore, data does not need to be rewritten in each read operation. As mentioned above, the data writing frequency can be significantly reduced compared to DRAM, resulting in a substantial reduction in power consumption.

[0083] Furthermore, for the semiconductor device according to the disclosed invention, data can be directly rewritten by overwriting new data onto the semiconductor device. Therefore, the erase operation necessary for flash memory and the like is eliminated, and the reduction in operating speed caused by the erase operation can be suppressed. In other words, high-speed operation of the semiconductor device can be achieved. Moreover, the high voltage required for writing and erasing data in conventional floating-gate transistors is not necessary; thus, the power consumption of the semiconductor device can be further reduced.

[0084] The semiconductor device according to the disclosed invention may include at least write transistors and read transistors; therefore, the area of ​​each memory cell can be sufficiently small compared to SRAM, which requires six transistors per memory cell. In other words, each semiconductor device can be arranged in a high density.

[0085] In conventional floating-gate transistors, charge travels through the gate insulating film (tunnel insulating film) during write operations, making degradation of the gate insulating film (tunnel insulating film) unavoidable. Conversely, in a memory cell according to an embodiment of the present invention, data is written via the switching operation of a write transistor; therefore, the degradation of the gate insulating film, which is typically considered a problem, can be ignored. This means that, in principle, there is no limit to the number of writes, and write endurance is very high. For example, even with 1×10 data writes... 9 The current-voltage characteristics will not degrade after 1 billion or more cycles.

[0086] Note that the field-effect mobility of the oxide semiconductor-containing transistor 162 used for writing is greater than or equal to 3 cm⁻¹ in the on-state. 2 / Vs and less than or equal to 250cm 2 / Vs, preferably greater than or equal to 5cm 2 / Vs and less than or equal to 200cm 2 / Vs, more preferably greater than or equal to 10cm 2 / Vs and less than or equal to 150cm 2 / Vs. Furthermore, the subthreshold swing (S-value) of the transistor containing oxide semiconductor is set to be less than or equal to 0.1V / dec. By using this transistor, the time required for data writing can be sufficiently short.

[0087] The channel length L of the oxide semiconductor-containing transistor 162 used for writing is preferably greater than or equal to 10 nm and less than or equal to 400 nm. With this channel size, various effects such as high-speed operation of the transistor, low power consumption, and high integration can be obtained.

[0088] Note that the transistor containing crystalline silicon is preferably used as the transistor 160 for reading. Specifically, in order to speed up the read operation, an n-channel transistor containing monocrystalline silicon is preferred. This monocrystalline silicon transistor can be formed using, for example, bulk silicon (so-called silicon wafer).

[0089] Note that the above description uses n-channel transistors; needless to say, p-channel transistors can be used instead of n-channel transistors.

[0090] <Planar and Cross-sectional Structures of Semiconductor Devices>

[0091] Figure 2A and 2B An example of the structure of a semiconductor device is shown. Figure 2A The cross-section of the semiconductor device is shown, while Figure 2B A plan view of a semiconductor device is shown. Here, Figure 2A Corresponding to along Figure 2BThe cross sections of lines A1-A2 and B1-B2 in the diagram. Figure 2A and 2B The semiconductor device shown includes a transistor 160 at the bottom, which contains a material other than oxide semiconductor, and a transistor 162 at the top, which contains oxide semiconductor. Note that transistors 160 and 162 are n-channel transistors; alternatively, p-channel transistors may be used. Specifically, it is easy to use a p-channel transistor as transistor 160.

[0092] The transistor 160 includes a channel formation region 116 disposed in a substrate 100 containing semiconductor material, an impurity region 114 and a high-concentration impurity region 120 disposed to clamp the channel formation region 116 (these two regions can be simply referred to as the impurity region), a gate insulating layer 108 disposed on the channel formation region 116, a gate electrode 110 disposed on the gate insulating layer 108, and a source electrode or drain electrode (hereinafter referred to as source electrode / drain electrode) 130a and source electrode / drain electrode 130b electrically connected to the impurity region 114.

[0093] A sidewall insulating layer 118 is disposed on the side surface of the gate electrode 110. As shown in the cross-sectional view, a high-concentration impurity region 120 is disposed in a region of the substrate 100 that does not overlap with the sidewall insulating layer 118. A metal compound region 124 is disposed on the high-concentration impurity region 120. An element isolation insulating layer 106 is disposed on the substrate 100 to surround the transistor 160. Interlayer insulating layers 126 and 128 are disposed to cover the transistor 160. Source / drain electrodes 130a and 130b are each electrically connected to the metal compound region 124 through openings formed in the interlayer insulating layers 126 and 128. That is, source / drain electrodes 130a and 130b are each electrically connected to the high-concentration impurity region 120 and the impurity region 114 through the metal compound region 124. An electrode 130c formed in a manner similar to that of source / drain electrodes 130a and 130b is electrically connected to the gate electrode 110.

[0094] Transistor 162 includes a gate electrode 136d disposed on an interlayer insulating layer 128, a gate insulating layer 138 disposed on the gate electrode 136d, an oxide semiconductor layer 140 disposed on the gate insulating layer 138, and a source electrode / drain electrode 142a and a source electrode / drain electrode 142b disposed on the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140.

[0095] Here, the gate electrode 136d is configured to be embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similar to the gate electrode 136d, electrodes 136a, 136b, and 136c are formed to contact the source / drain electrode 130a, source / drain electrode 130b, and electrode 130c, respectively.

[0096] A protective insulating layer 144 is disposed on the transistor 162, thereby contacting a portion of the oxide semiconductor layer 140. An interlayer insulating layer 146 is disposed on the protective insulating layer 144. Openings leading to the source / drain electrodes 142a and 142b are formed in the protective insulating layer 144 and the interlayer insulating layer 146, respectively. Electrodes 150d and 150e are formed to contact the source / drain electrodes 142a and 142b, respectively, through corresponding openings. Similar to electrodes 150d and 150e, electrodes 150a, 150b, and 150c are formed to contact electrodes 136a, 136b, and 136c, respectively, through openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146.

[0097] Here, the oxide semiconductor layer 140 is preferably a highly purified oxide semiconductor layer in which impurities such as hydrogen are sufficiently removed. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is less than or equal to 5 × 10⁻⁶. 19 atoms / cm 3 Preferably, it is less than or equal to 5 × 10 18 atoms / cm 3 More preferably, less than or equal to 5 × 10 17 atoms / cm 3 With a carrier concentration of approximately 1×10⁻⁶ 14 / cm 3 Compared to typical silicon wafers (silicon wafers with impurities such as trace amounts of phosphorus or boron), this extremely low hydrogen concentration results in a sufficiently low carrier concentration (e.g., less than 1 × 10⁻⁶). 12 / cm 3 or less than 1.45×10 10 / cm 3 By utilizing an oxide semiconductor that has been highly purified through sufficiently reducing hydrogen concentration to become intrinsic (type i) or essentially intrinsic (type i), a transistor 162 with significantly superior cutoff current characteristics can be obtained. For example, the cutoff current of transistor 162 at room temperature (25°C) (here, per unit channel width (1 μm)) is less than or equal to 10 zA / μm (1 zA (zepto amperes) is 1 × 10⁻⁶). -21 A), preferably less than or equal to 1 zA / μm. The cutoff current of transistor 162 at 85°C is less than or equal to 100 zA / μm (1×10⁻⁶). - 19 A / μm), preferably less than or equal to 10 μA / μm (1×10⁻⁶). -20(A / μm). By using an oxide semiconductor layer 140 that becomes intrinsic or essentially intrinsic by sufficiently reducing the hydrogen concentration, the cutoff current of the transistor 162 is reduced, thereby enabling a semiconductor device with a novel structure. Note that the hydrogen concentration in the oxide semiconductor layer 140 is measured by secondary ion mass spectrometry (SIMS).

[0098] An insulating layer 152 is disposed on the interlayer insulating layer 146. Electrodes 154a, 154b, 154c, and 154d are disposed and embedded in the insulating layer 152. Electrode 154a is in contact with electrode 150a. Electrode 154b is in contact with electrode 150b. Electrode 154c is in contact with electrodes 150c and 150d. Electrode 154d is in contact with electrode 150e.

[0099] That is, in Figure 2A and 2B In the semiconductor device shown, the gate electrode 110 of transistor 160 and the source / drain electrode 142a of transistor 162 are electrically connected via electrodes 130c, 136c, 150c, 154c and 150d.

[0100] Methods for Manufacturing Semiconductor Devices

[0101] Next, examples of methods for manufacturing semiconductor devices will be described. First, the following will refer to... Figures 3A to 3H The method for manufacturing the lower transistor 160 is described, and then references are made. Figure 4A to 4G and Figures 5A to 5D A method for manufacturing the upper transistor 162 is described.

[0102] <Method for manufacturing lower transistors>

[0103] First, a substrate 100 containing semiconductor material is prepared (see...). Figure 3A The substrate 100 containing semiconductor materials can be made of single-crystal semiconductor substrates or polycrystalline semiconductor substrates made of silicon, silicon carbide, etc., compound semiconductor substrates made of silicon germanium, SOI substrates, etc. Here, an example of using a single-crystal silicon substrate as the substrate 100 containing semiconductor materials is described.

[0104] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an insulating layer for components (see [reference]). Figure 3AFor example, an insulating layer formed using silicon oxide, silicon nitride, silicon oxynitride, etc., can be used as the protective layer 102. Note that before or after this step, impurity elements imparting n-type conductivity or p-type conductivity can be added to the substrate 100 to control the threshold voltage of the transistor. When the semiconductor material contained in the substrate 100 is silicon, phosphorus, arsenic, etc., can be used as impurities imparting n-type conductivity. Boron, aluminum, gallium, etc., can be used as impurities imparting p-type conductivity.

[0105] Next, by using the protective layer 102 as a mask, etching is performed to remove portions of the substrate 100 in areas not covered by the protective layer 102 (i.e., exposed areas). This forms isolated semiconductor regions 104 (see [link to documentation]). Figure 3B Dry etching is preferred for etching, but wet etching is also possible. The etching gas and etchant can be appropriately selected depending on the material of the layer to be etched.

[0106] Then, an insulating layer is formed to cover the semiconductor region 104, and the insulating layer in the region overlapping with the semiconductor region 104 is selectively removed, thereby forming a device isolation insulating layer 106 (see [link]). Figure 3B An insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. Etching and polishing processes (such as CMP) can be used as methods for removing the insulating layer. Note that the protective layer 102 is removed after the semiconductor region 104 is formed or after the element isolation insulating layer 106 is formed.

[0107] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer.

[0108] Since the insulating layer is later used as a gate insulating layer, it preferably has a monolayer or layered structure using a film comprising silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc., formed by CVD, sputtering, or the like. Alternatively, the insulating layer can be formed by oxidizing or nitriding the surface of the semiconductor region 104 through high-density plasma processing or thermal oxidation processing. For example, high-density plasma processing can be performed using rare gases such as He, Ar, Kr, or Xe, and a mixture of gases such as oxygen, nitrogen oxides, ammonia, nitrogen, or hydrogen. There is no specific limitation on the thickness of the insulating layer; for example, the thickness of the insulating layer can be greater than or equal to 1 nm and less than or equal to 100 nm.

[0109] Metallic materials such as aluminum, copper, titanium, tantalum, or tungsten can be used to form the layer containing the conductive material. Semiconductor materials such as polycrystalline silicon containing the conductive material can be used to form the layer containing the conductive material. There are no specific limitations on the method used to form the layer containing the conductive material, and various film formation methods can be employed, such as vapor deposition, CVD, sputtering, or spin coating. Note that this embodiment illustrates an example in which a metallic material is used to form the layer containing the conductive material.

[0110] Subsequently, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 and the gate electrode 110 (see [reference]). Figure 3C ).

[0111] Next, an insulating layer 112 is formed covering the gate electrode 110 (see...). Figure 3C Then, by adding phosphorus (P), arsenic (As), etc. to the semiconductor region 104, an impurity region 114 with a shallow junction depth relative to the substrate 100 is formed (see...). Figure 3C Note that phosphorus or arsenic is added here to form an n-channel transistor; in the case of forming a p-channel transistor, impurity elements such as boron (B) or aluminum (Al) may be added. By forming impurity region 114, a channel formation region 116 is formed in the semiconductor region 104 under the gate insulating layer 108 (see...). Figure 3C Here, the concentration of the added impurities can be appropriately set; this concentration is preferably increased when the size of the semiconductor device is greatly reduced. Here, the step of forming the impurity region 114 is adopted after the formation of the insulating layer 112; or, the insulating layer 112 can be formed after the formation of the impurity region 114.

[0112] Next, a sidewall insulating layer 118 is formed (see...) Figure 3D An insulating layer is formed to cover the insulating layer 112, and then the insulating layer is subjected to highly anisotropic etching, thereby forming the sidewall insulating layer 118 in a self-aligned manner. At this time, it is preferable to partially etch the insulating layer 112 to expose the top surface of the gate electrode 110 and the top surface of the impurity region 114.

[0113] Next, an insulating layer is formed to cover the gate electrode 110, the impurity region 114, the sidewall insulating layer 118, etc. Then, phosphorus (P), arsenic (As), etc., are added to the region where the insulating layer contacts the impurity region 114, thereby forming a high-concentration impurity region 120 (see...). Figure 3E Next, the insulating layer is removed, and a metal layer 122 is formed to cover the gate electrode 110, the sidewall insulating layer 118, the high-concentration impurity region 120, etc. (see...) Figure 3EThe metal layer 122 can be formed using various film formation methods such as vacuum evaporation, sputtering, or spin coating. The metal layer 122 is preferably formed using a metallic material that reacts with the semiconductor material included in the semiconductor region 104 to form a low-resistance metal compound. Examples of such metallic materials are titanium, tantalum, tungsten, nickel, cobalt, and platinum.

[0114] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. This forms a metal compound region 124 in contact with the high-concentration impurity region 120 (see [link]). Figure 3F Note that when polysilicon or the like is used to form the gate electrode 110, a metal compound region is also formed in the region where the gate electrode 110 contacts the metal layer 122.

[0115] For example, irradiation with a flash lamp can be used as a heat treatment. While another heat treatment method can be used, it is preferred to use a method that allows for a very short heat treatment time, thereby improving the controllability of the chemical reaction during the formation of the metal compound. Note that the metal compound region is formed through the reaction of the metallic and semiconductor materials and has sufficiently high conductivity. The formation of the metal compound region can appropriately reduce resistance and improve device characteristics. Note that after forming the metal compound region 124, the metal layer 122 is removed.

[0116] Then, interlayer insulation layer 126 and interlayer insulation layer 128 are formed to cover the component formed in the above steps (see...). Figure 3G Interlayer insulating layers 126 and 128 can be formed using materials containing inorganic insulating materials (such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide). Alternatively, organic insulating materials such as polyimide or acrylic resin can be used to form interlayer insulating layers 126 and 128. Note that a double-layer structure of interlayer insulating layers 126 and 128 is used here; however, the structure of the interlayer insulating layers is not limited to this structure. After forming interlayer insulating layer 128, the surface of interlayer insulating layer 128 is preferably planarized by CMP, etching, or the like.

[0117] Then, openings leading to the metal compound region 124 are formed in the interlayer insulating layers 126 and 128, and source / drain electrodes 130a and 130b are formed in the openings (see...). Figure 3H The source / drain electrodes 130a and 130b can be formed, for example, by forming a conductive layer in the region including the opening by PVD, CVD, etc., and then removing a portion of the conductive layer by etching, CMP, etc.

[0118] Note that when forming the source / drain electrodes 130a and 130b by removing a portion of the conductive layer, this process is preferably performed to planarize the surface. For example, when a titanium or titanium nitride film is formed in the region including the opening, and then a tungsten film is formed to embed into the opening, excess tungsten, titanium, titanium nitride, etc., can be removed, and the surface planarity can be improved by subsequent CMP. Planarizing the surfaces including the source / drain electrodes 130a and 130b in this way allows for the smooth formation of electrodes, wiring, insulating layers, semiconductor layers, etc., in subsequent steps.

[0119] Note that only the source / drain electrodes 130a and 130b in contact with the metal compound region 124 are shown here; however, electrodes in contact with the gate electrode 110 may also be formed in this step (e.g., Figure 2A Electrode 130c, etc. There are no specific limitations on the materials used for the source / drain electrodes 130a and 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium can be used.

[0120] Through the above steps, a transistor 160 using a substrate 100 containing semiconductor material is formed. Note that electrodes, wiring, insulating layers, etc., may be further formed after the above steps. When the wiring has a multilayer structure including interlayer insulating layers and conductive layers, a highly integrated semiconductor device can be provided.

[0121] <Method for manufacturing upper transistors>

[0122] Next, refer to Figures 4A to 4G as well as Figures 5A to 5D This describes the steps used to manufacture the transistor 162 on the interlayer insulating layer 128. Note that... Figures 4A to 4G as well as Figures 5A to 5D The steps for manufacturing electrodes, transistors 162, etc. on the interlayer insulating layer 128 are shown; therefore, transistors 160, etc., placed under transistors 162 are omitted.

[0123] First, an insulating layer 132 is formed on the interlayer insulating layer 128, the source / drain electrodes 130a and 130b, and the electrode 130c (see [reference]). Figure 4A The insulating layer 132 can be formed by PVD, CVD, or other methods. Materials including inorganic insulating materials (such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide) can be used to form the insulating layer 132.

[0124] Next, openings are formed in the insulating layer 132 to reach the source / drain electrodes 130a and 130b and the electrode 130c. At the same time, openings are also formed in the region where the gate electrode 136d will be formed later. Then, a conductive layer 134 is formed to embed these openings (see [link to documentation]). Figure 4B These openings can be formed by methods such as etching using a mask. The mask can be formed by methods such as exposure using a photomask. Wet etching or dry etching can be used as etching; dry etching is preferred for microfabrication. The conductive layer 134 can be formed by film formation methods such as PVD or CVD. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or alloys or compounds of any of these materials (e.g., nitrides) can be used to form the conductive layer 134.

[0125] Specifically, it is possible to employ a method in which a titanium thin film is formed in the region including the opening by PVD and a titanium nitride thin film is formed by CVD, followed by the formation of a tungsten film to embed within the opening. Here, the titanium film formed by PVD reduces the oxide film formed on the surface of the lower electrode (here, source / drain electrodes 130a and 130b, electrode 130c, etc.), thereby reducing the contact resistance with the lower electrode. The titanium nitride film formed after the titanium film has a barrier function to prevent the diffusion of conductive materials. After forming the barrier film of titanium, titanium nitride, etc., a copper film can be formed by electroplating.

[0126] After the conductive layer 134 is formed, a portion of the conductive layer 134 is removed by etching, CMP, etc., thereby exposing the insulating layer 132, and electrodes 136a, 136b, and 136c, as well as the gate electrode 136d (see [link to documentation]). Figure 4C Note that when forming electrodes 136a, 136b, and 136c, and gate electrode 136d, by removing a portion of conductive layer 134, this process is preferably performed to planarize these surfaces. Planarizing the surfaces of insulating layer 132, electrodes 136a, 136b, and 136c, and gate electrode 136d in this way allows for the smooth formation of electrodes, wiring, insulating layers, semiconductor layers, etc., in subsequent steps.

[0127] Next, a gate insulating layer 138 is formed to cover the insulating layer 132, electrodes 136a, 136b and 136c, and gate electrode 136d (see [link]). Figure 4DThe gate insulating layer 138 can be formed by CVD, sputtering, or the like. Silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, etc., are preferably used to form the gate insulating layer 138. Note that the gate insulating layer 138 can have a single-layer structure or a layered structure. For example, the gate insulating layer 138 made of silicon oxynitride can be formed by plasma CVD using silane (SiH4), oxygen, and nitrogen as source gases. There is no specific limitation on the thickness of the gate insulating layer 138; for example, the thickness of the gate insulating layer 138 can be greater than or equal to 10 nm and less than or equal to 500 nm. In the case of a layered structure, for example, the gate insulating layer 138 is preferably a stack of a first gate insulating layer with a thickness greater than or equal to 50 nm and less than or equal to 200 nm, and a second gate insulating layer on the first gate insulating layer with a thickness greater than or equal to 5 nm and less than or equal to 300 nm.

[0128] Note that oxide semiconductors that have become intrinsic or essentially intrinsic through impurity removal (highly purified oxide semiconductors) are quite susceptible to the effects of interface energy levels and interface charges; therefore, when such oxide semiconductors are used as oxide semiconductor layers, the interface with the gate insulating layer is important. In other words, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer needs to be of high quality.

[0129] For example, the gate insulating layer 138 is preferably formed using a high-density plasma CVD method with microwaves (2.45 GHz) because the gate insulating layer 238 can be dense and has high breakdown voltage and high quality. When the highly purified oxide semiconductor layer and the high-quality gate insulating layer are in contact with each other, the interface energy level can be reduced, and the interface characteristics can be good.

[0130] Needless to say, even when using a highly purified oxide semiconductor layer, alternative methods such as sputtering or plasma CVD can be employed, as long as a high-quality insulating layer can be formed as the gate insulating layer. Furthermore, it is possible to use an insulating layer whose interface quality and characteristics with the oxide semiconductor layer can be improved through heat treatment performed after the insulating layer is formed. In any case, the gate insulating layer 138 is formed as an insulating layer with good film quality and which reduces the interfacial energy level density with the oxide semiconductor layer to form a good interface.

[0131] If an oxide semiconductor contains impurities, dangling bonds are created between the impurities and the main components of the oxide semiconductor through stress cleavage, such as high electric fields or high temperatures, which causes a shift in the threshold voltage (Vth).

[0132] As described above, impurities (especially hydrogen and water) in the oxide semiconductor are reduced to a minimum, and the interface characteristics between the oxide semiconductor and the gate insulating layer are made good, thereby obtaining a transistor that is stable against stresses such as high electric fields and high temperatures.

[0133] Next, an oxide semiconductor layer is formed on the gate insulating layer 138 and processed by methods such as etching using a mask to form an island-shaped oxide semiconductor layer 140 (see [link to documentation]). Figure 4E ).

[0134] As the oxide semiconductor layer, In-Ga-Zn-O based oxide semiconductor layers, In-Sn-Zn-O based oxide semiconductor layers, In-Al-Zn-O based oxide semiconductor layers, Sn-Ga-Zn-O based oxide semiconductor layers, Al-Ga-Zn-O based oxide semiconductor layers, Sn-Al-Zn-O based oxide semiconductor layers, In-Zn-O based oxide semiconductor layers, Sn-Zn-O based oxide semiconductor layers, Al-Zn-O based oxide semiconductor layers, In-O based oxide semiconductor layers, Sn-O based oxide semiconductor layers, or Zn-O based oxide semiconductor layers are preferably used. Particularly preferred are these oxide semiconductor layers existing in an amorphous state. In this embodiment, an amorphous oxide semiconductor layer is formed as the oxide semiconductor layer using a sputtering method with a target for depositing In-Ga-Zn-O based oxide semiconductors. Note that since the crystallization of the amorphous oxide semiconductor layer can be suppressed by adding silicon, an oxide semiconductor layer can be formed, for example, using a target containing more than or equal to 2 wt% and less than or equal to 10 wt% SiO2.

[0135] For example, an oxide semiconductor deposition target containing zinc oxide as its main component can be used as a target for forming an oxide semiconductor layer by sputtering. Furthermore, for example, a target for depositing an oxide semiconductor containing In, Ga, and Zn can be used (In₂O₃:Ga₂O₃:ZnO composition ratio = 1:1:1 [molar ratio]). Alternatively, a target for depositing an oxide semiconductor containing In, Ga, and Zn can be used (In₂O₃:Ga₂O₃:ZnO composition ratio = 1:1:2 [molar ratio], or In₂O₃:Ga₂O₃:ZnO composition ratio = 1:1:4 [molar ratio]). The fill rate of the target for depositing the oxide semiconductor is greater than or equal to 90% and less than or equal to 100%, preferably greater than or equal to 95% (e.g., 99.9%). A dense oxide semiconductor layer is formed by using a target with a high fill rate for depositing oxide semiconductors.

[0136] The atmosphere in which the oxide semiconductor layer is formed is preferably a rare gas (usually argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (usually argon) and oxygen. Specifically, a high-purity gas is preferably used, for example, from which impurities such as hydrogen, water, compounds having hydroxyl groups, or hydrides have been removed to achieve a concentration of a few ppm (preferably a few ppb).

[0137] During the formation of the oxide semiconductor layer, the substrate is held in a processing chamber under reduced pressure, and the substrate temperature is set to greater than or equal to 100°C and less than or equal to 600°C, preferably greater than or equal to 200°C and less than or equal to 400°C. The oxide semiconductor layer is formed while the substrate is heated, thereby reducing the impurity concentration of the oxide semiconductor layer. Furthermore, damage to the oxide semiconductor layer caused by sputtering is reduced. Then, sputtering gas, after removing hydrogen and water, is introduced into the processing chamber where residual moisture is being removed, and the oxide semiconductor layer is formed using a metal oxide as a target. A trapping vacuum pump is preferably used to remove residual moisture in the processing chamber. For example, a cryogenic pump, an ion pump, or a titanium sublimation pump can be used. The exhaust unit can be a turbopump equipped with a cold trap. In the deposition chamber where the cryogenic pump exhausts the gas, hydrogen atoms and compounds containing hydrogen atoms (such as H₂O) are removed in addition to compounds containing carbon atoms, thereby reducing the impurity concentration of the oxide semiconductor layer formed in the deposition chamber.

[0138] The oxide semiconductor layer can be formed under conditions such as: a distance of 100 mm between the substrate and the target; a pressure of 0.6 Pa; a direct current (DC) power supply of 0.5 kW; and an oxygen atmosphere (oxygen flow rate of 100%). Note that a pulsed DC power supply is preferred because it reduces powder material (also known as particles or dust) generated during film deposition, and the thickness distribution can be smaller. The thickness of the oxide semiconductor layer is preferably greater than or equal to 2 nm and less than or equal to 200 nm, and more preferably greater than or equal to 5 nm and less than or equal to 30 nm. Note that the appropriate thickness varies depending on the oxide semiconductor material, and the thickness is appropriately set according to the material to be used.

[0139] Note that before forming the oxide semiconductor layer by sputtering, it is preferable to remove dust from the surface of the gate insulating layer 138 by introducing argon gas and generating plasma through backsputtering. Here, unlike normal sputtering where ions collide with the sputtering target, backsputtering is a method of modifying the surface by colliding ions with the surface to be treated. An example of a method for causing ions to collide with the surface to be treated is to apply a high-frequency voltage to the surface in an argon atmosphere to generate plasma near the substrate. Note that nitrogen, helium, oxygen, etc., can be used instead of an argon atmosphere.

[0140] Dry etching or wet etching can be used as the etching method for oxide semiconductor layers. Needless to say, dry etching and wet etching can be used in combination. The etching conditions (e.g., etching gas or etching solution, etching time, and temperature) are appropriately set according to the material, so that the oxide semiconductor layer can be etched into the desired shape.

[0141] Examples of etching gases used in dry etching include chlorine-containing gases (such as chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), or carbon tetrachloride (CCl4)). Additionally, fluorine-containing gases (such as carbon tetrafluoride (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), or trifluoromethane (CHF3), hydrogen bromide (HBr), oxygen (O2), and any of these gases with added rare gases such as helium (He) or argon (Ar) are also acceptable.

[0142] Parallel plate RIE (reactive ion etching) or ICP (inductively coupled plasma) etching can be used as dry etching methods. In order to etch the oxide semiconductor layer into the desired shape, the etching conditions (e.g., the amount of electrical power applied to the coiled electrode, the amount of electrical power applied to the electrode on the substrate side, and the electrode temperature on the substrate side) are appropriately set.

[0143] A mixture of phosphoric acid, acetic acid, and nitric acid can be used as an etchant for wet etching. Etching agents such as ITO07N (manufactured by KANTO CHEMICAL CO.,INC.) can also be used.

[0144] Then, a first heat treatment is preferably performed on the oxide semiconductor layer. This first heat treatment can be used to dehydrate or dehydrogenate the oxide semiconductor layer. The temperature of the first heat treatment is higher than or equal to 300°C and lower than or equal to 750°C, preferably higher than or equal to 400°C and lower than the strain point of the substrate. For example, the substrate is introduced into an electric furnace using a resistance heating element, and the oxide semiconductor layer 140 is heat-treated at 450°C in a nitrogen atmosphere for 1 hour. The oxide semiconductor layer 140 is not exposed to air during the heat treatment, thereby preventing the ingress of water and hydrogen.

[0145] Heat treatment apparatus is not limited to electric furnaces and can also be an apparatus for heating objects through heat conduction or thermal radiation from a medium such as a heated gas. For example, rapid thermal annealing (RTA) apparatuses such as gas rapid thermal annealing (GRTA) apparatuses or lamp rapid thermal annealing (LRTA) apparatuses can be used. An LRTA apparatus is an apparatus for heating the object to be treated by light (electromagnetic wave) radiation emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA apparatus is an apparatus for performing heat treatment using a high-temperature gas. An inert gas (e.g., nitrogen or a rare gas such as argon) that does not react with the object during heat treatment can be used as the gas.

[0146] For example, as a first heat treatment, the GRTA process can be performed as follows: The substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C for several minutes, and then removed from the inert gas. The GRTA process achieves a short-duration high-temperature heat treatment. Furthermore, the GRTA process can be used even when the temperature exceeds the substrate's strain point because it is a short-duration heat treatment.

[0147] Note that the first heat treatment is preferably carried out in an atmosphere containing nitrogen or a rare gas (e.g., helium, neon, or argon) as its main component and free from water, hydrogen, etc. For example, the purity of the nitrogen or rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is greater than or equal to 6N (99.9999%), preferably greater than or equal to 7N (99.99999%) (i.e., the impurity concentration is less than or equal to 1 ppm, preferably less than or equal to 0.1 ppm).

[0148] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may sometimes be crystallized into microcrystalline or polycrystalline forms. For example, the oxide semiconductor layer may sometimes become a microcrystalline oxide semiconductor layer with a crystallinity greater than or equal to 90% or greater than or equal to 80%. Furthermore, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be an amorphous oxide semiconductor layer that does not contain crystalline components.

[0149] In addition, oxide semiconductor layers sometimes become layers in which microcrystals (with a particle size greater than or equal to 1 nm and less than or equal to 20 nm, typically greater than or equal to 2 nm and less than or equal to 4 nm) are mixed into amorphous oxide semiconductors (e.g., the surface of oxide semiconductor layers).

[0150] The electrical properties of an oxide semiconductor layer can be altered by aligning microcrystals in the amorphous regions of the oxide semiconductor layer. For example, when forming an oxide semiconductor layer using a target for depositing In-Ga-Zn-O based oxide semiconductors, the electrical properties of the oxide semiconductor layer can be altered by forming microcrystal portions in which In2Ga2ZnO7 grains with electrical anisotropy are aligned.

[0151] More specifically, for example, when the grains are arranged such that the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer, the conductivity in the direction parallel to the surface of the oxide semiconductor layer can be improved, and the insulation properties in the direction perpendicular to the surface of the oxide semiconductor layer can be improved. Furthermore, such microcrystalline portions have the function of suppressing impurities such as water or hydrogen from entering the oxide semiconductor layer.

[0152] Note that the oxide semiconductor layer, including the microcrystalline portion, can be formed by heating the oxide semiconductor layer using the GRTA process. Furthermore, the oxide semiconductor layer can be more preferably formed using a sputtering target in which the amount of Zn is less than the amount of In or Ga.

[0153] A first heat treatment of the oxide semiconductor layer 140 can be performed on the oxide semiconductor layer 140 before it has been processed into an island-shaped oxide semiconductor layer 140. In this case, after the first heat treatment, the substrate is removed from the heating device and a photolithography step is performed.

[0154] Note that the first heat treatment may be referred to as a dehydration treatment, dehydrogenation treatment, etc., due to its dehydration or dehydrogenation effect on the oxide semiconductor layer 140. For example, this dehydration treatment or dehydrogenation treatment may be performed after the oxide semiconductor layer is formed, after the source and drain electrodes are stacked on the oxide semiconductor layer 140, or after a protective insulating layer is formed on the source and drain electrodes. This dehydration treatment or dehydrogenation treatment may be performed once or multiple times.

[0155] Next, the source / drain electrode 142a and the source / drain electrode 142b are formed to contact the oxide semiconductor layer 140 (see [reference]). Figure 4F The source / drain electrodes 142a and 142b can be formed by forming a conductive layer to cover the oxide semiconductor layer 140, and then selectively etching the conductive layer.

[0156] The conductive layer can be formed by PVD methods such as sputtering or CVD methods such as plasma CVD. As materials for the conductive layer, elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten can be used; alloys containing any of these elements as components, etc. Furthermore, one or more materials selected from manganese, magnesium, zirconium, beryllium, or thorium can be used. Aluminum can be used in combination with one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. The conductive layer can have a single-layer structure or a layered structure containing two or more layers. For example, the conductive layer can have a single-layer structure containing a silicon-aluminum film, a double-layer structure in which a titanium film is stacked on an aluminum film, or a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order.

[0157] Here, ultraviolet light, KrF laser, or ArF laser is preferably used for exposure when forming a mask for etching.

[0158] The channel length (L) of the transistor is determined based on the distance between the lower ends of the source / drain electrodes 142a and 142b. Note that for exposures with a channel length (L) less than 25 nm, far-ultraviolet light with wavelengths ranging from a few nanometers to several hundred nanometers is used to perform the mask formation. Exposure with far-ultraviolet light offers higher resolution and a greater depth of focus. For these reasons, the channel length (L) of the subsequently formed transistor can range from 10 nm to 1000 nm, and the circuit can operate at higher speeds. Furthermore, the cutoff current is extremely low, preventing increased power consumption.

[0159] The materials and etching conditions of the conductive layer and the oxide semiconductor layer 140 are appropriately adjusted so that the oxide semiconductor layer 140 is not removed during the etching of the conductive layer. Note that in some cases, the oxide semiconductor layer 140 is partially etched in the etching step depending on the materials and etching conditions, and thus has a groove portion (recessed portion).

[0160] An oxide conductive layer can be formed between the oxide semiconductor layer 140 and the source / drain electrode 142a, and between the oxide semiconductor layer 140 and the source / drain electrode 142b. The oxide conductive layer and the metal layer used to form the source / drain electrodes 142a and 142b can be formed continuously. The oxide conductive layer can serve as the source and drain regions. This placement of the oxide conductive layer reduces the resistance of the source and drain regions, thereby enabling the transistor to operate at high speed.

[0161] To reduce the number of masks used and the number of steps, the etching step can be performed using a resist mask formed by using a multi-tone mask, which is an exposure mask that transmits light and thus has multiple intensities. The resist mask formed by using a multi-tone mask has multiple thicknesses (with a stepped shape) and can also have its shape changed by ashing; therefore, the resist mask can be used in multiple etching steps to process different patterns. That is, a resist mask corresponding to at least two different patterns can be formed by using a multi-tone mask. This reduces the number of exposure masks and also reduces the number of corresponding photolithography steps, thereby simplifying the process.

[0162] Note that plasma treatment is preferably performed after the above steps using a gas such as N2O, N2, or Ar. This plasma treatment removes water and other substances adhering to the exposed surface of the oxide semiconductor layer. A mixture of oxygen and argon can be used to perform the plasma treatment.

[0163] Next, the protective insulating layer 144 is formed to contact a portion of the oxide semiconductor layer 140 without being exposed to air (see [link]). Figure 4G ).

[0164] The protective insulating layer 144 can be formed by a method (e.g., sputtering) that appropriately prevents impurities such as water and hydrogen from mixing into the protective insulating layer 144. The thickness of the protective insulating layer 144 is at least 1 nm. Silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, etc., can be used to form the protective insulating layer 144. The protective insulating layer 144 can have a single-layer structure or a layered structure. The substrate temperature for forming the protective insulating layer 144 is preferably higher than or equal to room temperature and lower than or equal to 300°C. The atmosphere used for forming the protective insulating layer 144 is preferably a rare gas (usually argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (usually argon) and oxygen.

[0165] If the protective insulating layer 144 contains hydrogen, the hydrogen can enter the oxide semiconductor layer or extract oxygen from the oxide semiconductor layer, thereby reducing the resistance of the oxide semiconductor layer on the back channel side and forming a parasitic channel. Therefore, it is important not to use hydrogen when forming the protective insulating layer 144 so that the oxide insulating layer 140 contains as little hydrogen as possible.

[0166] Furthermore, it is preferable to form a protective insulating layer 144 while removing water remaining in the processing chamber, so that neither the oxide semiconductor layer 140 nor the protective insulating layer 144 contains hydrogen, hydroxyl groups, or moisture.

[0167] A trapping vacuum pump is preferably used to remove residual moisture from the processing chamber. For example, a cryogenic pump, an ion pump, or a titanium sublimation pump is preferably used. The venting unit can be a turbopump equipped with a cold trap. In the deposition chamber vented by the cryogenic pump, hydrogen atoms, as well as hydrogen-containing compounds such as water (H2O), are removed, for example; thereby reducing the impurity concentration in the protective insulating layer 144 formed in the deposition chamber.

[0168] It is preferable to use a high-purity gas from which impurities such as hydrogen, water, compounds with hydroxyl groups, or hydrides have been removed to reduce the impurity concentration to a few ppm (preferably a few ppb) as the sputtering gas for forming the protective insulating layer 144.

[0169] Next, the second heat treatment is preferably performed in an inert gas atmosphere or an oxygen atmosphere (at a temperature greater than or equal to 200°C and less than or equal to 400°C, for example, at a temperature greater than or equal to 250°C and less than or equal to 350°C). For example, the second heat treatment is performed for 1 hour at 250°C in a nitrogen atmosphere. The second heat treatment can reduce changes in the electrical characteristics of the transistor.

[0170] Furthermore, heat treatment can be performed in air at 100°C to 200°C for up to 1 hour. This heat treatment can be carried out at a fixed heating temperature; alternatively, the following temperature changes can be repeated multiple times: the heating temperature is raised from room temperature to a temperature of 100°C to 200°C, and then lowered back to room temperature. Before forming the protective insulating layer, this heat treatment can be performed under reduced pressure. Under reduced pressure, the heat treatment time can be shortened. For example, this heat treatment under reduced pressure can be performed instead of a second heat treatment, or it can be performed before or after the second heat treatment.

[0171] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see...). Figure 5A The interlayer insulating layer 146 can be formed by PVD, CVD, or other methods. Materials including inorganic insulating materials (such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide) can be used to form the interlayer insulating layer 146. After forming the interlayer insulating layer 146, the surface of the interlayer insulating layer 146 is preferably planarized by CMP, etching, or other methods.

[0172] Next, openings leading to electrodes 136a, 136b, and 136c, and source / drain electrodes 142a and 142b, are formed in the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. Then, a conductive layer 148 is formed to embed into these openings (see...). Figure 5BThese openings can be formed by methods such as etching using a mask. The mask can be formed by methods such as exposure using a photomask. Wet etching or dry etching can be used as the etching; dry etching is preferred for microfabrication. The conductive layer 148 can be formed by film formation methods such as PVD or CVD. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or alloys or compounds (e.g., nitrides) of any of these materials can be used to form the conductive layer 148.

[0173] Specifically, it is possible to employ a method in which a titanium thin film is formed in the region including the opening by PVD and a titanium nitride thin film is formed by CVD, followed by the formation of a tungsten film to embed within the opening. Here, the titanium film formed by PVD has the function of reducing the contact resistance with the lower electrode by reducing the oxide film formed on the surface of the lower electrode (here, electrodes 136a, 136b, and 136c, and source / drain electrodes 142a and 142b). The titanium nitride film formed after the titanium film has a barrier function to prevent the diffusion of conductive materials. After forming the barrier film of titanium, titanium nitride, etc., a copper film can be formed by electroplating.

[0174] After the conductive layer 148 is formed, a portion of the conductive layer 148 is removed by etching, CMP, etc., thereby exposing the interlayer insulating layer 146, and electrodes 150a, 150b, 150c, 150d, and 150e are formed (see...). Figure 5C Note that when forming electrodes 150a, 150b, 150c, 150d, and 150e by removing a portion of the conductive layer 148, it is preferable to perform this process to planarize these surfaces. Planarizing the interlayer insulating layer 146 and the surfaces of electrodes 150a, 150b, 150c, 150d, and 150e in this way allows for the smooth formation of electrodes, wiring, insulating layers, etc., in subsequent steps.

[0175] Then, an insulating layer 152 is formed, and openings leading to electrodes 150a, 150b, 150c, 150d, and 150e are formed in the insulating layer 152. After a conductive layer is formed to embed into the openings, a portion of the conductive layer is removed by etching, CMP, or the like. This exposes the insulating layer 152, and electrodes 154a, 154b, 154c, and 154d are formed (see...). Figure 5D This step is similar to the step of forming electrode 150a, etc.; therefore, it will not be described in detail again.

[0176] When transistor 162 is formed by the above method, the hydrogen concentration in oxide semiconductor layer 140 is less than or equal to 5 × 10⁻⁶. 19 atoms / cm 3Furthermore, the cutoff current of transistor 162 is less than or equal to 100 ozA / μm. As described above, transistor 162 with excellent characteristics can be obtained by applying an oxide semiconductor layer 140 that is highly purified through a sufficient reduction in hydrogen concentration. Moreover, it is possible to manufacture a semiconductor device with excellent characteristics, comprising a lower transistor 160 formed using a material other than oxide semiconductor, and an upper transistor 162 formed using oxide semiconductor.

[0177] Note that silicon carbide (e.g., 4H-SiC) is presented as a semiconductor material comparable to oxide semiconductors. Oxide semiconductors and 4H-SiC share several characteristics. Carrier density is one of them. The intrinsic carrier density in oxide semiconductors at room temperature is estimated to be approximately 10-1. -7 / cm 3 The intrinsic carrier density is extremely small, similar to that in 4H-SiC, at 6.7 × 10⁻⁶. -11 / cm 3 When the intrinsic carrier density of an oxide semiconductor is similar to that of silicon (approximately 1.4 × 10⁻⁶), the intrinsic carrier density of silicon is... 10 / cm 3 When compared, it is easy to understand that the intrinsic carrier density of oxide semiconductors is quite low.

[0178] Furthermore, the band gap of oxide semiconductors is 3.0 eV to 3.5 eV, while that of 4H-SiC is 3.26 eV. Thus, oxide semiconductors and silicon carbide are similar in that they are both wide bandgap semiconductors.

[0179] On the other hand, a key difference between oxide semiconductors and silicon carbide lies in the processing temperature. Since silicon carbide typically requires heat treatment at 1500°C to 2000°C, it is difficult to form stacks of silicon carbide and semiconductor devices using other semiconductor materials. This is because such high temperatures damage the semiconductor substrate and semiconductor devices. Meanwhile, oxide semiconductors can be formed through heat treatment at 300°C to 500°C (less than or equal to the glass transition temperature, up to approximately 700°C); therefore, it is possible to form integrated circuits using semiconductor materials other than oxide semiconductors, and subsequently form semiconductor devices containing oxide semiconductors.

[0180] Furthermore, unlike silicon carbide, oxide semiconductors are advantageous because they can use substrates with low heat resistance, such as glass substrates. In addition, oxide semiconductors do not require high-temperature heat treatment, thus significantly reducing energy costs compared to silicon carbide, which is another advantage.

[0181] While numerous studies have been conducted on the properties of oxide semiconductors, none have included the idea of ​​sufficiently reducing the local energy levels within the bandgap. According to embodiments of the disclosed invention, highly purified oxide semiconductors are formed by removing water or hydrogen, which may be the cause of local energy level formation. This is based on the idea of ​​sufficiently reducing the local energy levels within the bandgap. Such highly purified oxide semiconductors enable the manufacture of highly refined industrial products.

[0182] Furthermore, it is possible to form more highly purified (type i) oxide semiconductors by supplying oxygen to the dangling bonds of the metal generated by oxygen vacancies, thereby reducing the local energy levels caused by oxygen vacancies. For example, an oxide film containing excess oxygen is formed in contact with the channel formation region, and oxygen is subsequently supplied from the oxide film to the channel formation region, thereby reducing the local energy levels caused by oxygen vacancies.

[0183] Defects in oxide semiconductors are said to be caused by shallow energy levels below the conduction band due to excess hydrogen and deep energy levels due to oxygen deficiency. To eliminate these defects, complete removal of hydrogen and sufficient supply of oxygen are required.

[0184] <Conduction mechanism of transistors containing oxide semiconductors>

[0185] Next, refer to Figure 11 , Figure 12A and 12B , Figure 13A and 13B ,as well as Figure 14 This describes the conduction mechanism of a transistor containing an oxide semiconductor. Note that, for simplicity, the following description is based on ideal assumptions.

[0186] Figure 11 This is a cross-sectional view of an inverted interleaved transistor containing oxide semiconductor. The oxide semiconductor layer (OS) is disposed on the gate electrode layer (GE1) through the gate insulating layer (GI), and the source electrode (S) and drain electrode (D) are disposed on the oxide semiconductor layer.

[0187] Figure 12A and 12B It is along Figure 11 A schematic diagram of the band structure of A-A' in the diagram. Figure 12A This shows that no voltage was applied to the gate electrode layer (V). G =0), and no voltage or the same voltage is applied to the drain and source electrodes (V D =V S =0 or V D =V S (The situation is as follows.) Figure 12B Showing positive voltage (V) D >0) is applied to the drain electrode while the voltage is not applied to the gate electrode layer (V G=0) (shown by the dashed line), and positive voltage (V) D >0) A positive voltage +V is applied to the drain electrode. G (V G >0) The case where a voltage is applied to the gate electrode layer (shown by the solid line). When no voltage is applied to the gate electrode layer, due to the high potential barrier, charge carriers (electrons) are not injected from the source electrode into the oxide semiconductor side, and thus no current flows, which means the off state. On the other hand, when a positive voltage is applied to the gate electrode layer, the potential barrier decreases, and current flows, which means the on state.

[0188] Figure 13A and 13B It is along Figure 11 The band structure diagram of B-B' in the diagram (illustrated). Figure 13A Showing a positive potential (V) G >0) is the state supplied to the gate electrode layer (GE1), that is, the conduction state in which charge carriers (electrons) flow between the source electrode and the drain electrode. Figure 13B Showing negative potential –V G (V G >0) is the state supplied to the gate (GE1), that is, the cut-off state (where minority carriers do not flow).

[0189] Figure 14 Showing the work function of vacuum energy levels and metals And the relationship between electron affinity (χ) of oxide semiconductors.

[0190] Metals are degenerate, and the Fermi level exists in the conduction band. Meanwhile, conventional oxide semiconductors are n-type, and the Fermi level (E...)... f The intrinsic Fermi level (E) far from the band gap center i It is located near the conduction band. It is known that hydrogen in oxide semiconductors partially becomes a donor and is one of the reasons for the formation of n-type oxide semiconductors. Furthermore, it is known that oxygen vacancies are one of the reasons for the formation of n-type oxide semiconductors.

[0191] Conversely, the oxide semiconductor according to embodiments of the disclosed invention becomes intrinsic (type i) or near-intrinsic oxide semiconductors by highly purifying and removing hydrogen, which is the cause of n-type oxide semiconductors, from the oxide semiconductor, thereby including as few elements as possible other than the main components of the oxide semiconductor (impurity elements), and eliminating oxygen vacancies. That is, an embodiment of the invention is characterized by making the oxide semiconductor into or near-highly purified type i (intrinsic) semiconductors not by adding impurity elements but by eliminating impurities such as hydrogen and water, as well as oxygen vacancies, as much as possible. Thus, the Fermi level (E f It can be compared with the intrinsic Fermi level (E i)quite.

[0192] The band gap (E) of oxide semiconductors g The work function of titanium (Ti) contained in the source or drain electrode is said to be 3.15 eV and the electron affinity (χ) is 4.3 eV. The work function of titanium (Ti) contained in the source or drain electrode is essentially equal to the electron affinity (χ) of the oxide semiconductor. In this case, no Schottky barrier to electrons is formed at the interface between the metal and the oxide semiconductor.

[0193] In the work function of metals Given an electron affinity (χ) equal to that of an oxide semiconductor, when a metal and an oxide semiconductor come into contact with each other, the following is obtained: Figure 12A The energy band diagram (schematic diagram).

[0194] exist Figure 12B In the diagram, the black dots (·) represent electrons. When a positive potential is supplied to the drain electrode, electrons cross the potential barrier (h) to be injected into the oxide semiconductor and flow to the drain electrode. The height of the potential barrier (h) depends on the gate voltage (V). G When a positive drain voltage is applied to the drain electrode, the height of the potential barrier (h) is lower than that of the electrode where no voltage is applied. Figure 12A The height of the intermediate potential barrier, i.e., the band gap (E) g Half of ).

[0195] At this time, as Figure 13A As shown, electrons travel near the interface between the gate insulating layer and the highly purified oxide semiconductor (where the oxide semiconductor is the energy-stable bottom).

[0196] like Figure 13B As shown, when a negative potential is supplied to the gate electrode (GE1), the current value is as close to 0 as possible since holes, which are minority carriers, are essentially non-existent.

[0197] For example, the cutoff current at room temperature (25°C) is less than or equal to 10 μA / μm (1×10⁻⁶). -20 A / μm), or less than or equal to 1zA / μm (1×10⁻⁶). -21 (A / μm). As a result, a transistor with a subthreshold swing (S value) of 0.1V / dec. can be obtained.

[0198] In this way, oxide semiconductors are highly purified to contain as few impurities as possible other than the main components of oxide semiconductors, thereby enabling transistors to operate well.

[0199] <Variant Example>

[0200] Figure 6 , Figure 7A and 7B , Figure 8A and8B ,as well as Figure 9B and 9B Examples of variations of the semiconductor device structure are shown. Various semiconductor devices in which transistor 162 has a different structure than those described above will be described below as examples of variations. That is, the structure of transistor 160 is the same as the structure described above.

[0201] Figure 6 An example of a semiconductor device including transistor 162 is shown, in which gate electrode 136d is placed under oxide semiconductor layer 140, while source / drain electrodes 142a and 142b are in contact with the bottom surface of oxide semiconductor layer 140. Note that the planar structure can be appropriately modified to correspond to the cross-section; therefore, only the cross-section is shown here.

[0202] Figure 6 Structure and Figure 2A The key difference between the structures lies in the location where the oxide semiconductor layer 140 is connected to the source / drain electrodes 142a and 142b. That is, in Figure 2A In the structure, the top surface of the oxide semiconductor layer 140 is in contact with the source / drain electrodes 142a and 142b, while... Figure 6 In the structure, the bottom surface of the oxide semiconductor layer 140 contacts the source / drain electrodes 142a and 142b. Furthermore, different contact positions result in different arrangements of other electrodes, insulating layers, etc. Details of each component are as follows... Figure 2A and 2B The same.

[0203] Specifically, Figure 6 The semiconductor device shown includes a gate electrode 136d disposed on an interlayer insulating layer 128, a gate insulating layer 138 disposed on the gate electrode 136d, source / drain electrodes 142a and 142b disposed on the gate insulating layer 138, and an oxide semiconductor layer 140 in contact with the top surfaces of the source / drain electrodes 142a and 142b.

[0204] Here, the gate electrode 136d is configured to be embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similar to the gate electrode 136d, electrodes 136a, 136b, and 136c are formed to contact the source / drain electrode 130a, source / drain electrode 130b, and electrode 130c, respectively.

[0205] A protective insulating layer 144 is disposed on the transistor 162, thereby contacting a portion of the oxide semiconductor layer 140. An interlayer insulating layer 146 is disposed on the protective insulating layer 144. Openings leading to the source / drain electrodes 142a and 142b are formed in the protective insulating layer 144 and the interlayer insulating layer 146, respectively. Electrodes 150d and 150e are formed to contact the source / drain electrodes 142a and 142b, respectively, through corresponding openings. Similar to electrodes 150d and 150e, electrodes 150a, 150b, and 150c are formed to contact electrodes 136a, 136b, and 136c, respectively, through openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146.

[0206] An insulating layer 152 is disposed on the interlayer insulating layer 146. Electrodes 154a, 154b, 154c, and 154d are disposed and embedded in the insulating layer 152. Electrode 154a is in contact with electrode 150a. Electrode 154b is in contact with electrode 150b. Electrode 154c is in contact with electrodes 150c and 150d. Electrode 154d is in contact with electrode 150e.

[0207] Figure 7A and 7B Examples of the structure of a semiconductor device in which the gate electrode 136d is placed on the oxide semiconductor layer 140 are shown respectively. Figure 7A An example of a structure in which the source / drain electrodes 142a and 142b are in contact with the bottom surface of the oxide semiconductor layer 140 is shown. Figure 7B An example of a structure in which the source / drain electrodes 142a and 142b are in contact with the top surface of the oxide semiconductor layer 140 is shown.

[0208] Figure 7A and 7B Structure and Figure 2A and Figure 6 The key difference between the structures is that the gate electrode 136d is placed on the oxide semiconductor layer 140. Furthermore, Figure 7A The structure and Figure 7B The key difference in the structure lies in the fact that the source / drain electrodes 142a and 142b are in contact with the bottom or top surface of the oxide semiconductor layer 140. Furthermore, these differences result in different arrangements of other electrodes, insulating layers, etc. Details of each component are as follows... Figure 2A and 2B The same as, etc.

[0209] Specifically, Figure 7AThe semiconductor device shown includes source / drain electrodes 142a and 142b disposed on an interlayer insulating layer 128, an oxide semiconductor layer 140 in contact with the top surfaces of the source / drain electrodes 142a and 142b, a gate insulating layer 138 disposed on the oxide semiconductor layer 140, and a gate electrode 136d on the gate insulating layer 138 in a region overlapping with the oxide semiconductor layer 140.

[0210] Figure 7B The semiconductor device includes an oxide semiconductor layer 140 disposed on an interlayer insulating layer 128, source / drain electrodes 142a and 142b disposed in contact with the top surface of the oxide semiconductor layer 140, a gate insulating layer 138 disposed on the oxide semiconductor layer 140 and the source / drain electrodes 142a and 142b, and a gate electrode 136d on the gate insulating layer 138 in a region overlapping with the oxide semiconductor layer 140.

[0211] Note that in Figure 7A and 7B In the structure, under certain circumstances, it can be obtained from Figure 2A and 2B Components (e.g., electrode 150a or electrode 154a) are omitted from the structure. In this case, auxiliary effects such as simplifying the manufacturing process can be obtained. Needless to say, in Figure 2A and 2B In structures like these, unnecessary components can be omitted.

[0212] Figure 8A and 8B Examples are shown where the components are relatively large and the gate electrode 136d is placed under the oxide semiconductor layer 140. In this case, the requirements for surface flatness and coverage are relatively moderate, so it is not necessarily necessary to form wiring, electrodes, etc. embedded in the insulating layer. For example, the gate electrode 136d, etc., can be formed by patterning after the conductive layer is formed. Note that although not shown here, the transistor 160 can be formed in a similar manner.

[0213] Figure 8A The structure and Figure 8B The key difference in the structure lies in the fact that the source / drain electrodes 142a and 142b are in contact with either the bottom or top surface of the oxide semiconductor layer 140. Furthermore, these differences result in different arrangements of other electrodes, insulating layers, etc. The details of each component are... Figure 2A and 2B The same as, etc.

[0214] Specifically, Figure 8AThe semiconductor device includes a gate electrode 136d disposed on an interlayer insulating layer 128, a gate insulating layer 138 disposed on the gate electrode 136d, source / drain electrodes 142a and 142b disposed on the gate insulating layer 138, and an oxide semiconductor layer 140 in contact with the top surfaces of the source / drain electrodes 142a and 142b.

[0215] Figure 8B The semiconductor device includes a gate electrode 136d disposed on an interlayer insulating layer 128, a gate insulating layer 138 disposed on the gate electrode 136d, an oxide semiconductor layer 140 disposed on the gate insulating layer 138 in a region overlapping with the gate electrode 136d, and source / drain electrodes 142a and 142b disposed in contact with the top surface of the oxide semiconductor layer 140.

[0216] Note that, also in Figure 8A and 8B In the structure, under certain circumstances, it can be obtained from Figure 2A and 2B Components are omitted from the structure. Similarly, in this case, auxiliary effects such as simplifying the manufacturing process can be achieved.

[0217] Figure 9A and 9B Examples are shown where the components are relatively large and the gate electrode 136d is placed on the oxide semiconductor layer 140. Similarly, in this case, the requirements for surface flatness and coverage are relatively moderate, so it is not necessary to form wiring, electrodes, etc., embedded in the insulating layer. For example, the gate electrode 136d, etc., can be formed by patterning after the conductive layer is formed. Note that although not shown here, the transistor 160 can be formed in a similar manner.

[0218] Figure 9A The structure and Figure 9B The key difference in the structure lies in the fact that the source / drain electrodes 142a and 142b are in contact with the bottom or top surface of the oxide semiconductor layer 140. Furthermore, this difference results in other electrodes, insulating layers, etc., being arranged differently. The details of each component are... Figure 2A and 2B The same as, etc.

[0219] Specifically, Figure 9A The semiconductor device includes source / drain electrodes 142a and 142b disposed on an interlayer insulating layer 128, an oxide semiconductor layer 140 in contact with the top surfaces of the source / drain electrodes 142a and 142b, a gate insulating layer 138 disposed on the source / drain electrodes 142a and 142b and the oxide semiconductor layer 140, and a gate electrode 136d disposed on the gate insulating layer 138 in a region overlapping with the oxide semiconductor layer 140.

[0220] Figure 9B The semiconductor device includes an oxide semiconductor layer 140 disposed on an interlayer insulating layer 128, source / drain electrodes 142a and 142b disposed in contact with the top surface of the oxide semiconductor layer 140, a gate insulating layer 138 disposed on the source / drain electrodes 142a and 142b and the oxide semiconductor layer 140, and a gate electrode 136d disposed on the gate insulating layer 138 in a region overlapping with the oxide semiconductor layer 140.

[0221] Note that, also in Figure 9A and 9B In the structure, under certain circumstances, it can be obtained from Figure 2A and 2B Components are omitted from the structure. Similarly, in this case, auxiliary effects such as simplifying the manufacturing process can be achieved.

[0222] As described above, a semiconductor device with a novel structure can be realized according to one embodiment of the disclosed invention. In this embodiment, various examples are described in which the semiconductor device is formed by stacking transistors 160 and 162; however, the structure of the semiconductor device is not limited to this structure. Furthermore, this embodiment shows an example in which the channel length direction of transistor 160 is perpendicular to the channel length direction of transistor 162; however, the positional relationship between transistors 160 and 162 is not limited to this example. Additionally, transistors 160 and 162 may be arranged to overlap each other.

[0223] In this embodiment, for simplicity, a semiconductor device with a minimum storage unit (1 bit) is described; however, the structure of the semiconductor device is not limited to this. More advanced semiconductor devices can be formed by appropriately connecting multiple semiconductor devices. For example, NAND or NOR type semiconductor devices can be formed by using multiple of the above-described semiconductor devices. The wiring configuration is not limited to... Figure 1 The wiring configuration can be adjusted as needed.

[0224] The semiconductor device according to this embodiment can store data for an extremely long time because transistor 162 has a low cutoff current. That is, the refresh operation necessary in DRAM and the like is not required, thereby suppressing power consumption. Furthermore, the semiconductor device according to this embodiment can be used as a substantially non-volatile semiconductor device.

[0225] Since data writing and other operations are performed using the switching operation of transistor 162, high voltage is unnecessary, and component degradation is negligible. Furthermore, data is written and erased based on the transistor's on and off states, easily enabling high-speed operation. Also advantageously, data erasure is unnecessary because data can be rewritten directly by controlling the potential input to the transistor, an operation essential in flash memory and similar applications.

[0226] Since transistors containing materials other than oxide semiconductors can operate at higher speeds than transistors containing oxide semiconductors, stored data can be read out at high speeds by using such transistors.

[0227] The structures and methods described in this embodiment can be appropriately combined with any of the structures and methods described in other embodiments.

[0228] (Example 2)

[0229] In this embodiment, reference will be made to Figure 15A and 15B To describe the structure and manufacturing method of a semiconductor device according to another embodiment of the disclosed invention.

[0230] Figure 15A An example of the circuit construction of a semiconductor device is shown. Figure 15A and Figure 1 The difference lies in the inclusion of capacitor 164. That is, in Figure 15A In this configuration, one of the source and drain electrodes of transistor 162, one of the electrodes of capacitor 164, and the gate electrode of transistor 160 are electrically connected to each other. A first line (also called source line BL) is electrically connected to the source electrode of transistor 160, and a second line (also called bit line BL) is electrically connected to the drain electrode of transistor 160. A third line (also called first signal line S1) is electrically connected to the other of the source and drain electrodes of transistor 162, and a fourth line (also called second signal line S2) is electrically connected to the gate electrode of transistor 162. A fifth line (also called word line WL) is electrically connected to the other of the electrodes of transistor 164. Note that in... Figure 15A and 15B In each of them, "OS" is written next to the transistor to indicate that the transistor is an oxide semiconductor.

[0231] Here, the aforementioned oxide semiconductor transistor is used as transistor 162. Oxide semiconductor transistors have a relatively small cutoff current characteristic. Therefore, when transistor 162 is turned off, the potential of the gate electrode of transistor 160 can be maintained for a long time. The capacitor 164 is provided to facilitate maintaining the charge supplied to the gate electrode of transistor 160 and reading stored data.

[0232] Note that there are no specific limitations on transistor 160. For increasing the speed of data readout, it is preferable to use transistors with high switching rates, such as those formed using single-crystal silicon.

[0233] Figure 15A The semiconductor device in the process utilizes the property of maintaining the potential of the gate electrode of transistor 160 to write, store, and read data as follows.

[0234] First, the description data is written and stored. First, the potential of the fourth line is set to the potential that turns on transistor 162, thus turning on transistor 162. Therefore, the potential of the third line is supplied to the gate electrode of transistor 160 and capacitor 164. That is, a predetermined charge is given to the gate electrode of transistor 160 (writing). Here, one of the two different potentials is used to supply the charge (hereinafter, the charge used to supply the low potential is called charge Q). L The charge used to supply high potential is called charge Q. H The gate electrode of transistor 160 is supplied with charge. Note that three or more different potentials can be applied to improve the storage capacitor. Then, the potential of the fourth line is set to the potential that turns off transistor 162, thereby turning off transistor 162. Thus, the charge supplied to the gate electrode of transistor 160 is retained (stored).

[0235] Because the cutoff current of transistor 162 is quite small, the charge on the gate electrode of transistor 160 is retained for a relatively long time.

[0236] Next, the data reading operation will be described. By supplying a predetermined potential (constant potential) to the first line while simultaneously supplying an appropriate potential (read potential) to the fifth line, the potential of the second line varies depending on the amount of charge held in the gate electrode of transistor 160. This is because, typically when transistor 160 is an n-channel transistor, when Q... H The apparent threshold voltage Vth_H given to the gate electrode of transistor 160 is lower than that given Q. L The apparent threshold voltage Vth_L is applied to the gate electrode of transistor 160. Here, the apparent threshold voltage refers to the potential of the fifth line, which is required for transistor 160 to conduct. Therefore, the potential of the fifth line is set to the intermediate potential V0 between Vth_H and Vth_L, thereby determining the charge applied to the gate electrode of transistor 160. For example, Q is applied during writing. H In this case, when the potential of the fifth line is set to V0 (>Vth_H), transistor 160 is turned on. During writing, Q is applied... L In this case, even when the potential of the fifth line is set to V0 (>Vth_L), transistor 160 remains in the off state. Therefore, the stored data can be read via the potential of the second line.

[0237] Note that when memory cells are arranged in an array for use, only the data of the required memory cell needs to be read. Therefore, when reading data from a predetermined memory cell without reading data from other memory cells, a potential below Vth_H, which allows transistor 160 to be turned off regardless of the state of its gate electrode, can be applied to the fifth line of the memory cell whose data is not being read. Alternatively, a potential above Vth_H can be applied to allow transistor 160 to be turned on regardless of the state of its gate electrode. th_L The potential can be applied to the fifth line.

[0238] Next, the described data is rewritten. Data rewriting is performed similarly to data writing or storage. That is, the potential of the fourth line is set to the potential that turns on transistor 162, thereby turning on transistor 162. Therefore, the potential of the third line (the potential associated with the new data) is supplied to the gate electrode of transistor 160 and capacitor 164. Then, the potential of the fourth line is set to the potential that turns off transistor 162, thereby turning off transistor 162. Therefore, the charge associated with the new data is applied to the gate electrode of transistor 160.

[0239] Therefore, in the semiconductor device according to the disclosed invention, data can be directly rewritten by overwriting new data. Thus, the high voltage required for charge extraction from the floating gate, as in flash memory and the like, is not necessary, and the reduction in operating speed due to the erase operation can be suppressed. That is, high-speed operation of the semiconductor device can be achieved.

[0240] Note that the source or drain electrode of transistor 162 is electrically connected to the gate electrode of transistor 160, thus having an effect similar to the floating gate of a floating gate transistor used in non-volatile memory elements. Therefore, in some cases, the portion of the transistor 162 whose source or drain electrode is electrically connected to the gate electrode of transistor 160 is referred to as the floating gate portion FG. When transistor 162 is turned off, the floating gate portion FG can be considered as embedded in an insulator, thus retaining charge in the floating gate portion FG. The amount of the cutoff current of transistor 162, which contains oxide semiconductor, is less than or equal to one ten-thousandth of the cutoff current death of transistors containing silicon semiconductor; therefore, the loss of charge accumulated in the floating gate portion FG due to the leakage current of transistor 162 is negligible. That is, using transistor 162, which contains oxide semiconductor, a non-volatile memory device that stores data without power supply can be realized.

[0241] For example, when the cutoff current of transistor 162 is less than or equal to 10 zA at room temperature (25°C) (1 zA (Zepto Ampere) is 1 × 10⁻⁶), -21 A) When the capacitance of capacitor 164 is approximately 10 fF, data can be stored up to 10 4Seconds or longer. Needless to say, storage time depends on transistor characteristics and capacitance value.

[0242] Furthermore, the gate insulating film (tunnel insulating film) degradation issue mentioned in conventional floating gate transistors does not exist in this case. That is, the gate insulating film degradation caused by electron injection into the floating gate, which is usually considered a problem, can be ignored. This means that, in principle, there is no limit to the number of write cycles. Moreover, the high voltage required for writing or erasing in conventional floating gate transistors is unnecessary.

[0243] Figure 15A In semiconductor devices, components such as transistors can be considered as being made of... Figure 15B The resistor and capacitor shown constitute the structure. That is, in Figure 15B In this diagram, transistor 160 and capacitor 164 are each considered to include a resistor and a capacitor, respectively. R1 and C1 represent the resistance and capacitance values ​​of capacitor 164, respectively. The resistance value R1 corresponds to the resistance value depending on the insulating layer included in capacitor 164. R2 and C2 represent the resistance and capacitance values ​​of transistor 160, respectively. The resistance value R2 corresponds to the resistance value depending on the gate insulating layer when transistor 160 is turned on. The capacitance value C2 corresponds to the so-called gate capacitance (the capacitance formed between the gate electrode and the source or drain electrode, and the capacitance formed between the gate electrode and the channel formation region).

[0244] Under the condition that the gate leakage of transistor 162 is sufficiently small and R1≥ROS and R2≥ROS, the electron retention period (also known as the data storage period) is mainly determined by the cutoff current of transistor 162, where the resistance value between the source and drain electrodes (also known as the effective resistance) when transistor 162 is cut off is ROS.

[0245] On the other hand, if the above conditions are not met, even if the cutoff current of transistor 162 is small enough, it is difficult to sufficiently ensure the hold period. This is because the leakage current of transistor 162 other than the cutoff current (such as the leakage current generated between the source electrode and the gate electrode) is relatively large. Therefore, it can be said that the semiconductor device disclosed in this embodiment ideally satisfies the above relationship.

[0246] Ideally, C1 ≥ C2. If C1 is large, the potential change of the fifth line can be suppressed when the potential of the floating gate section FG is controlled by the fifth line (e.g., during readout).

[0247] When the above relationships are satisfied, a more preferred semiconductor device can be realized. Note that R1 and R2 are controlled by the gate insulating layer of transistor 160 and the insulating layer of capacitor 164. The same relationship applies to C1 and C2. Therefore, the material, thickness, etc. of the gate insulating layer are ideally set as needed to satisfy the above relationships.

[0248] In the semiconductor device described in this embodiment, the floating gate portion FG has an effect similar to the floating gate of a floating gate transistor such as flash memory; however, the floating gate portion FG of this embodiment has characteristics that are fundamentally different from those of floating gates in flash memory. In the case of flash memory, due to the high voltage applied to the control gate, it is necessary to maintain an appropriate distance between cells to prevent potential from affecting the floating gate of neighboring cells. This is one of the suppression factors for the high integration of semiconductor devices. This factor is attributed to the basic principle of flash memory, in which tunneling current flows when a high electric field is applied.

[0249] Furthermore, due to the aforementioned principle of flash memory, the insulating film deteriorates, thus limiting the number of rewrite cycles (approximately 10). 4 Up to 10 5 Another issue (next time).

[0250] The semiconductor device according to the disclosed invention operates by switching transistors containing oxide semiconductors, without using the aforementioned principle of charge injection via tunneling current. That is, unlike flash memory, a high electric field for charge injection is not required. Therefore, there is no need to consider the effect of a high electric field from the control gate on neighboring cells, which facilitates high integration.

[0251] Furthermore, the absence of charge injection utilizing tunneling current means there is no cause for memory cell degradation. In other words, the semiconductor device according to the disclosed invention exhibits higher durability and reliability than flash memory.

[0252] Furthermore, it is also advantageous that, compared to flash memory, it does not require a high electric field and large auxiliary circuitry (such as boost circuitry).

[0253] When the dielectric constant εr1 of the insulating layer included in C1 differs from the dielectric constant εr2 of the insulating layer included in C2, it is easy to satisfy C1≥C2 while simultaneously satisfying 2·S2≥S1 (ideally S2≥S1), where S1 is the area of ​​C1 and S2 is the area of ​​C2. Specifically, for example, a film formed of a high-k material such as hafnium oxide, or a stack formed of a high-k material such as hafnium oxide, and a film formed of an oxide semiconductor are used in C1 so that εr1 can be set to greater than or equal to 10, preferably greater than or equal to 15, and silicon oxide is used in C2 so that εr2 can be set to 3 to 4. This combination of structures enables the high integration of the semiconductor device according to the disclosed invention.

[0254] Note that the above description uses an n-channel transistor. However, it goes without saying that a p-channel transistor can be used instead of an n-channel transistor.

[0255] As described above, the semiconductor device according to the embodiments of the disclosed invention has a non-volatile memory cell, which includes a write transistor in which the leakage current (cutoff current) between the source and drain is small in the off state, a read transistor formed of a different semiconductor material than the write transistor, and a capacitor.

[0256] The cutoff current of the write transistor is less than or equal to 100 ozA (1 × 10⁻⁶). -19 A), preferably less than or equal to 10zA (1×10) at room temperature (e.g., 25°C). -20 A), more preferably, is less than or equal to 1zA (1×10) at room temperature (e.g., 25°C). -21 A) In the case of conventional silicon semiconductors, it is difficult to obtain the aforementioned low cutoff current. However, in transistors obtained by processing oxide semiconductors under appropriate conditions, a low cutoff current can be obtained. Therefore, it is preferable to use transistors containing oxide semiconductors as write transistors.

[0257] Furthermore, transistors containing oxide semiconductors have a small subthreshold swing (S-value), allowing for sufficiently high switching speeds even with relatively low mobility. Therefore, by using this transistor as a write transistor, the rise of the write pulse applied to the floating gate portion FG can be very steep. Additionally, the cutoff current is small, and thus the amount of charge held in the floating gate portion FG can be reduced. In other words, by using transistors containing oxide semiconductors, data rewriting can be performed at high speed.

[0258] As for the read transistor, it is desirable to use a transistor that operates at high speed to improve the read rate. For example, it is preferable to use a transistor with a switching rate of less than or equal to 1 nanosecond as the read transistor.

[0259] Data is written to a memory cell by turning on the write transistor to supply a potential to a floating gate portion FG in which one of the source and drain electrodes of the write transistor, one of the electrodes of a capacitor, and the gate electrode of the read transistor are electrically connected, and then turning off the write transistor to retain a predetermined amount of charge in the floating gate portion FG. Here, the cutoff current of the write transistor is very small; thus, the charge supplied to the floating gate portion FG is retained for a relatively long time. When the cutoff current is, for example, essentially zero, the refresh operation required by conventional DRAM may be unnecessary, or the frequency of the refresh operation may be quite low (e.g., about once a month or once a year). Therefore, the power consumption of the semiconductor device can be significantly reduced.

[0260] Furthermore, data can be directly rewritten by overwriting new data onto the memory cell. Therefore, the erase operation necessary for flash memory and the like is eliminated, and the reduction in operating speed caused by the erase operation is suppressed. In other words, high-speed operation of the semiconductor device can be achieved. Moreover, the high voltage required for writing and erasing data using conventional floating-gate transistors is unnecessary; thus, the power consumption of the semiconductor device can be further reduced. According to this embodiment, the highest voltage applied to the memory cell (the difference between the highest and lowest potentials simultaneously applied to each terminal of the memory cell) can be less than or equal to 5V or less than or equal to 3V in each memory cell when writing second-order data (1 bit).

[0261] The memory cells disposed in the semiconductor device according to the disclosed invention may include at least write transistors and read transistors; therefore, for example, the area of ​​each memory cell can be sufficiently small compared to SRAM, which requires six transistors in each memory cell. In other words, memory cells can be arranged in a high density in the semiconductor device.

[0262] In conventional floating-gate transistors, charge travels through the gate insulating film (tunnel insulating film) during write operations, making degradation of the gate insulating film (tunnel insulating film) unavoidable. Conversely, in the memory cell according to an embodiment of the invention, data is written via the switching operation of the write transistor; therefore, there is no degradation of the gate insulating film. This means that, in principle, there is no limit to the number of writes, and rewrite durability is very high. For example, in a memory cell according to an embodiment of the invention, even after 1×10 data writes... 9 The current-voltage characteristics will not degrade even after multiple times (billions or more).

[0263] Furthermore, when using transistors containing oxide semiconductors as write transistors for memory cells, the current-voltage characteristics of the memory cells do not degrade even at high temperatures, such as 150°C, because oxide semiconductors generally have a wide bandgap (e.g., 3.0 to 3.5 eV in the case of In-Ga-Zn-O based oxide semiconductors) and very few thermally excited carriers.

[0264] By using this transistor with superior properties as a write transistor for memory cells, semiconductor devices with novel features can be provided.

[0265] The methods and structures described in this embodiment can be appropriately combined with any of the methods and structures described in other embodiments.

[0266] (Example 3)

[0267] In this embodiment, reference will be made to Figure 16 , Figure 17A and 17B , Figures 18A to 18C , Figure 19 , Figure 20 and Figure 21 To describe an application example of a semiconductor device according to another embodiment of the disclosed invention.

[0268] Figure 16 A schematic diagram of a semiconductor device according to this embodiment is shown.

[0269] Figure 16 It includes Figure 1 or Figure 15A An example of a circuit diagram of a plurality of semiconductor devices (hereinafter also referred to as memory cell 1200).

[0270] Figure 16 The semiconductor device includes a memory cell array in which multiple memory cells 1200 are arranged in a matrix, a first driving circuit 1211, a second driving circuit 1212, a third driving circuit 1213, a fourth driving circuit 1214, multiple lines L1 electrically connected to the first driving circuit 1211, multiple lines L2 electrically connected to the second driving circuit 1212, multiple lines L3 electrically connected to the third driving circuit 1213, and multiple lines L4 electrically connected to the fourth driving circuit 1214.

[0271] like Figure 16 As shown, lines L1, L2, L3, and L4 are electrically connected to each memory cell 1200. Therefore, the operation of each memory cell 1200 can be controlled using the first drive circuit 1211, the second drive circuit 1212, the third drive circuit 1213, and the fourth drive circuit 1214. The memory cells 1200 are arranged in a matrix, and lines L1, L2, L3, and L4 are positioned in the row and column directions of the grid pattern, thereby enabling write and read operations of the semiconductor device to be performed in each row or column of the memory cells 1200.

[0272] Note that in Figure 16 One line from each of the first drive circuit 1211 to the fourth drive circuit 1214 is electrically connected to the memory cell 1200; however, the disclosed invention is not limited thereto. Multiple lines from any one or a portion of the drive circuits may be electrically connected to the memory cell 1200. Alternatively, a configuration may be adopted in which lines from any one or a portion of the drive circuits are not electrically connected to any one or a portion of the memory cell 1200.

[0273] exist Figure 16In the semiconductor device described, the first driving circuit 1211, the second driving circuit 1212, the third driving circuit 1213, and the fourth driving circuit 1214 are arranged separately; however, the disclosed invention is not limited thereto. Driving circuits having any or a portion of these functions can be used alternatively. Note that it is desirable for the driving circuits to be formed using a single-crystal semiconductor material to ensure sufficient operating speed. For example, bulk silicon (so-called silicon wafer) is preferred.

[0274] Next, a more specific configuration example will be described.

[0275] Figure 17A and 17B Each includes Figure 15A An example of a circuit diagram of a plurality of semiconductor devices (hereinafter also referred to as memory cell 400) is shown. Figure 17A This is a circuit diagram of a so-called NAND semiconductor device in which memory cells 400 are connected in series. Figure 17B This is a circuit diagram of a so-called NOR semiconductor device in which memory cells 400 are connected in parallel.

[0276] Figure 17A The semiconductor devices in the memory include source line SL, bit line BL, first signal line S1, multiple second signal lines S2, multiple word lines WL, and multiple memory cells 400. Figure 17A In this embodiment, a source line SL and a bit line BL are disposed in the semiconductor device; however, the embodiments of the disclosed invention are not limited thereto. Multiple source lines SL and multiple bit lines BL can be disposed.

[0277] In each memory cell 400, the gate electrode of transistor 160, one of the source and drain electrodes of transistor 162, and one of the electrodes of capacitor 164 are electrically connected to each other. A first signal line S1 is electrically connected to the other of the source and drain electrodes of transistor 162, and a second signal line S2 is electrically connected to the gate electrode of transistor 162. A word line WL is electrically connected to the other of the electrodes of capacitor 164.

[0278] Furthermore, the source electrode of the transistor 160 included in the memory cell 400 is electrically connected to the drain electrode of the transistor 160 in the adjacent memory cell 400. The drain electrode of the transistor 160 included in the memory cell 400 is electrically connected to the source electrode of the transistor 160 in the adjacent memory cell 400. Note that the drain electrode of the transistor 160 included in the memory cell 400 located at one end of the series-connected plurality of memory cells is electrically connected to the bit line BL. The source electrode of the transistor 160 included in the memory cell 400 located at the other end of the series-connected plurality of memory cells is electrically connected to the source line SL.

[0279] exist Figure 17AIn the semiconductor device, write and read operations are performed in each row. The write operation is performed as follows: A potential that turns on transistor 162 is supplied to the second signal line S2 of the row to be written, thereby turning on transistor 162 of that row. Therefore, a potential on the first signal line S1 is supplied to the gate electrode of transistor 160 of the specified row, thereby applying a predetermined charge to the gate electrode. Thus, data can be written to the memory cell of the specified row.

[0280] Furthermore, the read operation is performed as follows. First, a potential that turns on transistor 160 regardless of the amount of charge applied to its gate electrode is supplied to the word line WL of the row other than the row to be read, thereby turning on transistor 160 of the row other than the row to be read. Then, a potential (read potential) that determines the on or off state of transistor 160 depending on the charge on its gate electrode is supplied to the word line WL of the row to be read. Afterward, a constant potential is supplied to the source line SL, thereby operating the read circuit (not shown) connected to the bit line BL. Here, multiple transistors 160 between the source line SL and the bit line BL are turned on, except for the transistor 160 of the row to be read; therefore, the conductivity between the source line SL and the bit line BL is determined by the state (on or off) of the transistor 160 of the row to be read. The conductivity of the transistor 160 performing the read depends on the charge in its gate electrode. Therefore, the potential of the bit line BL changes accordingly. Data can be read from the memory cell of a specified row by reading the potential of the bit line BL through the read circuit.

[0281] Figure 17B The semiconductor device includes multiple source lines SL, multiple bit lines BL, multiple first signal lines S1, multiple second signal lines S2, multiple word lines WL, and multiple memory cells 400. The gate electrode of transistor 160, one of the source and drain electrodes of transistor 162, and one of the electrodes of capacitor 164 are electrically connected to each other. The source line SL is electrically connected to the source electrode of transistor 160. The bit line BL is electrically connected to the drain electrode of transistor 160. The first signal line S1 is electrically connected to the other of the source and drain electrodes of transistor 162, and the second signal line S2 is electrically connected to the gate electrode of transistor 162. The word line WL is electrically connected to the other of the electrodes of capacitor 164.

[0282] exist Figure 17B In semiconductor devices, write and read operations are performed in each row. Write operations are performed in conjunction with... Figure 17AThe operation is performed in a similar manner to that of semiconductor devices. The read operation is performed as follows: First, a potential that turns off transistor 160 regardless of the amount of charge applied to its gate electrode is supplied to the word line WL of the row to be read, excluding the row to be read. Then, a potential (read potential) that determines the on or off state of transistor 160 depending on the charge on its gate electrode is supplied to the word line WL of the row to be read. Afterward, a constant potential is supplied to the source line SL, thereby operating the read circuit (not shown) connected to the bit line BL. Here, the conductivity between the source line SL and the bit line BL is determined by the state (on or off) of the transistor 160 of the row to be read. That is, the potential of the bit line BL depends on the charge in the gate electrode of the transistor 160 of the row to be read. By reading the potential of the bit line BL by the read circuit, data can be read from the memory cell of the specified row.

[0283] Although the amount of data that can be stored in each memory cell 400 is 1 bit in the above description, the structure of the memory device in this embodiment is not limited to this. By preparing three or more potentials supplied to the gate electrodes of the transistor 160, the amount of data stored in each memory cell 400 can be increased. For example, when the number of potentials supplied to the gate electrodes of the transistor 160 is 4, two bits of data can be stored in each memory cell.

[0284] Next, refer to Figures 18A to 18C Description can be used Figure 17A and 17B Examples of readout circuits for semiconductor devices, etc.

[0285] Figure 18A A schematic diagram of the readout circuit is shown. The readout circuit includes transistors and a readout amplifier circuit.

[0286] When reading data, terminal A is connected to bit line BL, which is connected to the memory cell from which data is read. Furthermore, a bias potential Vbias is applied to the gate electrode of the transistor, thereby controlling the potential of terminal A.

[0287] The resistance of the storage cell 400 varies depending on the data stored. Specifically, the storage cell 400 has a low resistance when the transistor 160 of the selected storage cell 400 is turned on, and a high resistance when the transistor 160 of the selected storage cell 400 is turned off.

[0288] When the storage unit has a high resistance, the potential of terminal A is higher than the reference potential Vref, and the sense amplifier circuit outputs a potential corresponding to the potential of terminal A. On the other hand, when the storage unit has a low resistance, the potential of terminal A is lower than the reference potential Vref, and the sense amplifier circuit outputs a potential corresponding to the potential of terminal A.

[0289] Thus, by using the read circuit, data can be read from the storage unit. Note that the read circuit of this embodiment is an example. Another circuit can be used. The read circuit may further include a precharge circuit. Instead of the reference potential Vref, the reference bit line BL may be connected to the sense amplifier circuit.

[0290] Figure 18B A differential sense amplifier, which is an example of a sense amplifier circuit, is shown. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the potential difference between Vin(+) and Vin(-). If the potential of Vin(+) is higher than the potential of Vin(-), Vout outputs the signal High, and if the potential of Vin(+) is lower than the potential of Vin(-), Vout outputs the signal Low. When the differential sense amplifier is used in the read circuit, one of Vin(+) and Vin(-) is connected to terminal A, and the reference potential Vref is supplied to the other of Vin(+) and Vin(-).

[0291] Figure 18C A latch sense amplifier, which is an example of a sense amplifier circuit, is shown. The latch sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, the control signals Sp and Sn are set to the signal High and the signal Low, respectively, and the power supply potential (Vdd) is interrupted....

[0292] Figure 19 is included Figure 15AAn example of a circuit diagram of a semiconductor device containing multiple semiconductor devices. Figure 19 The semiconductor devices in it have an m×n bit storage capacity.

[0293] Figure 19 The semiconductor device includes a memory cell array in which m word lines WL, m second signal lines S2, n bit lines BL, n source lines SL, n first signal lines S1, and a plurality of memory cells 1100 are arranged in an m (rows) (vertical direction) × n (columns) (horizontal direction) matrix (m and n are natural numbers), and peripheral circuits for a first driving circuit 1111, a second driving circuit 1112, a third driving circuit 1113, and a fourth driving circuit 1114. Here, the configuration described in any of the above embodiments (e.g., Figure 15A The configuration in the document is applied to storage unit 1100.

[0294] That is, each memory cell 1100 includes a first transistor 160, a second transistor 162, and a capacitor 164. The gate electrode of the first transistor 160, one of the source and drain electrodes of the second transistor 162, and one of the electrodes of the capacitor 164 are connected to each other. The source line SL is connected to the source electrode of the first transistor 160. The bit line BL is connected to the drain electrode of the first transistor 160. The first signal line S1 is connected to the other of the source and drain electrodes of the second transistor 162. The second signal line S2 is connected to the gate electrode of the second transistor 162. The word line WL is connected to the other of the electrodes of the capacitor 164.

[0295] Furthermore, the memory cell 1100 is connected in parallel between the source line SL and the bit line BL. For example, the memory cell 1100 in the i-th row and j-th column (i,j) (i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n) is connected to the source line SL(j), the bit line BL(j), the first signal line S1(j), the word line WL(i), and the second signal line S2(i).

[0296] The source line SL and bit line BL are connected to the first driver circuit 1111. The first signal line S1 is connected to the second driver circuit 1112. The second signal line S2 is connected to the third driver circuit 1113. The word line WL is connected to the fourth driver circuit 1114. Note that here, the first driver circuit 1111, the second driver circuit 1112, the third driver circuit 1113, and the fourth driver circuit 1114 are arranged separately; however, the disclosed invention is not limited thereto. A decoder having any or a portion of these functions can be used alternatively.

[0297] Next, refer to Figure 20 Timing diagram description Figure 19Write and read operations on semiconductor devices.

[0298] Although the operation of two rows and two columns of semiconductor devices will be described for the sake of simplicity, the disclosed invention is not limited thereto.

[0299] Figure 20 It is shown Figure 19 A diagram illustrating the operation of semiconductor devices. Figure 20 In the diagram, S1(1) and S1(2) are the potentials of the first signal line S1; S2(1) and S2(2) are the potentials of the second signal line S2; BL(1) and BL(2) are the potentials of the bit line BL; WL(1) and WL(2) are the potentials of the word line WL; and SL(1) and SL(2) are the potentials of the source line SL.

[0300] First, we will describe writing data to and reading data from memory cells (1,1) and (1,2) in the first row. Note that in the following description, it is assumed that the data to be written to memory cell (1,1) is "1" and the data to be written to memory cell (1,2) is "0".

[0301] First, the description is written. During the write cycle of the first row, a potential VH is supplied to the second signal line S2(1) of the first row, thereby turning on the second transistor 162 of the first row. In addition, a potential of 0V is supplied to the second signal line S2(2) of the second row, thereby turning off the second transistor 162 of the second row.

[0302] Next, potential V2 and potential 0V are applied to the first signal line Si (1) of the first column and the first signal line S1 (2) of the second column, respectively.

[0303] As a result, potentials V2 and 0V are applied to the floating gate portions FG of memory cells (1,1) and (1,2), respectively. Here, potential V2 is higher than the threshold voltage of the first transistor 160. Subsequently, the potential of the second signal line S2(1) of the first row is set to 0V, thereby turning off the second transistor 162 of the first row. Thus, the write operation is completed.

[0304] Note that word lines WL(1) and WL(2) are at 0V potential. Furthermore, before the potential of the first signal line S1(1) in the first row is changed, the potential of the second signal line S2(1) in the first row is set to 0V. Assuming that the terminal connected to word line WL in the memory element is the control gate electrode, the source electrode of the first transistor 160 is the source electrode, and the drain electrode of the second transistor 162 is the drain electrode, then the threshold voltage of the memory element with written data is Vw0 in the case of data "0" and Vw1 in the case of data "1". Here, the threshold voltage of the memory cell represents the voltage connected to the terminal of word line WL, which changes the resistance between the source and drain electrodes of the first transistor 160. Note that Vw0 > 0 > Vw1 is satisfied.

[0305] Next, the reading process will be described. During the first row's read cycle, potentials 0V and VL are supplied to word line WL(1) of the first row and word line WL(2) of the second row, respectively. Potential VL is below the threshold voltage Vw1. When WL(1) is at potential 0V, in the first row, the first transistor 160 of the memory cell (1,2) storing data "0" is turned off, while the first transistor 160 of the memory cell (1,1) storing data "1" is turned on. When WL(2) is at potential VL, in the second row, the first transistor 160 of the memory cells (2,1) and (2,2) storing data "0" or data "1" is turned off.

[0306] Next, a 0V potential is supplied to the source line SL(1) of the first column and the source line SL(2) of the second column.

[0307] As a result, the first transistor 160 of the memory cell (1,1) between bit line BL(1) and source line SL(1) is turned on, thus having low resistance, while the first transistor 160 of the memory cell (1,2) between bit line BL(2) and source line SL(2) is turned off, thus having high resistance. The read circuit connected to bit line BL(1) and bit line BL(2) can read data based on the difference in resistance between the bit lines.

[0308] Furthermore, a potential of 0V and a potential of VL are supplied to the second signal line S2(1) and the second signal line S2(2), respectively, thereby turning off all the second transistors 162. The potential of the floating gate portion FG of the first row is 0V or V2; thus, the potential of the second signal line S2(1) is set to 0V, thereby turning off all the second transistors 162 of the first row. On the other hand, if the potential VL is supplied to the word line WL(2), the potential of the floating gate portion FG of the second row is lower than the potential immediately after the data is written. Therefore, in order to prevent the second transistors 162 from turning on, the potential of the second signal line S2(2) is set low, similar to the potential of the word line WL(2). Thus, all the second transistors 162 are turned off.

[0309] Next, the description will be in Figure 21 The circuit in the diagram is used as the output potential in the case of a read circuit. Since the resistance between bit line BL(1) and source line SL(1) is low, a low potential is supplied to the time-controlled inverter, and the output D(1) is the signal High. Since the resistance between bit line BL(2) and source line SL(2) is high, a high potential is supplied to the time-controlled inverter, and the output D(2) is the signal Low.

[0310] For the operating voltage, we can assume, for example, that VDD = 2V, V2 = 1.5V, VH = 2V, and VL = -2V.

[0311] As described in this embodiment, the storage capacity of a semiconductor device can be increased by providing multiple storage cells. Note that the number and arrangement of storage cells, the number and arrangement of lines, the number and arrangement of drive circuits, etc., can be appropriately designed; therefore, they are not limited to the above-described structure.

[0312] The methods and structures described in this embodiment can be appropriately combined with any of the methods and structures described in other embodiments.

[0313] (Example 4)

[0314] In this embodiment, reference will be made to Figure 22A and 22B , Figures 23A to 23D ,as well as Figures 24A to 24C This describes the structure and manufacturing method of a semiconductor device according to another embodiment of the disclosed invention, different from Embodiments 1 and 2. Note that transistor 260, transistor 262, and capacitor 264 described in this embodiment can be used as transistor 160, transistor 162, and capacitor 164 in the circuit diagrams of the above embodiments, respectively.

[0315] <Cross-sectional and planar structures of semiconductor devices>

[0316] Figure 22A and 22B An example of the structure of a semiconductor device is shown. Figure 22A The cross-section of the semiconductor device is shown, while Figure 22B A plan view of a semiconductor device is shown. Here, Figure 22A Corresponding to along Figure 22B The cross-sections of lines C1-C2 and D1-D2 in the diagram. Figure 22B In the plan view, some components such as source / drain electrode 254 and line 256 are omitted to avoid complexity. Figure 22A and 22BThe semiconductor device shown includes a transistor 260 at the bottom, which contains a semiconductor material other than oxide semiconductor, and a transistor 262 at the top, which contains oxide semiconductor. Transistors formed using semiconductor materials other than oxide semiconductor can easily operate at high speeds. On the other hand, transistors containing oxide semiconductor can retain charge for a longer period of time due to their characteristics.

[0317] Although all transistors herein are n-channel transistors, it goes without saying that p-channel transistors can be used. Since the technical essence of the disclosed invention is the use of oxide semiconductors in transistor 262 to store data, there is no need to limit the specific structure of the semiconductor device to the structure described herein.

[0318] exist Figure 22A and 22B In the semiconductor device, transistor 262 and capacitor 264 are arranged to overlap with transistor 260. By employing... Figure 22B This planar layout allows for high integration. For example, given a minimum processing size of F, the storage cell area could be 15F. 2 Up to 25F 2 .

[0319] Figure 22A and 22B The semiconductor device in this embodiment differs from the semiconductor device described in the above embodiments in that the transistor 260 does not have a sidewall insulating layer. That is, Figure 22A and 22B The semiconductor device in this example does not include a sidewall insulating layer. Because no sidewall insulating layer is formed, no impurity region 114 is formed (e.g., see...). Figure 2A and 2B Therefore, without sidewall insulation, high integration is easier compared to when sidewall insulation is present. Furthermore, the manufacturing process is simplified compared to when sidewall insulation is present.

[0320] Figure 22A and 22B The semiconductor device in this embodiment differs from the semiconductor device described in the above embodiments in that it has an interlayer insulating layer in the transistor 260. That is, Figure 22A and 22BThe semiconductor device includes a hydrogen-containing interlayer insulating layer 225 in contact with the metal compound region 224 of transistor 260. By providing the hydrogen-containing interlayer insulating layer 225 in contact with the metal compound region 224, hydrogen can be supplied to transistor 260 to improve the characteristics of transistor 260. For example, a hydrogen-containing silicon nitride layer formed by plasma CVD is provided as the interlayer insulating layer 225. Furthermore, by using an insulating layer with a low hydrogen concentration therein as the interlayer insulating layer 226, hydrogen that could adversely affect transistor 262 can be prevented from entering transistor 262. For example, a silicon nitride layer formed by sputtering in the absence of hydrogen is provided as the interlayer insulating layer 226. When this structure is adopted, the characteristics of transistors 260 and 262 can be sufficiently improved. Note that in Figure 22A and 22B In this embodiment, the substrate 200, the element isolation insulating layer 206, the gate insulating layer 208, the gate electrode 210, the channel formation region 216, the high concentration impurity region 220, and the metal compound region 224 correspond to the substrate 100, the element isolation insulating layer 106, the gate insulating layer 108, the gate electrode 110, the channel formation region 116, the high concentration impurity region 120, and the metal compound region 124 in Example 1, respectively.

[0321] Figure 22A and 22B The semiconductor device in this embodiment differs from the semiconductor device in the above embodiment in that, in transistor 262, insulating layers 243a and 243b are respectively disposed between oxide semiconductor layer 244 and source electrode 242a, and between oxide semiconductor layer 244 and drain electrode 242b. By disposing insulating layers 243a and 243b in this way, the so-called gate capacitance formed by gate electrode 248a and source electrode 242a (or gate electrode 248a and drain electrode 242b) can be reduced, thereby improving the operating speed of transistor 262.

[0322] Note that, as in Embodiment 1, the source electrode 242a is formed directly on the gate electrode 210, thereby electrically connecting the lower transistor 260 and the upper transistor 262 to each other. This structure improves integration density compared to the case where additional electrodes and lines are provided. Furthermore, it simplifies the manufacturing process.

[0323] Although this embodiment describes all the different structures, a structure including any of these different structures may be used.

[0324] Methods for Manufacturing Semiconductor Devices

[0325] Next, an example of a method for manufacturing the above-described semiconductor device will be described. Reference will be made below. Figures 23A to 23D as well as Figures 24A to 24CThe steps performed after forming the lower transistor 260 and the method for manufacturing the upper transistor 262 are described. The lower transistor 260 can be formed using a method similar to that described in Embodiment 1. For details, please refer to Embodiment 1. Note that a capacitor 264 is provided in this embodiment. Furthermore, three interlayer insulating layers 225, 226, and 228 are formed in this embodiment to cover the transistor 260. Note that in this embodiment, the source / drain electrodes 130a and 130b of Embodiment 1 are not formed by the manufacturing process of the transistor 260, and for convenience, the structure in which the source / drain electrodes 130a and 130b are not formed is still referred to as transistor 260.

[0326] First, the lower transistor 260 is formed using the method described in Example 1, and then a portion of the top surface of the gate electrode 210 of the transistor 260 is removed. For the removal step, a polishing process such as CMP (chemical mechanical polishing) can be used. Therefore, portions of the interlayer insulating layers 225, 226, and 228 on the top surface of the gate electrode 210 are removed. Note that the surface subjected to this polishing process is sufficiently planarized, thereby facilitating the formation of electrodes, wires, insulating layers, semiconductor layers, etc., in subsequent steps.

[0327] Next, conductive layers are formed on the gate electrode 210 and the interlayer insulating layers 225, 226, and 227, and the conductive layers are selectively etched to form the source electrode and drain electrode 242a and 242b (see [link to documentation]). Figure 23A Here, the source electrode 242a is formed to be in direct contact with the gate electrode 210.

[0328] The conductive layers for forming the source and drain electrodes 242a and 242b can be formed using materials similar to those described in Example 1 for the source / drain electrodes 142a and 142b. Furthermore, the conductive layers can be etched using methods similar to those described in Example 1. For details, please refer to Example 1.

[0329] Next, an insulating layer is formed to cover the source and drain electrodes 242a and 242b, and the insulating layer is selectively etched, thereby forming insulating layers 243a and 243b on the source and drain electrodes 242a and 242b, respectively (see [reference]). Figure 23B ).

[0330] By providing insulating layers 243a and 243b, the parasitic capacitance formed between the gate electrode 248a and the source and drain electrodes 242a and 242b that are formed later can be reduced.

[0331] Subsequently, an oxide semiconductor layer 244 is formed to cover the source and drain electrodes 242a and 242b, and a gate insulating layer 246 is formed on the oxide semiconductor layer 244 (see [link]). Figure 23C ).

[0332] The oxide semiconductor layer 244 can be formed using the materials and methods of the oxide semiconductor layer 140 described in Example 1. Furthermore, it is desirable that the oxide semiconductor layer 244 undergo heat treatment (a first heat treatment). For details, please refer to Example 1.

[0333] The gate insulating layer 246 can be formed using the materials and methods of the gate insulating layer 138 described in Example 1. Furthermore, it is desirable that the formed gate insulating layer 246 undergo heat treatment (second heat treatment) in an inert gas atmosphere or an oxygen atmosphere. For details, please refer to Example 1.

[0334] Next, on the gate insulating layer 246, a gate electrode 248a is formed in a region overlapping with the region of the transistor 262 that serves as the channel formation region, and an electrode 248b is formed in a region overlapping with the source electrode 242a (see [link to documentation]). Figure 23D ).

[0335] Gate electrodes 248a and 248b can be formed by forming a conductive layer on the gate insulating layer 246 and then selectively etching the conductive layer. The conductive layer that will become gate electrodes 248a and 248b can be formed by a PVD method, such as sputtering, or a CVD method, such as plasma CVD. Details are similar to those for source electrode 242a, etc.; therefore, please refer to its description.

[0336] Next, interlayer insulating layers 250 and 252 are formed on the gate insulating layer 246, the gate electrode 248a, and the electrode 248b (see...). Figure 24A Interlayer insulating layers 250 and 252 can be formed using the materials and methods described in Example 1 for protective insulating layer 144 and interlayer insulating layer 146. For details, please refer to Example 1.

[0337] Note that it is desirable to form the interlayer insulating layer 252 with a planar surface. This is because, even with the reduction in the size of semiconductor devices, electrodes, wires, etc., can be easily formed on the interlayer insulating layer 252. Methods such as CMP (chemical mechanical polishing) can be used to planarize the interlayer insulating layer 252.

[0338] Subsequently, interlayer insulating layers 225, 226, and 228, oxide semiconductor layer 244, gate insulating layer 246, and interlayer insulating layers 250 and 252 are selectively etched to form an opening in the metal compound region 224 leading to transistor 260 (see [link]). Figure 24B Dry etching or wet etching can be used for this etching; dry etching is preferred for microfabrication.

[0339] A source / drain electrode 254 is formed to be embedded in the opening. Then, a line 256 is formed to connect to the source / drain electrode 254 (see [link]). Figure 24C ).

[0340] The source / drain electrode 254 can be formed, for example, by forming a conductive layer in the region including the opening using PVD, CVD, or the like, and then removing a portion of the conductive layer by etching, CMP, or the like. Specifically, it is possible to employ a method in which a titanium thin film is formed in the region including the opening using PVD, a titanium nitride thin film is formed using CVD, and a tungsten film is subsequently formed to embed into the opening. Here, the titanium film formed by PVD has the function of reducing the oxide film (e.g., a natural oxide film) formed on the surface on which the titanium film is formed, thereby reducing the contact resistance with the lower electrode (here, for example, the metal compound region 224). The titanium nitride film formed after the titanium film has a barrier function to prevent the diffusion of conductive materials. After forming the barrier film of titanium, titanium nitride, etc., a copper film can be formed by electroplating.

[0341] Line 256 can be formed as follows: a conductive layer is formed to contact the source / drain electrode 254, and then the conductive layer is selectively etched. This conductive layer can be formed by a PVD method, such as sputtering, or a CVD method, such as plasma CVD. Details are similar to those of the source electrode 242a, etc.

[0342] Thus, a semiconductor device comprising transistor 260, transistor 262, and capacitor 264 is completed.

[0343] In the semiconductor device described in this embodiment, for example, transistor 262 and capacitor 264 overlap with transistor 260, transistor 260 does not include a sidewall insulating layer, and source electrode 242a is formed directly on gate electrode 210; therefore, high integration is possible. Furthermore, the manufacturing process is simplified.

[0344] Furthermore, in the semiconductor device described in this embodiment, a hydrogen-containing interlayer insulating layer and an insulating layer with a reduced hydrogen concentration are used as interlayer insulating layers 225 and 226, respectively; thus, the characteristics of transistors 260 and 262 are improved. Due to insulating layers 243a and 243b, the so-called gate capacitance is reduced, and thereby the operating speed of transistor 262 is improved.

[0345] The features described in this embodiment make it possible to provide a semiconductor device with significantly superior properties.

[0346] The methods and structures described in this embodiment can be appropriately combined with any of the methods and structures described in other embodiments.

[0347] (Example 5)

[0348] This embodiment refers to Figures 10A to 10F Examples of electronic devices in which the semiconductor devices obtained in any of the above embodiments are installed are described. The semiconductor devices obtained in any of the above embodiments can store data when no power is supplied. Furthermore, no degradation occurs due to writing and erasing. Moreover, the writing and erasing operations are also high-speed. Therefore, it is possible to provide electronic devices with novel structures using the above-described semiconductor devices. Note that the semiconductor devices according to any of the above embodiments are mounted on integrated circuit boards, etc., and are installed inside various electronic devices.

[0349] Figure 10A It is a notebook computer that includes a semiconductor device according to any of the above embodiments and has a housing 301, a housing 302, a display portion 303, a keyboard 304, etc.

[0350] Figure 10B It is a personal digital assistant (PDA), which includes a semiconductor device according to any of the above embodiments, and is provided with a housing 311, a display portion 313, an external interface 315, operation buttons 314, etc. In addition, a pointer pen 312 is provided as an operation accessory.

[0351] As an example of electronic paper Figure 10C The e-book reader 320 includes a semiconductor device according to any of the above embodiments. The e-book reader 320 includes two housings—housing 321 and housing 323. Housings 321 and 323 are attached by a hinge 337, allowing the e-book reader 320 to be opened or closed along the hinge 337. With this structure, the e-book reader 320 can be used similarly to a paper book.

[0352] Display portion 325 is integrated into housing 321, while display portion 327 is integrated into housing 323. Display portion 325 and display portion 327 can display one image or different images. For example, in the case where display portion 325 and display portion 327 display different images, the right-hand display portion ( Figure 10C The display portion 325 in the middle can display text, while the display portion on the left ( Figure 10C The display section 327) can display graphics.

[0353] Figure 10CAn example is shown where the housing 321 is equipped with operating parts, etc. For example, the housing 321 includes a power supply 331, operation keys 333, a speaker 335, etc. Pages can be turned using the operation keys 333. Note that a keyboard, pointing device, etc., can also be provided on the surface of the housing where the display part is provided. In addition, external connection terminals (headphone terminals, USB terminals, terminals that can be connected to various cables such as AC adapters and USB cables, etc.), recording media insertion parts, etc., can be provided on the back or side of the housing. Furthermore, the e-book reader 320 may have the function of an electronic dictionary.

[0354] Furthermore, the e-book reader 320 can wirelessly send and receive data. Through wireless communication, it can purchase and download desired book data from an e-book server.

[0355] Note that e-paper can be applied to devices in any field, as long as they can display data. Furthermore, besides e-book readers, e-paper can be used in posters, advertisements in vehicles such as trains, displays on various cards such as credit cards, and more.

[0356] Figure 10D This refers to a cellular phone that includes a semiconductor device according to any of the above embodiments. The cellular phone includes two housings—housing 340 and housing 341. Housing 341 includes a display panel 342, a speaker 343, a microphone 344, a pointing device 346, a camera lens 347, an external connection terminal 348, etc. Furthermore, housing 341 includes a solar cell unit 349 for charging the cellular phone, an external storage slot 350, etc. Additionally, an antenna is integrated into housing 341.

[0357] Display panel 342 is used as a touchpad, and Figure 10D The ground is indicated by a dotted line, and multiple operation keys 345 are displayed as images. Note that the cellular phone is equipped with a boost circuit to increase the output voltage of the solar cell unit to the required voltage for each circuit. In addition to the above structure, the cellular phone may also incorporate contactless IC chips, small storage devices, etc.

[0358] The display orientation of the display panel 342 can be appropriately changed according to the usage mode. Furthermore, since the camera lens 347 is mounted on the same surface as the display panel 342, the cellular phone can be used as a video phone. The speaker 343 and microphone 344 can be used not only for voice calls but also for video phone calls, recording, and sound playback. Additionally, as... Figure 10D The housings 340 and 341 shown are slidable, so that one overlaps the other; thus, the size of the cellular phone can be reduced, making the cellular phone portable.

[0359] The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable, thereby enabling the cellular phone to be charged or to perform data communication. Furthermore, by inserting a recording medium into the external storage slot 350, the cellular phone can handle the storage and transfer of large amounts of data. In addition to the above functions, infrared communication and television reception functions are also available.

[0360] Figure 10E It is a digital camera that includes a semiconductor device according to any of the above embodiments. The digital camera includes a main body 361, a display portion A 367, an eyepiece 363, an operation switch 364, a display portion B 365, a battery 366, etc.

[0361] Figure 10F This is a television set including the semiconductor device according to any of the above embodiments. The television set 370 has a display portion 373 integrated in a housing 371. Images can be displayed on the display portion 373. Note that here, the housing 371 is supported by a bracket 375.

[0362] The television 370 can be operated using the operating switch on the housing 371 or a separate remote control 380. The operating keys 379 on the remote control 380 can be used to control the channels and volume, thereby controlling the image displayed on the display section 373. Furthermore, the remote control 380 may have a display section 377, in which information output from the remote control 380 is displayed.

[0363] Note that the television set 370 is preferably equipped with a receiver, modem, etc. Using this receiver, general television broadcasts can be received. Furthermore, when the display device is connected to a communication network via a modem or without a cable, one-way (from transmitter to receiver) or two-way (between transmitter and receiver, between receivers, etc.) data communication can be performed.

[0364] The structures and methods described in this embodiment can be appropriately combined with any of the structures and methods described in other embodiments.

[0365] (Example 1)

[0366] In this example, the results obtained by measuring the cutoff current of a transistor comprising a highly purified oxide semiconductor will be described.

[0367] First, considering the very small cutoff current of transistors including highly purified oxide semiconductors, transistors with a channel width of 1m that is wide enough are fabricated, and the cutoff current is measured. Figure 25 The results are shown, obtained by measuring the cutoff current of a transistor with a channel width W of 1 m. Figure 25In the diagram, the horizontal axis represents the gate voltage VG, while the vertical axis represents the drain current ID. With a drain voltage VD of +1V or +10V and a gate voltage VG in the range of -5V to -20V, the transistor's cutoff current was found to be less than or equal to 1 × 10⁻⁶, which serves as the detection limit. -13 A. Furthermore, it was found that the transistor's cutoff current (per unit channel width (1 μm)) was less than or equal to 1 A / μm (1 × 10⁻⁶). -18 A / μm).

[0368] Next, the results obtained by more accurately measuring the cutoff current of transistors comprising highly purified oxide semiconductors will be described. As mentioned above, it was found that the cutoff current of transistors comprising highly purified oxide semiconductors is less than or equal to 1 × 10⁻⁶, which is the measurement limit of the measuring instrument. -13 A. Here, the results obtained by measuring a more accurate cutoff current (less than or equal to the detection limit of the measuring instrument in the above measurements) using components for characteristic evaluation will be described.

[0369] First, refer to Figure 26 Describe the components used for characteristic evaluation.

[0370] exist Figure 26 In the component used for characteristic evaluation, three measurement systems 800 are connected in parallel. Measurement system 800 includes capacitor 802, transistor 804, transistor 805, transistor 806, and transistor 808. Transistors comprising highly purified oxide semiconductors are used in each of transistors 804, 805, and 806.

[0371] In the measurement system 800, one of the source and drain terminals of transistor 804, one of the terminals of capacitor 802, and one of the source and drain terminals of transistor 805 are connected to a power supply (for supplying V2). The other of the source and drain terminals of transistor 804, one of the source and drain terminals of transistor 808, the other of the terminals of capacitor 802, and the gate terminal of transistor 805 are connected to each other. The other of the source and drain terminals of transistor 808, one of the source and drain terminals of transistor 806, and the gate terminal of transistor 806 are connected to a power supply (for supplying V1). The other of the source and drain terminals of transistor 805 and the other of the source and drain terminals of transistor 806 are connected to each other. Furthermore, an output terminal is provided.

[0372] The potential Vext_b2, used to control the on and off states of transistor 804, is supplied to the gate terminal of transistor 804. The potential Vext_b1, used to control the on and off states of transistor 808, is supplied to the gate terminal of transistor 808. The potential Vout is output from the output terminal.

[0373] Next, a method for measuring current using components for characteristic evaluation will be described.

[0374] First, the initial period in which a potential difference is applied to measure the cutoff current will be outlined. In the initial period, a potential Vext_b1 for turning on transistor 808 is input to the gate terminal of transistor 808, while potential V1 is supplied to node A, which is the node connected to the other of the source and drain terminals of transistor 804 (i.e., the node connected to one of the source and drain terminals of transistor 808, the other of the terminals of capacitor 802, and the gate terminal of transistor 805). Here, potential V1 is, for example, a high potential. Transistor 804 is off.

[0375] Then, the potential Vext_b1 used to turn on transistor 808 is input to the gate terminal of transistor 808, thereby turning off transistor 808. After transistor 808 is turned off, the potential V1 is set low. Transistor 804 remains off. Potential V2 is the same as V1. Thus, the initial cycle is completed. In the state after the initial cycle is completed, a potential difference is generated between node A and one of the source and drain terminals of transistor 804, and similarly, a potential difference is generated between node A and the other of the source and drain terminals of transistor 808. Thus, charge flows slightly through transistors 804 and 808. In other words, a cutoff current is generated.

[0376] Next, the measurement period of the cutoff current will be outlined. During the measurement period, the potential of one of the source and drain terminals of transistor 804 (i.e., V2) and the potential of the other of the source and drain terminals of transistor 808 (i.e., V1) are set low and fixed. On the other hand, the potential of node A is not fixed during the measurement period (node ​​A is in a floating state). Therefore, charge flows through transistor 804, and the amount of charge held at node A changes over time. Furthermore, as the amount of charge held at node A changes, the potential of node A changes. That is, the output potential Vout of the output terminal also changes.

[0377] Figure 27 The time series diagram shows the relationship between the potentials in the initial period when a potential difference is applied and in subsequent measurement periods.

[0378] In the initial cycle, firstly, the potential Vext_b2 is set to the high potential (turning on transistor 804). This changes the potential of node A to V2, a low potential (VSS). Next, Vext_b2 is set to the low potential (turning off transistor 804), thus turning off transistor 804. Then, the potential Vext_b1 is set to the high potential (turning on transistor 808). This changes the potential of node A to V1, a high potential (VDD). Finally, Vext_b1 is set to the low potential (turning off transistor 808). Therefore, node A becomes floating, and the initial cycle is complete.

[0379] In subsequent measurement cycles, potentials V1 and V2 are each set to potentials that cause charge to flow to or from node A. Here, potentials V1 and V2 are low potentials (VSS). Note that the output circuit must be operated when measuring the output potential Vout; therefore, in some cases, V1 is temporarily set to a high potential (VDD). The period during which V1 is at a high potential (VDD) is set to be short enough not to affect the measurement.

[0380] When a potential difference is applied as described above to begin the measurement cycle, the amount of charge held at node A changes over time, and therefore, the potential of node A changes. This means that the potential of the gate terminal of transistor 805 changes, and therefore the output potential Vout of the output terminal also changes over time.

[0381] The following describes a method for calculating the cutoff current based on the obtained output potential Vout.

[0382] Before calculating the cutoff current, the potential V at node A should be obtained in advance. A The relationship between the output potential Vout and the output potential Vout. Therefore, the potential V of node A can be obtained from the output potential Vout. A Based on the above relationship, the potential V of node A is... A The output potential Vout can be expressed as a function of the following equation.

[0383] [Equation 1]

[0384] V A =F(Vout)

[0385] Using the potential V of node A A Capacitor C connected to node A A The charge Q at node A is expressed by the following equation, along with the constant (const). A Here, capacitor C is connected to node A. A It is the sum of the capacitance of capacitor 802 and the capacitance of other capacitors.

[0386] [Equation 2]

[0387] Q A =C A V A +const

[0388] The current I at node A is obtained by differentiating the charge flowing towards node A with respect to time. A Therefore, the current I at node A A Expressed by the following equation.

[0389] [Equation 3]

[0390]

[0391] Therefore, based on the capacitance C connected to node A A The current I at node A is obtained by using the output potential Vout of the output terminal. A .

[0392] The above method can be used to calculate the leakage current (cutoff current) flowing between the source and drain of a cutoff transistor.

[0393] In this example, transistors 804, 805, 806, and 808 are fabricated using highly purified oxide semiconductors, with a channel length L of 10 μm and a channel width W of 50 μm. In the parallel-arranged measurement systems 800, capacitors 802a, 802b, and 802c have capacitance values ​​of 100 fF, 1 pF, and 3 pF, respectively.

[0394] Note that the measurement according to this example is performed assuming VDD = 5V and VSS = 0V. During the measurement period, the potential V1 is essentially set to VSS, and only set to VDD for 100 milliseconds in a period of 10 to 300 seconds, and Vout is measured. Furthermore, the Δt used for the current I flowing through the element is approximately 30,000 seconds.

[0395] Figure 28 This illustrates the relationship between the output potential Vout and the elapsed time Time in current measurement. According to... Figure 28 The potential changes over time.

[0396] Figure 29 The cutoff current at room temperature (25°C) is shown, calculated based on the current measurements described above. Note that... Figure 29 The relationship between source-drain voltage V and cutoff current I is shown. According to... Figure 29 The cutoff current is approximately 40 zA / μm, with a source-drain voltage of 4V. When the source-drain voltage is 3.1V, the cutoff current is less than or equal to 10 zA / μm. Note that 1 zA equals 10 -21 A.

[0397] also, Figure 30 The cutoff current is shown in an environment with a temperature of 85°C, which is calculated based on the current measurement mentioned above. Figure 30 The relationship between source-drain voltage V and cutoff current I is shown in an environment of 85°C. According to... Figure 30 At a source-drain voltage of 3.1V, the cutoff current is approximately 100 ozA / μm.

[0398] This example demonstrates that the cutoff current is sufficiently small in transistors containing highly purified oxide semiconductors.

[0399] [Example 2]

[0400] The test measures the number of times data can be rewritten using a semiconductor device according to an embodiment of the disclosed invention. In this example, reference will be made to... Figure 31 Describe the test results.

[0401] The semiconductor device used for testing is one with Figure 15A The circuit structure in the circuit is a semiconductor device. Here, an oxide semiconductor is used as the transistor corresponding to transistor 162, and a capacitor with a capacitance of 0.33pF is used as the capacitor corresponding to capacitor 164.

[0402] The test is performed by comparing the initial storage window width with the storage window width after a predetermined number of repeated storage and write operations. This is done by applying 0V or 5V to the corresponding... Figure 15A The third line in the circuit is connected, and 0V or 5V is applied to the corresponding line. Figure 15A The fourth line is used to store and write data. When the potential corresponding to the fourth line is 0V, the transistor corresponding to transistor 162 (the write transistor) is turned off; thus, the potential supplied to node FG is maintained. When the potential corresponding to the fourth line is 5V, the transistor corresponding to transistor 162 (the write transistor) is turned on; thus, the potential corresponding to the third line is supplied to node FG.

[0403] The memory window width is one of the indicators of the characteristics of a memory device. Here, the memory window width represents the offset ΔVcg in the curve (Vcg-Id curve) between different memory states, showing the relationship between the potential Vcg corresponding to the fifth line and the leakage current Id of the transistor (read transistor) corresponding to transistor 160. The different memory states represent the state where 0V is applied to node FG (hereinafter referred to as the low state) and the state where 5V is applied to node FG (hereinafter referred to as the high state). That is, the memory window width can be checked by scanning the potential Vcg in the low and high states.

[0404] Figure 31 This shows that 1×10 writes were performed. 9The test results for the storage window width after this step. Note that in... Figure 31 In the diagram, the horizontal axis represents Vcg(V), while the vertical axis represents Id(A). According to... Figure 31 When data is written to 1×10 9 The storage window width remains unchanged after this, which means that at least 1×10 data will be written. 9 During subsequent cycles, the semiconductor devices do not degrade.

[0405] As described above, in the semiconductor device according to the embodiments of the disclosed invention, even when storing and writing data 1×10 9 The characteristics remain unchanged after this process, and the rewrite resistance is very high. In other words, it can be said that, according to the embodiments of the disclosed invention, a significantly reliable semiconductor device can be realized.

[0406] This application is based on Japanese Patent Application S / N.2009-249330, filed with the Japan Patent Office on October 29, 2009, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, Including the first transistor and the second transistor, The first transistor has a first channel formation region. The second transistor has a second channel formation region. The first channel formation region contains silicon. The second channel formation region has an oxide semiconductor. A first insulating layer is disposed above the first channel forming region. A second channel forming region is disposed above the first insulating layer. A second insulating layer is disposed above the second channel forming region. A first conductive layer, a second conductive layer, and a third conductive layer are disposed above the second insulating layer. One of the source and drain of the second transistor is electrically connected to the gate of the first transistor via the first conductive layer. One of the source and drain terminals of the first transistor is electrically connected to the second conductive layer. The other of the source and drain terminals of the first transistor is electrically connected to the third conductive layer. When viewed from above, the first channel forming area does not overlap with the second channel forming area. When viewed from above, the second conductive layer extends in the first direction. When viewed from above, the third conductive layer extends in the first direction. When viewed from above, the first conductive layer extends in a second direction that intersects the first direction.

2. The semiconductor device of claim 1, wherein... When viewed from above, the gate of the second transistor is configured to extend in the first direction.

3. A semiconductor device comprising a plurality of circuits arranged in a matrix. in, The circuit includes a first transistor, a second transistor, and a capacitor. The first transistor has a first semiconductor layer including a first channel formation region. The second transistor has a second semiconductor layer including a second channel formation region. The first channel formation region contains silicon. The second channel formation region has an oxide semiconductor. The first conductive layer, which functions as the source or drain electrode of the second transistor, is connected to the upper surface of the second conductive layer, which functions as the gate electrode of the first transistor, and has a region that functions as an electrode of the capacitor. When viewed from above, the capacitor has a region that overlaps with the gate electrode of the first transistor. The second semiconductor layer has a region that overlaps with the first conductive layer and is electrically connected to the second conductive layer via the first conductive layer.

4. A semiconductor device comprising a plurality of circuits arranged in a matrix. in, The circuit includes a first transistor, a second transistor, and a capacitor. The first transistor has a first semiconductor layer including a first channel formation region. The second transistor has a second semiconductor layer including a second channel formation region. The first channel formation region contains silicon. The second channel formation region has an oxide semiconductor. The first conductive layer, which functions as the source or drain electrode of the second transistor, is connected to the upper surface of the second conductive layer, which functions as the gate electrode of the first transistor, and has a region that functions as an electrode of the capacitor. When viewed from above, the capacitor has a region that overlaps with the gate electrode of the first transistor. When viewed from above, the gate electrode of the first transistor does not overlap with the gate electrode of the second transistor. The second semiconductor layer has a region that overlaps with the first conductive layer and is electrically connected to the second conductive layer via the first conductive layer.

5. A semiconductor device comprising a plurality of circuits arranged in a matrix. in, The circuit includes a first transistor, a second transistor, and a capacitor. The first transistor has a first semiconductor layer including a first channel formation region. The second transistor has a second semiconductor layer including a second channel formation region. The first channel formation region contains silicon. The second channel formation region has an oxide semiconductor. The first conductive layer, which functions as the source or drain electrode of the second transistor, is connected to the upper surface of the second conductive layer, which functions as the gate electrode of the first transistor, and has a region that functions as an electrode of the capacitor. When viewed from above, the capacitor has a region that overlaps with the gate electrode of the first transistor. Viewed from above, the second semiconductor layer is configured to overlap with the gate electrode of the capacitor and the first transistor. The second semiconductor layer has a region that overlaps with the first conductive layer and is electrically connected to the second conductive layer via the first conductive layer.

6. A semiconductor device comprising a plurality of circuits arranged in a matrix. in, The circuit includes a first transistor, a second transistor, and a capacitor. The first transistor has a first semiconductor layer including a first channel formation region. The second transistor has a second semiconductor layer including a second channel formation region. The first channel formation region contains silicon. The second channel formation region includes an oxide semiconductor. The first conductive layer, which functions as the source or drain electrode of the second transistor, is connected to the upper surface of the second conductive layer, which functions as the gate electrode of the first transistor, and has a region that functions as an electrode of the capacitor. When viewed from above, the capacitor has a region that overlaps with the gate electrode of the first transistor. When viewed from above, the gate electrode of the first transistor does not overlap with the gate electrode of the second transistor. Viewed from above, the second semiconductor layer is configured to overlap with the gate electrode of the capacitor and the first transistor. The second semiconductor layer has a region that overlaps with the first conductive layer and is electrically connected to the second conductive layer via the first conductive layer.

7. A semiconductor device comprising a plurality of circuits arranged in a matrix. in, The circuit includes a first transistor, a second transistor, and a capacitor. The first transistor has a first channel formation region. The second transistor has a second channel formation region. The first channel formation region contains silicon. The second channel formation region has an oxide semiconductor layer. The upper surfaces of the source and drain electrodes of the second transistor are respectively connected to the oxide semiconductor layer. The gate electrode of the second transistor is disposed above the oxide semiconductor layer, separated by a gate insulating layer.

8. A semiconductor device comprising a plurality of circuits arranged in a matrix. in, The circuit includes a first transistor, a second transistor, and a capacitor. The first transistor has a first channel formation region. The second transistor has a second channel formation region. The first channel formation region contains silicon. The second channel formation region has an oxide semiconductor layer. The upper and side surfaces of the source and drain electrodes of the second transistor are respectively in contact with the oxide semiconductor layer. The gate electrode of the second transistor is configured to overlap the oxide semiconductor layer through the gate insulating layer of the second transistor.

9. The semiconductor device of claim 7 or 8, wherein The first channel formation region is formed in the semiconductor layer.

10. The semiconductor device of claim 7 or 8, wherein The first channel formation region is formed on a single-crystal silicon substrate.

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