Electronic system device and method of starting thereof

Abstract

An electronic system device includes a power generation device that generates a power supply voltage, a substrate bias generation circuit connected to the power generation device, a memory circuit, a monitoring circuit, and a capacitor connected to the substrate bias generation circuit via a switch. The substrate bias generation circuit generates a substrate bias voltage from the power supply voltage, and supplies electric charge to the capacitor based on the substrate bias voltage when the switch is in an on state. The capacitor stores accumulated electric charge based on the substrate bias voltage when the switch is in an off state. The substrate bias generation circuit adds to the held electric charge based on the substrate bias voltage when the switch is in the on state, and declares a reverse bias voltage. The substrate bias generation circuit supplies the reverse bias voltage to the memory circuit.

Description

[0001] Cross-references to related applications

[0002] The publication of Japanese Patent Application No. 2019-191713, filed on October 21, 2019, including its description, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a method for starting an electronic system device and to an electronic system device. Background Technology

[0004] Energy harvesting (environmental power generation) technology is known, in which electricity is obtained from energy such as sunlight, vibration, and heat, and electronic systems are driven by electricity. These electronic systems include semiconductor devices and power generation devices.

[0005] The publicly available technologies listed below exist.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 8-36070

[0007] Patent Document 1 discloses a solar cell clock, which includes a solar cell, two capacitors, and watch circuitry. Patent Document 1 discloses a clock circuit driven by the charge stored in the capacitors for rapid startup upon activation. Summary of the Invention

[0008] Patent Document 1 discloses that when the clock circuit consumes a large amount of power at startup, this power consumption may not be compensated for by the charge stored in the capacitor for rapid startup. Therefore, solar cell clocks suffer from the problem of not being able to stably complete the startup operation. Other objects and novel features will become apparent from the description and drawings in this specification.

[0009] According to one embodiment, the present invention is as follows.

[0010] An electronic system device includes: a power generation device that generates a first power supply voltage and supplies it to a first power node; a substrate bias generation circuit connected to the power generation device via the first power node and generating a substrate bias voltage based on the first power supply voltage; a first memory circuit connected to the power generation device via the first power node and configured with a field-effect transistor; a first control switch connected to the substrate bias generation circuit; a first capacitor connected to the first control switch via a second power node and receiving the substrate bias voltage from the substrate bias generation circuit; and a power monitoring circuit connected to the first power node and controlling the first control switch based on the voltage of the first power node. When the power monitoring circuit sets the first control switch to the ON state, the substrate bias generation circuit stores charge in the first capacitor based on the substrate bias voltage. When the power monitoring circuit sets the first control switch to the OFF state, the first capacitor retains the accumulated charge. When the power monitoring circuit sets the first control switch to the ON state, the substrate bias generation circuit adds charge to the retained charge based on the substrate bias voltage to obtain a reverse bias voltage through the injected charge. Furthermore, the substrate bias generation circuit supplies a reverse bias voltage to the well region of the field-effect transistor.

[0011] According to another embodiment, the present invention is as follows.

[0012] An electronic system device includes: a power generation device that generates a first power supply voltage and supplies the first power supply voltage to a first power node; a power switch connected to the power generation device via the first power node; a substrate bias generation circuit connected to the power switch via a second power node and generating a substrate bias voltage based on the first power supply voltage; a memory circuit connected to the second power node and configured with an SOTB transistor; a control switch connected to the substrate bias generation circuit; a first capacitor connected to the first control switch via a third power node and receiving a substrate bias voltage from the substrate bias generation circuit; a first power monitoring circuit connected to the first power node and controlling the power switch based on the voltage of the first power node; and a second power monitoring circuit connected to the second power node and controlling the control switch based on the voltage of the second power node. When the second power monitoring circuit sets the control switch to an on state, the substrate bias generation circuit accumulates charge in the first capacitor based on the substrate bias voltage. When the second power monitoring circuit sets the control switch to an off state, the first capacitor retains the accumulated charge. When the second power monitoring circuit sets the control switch to the ON state, the held charge is injected with charge based on the substrate bias voltage, so as to obtain a reverse bias voltage through the injected charge.

[0013] The substrate bias generation circuit supplies a reverse bias voltage to the well region of the SOTB transistor.

[0014] According to yet another embodiment, the present invention is as follows.

[0015] A method for starting up an electronic system device, the electronic system device comprising: a power generation device that generates a first power supply voltage and supplies the first power supply voltage to a first power node; a substrate bias generation circuit connected to the power generation device via the first power node and generating a first substrate bias voltage based on the first power supply voltage; a memory circuit connected to the power generation device via the first power node and including an n-type SOTB transistor; a first control switch connected to the substrate bias generation circuit; a first capacitor connected to the first control switch via a second power node and receiving the first substrate bias voltage from the substrate bias generation circuit; and a power monitoring circuit connected to the first power node and controlling the first control switch based on the voltage of the first power node. The method for starting up the electronic system device includes step (a), whereby, when the power monitoring circuit sets the first control switch to an on state, the substrate bias generation circuit accumulates charge in the first capacitor based on the first substrate bias voltage. The method for starting up the electronic system device includes step (b), whereby, after step (a), when the power monitoring circuit sets the first control switch to an off state, the charge accumulated in step (a) is stored in the first capacitor. The startup method of the electronic system device includes step (c): after step (b), when the power monitoring circuit sets the first control switch to the ON state, charge is injected and added to the charge held in the substrate bias generation circuit by step (b) based on a first substrate bias voltage, and a first reverse bias voltage is obtained based on the injected charge. The startup method of the electronic system device includes step (d): supplying the first reverse bias voltage to the well region of the n-type SOTB transistor through the substrate bias generation circuit.

[0016] According to embodiments, a startup method and an electronic system device can be provided for stably performing startup operations. Attached Figure Description

[0017] Figure 1 This is a block diagram illustrating an exemplary configuration of an electronic system device according to a first embodiment.

[0018] Figure 2 This is a cross-sectional view illustrating an exemplary SOTB transistor structure.

[0019] Figure 3 This is a diagram used to explain an exemplary startup sequence for an electronic system device.

[0020] Figure 4This is a diagram used to explain exemplary operation of an electronic system device according to a first embodiment.

[0021] Figure 5 This is a block diagram illustrating an example configuration of an electronic system device based on a comparative example.

[0022] Figure 6 This is a diagram used to explain an operational example of an electronic system device based on a comparative example.

[0023] Figure 7 This is a block diagram illustrating an exemplary configuration of an electronic system device according to a second embodiment.

[0024] Figure 8 This is a diagram used to explain exemplary operation of an electronic system device according to a second embodiment.

[0025] Figure 9 This is a block diagram illustrating an exemplary configuration of an electronic system device according to a third embodiment. Detailed Implementation

[0026] In the following embodiments, the description will be divided into multiple parts or embodiments when convenient and necessary. However, unless otherwise stated, these parts or embodiments are not independent of each other and involve some or all of the following: modified examples, other parts or embodiments, application content, specific description, supplementary description, etc. In the following embodiments, unless specifically indicated and explicitly limited in principle to a specific number, the number of components, etc. (including the number, value, quantity, range, etc. of elements) is not limited to a specific number, but may be not less than or equal to a specific number.

[0027] Furthermore, in the following embodiments, unless specifically stated or obviously necessary in principle, the constituent elements (including operating steps, etc.) are not essential. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, they should have substantially similar shapes, etc., unless specifically indicated or not obvious in principle.

[0028] First Embodiment

[0029] Figure 1 This is a block diagram illustrating an exemplary configuration of an electronic system device 1 according to a first embodiment.

[0030] Electronic system device 1 includes a power generation device P, a semiconductor device SC1, a capacitor (second capacitor) C1, a capacitor (first capacitor) C2, and a capacitor (first capacitor and second capacitor) C3. Electronic system device 1 is used, for example, in a wristwatch.

[0031] The electronic system device 1 is driven by energy harvesting technology. Capacitors C1, C2, and C3 are not limited to capacitors and can be capacitors. Figure 1 In the semiconductor device SC1, capacitors C1, C2, and C3 are formed on the outside of the semiconductor device SC1, but they can also be formed on the inside of the semiconductor device SC1.

[0032] Semiconductor device SC1 includes a power supply circuit ECH1, a central processing unit (hereinafter referred to as CPU) 10, a memory circuit (first memory circuit) ME1, a memory circuit (second memory circuit) ME2, a control circuit CNT1, a substrate bias generation circuit VBC, a switch (control switch) SW2, a switch (control switch) SW3, a monitoring circuit (substrate bias monitoring circuit) M2, and a monitoring circuit (substrate bias monitoring circuit) M3. The power supply circuit ECH1 has a diode D, a monitoring circuit (power monitoring circuit) M1, and a switch (power switch) SW1. The power supply circuit ECH1 supplies operating power to the CPU 10, memory circuits ME1 and ME2, control circuit CNT1, and substrate bias generation circuit VBC.

[0033] Furthermore, the semiconductor device SC1 has a low-speed mode (first mode), a high-speed mode (second mode), and a standby mode (third mode) for low-speed operation. In the high-speed mode (second mode), the semiconductor device SC1 operates at a higher speed than in the low-speed mode, and in the standby mode (third mode), certain circuit blocks in the CPU 10 are in a sleep state. In other words, when the semiconductor device SC1 operates in the low-speed mode or standby mode, the electronic system device 1 operates in a low-power mode. On the other hand, when the semiconductor device SC1 operates in the high-speed mode, the electronic system device 1 operates in a normal operating mode.

[0034] The power supply circuit ECH1, CPU 10, memory circuits ME1 and ME2, control circuit CNT1, and substrate bias generation circuit VBC include multiple field-effect transistors (FETs). FETs are, for example, SOTB (Silicon-on-Thin Buried Oxide) transistors or MOS (Metal-Oxide-Semiconductor) transistors. SOTB transistors refer to transistors using a substrate in which a thin insulating film and a thin silicon film are formed on a silicon substrate. MOS transistors are different from SOTB transistors and are called body transistors. p-type FETs include p-type SOTB transistors and p-type MOS transistors. n-type FETs include n-type MOSSOTB transistors and n-type MOS transistors.

[0035] Specifically, CPU 10, memory circuit ME1, and memory circuit ME2 include SOTB transistors, and the substrate bias generation circuit VBC and control circuit CNT1 include MOS transistors. CPU 10, memory circuit ME1, and memory circuit ME2 can be formed using MOS transistors. Furthermore, other circuits can be constructed using SOTB transistors.

[0036] The power generation device P generates a power supply voltage (first power supply voltage) VSC and supplies the power supply voltage VSC to the semiconductor device SC1. The generation current ISC supplied from the power generation device P is, for example, 5μA. Figure 1 The power generation device P shown is a solar cell. However, the power generation device P is not limited to solar cells and can be a small power source capable of supplying only small power, such as a thermocouple or an antenna for receiving weak radio waves. The electronic system device 1 is powered by energy harvesting technology.

[0037] The power generation device P is connected to diode D, and supplies the power supply voltage VSC to the power node (first power node) N1 via diode D. Diode D is used to prevent backflow.

[0038] Monitoring circuit M1 is connected to power generation device P via power node N1 and diode D. Switch SW1 is connected to power generation device P via power node N1 and diode D. Capacitor C1 is connected to power generation device P via power node N1 and diode D. Capacitor C1 is positioned between power node N1 and ground GND. That is, each of monitoring circuit M1, switch SW1, and capacitor C1 is connected in parallel to power node N1.

[0039] The charge output by the power generation device P is stored in capacitor C1 via diode D and power node N1. In other words, the power supply voltage VSC generated by the power generation device P is charged into capacitor C1. As a result, capacitor C1 receives the power supply voltage VSC as the power supply voltage VCC-EH.

[0040] Monitoring circuit M1 monitors the voltage of power node N1 and controls switches SW1, SW2, and SW3, as well as control circuit CNT1, based on the voltage of power node N1. Furthermore, monitoring circuit M1 has a threshold voltage (second threshold voltage) Vst and a threshold voltage (third threshold voltage) Vre as threshold voltages. The value of threshold voltage Vst is higher than the value of threshold voltage Vre.

[0041] Monitoring circuit M1 supplies control signal CS1 to switches SW1, SW2, and SW3. Switches SW1, SW2, and SW3 are set to an on or off state according to control signal CS1. Specifically, when the voltage of power node N1 reaches the threshold voltage Vst, monitoring circuit M1 outputs control signal CS1 (e.g., a high-level control signal CS1). As a result, based on control signal CS1, switches SW1, SW2, and SW3 are set from the off state to the on state. When the voltage of power node N1 drops and thus the voltage of power node N1 reaches the threshold voltage Vre, monitoring circuit M1 outputs control signal CS1 (e.g., a low-level control signal CS1). As a result, based on control signal CS1, switches SW1, SW2, and SW3 are set from the on state to the off state.

[0042] The monitoring circuit M1 supplies a reset signal RS1 to the control circuit CNT1. Specifically, when the voltage of power node N1 drops and thus the voltage of power node N1 reaches the threshold voltage Vre, the monitoring circuit M1 outputs the reset signal RS1 (e.g., a low-level reset signal RS1) to the control circuit CNT1. As a result, based on the reset signal RS1, the control circuit CNT1 sets its internal register RE and the internal registers (not shown) of other circuit blocks of the semiconductor device SC1 (e.g., CPU 10, memory circuits ME1 and ME2, and substrate bias generation circuit VBC) to a reset state (reset operation). The reset state means that even if the operating power supply voltage is supplied to each circuit block, each circuit block cannot be activated.

[0043] On the other hand, in the monitoring circuit M1, when the voltage of power node N1 is higher than the threshold voltage Vre, the control circuit CNT1 releases the reset state of the corresponding circuit block based on the reset signal RS1 (e.g., a high-level reset signal RS1). Therefore, if the operating power supply voltage is supplied to each circuit block, each circuit block can be activated.

[0044] Power node N2 is connected to power node N1 via switch SW1. CPU 10, memory circuits ME1 and ME2, control circuit CNT1, and substrate bias generation circuit VBC are connected to power node N2. Therefore, CPU 10, memory circuits ME1 and ME2, control circuit CNT1, and substrate bias generation circuit VBC are connected to power generation device P and capacitor C1 via switch SW1 and power nodes N1 and N2. When switch SW1 is turned on, CPU 10, memory circuits ME1 and ME2, control circuit CNT1, and substrate bias generation circuit VBC receive power supply voltage VCC_MCU based on power supply voltage VSC and power supply voltage VCC_EH. In other words, when switch SW1 is turned on, CPU 10, memory circuits ME1 and ME2, control circuit CNT1, and substrate bias generation circuit VBC receive at least the power supply voltage VSC generated by power generation device P as power supply voltage VCC_MCU via switch SW1 and power nodes N1 and N2. CPU 10, memory circuits ME1 and ME2, control circuit CNT1, and substrate bias generation circuit VBC operate based on the power supply voltage VCC_MCU. Therefore, the power supply voltage VCC_MCU is the operating power supply voltage for those circuit blocks.

[0045] On the other hand, when switch SW1 is turned off, power nodes N1 and N2 are disconnected via switch SW1. Therefore, power supply voltages VSC and VCC-EH are not supplied to CPU 10, memory circuits ME1 and ME2, control circuit CNT1, and substrate bias generation circuit VBC. As a result, these circuit blocks cannot operate based on power supply voltage VCC_MCU.

[0046] Figure 1 The resistor element RMCU is shown as a load on the semiconductor device SC1, and the resistor element RMCU is connected to the power node N2.

[0047] CPU 10, control circuit CNT1, memory circuit ME1 and memory circuit ME2 are connected via a bus not shown in the figure.

[0048] CPU 10 reads the user program from memory circuit ME2 via the bus and executes the program accordingly. CPU 10 outputs the instruction signal MCN to control circuit CNT1.

[0049] The memory circuit ME1 is, for example, a static random access memory. The CPU 10 stores main data (e.g., processing result data according to the user program) in the memory circuit ME1 via a bus.

[0050] The memory circuit ME2 is an electrically rewritable non-volatile memory such as flash memory. The memory circuit ME2 stores the user program and initial values. The initial values ​​are values ​​that indicate the initialization of the aforementioned internal registers (e.g., trim values). The user program is a program that executes after the initial setup, and this program is created by the user. The memory circuit ME2 is connected via input / output circuitry (…). Figure 1 (Not shown) is connected to the outside of semiconductor device SC1. As a result, the contents and initial values ​​of the user program can be rewritten from the outside of semiconductor device SC1. Figure 1 In this process, the memory circuit ME2 is formed inside the semiconductor device SC1, but it can also be formed outside the semiconductor device SC1.

[0051] The control circuit CNT1 has an internal register RE. The control circuit CNT1 receives a reset signal RS1 supplied from the monitoring circuit M1, an instruction signal MCN supplied from the CPU 10, and an instruction signal from (…). Figure 1 The input / output circuit (not shown) supplies a high-speed clock signal HCK and a low-speed clock signal LCK.

[0052] The control circuit CNT1 selects either the high-speed clock signal HCK or the low-speed clock signal LCK based on the instruction signal MCN, and supplies the selected signal to the CPU 10 as the operation clock signal OCK. In other words, the control circuit CNT1 specifies the high-speed mode, low-speed mode, or standby mode through the instruction signal MCN. In the high-speed mode, the control circuit CNT1 supplies the high-speed clock signal HCK to the CPU 10 as the operation clock signal OCK. In the low-speed mode, the control circuit CNT1 supplies the low-speed clock signal LCK to the CPU 10 as the operation clock signal OCK. In the standby mode, the control circuit CNT1 prevents the operation clock signal OCK from being supplied to the CPU 10.

[0053] CPU 10 operates synchronously with the operating clock signal OCK. Therefore, when the low-speed clock signal LCK is supplied as the operating clock signal OCK, the operating speed of CPU 10 decreases. When the high-speed clock signal HCK is supplied as the operating clock signal OCK, the operating speed of CPU 10 increases.

[0054] Therefore, in low-speed mode, the operating speed of CPU 10 decreases, and the power consumed by CPU 10 decreases. Consequently, the power consumed by electronic system device 1 decreases. Furthermore, in standby mode, since the operating clock signal OCK is not supplied to CPU 10, the operating clock signal OCK is in a sleep state in a specific circuit within CPU 10. Therefore, the power consumed by electronic system device 1 decreases.

[0055] The control circuit CNT1 generates a mode specification signal VC for controlling the substrate bias generation circuit VBC based on the command signal MCN, and supplies the mode specification signal VC to the substrate bias generation circuit VBC. The substrate bias generation circuit VBC is controlled by the mode specification signal VC.

[0056] When the specified signal MCN supports low-speed mode or standby mode, the substrate bias generation circuit VBC generates substrate bias voltages VBN and VBP based on the mode specification signal VC. VBN is the negative input voltage of the power supply voltage VCC_MCU, while VBP is the positive input voltage. In other words, the substrate bias generation circuit VBC generates substrate bias voltages VBN and VBP from at least the power supply voltage VSC supplied from the power generation device P.

[0057] On the other hand, when the specified signal MCN supports high-speed mode, the substrate bias generation circuit VBC does not generate substrate bias voltages VBN and VBP from the power supply voltage VCC_MCU.

[0058] The substrate bias generation circuit VBC is a common charge pump circuit device. For example, if the power supply voltage VCC_MCU is defined as "VDD" and the bias change is "VBB", then the substrate bias voltage VBN is voltage (-VBB), and the substrate bias voltage VBP is voltage (VDD+VBB).

[0059] The substrate bias generation circuit VBC is connected to capacitor C2 via switch SW2 and power node N3. Specifically, the substrate bias generation circuit VBC is connected to switch SW2. Switch SW2 is connected to capacitor C2 via power node N3. Capacitor C2 is positioned between power node N3 and ground GND.

[0060] When switch SW2 is turned on via monitoring circuit M1, substrate bias generation circuit VBC supplies substrate bias voltage VBN to capacitor (first capacitor) C2 via switch SW2 and power node N3. In other words, substrate bias generation circuit VBC stores charge (negative charge) in capacitor C2 based on substrate bias voltage VBN via switch SW2 and power node (second power node) N3. Thus, capacitor C2 accumulates charge and obtains substrate bias voltage VBN. On the other hand, when switch SW2 is turned off via monitoring circuit M1, substrate bias voltage VBN is not supplied to capacitor C2 via switch SW2 and power node N3.

[0061] A monitoring circuit (substrate bias monitoring circuit) M2 is connected in parallel with capacitor C2 to power node N3. Monitoring circuit M2 monitors the voltage of power node N3 and, based on the voltage of power node N3, controls the substrate bias generation circuit VBC. Monitoring circuit M2 has a threshold voltage (target voltage, first threshold voltage) VbackN. When the voltage of power node N3 reaches the threshold voltage VbackN, monitoring circuit M2 supplies control signal CS2 to the substrate bias generation circuit VBC. The substrate bias generation circuit VBC supplies the substrate bias voltage VBN, which reaches the threshold voltage VbackN, as a reverse bias voltage VNS to the well regions of the n-type field-effect transistors in CPU 10, memory circuit ME1, and memory circuit ME2. In other words, the substrate bias generation circuit VBC supplies the substrate bias voltage VBN, which reaches the threshold voltage VbackN, to the well regions of the n-type SOTB transistors in CPU 10, memory circuit ME1, and memory circuit ME2.

[0062] The substrate bias generation circuit VBC is connected to capacitor C3 via switch SW3 and power node N4. Specifically, the substrate bias generation circuit VBC is connected to switch SW3. Switch SW3 is connected to capacitor C3 via power node N4. Capacitor C3 is positioned between power node N4 and ground GND.

[0063] When switch SW3 is turned on by monitoring circuit M1, substrate bias generation circuit VBC supplies substrate bias voltage VBP to capacitor C3 via switch SW3 and power node N4. In other words, substrate bias generation circuit VBC stores charge (positive charge) in capacitor C3 based on substrate bias voltage VBP via switch SW3 and power node N4. Thus, capacitor C3 accumulates charge and obtains substrate bias voltage VBP. On the other hand, when switch SW3 is turned off by monitoring circuit M1, substrate bias voltage VBP is not supplied to capacitor C3 via switch SW3 and power node N4.

[0064] A monitoring circuit (substrate bias monitoring circuit) M3 is connected in parallel with capacitor C3 to power node N4. Monitoring circuit M3 monitors the voltage of power node N4 and, based on the voltage of power node N4, controls the substrate bias generation circuit VBC. Monitoring circuit M3 has a threshold voltage (target voltage) VbackP. When the voltage of power node N4 reaches the threshold voltage (target voltage) VbackP, monitoring circuit M3 supplies a control signal CS3 to the substrate bias generation circuit VBC. Then, the substrate bias generation circuit VBC supplies the substrate bias voltage VBP, which reaches the threshold voltage VbackP, as a reverse bias voltage VPS to the well regions of the p-type field-effect transistors in CPU 10, memory circuit ME1, and memory circuit ME2. In other words, the substrate bias generation circuit VBC supplies the substrate bias voltage VBP, which reaches the threshold voltage VbackP, to the well regions of the p-type SOTB transistors in CPU 10, memory circuit ME1, and memory circuit ME2.

[0065] When reverse bias voltages VPS and VNS are supplied to CPU 10, memory circuit ME1, and memory circuit ME2, semiconductor device SC1 consumes less power. Therefore, the power dissipation of electronic system device 1 is reduced, and electronic system device 1 operates in a low-power consumption mode.

[0066] In the foregoing discussion, when the specified signal MCN supports low-speed mode or standby mode, the substrate bias generation circuit VBC begins to generate substrate bias voltages VBN and VBP based on the mode specification signal VC. However, the substrate bias generation circuit is not limited to this configuration, and it can begin generating substrate bias voltages VBN and VBP upon receiving the power supply voltage VCC_MCU, regardless of the mode specification signal VC. In this configuration, in low-speed mode or standby mode, the substrate bias generation circuit VBC begins to provide a reverse bias voltage VNS to the CPU 10, memory circuit ME1, and memory circuit ME2 based on both the mode specification signal VC and the control signal CS3. Similarly, in slow or standby mode, the substrate bias generation circuit VBC begins to supply a reverse bias voltage VPS to the CPU 10, memory circuit ME1, and memory circuit ME2 based on both the mode specification signal VC and the control signal CS3.

[0067] Additionally, the threshold voltages Vst, Vre, VbackN, and VbackP are different from each other.

[0068] Figure 2 This is a cross-sectional view illustrating an exemplary SOTB transistor structure.

[0069] exist Figure 2In the diagram, the p-type SOTB transistor PT and the n-type SOTB transistor NT are shown as SOTB transistors. The SOTB transistor has a deep n-type well region DNW, which is formed on the p-type substrate SU.

[0070] In a p-type SOTB transistor PT, an n-type well region NW is formed on the n-type well region DNW. An insulating film BOX is formed on the n-type well region NW. A semiconductor layer SL1 is formed on the n-type well region NW, thus sandwiching the insulating film BOX in between. In the semiconductor layer SL1, p+ type regions SR1 and DR1 are formed; SR1 serves as the source region of the p-type SOTB transistor PT, and DR1 serves as the drain region. In the semiconductor layer SL1, a channel region CH1 is formed between the p+ type regions SR1 and DR1. The channel region CH1 is substantially free of impurities. The impurity density of the channel region CH1 is 3 × 10⁻⁶. 17 cm -3 Or less. The gate electrode G1 of the p-type SOTB transistor PT is formed on the channel region CH1 via the gate insulating film DL1.

[0071] In an n-type SOTB transistor NT, a p-type well region PW is formed on the n-type well region DNW. An insulating film BOX is formed on the p-type well region PW. A semiconductor layer SL2 is formed on the p-type well region PW, thus sandwiching the insulating film BOX in between. In the semiconductor layer SL2, n+ type regions SR2 and DR2 are formed; SR2 serves as the source region of the n-type SOTB transistor NT, and DR2 serves as the drain region. In the semiconductor layer SL2, a channel region CH2 is formed between the n+ type regions SR2 and DR2. The channel region CH2 is substantially free of impurities. The impurity density of the channel region CH2 is 3 × 10⁻⁶. 17 cm -3 Or less. The gate electrode G2 of the n-type SOTB transistor NT is formed on the channel region CH2 via the gate insulating film DL2.

[0072] The thickness of the insulating film BOX is, for example, about 10 nanometers. In the p-type SOTB transistor PT, a substrate bias generation circuit VBC is formed on the n-type well region NW for the n+ type region NR, which supplies a reverse bias voltage VPS to the n-type well region NW. In the n-type SOTB transistor NT, a substrate bias generation circuit VBC is formed on the p-type well region PW for the p+ type region PR, which supplies a reverse bias voltage VNS to the p-type well region PW. Additionally, the p-type SOTB transistor PT, the n-type SOTB transistor NT, the p+ type region PR, and the n+ type region NR are separated by a device isolation film STI.

[0073] For an n-type SOTB transistor NT, setting the reverse bias voltage VNS to a negative voltage increases the absolute value of the threshold voltage, thereby reducing the leakage current. On the other hand, for a p-type SOTB transistor PT, setting the reverse bias voltage VPS to a positive voltage increases the absolute value of the threshold voltage, thus reducing the leakage current. The leakage current changes exponentially with the reverse bias voltage.

[0074] Therefore, by controlling the threshold voltages of the p-type SOTB transistor PT and the n-type SOTB transistor NT through the reverse bias voltages VNS and VPS, leakage current can be suppressed. As a result, the power consumed by the CPU 10, memory circuit ME1, and memory circuit ME2, which include the p-type SOTB transistor PT and the n-type SOTB transistor NT, can be reduced.

[0075] Figure 3 This is a diagram illustrating an exemplary activation sequence of electronic system device 1.

[0076] The power generation device P generates a power supply voltage VSC and supplies the power supply voltage VSC to the semiconductor device SC1 and the capacitor C1.

[0077] Therefore, as Figure 3 As shown, the power supply voltage VCC_EH is increased. When the power supply voltage VCC_EH reaches the threshold voltage Vst, the monitoring circuit M1 sets the switch SW1 from the off state to the on state. As a result, the control circuit CNT1 starts and reads the initial value from the memory circuit ME2 (the read initial value).

[0078] Based on the initial value read from memory circuit ME2, control circuit CNT1 sets the internal register RE and other circuit blocks (e.g., CPU 10, memory circuits ME1 and ME2, substrate bias generation circuit VBC) in control circuit CNT1 from the reset state to the initial state (initialization of each circuit block).

[0079] After the registers of the corresponding circuit block are initialized, CPU 10 reads the user program from memory circuit ME2 and executes it. The user program initialization operation is performed first. Subsequently, according to the user program, reverse bias voltages VPS and VNS are supplied to CPU 10, memory circuit ME1, and memory circuit ME2. Therefore, electronic system device 1 enters a low-power mode, thereby reducing the current consumed by electronic system device 1. Thus, the current consumed by electronic system device 1 is high until electronic system device 1 enters low-power mode. In other words, the current consumed by semiconductor device SC1 is high until semiconductor device SC1 switches to low-speed mode or standby mode.

[0080] Figure 4 This is a diagram used to explain exemplary operation of the electronic system device 1 according to the first embodiment. Figure 4 A startup method for electronic system device 1 is shown, exemplarily including power supply voltage VCC_EH, power supply voltage VCC_MCU, substrate bias voltage VBN, substrate bias voltage VBP, and current ICC.

[0081] like Figure 4 As shown, at time T0, the power generation device P generates a power supply voltage VSC and supplies it to the semiconductor device SC1 and capacitor C1. This initiates the startup operation of the electronic system device 1. Capacitor C1 receives the power supply voltage VSC as its power supply voltage VCC-EH.

[0082] At time T1, the power supply voltage VCC_EH reaches the threshold voltage Vst. The voltage at power node N1 reaches the threshold voltage Vst, and the monitoring circuit M1 sets switches SW1, SW2, and SW3 from the off state to the on state. The power supply voltage VCC_EH is supplied from power node N1 to power node N2 via switch SW1. As a result, the power supply voltage VCC_MCU rises and becomes the same value as the power supply voltage VCC_EH. Additionally, the current ICC flows to CPU 10, memory circuits ME1 and ME2, control circuit CNT1, and substrate bias generation circuit VBC.

[0083] At time T1, the power supply voltage VCC-MCU rises, thereby initiating the operation of CPU 10, memory circuits ME1 and ME2, control circuit CNT1, and substrate bias generation circuit VBC. As a result, as described above, control circuit CNT1 reads initial values ​​from memory circuit ME2 and initializes the corresponding circuit blocks. After the initialization of the corresponding circuit blocks is complete, CPU 10 reads the user program from memory circuit ME2 and executes it. According to the user program, CPU 10 supplies the designated signal MCN, corresponding to slow mode or standby mode, to control circuit CNT1. Control circuit CNT1 supplies the mode designation signal VC to substrate bias generation circuit VBC, and substrate bias generation circuit VBC begins generating substrate bias voltages VBN and VBP from the power supply voltage VCC-MCU.

[0084] At time T1, as switch (first control switch) SW2 is switched from the off state to the on state by monitoring circuit M1, substrate bias voltage (first substrate bias voltage) VBN is supplied to capacitor (first capacitor) C2 via switch SW2 and power node (second power node) N3. Similarly, as switch SW3 is switched from the off state to the on state by monitoring circuit M1, substrate bias voltage (second substrate bias voltage) VBP is supplied to capacitor (second capacitor) C3 via switch (second control switch) SW3 and power node (third power node) N4. Therefore, when switch SW2 is set to the on state, capacitor C2 accumulates charge based on substrate bias voltage VBN. When switch SW3 is set to the on state, capacitor C3 accumulates charge based on substrate bias voltage VBP. Therefore, as Figure 4 As shown, the substrate bias voltage VBN begins to decrease, while the substrate bias voltage VBP begins to increase.

[0085] After time T1, the current consumed by semiconductor device SC1 can be compensated by two factors: the generated current ISC supplied from power generation device P, and the charge charged in capacitor C1. Figure 4 Exemplary operation is not shown, but the substrate bias generation circuit VBC continuously supplies the substrate bias voltage VBN to capacitor C2 via switch SW2 and power node N3, and the voltage at power node N3 reaches the threshold voltage VbackN. Similarly, the substrate bias generation circuit VBC continuously supplies the substrate bias voltage VBP to capacitor C3 via switch SW3 and power node N4, and the voltage at power node N4 reaches the threshold voltage VbackP. As a result, monitoring circuit M2 outputs control signal CS2 to substrate bias generation circuit VBC, and monitoring circuit M3 outputs control signal CS3 to substrate bias generation circuit VBC.

[0086] Therefore, the substrate bias generation circuit VBC supplies a reverse bias voltage (first reverse bias voltage) VNS to the n-type field-effect transistor well regions in CPU 10, memory circuit ME1, and memory circuit ME2. Similarly, the substrate bias generation circuit VBC supplies a reverse bias voltage (second reverse bias voltage) VPS to the p-type field-effect transistor well regions in CPU 10, memory circuit ME1, and memory circuit ME2. As a result, the power consumed by CPU 10, memory circuit ME1, and memory circuit ME2 is reduced, and the startup operation of electronic system device 1 is successfully completed.

[0087] On the other hand, after time T1, the current consumed by semiconductor device SC1 may not be compensated by the following two factors: the generated current ISC supplied from power generation device P, and the charge charged in capacitor C1. Figure 4 An exemplary startup operation of the electronic system device 1 is shown in the figure.

[0088] At time T1, the current ICC reaches the current value Istart, and the current ICC flows to the corresponding circuit block of semiconductor device SC1. As a result, the power supply voltage VCC_EH begins to decrease.

[0089] At time T2, the power supply voltage VCC-EH drops and reaches the threshold voltage Vre. Similarly, the power supply voltage VCC-MCU also reaches the threshold voltage Vre.

[0090] Since the voltage at power node N1 has reached the threshold voltage Vre, monitoring circuit M1 outputs a reset signal RS1 to control circuit CNT1. As described above, based on the reset signal RS1, the internal register RE in control circuit CNT1, as well as the internal registers in other circuit blocks of semiconductor device SC1 (e.g., CPU 10, memory circuits ME1 and ME2, and substrate bias generation circuit VBC), are set from the initialization state to the reset state (reset operation).

[0091] Since the voltage at power node N1 has reached the threshold voltage Vre, monitoring circuit M1 switches SW1, SW2, and SW3 from the ON state to the OFF state. As a result, power supply voltages VSC and VCC-EH are no longer supplied from power node N1 to power node N2. Therefore, at time T2, power supply voltage VCC-MCU drops to 0V. Similarly, current ICC flows to resistor element RMCU and drops to 0A.

[0092] Furthermore, as switches SW2 and SW3 are switched from the ON state to the OFF state, capacitors C2 and C3 are disconnected from the substrate bias generation circuit VBC. As a result, capacitor C2 retains the charge accumulated from time T1 to time T2, and capacitor C3 stores the charge accumulated from time T1 to time T2. In other words, when switch SW2 is set to the OFF state, capacitor C2 stores the charge accumulated from time T1 to time T2. When switch SW3 is set to the OFF state, capacitor C3 stores the charge stored from time T1 to time T2.

[0093] Since power nodes N1 and N2 are disconnected by switch SW1 after time T2, the load connected to capacitor C1 decreases. As a result, capacitor C1 begins to recharge by power generation device P, and the power supply voltage VCC-EH rises. Therefore, since the voltage at power node N1 exceeds the threshold voltage Vre, the reset state of the corresponding circuit block is released.

[0094] At time T3, the power supply voltage VCC_EH reaches the threshold voltage Vst. Consequently, the monitoring circuit M1 again switches SW1, SW2, and SW3 from the off state to the on state. As a result, the power supply voltage VCC_MCU rises, becoming the same value as the power supply voltage VCC_EH, and the current ICC flows to each circuit block. Thus, the CPU 10, memory circuits ME1 and ME2, control circuit CNT1, and substrate bias generation circuit VBC are driven again.

[0095] At time T3, similar to time T1, the initialization operation of the corresponding circuit block begins, and CPU 10 executes the user program. As a result, control circuit CNT1 supplies the mode specification signal VC to substrate bias generation circuit VBC, and similar to time T1, substrate bias generation circuit VBC begins to generate substrate bias voltages VBN and VBP from the power supply voltage VCC-MCU.

[0096] At time T3, similar to time T1, the substrate bias generation circuit VBC begins to supply the substrate bias voltage VBN to capacitor C2 via switch SW2 and power node N3. Similarly, the substrate bias generation circuit VBC begins to supply the substrate bias voltage VBP to capacitor C3 via switch SW3 and power node N4. That is, in capacitor C2, the substrate bias generation circuit VBC also adds charge to the charge held between time T2 and time T3 based on the substrate bias voltage VBN. Similarly, in capacitor C3, the substrate bias generation circuit VBC also adds charge to the charge held between time T2 and time T3 based on the substrate bias voltage VBP. In other words, when switch SW2 is set to the ON state, the substrate bias generation circuit VBC adds additional charge to the charge held by capacitor C2 based on the substrate bias voltage VBN. When switch SW3 is set to the ON state, the substrate bias generation circuit VBC adds additional charge to the charge held by capacitor C3 based on the substrate bias voltage VBP. Therefore, as Figure 4 As shown, the substrate bias voltage VBN begins to decrease again, and the substrate bias voltage VBP begins to increase.

[0097] At time T4, the substrate bias voltage VBN reaches the threshold voltage VbackN. That is, the voltage based on the charge in capacitor C2 reaches the threshold voltage VbackN. As a result, the voltage at power node N3 reaches the threshold voltage VbackN, and the monitoring circuit M2 outputs the voltage of the control signal CS2 to the substrate bias generation circuit VBC.

[0098] Similarly, at time T4, the substrate bias voltage VBP reaches the threshold voltage VbackP. That is, the voltage based on the charge in capacitor C3 reaches the threshold voltage VbackP. As a result, the voltage at power node N4 reaches the threshold voltage VbackP, and the monitoring circuit M3 outputs the voltage of the control signal CS3 to the substrate bias generation circuit VBC.

[0099] Therefore, as described above, the substrate bias generation circuit VBC supplies the substrate bias voltage VBN, which reaches the threshold voltage VbackN, as the reverse bias voltage VNS to the n-type field-effect transistor well regions in CPU 10, memory circuit ME1, and memory circuit ME2. The substrate bias generation circuit VBC also supplies the substrate bias voltage VBP, which reaches the threshold voltage VbackP, as the reverse bias voltage VPS to the p-type field-effect transistor well regions in CPU 10, memory circuit ME1, and memory circuit ME2. As a result, the electronic system device 1 operates in a low-power mode, and the power consumption of CPU 10, memory circuit ME1, and memory circuit ME2 is reduced. Therefore, the electronic system device 1 can successfully complete the startup operation. Additionally, the current consumption of semiconductor device SC1 is reduced, and the current ICC is maintained at the value of current Iregular.

[0100] Therefore, electronic system device 1 can complete the startup operation through two drive operations and one reset operation. Electronic system device 1 can stably complete the startup sequence by repeating the drive operation and reset operation multiple times.

[0101] That is, as described above, the startup method of the electronic system device 1 includes the following first step, second step, third step, and fourth step. In the first step, capacitor C2 accumulates charge based on the substrate bias voltage VBN, and capacitor C3 accumulates charge based on the substrate bias voltage VBP. In the second step following the first step, each of capacitors C2 and C3 stores the charge stored in the first step. In the third step following the second step, the substrate bias generation circuit VBC obtains a reverse bias voltage VNS based on the injected charge on the charge held by capacitor C2 in the second step. Similarly, the substrate bias generation circuit VBC also adds charge to the charge held by capacitor C3 in the second step based on the substrate bias voltage VBP, and obtains a reverse bias voltage VNP based on the added charge. In the fourth step following the third step, when the voltage at power node N3 reaches the threshold voltage VbackN, the substrate bias generation circuit VBC supplies a reverse bias voltage VNS to the well regions of the field-effect transistors (n-type SOTB transistors) in CPU 10, memory circuit ME1, and memory circuit ME2. Similarly, when the voltage at power node N4 reaches the threshold voltage VbackP, the substrate bias generation circuit VBC supplies a reverse bias voltage VNP to the well regions of the field-effect transistors (p-type SOTB transistors) in CPU 10, memory circuit ME1, and memory circuit ME2.

[0102] Additionally, even during the startup operation of electronic system device 1, when it transitions to a reset operation, capacitors C2 and C3 retain their charge. Therefore, the time required for the substrate bias voltage VBP to reach the threshold voltage VbackP is shortened, and similarly, the time required for the substrate bias voltage VBP to reach the threshold voltage VbackP is shortened. As a result, the substrate bias generation circuit VBC can immediately supply each of the reverse bias voltages VNS and VPS to the well regions of the field-effect transistors in CPU 10, memory circuit ME1, and memory circuit ME2. Therefore, electronic system device 1 immediately enters a low-power mode, thereby reducing the power dissipation of electronic system device 1.

[0103] <<Comparison Examples>>

[0104] Figure 5 This is a block diagram illustrating an example configuration of electronic system device 2 according to a comparative example.

[0105] Electronic system device 2 includes a power generation device P, a semiconductor device SC2, capacitors C1, C2, and C3. Since the configuration of electronic system device 2 is the same as that of electronic system device 1 except for the semiconductor device SC2, the same reference numerals are given, and their descriptions are omitted.

[0106] Semiconductor device SC2 has a power supply circuit ECH2 instead of the power supply circuit ECH1 of semiconductor device SC1. Power supply circuit ECH2 has a monitoring circuit M4 instead of the monitoring circuit M1 of power supply circuit ECH1. Power supply circuit ECH2 has a switch SW4 instead of the switch SW1 of power supply circuit ECH1. In power supply circuit ECH2, the configuration is the same as that of power supply circuit ECH1 except for the monitoring circuit M4 and the switch SW4, therefore its description is omitted.

[0107] Furthermore, compared to semiconductor device SC1, semiconductor device SC2 does not include switches SW2 and SW3. Since the remaining configuration in semiconductor device SC2 is the same as that in semiconductor device SC1, the same reference numerals are assigned, and their description is omitted.

[0108] Monitoring circuit M4 monitors the voltage of power node N1 and controls switch SW4 and control circuit CNT1 based on the voltage of power node N1. Monitoring circuit M4 supplies control signal CS4 to switch SW4. Monitoring circuit M4 supplies reset signal RS1 to control circuit CNT1 in the same manner as monitoring circuit M1. Similar to monitoring circuit M1, monitoring circuit M4 has threshold voltages Vst and Vre.

[0109] Similar to switch SW1, switch SW4 is connected to power generation device P via power node N1 and diode D. Switch SW4 is positioned between power node N1 and power node N2. Switch SW4 is identical to switch SW1 except that it is controlled based on control signal CS4 instead of control signal CS1. Additionally, when switch SW4 is in the ON state, similar to semiconductor device SC1, CPU 10, memory circuits ME1 and ME2, control circuit CNT1, and substrate bias generation circuit VBC receive power supply voltage VCC_MCU via power node N2 based on power supply voltages VSC and VCC_EH, and operate based on power supply voltage VCC_MCU. On the other hand, when switch SW4 is OFF, power nodes N1 and N2 are disconnected by switch SW4.

[0110] Figure 6 This is a diagram illustrating an example of the operation of electronic system device 2 in the comparative example. Similar to... Figure 4 , Figure 6 A startup method for electronic system device 2 is shown, including exemplary power supply voltage VCC_EH, power supply voltage VCC_MCU, power supply voltage VCC_MCU, substrate bias voltage VBN, substrate bias voltage VBP, and current ICC.

[0111] At time T10, identical to time T0, the power generation device P supplies the power supply voltage VSC to the semiconductor device SC2 and capacitor C1. This initiates the startup operation of the electronic system device 2. Capacitor C1 receives the power supply voltage VSC as its power supply voltage VCC-EH.

[0112] At time T11, when the power supply voltage VCC_EH reaches the threshold voltage Vst, switch SW4 is switched from the off state to the on state by control signal CS4. As a result, similar to time T1, CPU 10, memory circuits ME1 and ME2, control circuit CNT1, and substrate bias generation circuit VBC begin to be driven. Similar to time T1, CPU 10 executes the user program. Therefore, the substrate bias generation circuit VBC begins to generate substrate bias voltages VBN and VBP from the power supply voltage VCC_MCU.

[0113] Furthermore, at time T11, similar to time T1, the substrate bias generation circuit VBC supplies the substrate bias voltage VBN to capacitor C2, and capacitor C2 accumulates charge. Similarly, the substrate bias generation circuit VBC supplies the substrate bias voltage VBP to capacitor C3, and capacitor C3 stores charge. Therefore, the substrate bias voltage VBN begins to decrease, and the substrate bias voltage VBP begins to increase.

[0114] After time T11, similar to the first embodiment, the current consumed by semiconductor device SC2 may not be compensated by either the generated current ISC supplied from power generation device P, or the charge charged in capacitor C1. An example of startup operation in this situation is... Figure 6 As shown in the image.

[0115] At time T11, similar to time T1, the current ICC reaches the current value Istart, and the current ICC flows to the corresponding circuit block of semiconductor device SC2. As a result, the power supply voltage VCC_EH begins to decrease.

[0116] At time T12, similar to time T2, the power supply voltage VCC_EH and power supply voltage VCC_MCU decrease, reaching the threshold voltage Vre.

[0117] As a result, because the voltage at power node N1 reaches the threshold voltage Vre, the monitoring circuit M4 sets switch SW4 from the ON state to the OFF state. Similar to time T2, the power supply voltage VCC_MCU and current ICC are reduced, and a reset operation is performed.

[0118] At time T12, unlike electronic system device 1, capacitors C2 and C3 of electronic system device 2 are connected to the substrate bias generation circuit VBC. At time T12, since the power supply voltage VCC_MCU is not supplied to the substrate bias generation circuit VBC, the substrate bias generation circuit VBC is not limited. As a result, leakage current is generated, and the charge accumulated in capacitors C2 and C3 escapes. The substrate bias voltages VBN and VBP, based on the charge in capacitors C2 and C3, change to 0V.

[0119] At time T13, the substrate bias voltages VBN and VBP reach 0V.

[0120] After time T13, since power nodes N1 and N2 are disconnected by switch SW4, the load connected to capacitor C1 decreases. As a result, capacitor C1 begins to recharge by power generation device P, and the power supply voltage VCC-EH rises. Therefore, at time T14, similar to time T11, monitoring circuit M4 again sets switch SW4 from the off state to the on state, the power supply voltage VCC_MCU rises, and current ICC flows to the corresponding circuit block.

[0121] The operation of electronic system device 2 after time T14 is repeated. Therefore, the substrate bias voltage VBN based on the charge in capacitor C2 cannot reach the threshold voltage VbackN. Similarly, the substrate bias voltage VBP based on the charge in capacitor C3 cannot reach the threshold voltage VbackP. Therefore, the substrate bias generation circuit VBC cannot supply the reverse bias voltages VNS and VPS to CPU 10, memory circuit ME1, and memory circuit ME2, and electronic system device 2 cannot transition to a low-power mode. In other words, the current draw of electronic system device 2 remains high. As a result, the startup operation of electronic system device 2 cannot be successfully completed.

[0122] On the other hand, as described above, even if the electronic system device 1 of the first embodiment transitions to a reset operation during the startup operation, capacitors C2 and C3 retain their charge. Therefore, the electronic system device 1 immediately transitions to a low-power mode. Compared to the electronic system device 2 of the comparative example, the electronic system device 1 of the first embodiment can stably execute the startup sequence and complete the startup operation.

[0123] Second Embodiment

[0124] Figure 7 This is a block diagram illustrating an exemplary configuration of an electronic system device 3 according to a second embodiment.

[0125] Electronic system device 3 includes a power generation device P, a semiconductor device SC3, capacitors C1, C2, and C3. Since the configuration of electronic system device 3, except for the semiconductor device SC3, is the same as that of electronic system device 1, the same reference numerals are given, and their descriptions are omitted.

[0126] Semiconductor device SC3 has a power supply circuit ECH3 instead of the power supply circuit ECH1 of semiconductor device SC1. Power supply circuit ECH3 has a monitoring circuit (power monitoring circuit) M5 instead of the monitoring circuit M1 of power supply circuit ECH1. Power supply circuit ECH3 has a switch (power switch) SW5 instead of the switch SW1 of power supply circuit ECH1. In power supply circuit ECH3, the configuration is the same as that of power supply circuit ECH1 except for monitoring circuit M5 and switch SW5, therefore its description is omitted.

[0127] Semiconductor device SC3 has switch (control switch) SW6 instead of switch SW2 in semiconductor device SC1. Furthermore, semiconductor device SC3 has switch (control switch) SW7 instead of switch SW3 in semiconductor device SC1. In semiconductor device SC3, the configuration is the same as that of semiconductor device SC1, except for the power supply circuit ECH3, switch SW6, and switch SW7; therefore, their description is omitted.

[0128] The monitoring circuit (power monitoring circuit) M5 is similar to monitoring circuit M1. Monitoring circuit M5 is connected to the power generation device P via power node N1 and diode D. Monitoring circuit M5 monitors the voltage of power node N1 and supplies control signal CS5 to switches SW5, SW6, and SW7. Therefore, based on control signal CS5, monitoring circuit M5 sets switches SW5, SW6, and SW7 to the on or off state. Monitoring circuit M5 supplies reset signal RS1 to control circuit CNT1 in the same manner as monitoring circuit M1.

[0129] Monitoring circuit M5 has threshold voltages VstH and VstL, replacing the threshold voltage (second threshold voltage) Vst of monitoring circuit M1. Threshold voltage VstL is lower than threshold voltage VstH. Similar to monitoring circuit M1, monitoring circuit M5 also has a threshold voltage (third threshold voltage) Vre as its threshold voltage. Threshold voltages VstH, VstL, Vre, VbackN, and VbackP are different from each other.

[0130] Unlike monitoring circuit M1, monitoring circuit M5 receives an external mode signal MO. Monitoring circuit M5 selects either threshold voltage VstH or threshold voltage VstL based on the external mode signal MO.

[0131] Specifically, monitoring circuit M5 selects threshold voltage VstH as the threshold voltage based on external mode signal MO (e.g., a high-level external mode signal MO). Therefore, the threshold voltage of monitoring circuit M5 is set to threshold voltage VstH. Then, when the voltage of power node N1 reaches the threshold voltage VstH, monitoring circuit M5 outputs control signal CS5 (e.g., a high-level control signal CS5), and switches SW5, SW6, and SW7 are set from the off state to the on state based on control signal CS5.

[0132] Monitoring circuit M5 selects threshold voltage VstL as the threshold voltage based on an external mode signal MO (e.g., a low-level external mode signal MO). Therefore, the threshold voltage of monitoring circuit M5 is set to threshold voltage VstL. Then, when the voltage at power node N1 reaches the threshold voltage VstL, monitoring circuit M5 outputs control signal CS5 (e.g., a high-level control signal CS5), and switches SW5, SW6, and SW7 are set from the off state to the on state based on control signal CS5. Therefore, based on the external mode signal MO, the value of the threshold voltage of monitoring circuit M5 changes from threshold voltage VstH to threshold voltage VstL.

[0133] Similar to monitoring circuit M1, when the voltage of power node N1 drops, monitoring circuit M5 outputs control signal CS5 (e.g., low-level control signal CS5), thereby causing the voltage of power node N1 to reach the threshold voltage Vre, and switches SW5, SW6 and SW7 are set from the on state to the off state based on control signal CS5.

[0134] Similar to monitoring circuit M1, when the voltage of power node N1 drops, monitoring circuit M5 outputs a reset signal RS1 to control circuit CNT1, thereby causing the voltage of power node N1 to reach the threshold voltage Vre. As a result, a reset operation is performed. On the other hand, similar to monitoring circuit M1, when the voltage of power node N1 is higher than the threshold voltage Vre, control circuit CNT1 releases the reset state of the corresponding circuit block.

[0135] Similar to switch SW1, switch SW5 is connected to power generation device P via power node N1 and diode D. Switch SW5 is positioned between power node N1 and power node N2. Switch SW5 is similar to switch SW1, except that switch SW5 is controlled based on control signal CS5 instead of control signal CS1.

[0136] When switch SW5 is turned on, CPU 10, memory circuit ME1, memory circuit ME2, control circuit CNT1, and substrate bias generation circuit VBC receive power supply voltage VCC_EH via power node N2 based on power supply voltage VSC and power supply voltage VCC_MCU. In other words, their circuit blocks at least receive power supply voltage VSC generated by power generation device P as power supply voltage VCC_MCU.

[0137] On the other hand, when switch SW5 is turned off, power nodes N1 and N2 are disconnected by switch SW5.

[0138] Similar to switch SW2, switch SW6 is positioned between the substrate bias generation circuit VBC and capacitor C2. Switch SW6 is similar to switch SW2, except that it is controlled by control signal CS5 instead of control signal CS1. Therefore, when switch SW6 is turned on by monitoring circuit M5, the substrate bias generation circuit VBC supplies the substrate bias voltage VBN to capacitor C2 via switch SW6 and power node N3. Conversely, when switch SW6 is turned off by monitoring circuit M5, the substrate bias voltage VBN is not supplied to capacitor C2 via switch SW6 and power node N3.

[0139] Similar to switch SW3, switch SW7 is positioned between the substrate bias generation circuit VBC and capacitor C3. Switch SW7 is similar to SW3, except that it is controlled by control signal CS5 instead of control signal CS1. Therefore, when switch SW7 is turned on by monitoring circuit M5, the substrate bias generation circuit VBC supplies the substrate bias voltage VBN to capacitor C3 via switch SW7 and power node N3. Conversely, when switch SW7 is turned off by monitoring circuit M5, the substrate bias voltage VBP is not supplied to capacitor C3 via switch SW7 and power node N3.

[0140] Figure 8 This is a diagram used to explain exemplary operation of the electronic system device 3 according to the second embodiment. Figure 8 It also shows in such Figure 4 An example of the startup method for electronic system device 3, including power supply voltage VCC_EH, power supply voltage VCC_MCU, substrate bias voltage VBN, and substrate bias voltage VBP. Similar to the startup operation of electronic system device 1, the startup steps of electronic system device 3 include the first step, second step, third step, and fourth step described above.

[0141] Figure 8The upper part illustrates an exemplary operation of electronic system device 3 when the threshold voltage of monitoring circuit M5 is set to threshold voltage VstL. Monitoring circuit M5 selects the threshold voltage VstL based on external mode signal MO. Therefore, when the power supply voltage VCC_EH reaches the threshold voltage VstL, monitoring circuit M5 sets switches SW5, SW6, and SW7 from the off state to the on state. Similar to electronic system device 1, electronic system device 3 begins the aforementioned drive operation, the initialization operation of the corresponding circuit blocks, and the actual operation of the user program. When the power supply voltage VCC_EH drops and reaches the threshold voltage Vre, monitoring circuit M5 sets switches SW5, SW6, and SW7 from the on state to the off state and outputs reset signal RS1 to control circuit CNT1. Electronic system device 3 begins the reset operation in the same manner as electronic system device 1. Other operations are the same as those of electronic system device 1, and therefore their description is omitted. Therefore, as Figure 8 As shown in the upper section, when the threshold voltage of the monitoring circuit M5 is the threshold voltage VstL, the electronic system device 3 can complete the startup operation through three drive operations and two reset operations.

[0142] on the other hand, Figure 8 The lower part illustrates an exemplary operation of electronic system device 3 when the threshold voltage of monitoring circuit M5 is set to threshold voltage VstH. Monitoring circuit M5 selects the threshold voltage VstH based on an external mode signal MO. In other words, monitoring circuit M5 changes from threshold voltage VstL to threshold voltage VstH based on the external mode signal MO. Therefore, when the power supply voltage VCC_EH reaches the threshold voltage VstH, monitoring circuit M5 sets switches SW5, SW6, and SW7 from the off state to the on state. Similar to electronic system device 1, electronic system device 3 begins the aforementioned drive operation, the initialization operation of the corresponding circuit blocks, and the user program. When the power supply voltage VCC_EH drops and reaches the threshold voltage Vre, monitoring circuit M5 sets switches SW5, SW6, and SW7 from the on state to the off state and outputs a reset signal RS1 to control circuit CNT1. Electronic system device 3 begins the reset operation in the same manner as electronic system device 1. Other operations are the same as those of electronic system device 1, and therefore their description is omitted. Therefore, as Figure 8 As shown in the lower part, when the threshold voltage of the monitoring circuit M5 is the threshold voltage VstH, the electronic system device 3 can complete the startup operation through two drive operations and one reset operation.

[0143] like Figure 8As shown, the voltage difference between the threshold voltage VstH and the threshold voltage Vre is greater than the voltage difference between the threshold voltage VstL and the threshold voltage Vre. Therefore, when the threshold voltage of the monitoring circuit M5 is the threshold voltage VstH, the switches SW5, SW6, and SW7 take longer to transition from the ON state to the OFF state than when the threshold voltage of the monitoring circuit M5 is the threshold voltage VstL. As a result, the substrate bias generation circuit VBC operates for a longer period of time, and the amount of charge supplied to capacitors C2 and C3 is greater. Therefore, compared to the threshold voltage VstL, for the threshold voltage VstH, the electronic system device 3 can reduce the number of drive and reset operations, thereby reducing the current drawdown caused by its operation.

[0144] Additionally, since electronic system device 3 can change the threshold voltage compared to electronic system device 1, it is suitable for various environments. For example, if the sunlight is low, the threshold voltage of monitoring circuit M5 is set to threshold voltage VstL. In this example, even if the amount of power supplied from power generation device P is low, monitoring circuit M5 can set switches SW5, SW6, and SW7 from the off state to the on state. As a result, electronic system device 3 can stably complete the startup sequence.

[0145] Third Embodiment

[0146] Figure 9 This is a block diagram illustrating an exemplary configuration of an electronic system device 4 according to a third embodiment.

[0147] Electronic system device 4 includes a power generation device P, a semiconductor device SC4, a capacitor (second capacitor) C1, a capacitor (capacitor) C2, a capacitor (first capacitor) C3, and a capacitor C4. Since the configuration of electronic system device 4, except for capacitor C4 and semiconductor device SC4, is the same as that of electronic system device 1, the same reference numerals are given, and their descriptions are omitted.

[0148] Semiconductor device SC4 has a power supply circuit ECH4 instead of the power supply circuit ECH1 of semiconductor device SC1. Power supply circuit ECH4 has a monitoring circuit (first power monitoring circuit) M6 instead of the monitoring circuit M1 of power supply circuit ECH1. Power supply circuit ECH4 has a switch (power switch) SW8 instead of the switch SW1 of power supply circuit ECH1. In power supply circuit ECH4, the configuration is the same as that of power supply circuit ECH1 except for monitoring circuit M6 and switch SW8, therefore its description is omitted.

[0149] Semiconductor device SC4 has switch (control switch) SW9 replacing switch SW2 of semiconductor device SC1. Semiconductor device SC4 has switch (control switch) SW10 replacing switch SW3 of semiconductor device SC1. Semiconductor device SC4 has control circuit CNT2 replacing control circuit CNT1 of semiconductor device SC1. The difference between semiconductor device SC4 and semiconductor device SC1 is that semiconductor device SC4 also has a monitoring circuit (second power supply monitoring circuit) M7. In semiconductor device SC4, the configuration is the same as that of semiconductor device SC1, except for power supply circuit ECH4, monitoring circuit M7, switch SW9, switch SW10, and control circuit CNT2, therefore its description is omitted.

[0150] Monitoring circuit M6 is similar to monitoring circuit M1, and is connected to power generation device P via power node N1 and diode D. Monitoring circuit M6 monitors the voltage at power node N1 and supplies control signal CS6 to switch SW8. Therefore, based on control signal CS6, monitoring circuit M6 sets switch SW8 to the on or off state. Similar to monitoring circuit M1, monitoring circuit M6 has threshold voltages Vst and Vre as threshold voltages.

[0151] When the voltage of power node N1 reaches the threshold voltage (second threshold voltage) Vst, monitoring circuit M6 outputs control signal CS6 (e.g., a high-level control signal CS6), and switch SW8 is switched from the off state to the on state based on control signal CS1. When the voltage of power node N1 drops, and thus the voltage of power node N1 reaches the threshold voltage (third threshold voltage) Vre, monitoring circuit M6 outputs control signal CS6 (e.g., a low-level control signal CS6), and switch SW8 is switched from the on state to the off state based on control signal CS6.

[0152] Similar to switch SW1, switch SW8 is connected to power generation device P via power node N1 and diode D. Switch SW8 is positioned between power node N1 and power node (second power node) N2. Switch SW8 is similar to switch SW1, except that, unlike switch SW1, switch SW8 is controlled based on control signal CS6 instead of control signal CS1.

[0153] Furthermore, when switch SW9 is set to the ON state, CPU 10, memory circuit ME1, memory circuit ME2, control circuit CNT2, monitoring circuit M7, and substrate bias generation circuit VBC receive power supply voltage VCC_MCU via power node N2 based on power supply voltage VSC and power supply voltage VCC_EH. In other words, their circuit blocks at least receive power supply voltage VSC generated by power generation device P as power supply voltage VCC_MCU.

[0154] On the other hand, when switch SW9 is turned off, power nodes N1 and N2 are disconnected by switch SW9.

[0155] Similar to switch SW2, switch SW9 is positioned between the substrate bias generation circuit VBC and capacitor (first capacitor) C2. Switch SW9 is similar to switch SW2, except that it is controlled by control signal CS7 instead of control signal CS1. Therefore, when switch SW9 is turned on by monitoring circuit M7, the substrate bias generation circuit VBC supplies the substrate bias voltage VBN to capacitor C2 via switch SW9 and power node (third power node) N3. Conversely, if switch SW9 is turned off by monitoring circuit M7, the substrate bias voltage VBN is not supplied to capacitor C2 via switch SW9 and power node N3.

[0156] Similar to switch SW3, switch SW10 is positioned between the substrate bias generation circuit VBC and capacitor (first capacitor) C3. Switch SW10 is similar to switch SW3, except that, unlike switch SW3, switch SW10 is controlled by control signal CS7 instead of control signal CS1. Therefore, when switch SW10 is turned on by monitoring circuit M7, the substrate bias generation circuit VBC supplies the substrate bias voltage VBP to capacitor C3 via switch SW10 and power node (third power node) N4. Conversely, when switch SW10 is turned off by monitoring circuit M7, the substrate bias voltage VBP is not supplied to capacitor C3 via switch SW10 and power node N4.

[0157] Capacitor C4 is connected to power node N2. Capacitor C4 is positioned between power node N2 and ground GND. Therefore, the power supply voltage VCC_MCU is supplied to capacitor C2 via power node N2, and capacitor C4 stores charge based on the power supply voltage VCC_MCU. Capacitor C4 thus receives the power supply voltage VCC_MCU. At least, capacitor C4 receives the power supply voltage VSC via power node N2 and stores charge based on the power supply voltage VSC, which is generated at least by the power generation device P.

[0158] Similar to control circuit CNT1, control circuit CNT2 is connected to power node N2 and has an internal register RE. Control circuit CNT2 is similar to control circuit CNT1, except that, unlike control circuit CNT1, control circuit CNT2 is controlled based on reset signal RS2 instead of reset signal RS1.

[0159] The monitoring circuit M7 is connected to the power node N2. In other words, the monitoring circuit M7 is connected to the power generation device P via diode D, power node N1, switch SW8, and power node N2.

[0160] Monitoring circuit M7 monitors the voltage at power node N2, i.e., the power supply voltage VCC-MCU. Based on the voltage at power node N2, monitoring circuit M7 controls switches SW9 and SW10, and control circuit CNT2. Monitoring circuit M7 supplies control signal CS7 to switches SW9 and SW10. Monitoring circuit M7 also supplies reset signal RS2 to control circuit CNT2. Monitoring circuit M7 has a threshold voltage (second threshold voltage) Vst and a threshold voltage (fourth threshold voltage) Vrem. The threshold voltage Vrem is higher than the threshold voltage Vre.

[0161] When the voltage at power node N2 rises and reaches the threshold voltage Vst, monitoring circuit M7 outputs control signal CS7 (e.g., a high-level control signal CS7), and switches SW9 and SW10 are switched from the off state to the on state based on control signal CS7. When the voltage at power node N2 falls and reaches the threshold voltage Vrem, monitoring circuit M7 outputs control signal CS7 (e.g., a low-level control signal CS7), and switches SW9 and SW10 are switched from the on state to the off state based on control signal CS7.

[0162] When the voltage at power node N2 drops and reaches the threshold voltage Vrem, monitoring circuit M7 outputs a reset signal RS2 (e.g., a low-level reset signal RS2) to control circuit CNT2. As a result, control circuit CNT2, based on the reset signal RS2, sets the internal registers in control circuit CNT2 and other circuit blocks of semiconductor device SC4 (e.g., CPU 10, memory circuits ME1 and ME2, and substrate bias generation circuit VBC) to the reset state (reset operation). When the voltage at power node N2 is higher than the threshold voltage Vrem, monitoring circuit M7 outputs a reset signal RS2 (e.g., a high-level reset signal RS2) to control circuit CNT1. Therefore, control circuit CNT2 releases the reset state of each circuit block based on the reset signal RS2. Thus, if the operating power supply voltage is supplied to each circuit block, each circuit block can be activated.

[0163] Typically, because the substrate bias generation circuit VBC uses circuitry with low current drive capability (e.g., a charge pump), it has a long startup time. Therefore, even if the substrate bias generation circuit VBC receives the power supply voltage VCC-MCU via power node N2, it does not start immediately and may be in an indeterminate state. As a result, the substrate bias generation circuit VBC cannot supply the substrate bias voltages VBN and VBP to capacitors C2 and C3, respectively. Furthermore, if switches SW9 and SW10 are turned on before the substrate bias voltages VBN and VBP are supplied to capacitors C2 and C3, respectively, the charge accumulated in capacitors C2 and C3 as described above may escape.

[0164] However, during the startup operation of electronic system device 4, when the voltage of power node N1 reaches the threshold voltage Vst, monitoring circuit M6 sets switch SW8 from the off state to the on state. Subsequently, substrate bias generation circuit VBC receives power supply voltage VCC_MCU. Afterwards, as the power supply voltage VCC_MCU gradually rises and the voltage of power node N2 reaches the threshold voltage Vst, monitoring circuit M7 sets switches SW9 and SW10 from the off state to the on state.

[0165] Therefore, when the substrate bias generation circuit VBC performs its startup operation based on the power supply voltage VCC_MCU, switches SW9 and SW10 are turned off. In other words, when switches SW9 and SW10 are off, the substrate bias generation circuit VBC can be fully activated to generate substrate bias voltages VBN and VBP. Afterward, switches SW9 and SW10 are turned on, and the substrate bias generation circuit VBC stably supplies substrate bias voltages VBN and VBP to capacitors C2 and C3, respectively. Therefore, even when switches SW9 and SW10 are turned on, the charge in capacitors C2 and C3 is difficult to be pulled out due to the stable operation of the substrate bias generation circuit VBC. Consequently, the time required for the substrate bias voltages VBN and VBP to reach the threshold voltages VbackN and VbackP is reduced.

[0166] In the startup operation of electronic system device 4, similar to the startup operation of electronic system device 1, the current consumed by semiconductor device SC4 may not be compensated by the following two: the generated current ISC supplied from power generation device P, and the charge in capacitor C1.

[0167] During the startup operation of electronic system device 4, when the voltages of power nodes N1 and N2 drop and the voltage of power node N2 reaches the threshold voltage Vrem, monitoring circuit M7 sets switches SW9 and SW10 from the ON state to the OFF state. Subsequently, when the voltage of power node N1 further decreases and reaches the threshold voltage Vre, monitoring circuit M6 sets switch SW8 from the ON state to the OFF state.

[0168] If switches SW9 and SW10 are set to the ON state after switch SW8 is set to the OFF state, the substrate bias generation circuit VBC will operate erratically due to the voltage drop at power node N2. At this time, when the substrate bias generation circuit VBC is connected to capacitors C2 and C3, the charge accumulated in capacitors C2 and C3 will escape, as described above.

[0169] On the other hand, before the substrate bias generation circuit VBC performs unstable operation due to the voltage drop at power node N2, the electronic system device 4 sets switches SW9 and SW10 to the off state. In other words, since the monitoring circuit M7 has a higher threshold voltage Vrem than the threshold voltage Vre of the monitoring circuit M6, switches SW9 and SW10 are set to the off state before switch SW8 is set to the off state. Therefore, capacitors C2 and C3 are disconnected from the substrate bias generation circuit VBC and can stably store the accumulated charge. Therefore, the time for the substrate bias voltages VBN and VBP to reach the threshold voltages VbackN and VbackP is reduced.

[0170] Therefore, the substrate bias generation circuit VBC of the electronic system device 4 can provide reverse bias voltages VNS and VPS to the CPU 10, memory circuit ME1, and memory circuit ME2 as quickly as possible. Thus, the electronic system device 4 can stably execute and complete the startup sequence.

[0171] Similar to the startup operation of electronic system device 1, the startup operation of electronic system device 4 includes the first, second, third, and fourth steps described above. Furthermore, even if the operation transitions to a reset operation during the startup operation of electronic system device 4, since capacitors C2 and C3 maintain their charge in the same manner as in electronic system device 1, the startup sequence can be stably completed by repeatedly performing the drive and reset operations multiple times.

Claims

1. An electronic system device, comprising: A power generation device that generates a first power supply voltage and supplies it to a first power node; A substrate bias generation circuit is connected to the power generation device via the first power node and generates a substrate bias voltage based on the first power supply voltage. A first memory circuit, which is connected to the power generation device via the first power node, and is configured with a field-effect transistor; A first control switch is connected to the substrate bias generation circuit. A first capacitor is connected to the first control switch via a second power node and receives the substrate bias voltage from the substrate bias generation circuit. as well as A power monitoring circuit is connected to the first power node and controls the first control switch based on the voltage of the first power node. When the power monitoring circuit sets the first control switch to the ON state, the substrate bias generation circuit stores charge in the first capacitor based on the substrate bias voltage. When the power monitoring circuit sets the first control switch to the off state, the first capacitor retains the accumulated charge. When the power monitoring circuit sets the first control switch to the ON state, the substrate bias generation circuit adds charge to the already held charge based on the substrate bias voltage to obtain a reverse bias voltage through the injected charge. and The substrate bias generation circuit supplies the reverse bias voltage to the well region of the field-effect transistor.

2. The electronic system device according to claim 1, wherein the field-effect transistor is an SOTB transistor. The SOTB transistor mentioned above includes: Substrate; A well region, the well region being formed on the substrate; A semiconductor layer is formed on the well region by means of an insulating film; The source region, drain region, and channel region are formed in the semiconductor layer; as well as A gate electrode, which is disposed on the channel region via a gate insulating film.

3. The electronic system apparatus according to claim 2, further comprising: A substrate bias monitoring circuit is connected to the second power node and controls the substrate bias generation circuit based on the voltage of the second power node. The substrate bias monitoring circuit has a first threshold voltage. When the voltage of the second power node reaches the first threshold voltage due to the injected charge, the substrate bias monitoring circuit supplies a control signal to the substrate bias generation circuit, and The substrate bias generation circuit supplies the reverse bias voltage to the well region of the field-effect transistor based on the control signal.

4. The electronic system apparatus according to claim 3, further comprising: A power switch, which is connected to the power generation device via the first power node. The substrate bias generation circuit is connected to the first power node via the power switch. The power monitoring circuit controls the power switch and the control switch based on the voltage of the first power node, and the power monitoring circuit has a second threshold voltage and a third threshold voltage. When the voltage of the first power node reaches the second threshold voltage, the power monitoring circuit sets the power switch and the control switch from the off state to the on state, and When the voltage of the first power node reaches the third threshold voltage, the power monitoring circuit sets the power switch and the control switch from the on state to the off state.

5. The electronic system apparatus according to claim 4, further comprising: A control circuit, which is connected to the first power node via the power switch, and the control circuit includes an internal register; A central processing unit, which is connected to the first power node via the power switch; as well as A second memory circuit, connected to the first power node via the power switch, stores the user program and initial values. When the power monitoring circuit sets the power switch to the ON state, the control circuit reads the initial value from the second memory circuit and sets the initial value into the internal register. After the initial value is set in the internal register, the central processing unit reads the user program from the second memory circuit and executes the user program. The central processing unit supplies designated signals to the control circuit according to the user program. The control circuit, based on the specified signal, supplies a mode specification signal to the substrate bias generation circuit, and The substrate bias generation circuit generates the substrate bias voltage from the first power supply voltage based on the mode specification signal.

6. The electronic system apparatus according to claim 5, When the voltage of the first power node reaches the third threshold voltage, the power monitoring circuit supplies a reset signal to the control circuit, and The control circuit thereunder sets the internal register to a reset state based on the reset signal.

7. The electronic system apparatus according to claim 6, further comprising: A second capacitor is connected in parallel with the power switch to the first power node. The second capacitor stores the charge based on the first power supply voltage.

8. The electronic system apparatus according to claim 4, The power monitoring circuit receives an external mode signal and changes the value of the second threshold voltage based on the external mode signal.

9. The electronic system device of claim 4, wherein the second threshold voltage is higher than the third threshold voltage.

10. An electronic system device, comprising: A power generation device that generates a first power supply voltage and supplies the first power supply voltage to a first power node; A power switch, which is connected to the power generation device via the first power node; A substrate bias generation circuit is connected to the power switch via a second power node and generates a substrate bias voltage based on the first power supply voltage. A memory circuit, which is connected to the second power node and is configured with an SOTB transistor; A control switch, which is connected to the substrate bias generation circuit; A first capacitor is connected to the control switch via a third power node and receives the substrate bias voltage from the substrate bias generation circuit. A first power monitoring circuit is connected to the first power node and controls the power switch based on the voltage of the first power node. as well as A second power monitoring circuit is connected to the second power node and controls the control switch based on the voltage of the second power node. When the second power monitoring circuit sets the control switch to the ON state, the substrate bias generation circuit accumulates charge on the first capacitor based on the substrate bias voltage. When the second power monitoring circuit sets the control switch to the off state, the first capacitor retains the accumulated charge. When the second power monitoring circuit sets the control switch to the ON state, the held charge is charged based on the substrate bias voltage to obtain a reverse bias voltage through the injected charge. The substrate bias generation circuit supplies the reverse bias voltage to the well region of the SOTB transistor.

11. The electronic system apparatus of claim 10, further comprising: A substrate bias monitoring circuit is connected to the third power node and controls the substrate bias generation circuit based on the voltage of the third power node. The substrate bias monitoring circuit has a first threshold voltage. When the substrate bias monitoring circuit monitors the voltage of the third power node, if the voltage of the third power node reaches the first threshold voltage due to the injected charge, the substrate bias monitoring circuit supplies a control signal to the substrate bias generation circuit. The substrate bias generation circuit supplies the reverse bias voltage to the well region of the SOTB transistor based on the control signal.

12. The electronic system apparatus according to claim 11, The first power monitoring circuit and the second power monitoring circuit have a second threshold voltage. When the voltage of the first power node reaches the second threshold voltage, the first power monitoring circuit sets the power switch from the off state to the on state. After the power switch is set from the off state to the on state, when the voltage of the second power node reaches the second threshold voltage, the second power monitoring circuit sets the control switch from the off state to the on state.

13. The electronic system apparatus according to claim 12, The first power monitoring circuit has a third threshold voltage. The second power monitoring circuit has a fourth threshold voltage, which is higher than the third threshold voltage. When the voltage of the second power node reaches the fourth threshold voltage, the second power monitoring circuit sets the control switch from the ON state to the OFF state. After the control switch is set from the ON state to the OFF state, when the voltage of the first power node reaches the third threshold voltage, the first power monitoring circuit sets the power switch from the ON state to the OFF state.

14. The electronic system apparatus according to claim 13, The SOTB transistor mentioned above includes: Substrate; A well region, the well region being formed on the substrate; A semiconductor layer is formed on the well region through an insulating film, and a source region, a drain region, and a channel region are formed in the semiconductor layer; as well as A gate electrode, which is disposed on the channel region via a gate insulating film.

15. The electronic system apparatus of claim 14, further comprising: A second capacitor is connected in parallel with the power switch to the first power node. The second capacitor stores the charge based on the first power supply voltage.

16. A method for starting an electronic system device, comprising: A power generation device that generates a first power supply voltage and supplies the first power supply voltage to a first power node; A substrate bias generation circuit is connected to the power generation device via the first power node and generates a first substrate bias voltage based on the first power supply voltage. A memory circuit, which is connected to the power generation device via the first power node, and includes an n-type SOTB transistor; A first control switch is connected to the substrate bias generation circuit. A first capacitor is connected to the first control switch via a second power node and receives the first substrate bias voltage from the substrate bias generation circuit. as well as A power monitoring circuit is connected to the first power node and controls the first control switch based on the voltage of the first power node. The startup method includes the following steps: (a) When the power monitoring circuit sets the first control switch to the ON state, the substrate bias generation circuit accumulates charge in the first capacitor based on the first substrate bias voltage. (b) After step (a), when the power monitoring circuit sets the first control switch to the off state, the charge accumulated in step (a) is stored in the first capacitor. (c) After step (b), when the power monitoring circuit sets the first control switch to the ON state, charge is added to the charge maintained by step (b) in the substrate bias generation circuit based on the first substrate bias voltage, and a first reverse bias voltage is obtained based on the injected charge. (d) The first reverse bias voltage is supplied to the well region of the n-type SOTB transistor through the substrate bias generation circuit.

17. The startup method according to claim 16, The substrate bias generation circuit generates a second substrate bias voltage based on the first power supply voltage, and the second substrate bias voltage is different from the first substrate bias voltage. The memory circuit also includes a p-type SOTB transistor.

18. The startup method according to claim 17, The electronic system device further includes: A second control switch is connected to the substrate bias generation circuit. as well as The second capacitor, which is connected to the second control switch via a third power node, receives the second substrate bias voltage from the substrate bias generation circuit. The power monitoring circuit controls the first control switch and the second control switch based on the voltage of the first power node. In step (a), when the power monitoring circuit sets the second control switch to the ON state, the substrate bias generation circuit accumulates charge in the second capacitor based on the second substrate bias voltage. In step (b), when the power monitoring circuit sets the second control switch to the off state, the second capacitor retains the accumulated charge. In step (c), when the power monitoring circuit sets the second control switch to the on state, the substrate bias generation circuit adds charge to the charge in the second capacitor based on the second substrate bias voltage, and obtains a second reverse bias voltage by injection. In step (d), the substrate bias generation circuit supplies the second reverse bias voltage to the well region of the p-type SOTB transistor.

19. The startup method according to claim 18, The electronic system device further includes a power switch connected to the power generation device via the first power node. The substrate bias generation circuit is connected to the first power node via the power switch. The memory circuit is connected to the first power node via the power switch. The power monitoring circuit described herein has a first threshold voltage and a second threshold voltage. When the voltage of the first power node reaches the first threshold voltage, the power monitoring circuit sets the power switch, the first control switch, and the second control switch from the off state to the on state. When the voltage of the first power node reaches the second threshold voltage, the power monitoring circuit sets the power switch, the first control switch, and the second control switch from the ON state to the OFF state.

20. The startup method according to claim 19, The first threshold voltage is higher than the second threshold voltage.

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