Luminous display panel

Abstract

A light-emitting display panel with high resolution is provided. The light-emitting display panel includes a plurality of pixels. Each of the plurality of pixels includes: a first pixel circuit layer including a first pixel circuit, the first pixel circuit having a first layer electrode; a second pixel circuit layer including a second pixel circuit, the second pixel circuit including a driving transistor and a second layer electrode; a first capacitor having a first plate and a second plate, the first plate including the first layer electrode, the second plate including the second layer electrode; and a light-emitting device layer including a light-emitting device electrically connected to a driving transistor disposed in the second pixel circuit layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0134397, filed on October 28, 2019, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a light-emitting display panel. Background Art

[0004] Since the light-emitting display apparatus displays an image by using a self-luminous device, the light-emitting display apparatus has a fast response time, low power consumption, and a good viewing angle, and thus, the light-emitting display apparatus has received much attention as a next-generation display apparatus.

[0005] Each of the plurality of pixels constituting the light-emitting display panel of the light-emitting display device includes a pixel driving circuit. The pixel driving circuit controls the level of current flowing from the driving power supply to the light-emitting device based on the switching of the driving transistor according to the data voltage, thereby making the light-emitting device emit light. Therefore, the light-emitting display device displays a specific image.

[0006] In a light-emitting display panel, the current flowing in the light-emitting device of each pixel may vary based on the deviation of the threshold voltage of the driving transistor caused by the process deviation. Therefore, even when the same data voltage is supplied to the pixel driving circuit of the light-emitting display panel, the current output from the driving transistor may vary for each pixel, and thus, uniform image quality may not be achieved. Therefore, an internal compensation circuit for compensating the threshold voltage of the driving transistor is included in each pixel driving circuit.

[0007] Recently, the resolution of a light-emitting display panel applied to a mobile electronic device, a virtual image display device, or a head-mounted display device has gradually increased. As the resolution of the light-emitting display panel gradually increases, the size of each pixel gradually decreases. Therefore, it is difficult to form (or place) a pixel driving circuit including an internal compensation circuit in a pixel, and thus, it is difficult to manufacture a high-resolution light-emitting display panel. Summary of the invention

[0008] Accordingly, the present disclosure is directed to a light emitting display panel that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0009] One aspect of the present disclosure is to provide a light-emitting display panel with high resolution.

[0010] Other advantages and features of the present disclosure will be described in part in the following description, and in part will become apparent to those of ordinary skill in the art after reading the following, or may be learned from the practice of the present disclosure. The purposes and other advantages of the present disclosure can be realized and obtained through the structures specifically indicated in the written description and claims and the drawings.

[0011] To achieve these and other advantages, and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a light-emitting display panel is provided, the light-emitting display panel comprising a plurality of pixels, wherein each of the plurality of pixels comprises: a first pixel circuit layer, the first pixel circuit layer comprising a first pixel circuit, the first pixel circuit having a first layer electrode; a second pixel circuit layer, the second pixel circuit layer comprising a second pixel circuit, the second pixel circuit comprising a driving transistor and a second layer electrode; a first capacitor, the first capacitor having a first plate and a second plate, wherein the first plate comprises the first layer electrode and the second plate comprises the second layer electrode; and a light-emitting device layer comprising a light-emitting device electrically connected to a driving transistor disposed in the second pixel circuit layer.

[0012] The present disclosure also provides a display device, including: a display panel, including multiple pixels, wherein each of the multiple pixels includes: a first pixel circuit layer, the first pixel circuit layer includes a first pixel circuit, the first pixel circuit has a first layer electrode; a second pixel circuit layer, the second pixel circuit layer includes a second pixel circuit, the second pixel circuit includes a second layer electrode, the second layer electrode and the first layer electrode together constitute a first capacitor; and a light-emitting device layer, the light-emitting device layer includes a light-emitting device electrically connected to a driving transistor arranged in the second pixel circuit layer.

[0013] In the light-emitting display panel according to the present disclosure, the pixel driving circuit included in each pixel can be implemented as a double-layer structure. Therefore, even if the size of each pixel is reduced due to achieving high resolution, the pixel driving circuit can be fully arranged in each pixel, thereby realizing a high-resolution light-emitting display panel.

[0014] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present disclosure includes accompanying drawings to provide a further understanding of the present disclosure, which are incorporated into and constitute a part of the present application, and which illustrate embodiments of the present disclosure and are used together with the description to explain the principles of the present disclosure. In the accompanying drawings:

[0016] Figure 1 is a diagram schematically showing a light-emitting display device to which a light-emitting display panel according to an embodiment of the present disclosure is applied;

[0017] Figure 2 is a circuit diagram of an embodiment of a pixel applied to a light-emitting display panel according to the present disclosure;

[0018] Figure 3 It is shown Figure 2 A cross-sectional view of the layer structure of a pixel shown in FIG.

[0019] Figure 4 It is shown Figure 3 A diagram of the circuit configuration of each layer shown in ;

[0020] Figure 5 It is shown Figure 2 An exemplary diagram of a first pixel circuit shown in ;

[0021] Figure 6 It is shown that Figure 5 An exemplary diagram of a layout of a first pixel circuit layer of a first pixel circuit shown in ;

[0022] Figure 7 It is along Figure 6 A cross-sectional view taken along the line AA' shown in FIG.

[0023] Figure 8 It is shown Figure 2 An exemplary diagram of a second pixel circuit shown in ;

[0024] Fig. 9 It is shown that Figure 8 An exemplary diagram of a layout of a second pixel circuit layer of a second pixel circuit shown in FIG.

[0025] Fig.10 It is along Fig. 9 A cross-sectional view taken along the line BB' shown in FIG.

[0026] Fig.11A and Fig. 11B are exploded cross-sectional views respectively showing a first pixel circuit layer and a second pixel circuit layer respectively constituting a light-emitting display panel according to an embodiment of the present disclosure; and

[0027] Fig.12 It shows that Fig.11A and Fig. 11B 0 is a cross-sectional view of an example in which a first pixel circuit layer and a second pixel circuit layer are coupled to each other. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0029] The advantages and features of the present disclosure and its implementation methods will be described by referring to the following embodiments described in the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments described herein. On the contrary, these embodiments are provided to make the present disclosure thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0030] The shapes, sizes, ratios, angles and quantities disclosed in the drawings for describing the embodiments of the present disclosure are merely examples, and therefore the present disclosure is not limited to the details listed. Similar reference numerals refer to similar elements throughout the drawings. In the following description, when it is determined that the detailed description of the relevant known functions or configurations unnecessarily obscures the main points of the present disclosure, the detailed description will be omitted. In the case of using "including", "having" and "comprising" described in this specification, another component may be added unless "only" is used. Unless otherwise indicated, terms in the singular may include plural forms.

[0031] In interpreting an element, although there is no explicit description, the element is interpreted as including an error range.

[0032] When describing a positional relationship, for example, when the positional relationship between two components is described as "on," "above," "below," or "near," one or more other components may be disposed between the two components, unless "just" or "directly" is used.

[0033] When describing a time relationship, for example, when a time sequence is described as “after,” “subsequently,” “next,” and “before,” discontinuous cases may be included unless “just” or “directly” is used.

[0034] It will be understood that although the terms "first", "second", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0035] When describing the elements of the present disclosure, terms such as first, second, A, B, (a), (b) etc. may be used. These terms are only used to distinguish corresponding elements from other elements, and corresponding elements are not limited by these terms in their essence, order and priority. It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it may be directly on or directly connected to another element or layer, or there may be an intermediate element or layer. In addition, it should be understood that when an element is arranged on or under another element, this may represent a situation where the elements are arranged to be in direct contact with each other, but may also represent that the elements are arranged not to be in direct contact with each other.

[0036] The term "at least one" should be understood to include any and all combinations of one or more of the related listed elements. For example, the meaning of "at least one of a first element, a second element, and a third element" represents the combination of all elements proposed from two or more first elements, second elements, and third elements, as well as the first element, the second element, and the third element.

[0037] As those skilled in the art can fully understand, the features of the various embodiments of the present disclosure may be partially or completely coupled or combined with each other, and may interoperate and technically drive each other in various ways. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a dependent relationship.

[0038] Figure 1 is a diagram schematically showing a light-emitting display device to which a light-emitting display panel according to an embodiment of the present disclosure is applied.

[0039] like Figure 1 As shown, a light-emitting display device to which the light-emitting display panel according to an embodiment of the present disclosure is applied may include a light-emitting display panel 100 , a timing controller 400 , a data driver 300 , and a gate driver 200 .

[0040] The light-emitting display panel 100 may include a substrate, a display area AA defined on the substrate, and a non-display area IA surrounding the display area AA.

[0041] The substrate may be a base substrate (or base layer) and may include a plastic material or a glass material. The substrate according to the embodiment may have a planar square shape, a square shape with each corner rounded with a specific radius of curvature, or a non-square shape including at least seven edges. Here, the substrate having a non-square shape may include at least one protrusion or at least one notch.

[0042] The substrate according to an embodiment may include a colored polyimide material. For example, the substrate including the polyimide material may be formed by curing a polyimide resin, which is coated to have a specific thickness on the front surface of a release layer provided in a relatively thick carrier substrate. In this case, the carrier substrate may be separated from the substrate by releasing the release layer through a laser release process. The substrate according to an embodiment may further include a backplane coupled to the rear surface of the substrate relative to the thickness direction Z. The backplane may maintain the substrate in a planar state. The backplane according to an embodiment may include a plastic material, for example, may include polyethylene terephthalate. The backplane may be stacked on the rear surface of the substrate separated from the carrier substrate.

[0043] According to another embodiment, the substrate may be a flexible glass substrate. For example, the substrate including the glass material may be a thin glass substrate having a thickness of 100 μm or less, or may be a carrier glass substrate etched to have a thickness of 100 μm or less by a substrate etching process performed after the manufacturing process is completed.

[0044] A plurality of initialization voltage lines IVL, a plurality of scan control lines SCL, a plurality of emission control lines ECL, a plurality of data lines DL, a plurality of pixel driving voltage lines PL, a common electrode layer, and a plurality of pixels P may be disposed in the display area AA.

[0045] The plurality of initialization voltage lines IVL may extend long in a second direction Y intersecting the first direction X, and may be spaced apart from each other in the first direction X. Here, the first direction X may be a direction parallel to the transverse direction of the substrate and the second direction Y may be a direction parallel to the longitudinal direction of the substrate. However, the present disclosure is not limited thereto, and the first direction X may be a direction parallel to the longitudinal direction of the substrate and the second direction Y may be a direction parallel to the transverse direction of the substrate. Each of the plurality of initialization voltage lines IVL may transmit an initialization voltage supplied from the data driver 300 or the power supply circuit to a corresponding pixel among the plurality of pixels.

[0046] The plurality of scan control lines SCL may extend long in the first direction X and may be disposed adjacent to the plurality of emission control lines ECL, respectively. Each of the plurality of scan control lines SCL may transmit a scan control signal supplied from the gate driver 200 to a corresponding pixel among the plurality of pixels.

[0047] The plurality of emission control lines ECL may extend long in the first direction X and may be disposed in parallel with the plurality of scan control lines SCL. Each of the plurality of emission control lines ECL may transmit an emission control signal supplied from the gate driver 200 to a corresponding pixel among the plurality of pixels.

[0048] The plurality of data lines DL may extend long in the second direction Y and may be spaced apart from each other in the first direction X. Each of the plurality of data lines DL may transmit a data voltage supplied from the data driver 300 to a corresponding pixel among the plurality of pixels.

[0049] The plurality of pixel driving voltage lines PL may be respectively disposed in parallel with the plurality of data lines DL. Each of the plurality of pixel driving voltage lines PL may transmit a pixel driving voltage supplied from the data driver 300 or a power supply circuit to a corresponding pixel among the plurality of pixels.

[0050] Each of the plurality of pixel driving voltage lines PL according to the embodiment may be disposed to correspond to two pixels respectively disposed adjacent to each other in the first direction X. That is, one pixel driving voltage line PL may be disposed to be shared by two pixels disposed adjacent to each other in the first direction X.

[0051] The common electrode layer may be disposed in the entire display area AA. The common electrode layer may transmit a common voltage Vss supplied from the data driver 300 or a power circuit to a plurality of pixels. At least one common power line electrically connected to the common electrode layer may be disposed in the display area AA.

[0052] Each of the multiple pixels P can be arranged in a pixel area defined in the display area AA, and can be electrically connected to a corresponding initialization voltage line IVL, a corresponding scanning control line SCL, a corresponding light emitting control line ECL, a corresponding data line DL, a pixel driving voltage line PL and a common electrode layer that pass through the pixel area or are arranged adjacent to the pixel area.

[0053] In this case, in order to realize the light-emitting display panel 100 with high resolution, each of the scanning control line SCL and the light-emitting control line ECL may be arranged to pass through or through the pixel area, and each of the initialization voltage line IVL, the data line DL, and the pixel driving voltage line PL may be arranged outside the pixel area. In addition, two pixels arranged adjacent to each other in the first direction X may have a symmetrical structure with respect to the pixel driving voltage line PL.

[0054] The pixels P according to the embodiment may be arranged in a stripe structure in the display area AA. In this case, one unit pixel may include a red pixel, a green pixel, and a blue pixel, and further may include a white pixel.

[0055] According to another embodiment, the pixel P may be arranged to have a Pentile structure in the display area AA. In this case, one unit pixel may include at least one red pixel, at least two green pixels, and at least one blue pixel, which are arranged to have a polygonal shape in one dimension. For example, one unit pixel with a Pentile structure may be arranged so that one red pixel, two green pixels, and one blue pixel are arranged to have an octagonal shape in one dimension, in which case the blue pixel may include an opening area (or light emitting area) having a relatively maximum size and the green pixel may include an opening area having a relatively minimum size.

[0056] Each of the plurality of pixels P may operate in the order of an initialization period, a sampling period, and a light emitting period to emit light having brightness corresponding to a data voltage supplied through a corresponding data line DL.

[0057] The non-display area IA may be disposed along an edge of the substrate to surround the display area AA. One of the non-display areas IA may include a pad portion.

[0058] The pad portion may be disposed in one non-display area of ​​the substrate, and may be electrically connected to a line disposed in the display area AA along the second direction Y. In addition, the pad portion may be electrically connected to the data driver 300 .

[0059] The timing controller 400 may align input video data Idata based on driving of the light-emitting display panel 100 to generate pixel data Pdata, generate a data control signal DCS based on a timing synchronization signal TSS, and provide the pixel data Pdata and the data control signal DCS to the data driver 300 .

[0060] The timing controller 400 may generate a gate control signal GCS including a gate start signal and a plurality of gate shift clocks based on the timing synchronization signal TSS, and may provide the gate control signal GCS to the gate driver 200. The gate control signal GCS may be provided to the gate driver 200 via a pad portion.

[0061] The data driver 300 may be connected to a plurality of data lines DL provided in the light-emitting display panel 100 via a pad portion. The data driver 300 may convert pixel data Pdata into analog data voltages by using a data control signal DCS and a plurality of reference gamma voltages provided from the timing controller 400, and may provide the converted data voltages to corresponding data lines DL.

[0062] The gate driver 200 can generate an initialization control signal, a scanning control signal and a light-emitting control signal corresponding to the initialization period, the sampling period and the light-emitting period of each pixel in the multiple pixels P based on the gate control signal GCS provided from the timing controller 400, and can provide the initialization control signal, the scanning control signal and the light-emitting control signal to the multiple pixels P.

[0063] The gate driver 200 according to the embodiment may generate light emitting control signals having the same cycle and sequential phase shift, and may provide the light emitting control signals to the plurality of light emitting control lines ECL.

[0064] The gate driver 200 according to the embodiment may be disposed in the left non-display area and / or the right non-display area of ​​the substrate through a process of manufacturing a thin film transistor (TFT) of each pixel P.

[0065] For example, the gate driver 200 may be disposed in a left non-display area of ​​the substrate, and may supply a light emission control signal to one end of each light emission control line ECL based on a single-stage feeding method.

[0066] As another example, the gate driver 200 may be disposed in each of left and right non-display areas of the substrate, and may supply a light emission control signal to both ends of each light emission control line ECL based on a dual feed method.

[0067] Figure 2 is a circuit diagram of an embodiment of a pixel applied to a light-emitting display panel according to the present disclosure, Figure 3 It is shown Figure 2 A cross-sectional view of the layer structure of a pixel shown in FIG. Figure 4 It is shown Figure 3 The circuit composition of each layer is shown in the diagram.

[0068] like Figures 2 to 4 As shown, a pixel P applied to a light-emitting display panel according to the present disclosure may include: a pixel driving circuit layer 130, which includes a pixel driving circuit PDC; a light-emitting device layer 170, which includes a light-emitting device ED electrically connected to the pixel driving circuit PDC; and a planarization layer 160, which is arranged between the pixel driving circuit layer 130 and the light-emitting device layer 170.

[0069] The pixel driving circuit layer 130 may include a first pixel circuit layer 110 including a first pixel circuit PC1 and a second pixel circuit layer 120 including a second pixel circuit PC2 .

[0070] First, according to the embodiment, the first pixel circuit layer 110 may include a substrate 10, a first pixel circuit PC1, a light emitting control line ECL for transmitting a light emitting control signal to the first pixel circuit PC1, a data line DL for transmitting a data voltage to the first pixel circuit PC1, and an nth scan control line SCL(n) for transmitting an nth scan control signal to the first pixel circuit PC1.

[0071] The light emission control line ECL may be disposed in the pixel P in parallel with the first direction X.

[0072] The pixel driving voltage line PL may be disposed in the pixel P in parallel with the second direction Y.

[0073] The data line DL may be disposed at one edge of the pixel P in parallel with the second direction Y. The data line DL according to an embodiment may be disposed at one edge of the pixel P to one-dimensionally overlap or not overlap with the pixel driving voltage line PL disposed in the first pixel circuit layer 110. For example, the data line DL may be disposed at one edge of the pixel P to overlap with the pixel driving voltage line PL disposed in the first pixel circuit layer 110.

[0074] The nth scan control line SCL(n) may be disposed in the pixel P and may be spaced apart from and parallel to the emission control line ECL. The nth scan control line SCL(n) according to an embodiment may be disposed in the pixel P to one-dimensionally overlap or not overlap with the emission control line ECL disposed in the first pixel circuit layer 110.

[0075] The first pixel circuit PC1 may store a data voltage supplied through the data line DL and a threshold voltage of a driving transistor Tdr included in the second pixel circuit PC2 , and may control light emission timing of the light emitting device ED.

[0076] The first pixel circuit PC1 according to the embodiment may include: a first capacitor C1 including a first terminal C1a; a first transistor T1 including a gate connected to the light emission control line ECL and a first terminal connected to the pixel driving voltage line PL; a second transistor T2 including a gate connected to the n-2 scan control line SCL(n-2) and a first terminal connected to the first terminal C1a of the first capacitor C1; a third transistor T3 including a gate connected to the n-th scan control line SCLn, a first terminal connected to the data line DL and a second terminal connected to the first terminal of the second transistor T2; and a second capacitor C2 including a first terminal C2a connected to the first terminal of the first transistor T1 and a second terminal C2b connected to the first terminal C1a of the first capacitor C1. In the following description, the first terminal C2a of the second capacitor C2 may be referred to as a first electrode C2a, the second terminal C2b of the second capacitor C2 may be referred to as a second electrode C2b, the first terminal C1a of the first capacitor C1 may be referred to as a third electrode C1a, and the second terminal C1b of the first capacitor C1 may be referred to as a fourth electrode C1b.

[0077] First, the first transistor T1 may be turned on based on a light emission control signal supplied through the light emission control line ECL, and when the first transistor T1 is turned on, current may flow through the driving transistor Tdr and the light emitting device ED, and thus the light emitting device ED may emit light.

[0078] The first transistor T1 according to the embodiment may include a first gate connected to the light emission control line ECL, a second terminal connected to the first terminal of the driving transistor Tdr, and a first terminal connected to the second capacitor C2. In the following description, in the case where the gates of the first transistor T1 to the fifth transistor T5 should be distinguished from each other, the gates may be referred to as the first gate to the fifth gate. In addition, the gate of the driving transistor Tdr may be referred to as a driving gate.

[0079] A first terminal of the driving transistor Tdr may be a source and a second terminal thereof may be a drain. The first transistor T1 may be turned on based on a light emission control signal supplied through the light emission control line ECL, and thus current may flow in the first transistor T1, the driving transistor Tdr, and the light emitting device ED.

[0080] Subsequently, the second transistor T2 may be turned on or off based on a second scan control signal supplied through the n-2 th scan control line SCL(n-2) among the plurality of scan control lines SCL. When the second transistor T2 is turned on, a data voltage or a sensing voltage supplied through the data line DL may be charged into at least one of the first capacitor C1 and the second capacitor C2.

[0081] The second transistor T2 according to an embodiment may include a second gate connected to the n-2 th scan control line SCL(n-2), a first terminal connected to the second terminal of the third transistor T3 , and a second terminal connected to the second terminal of the first transistor T1 .

[0082] Subsequently, the third transistor T3 may be turned on or off based on an nth scan control signal supplied through an nth scan control line SCL(n) among the plurality of scan control lines SCL. When the third transistor T3 is turned on, a data voltage or a sensing voltage supplied through the data line DL may be charged into at least one of the first capacitor C1 and the second capacitor C2.

[0083] The third transistor T3 according to the embodiment may include a third gate connected to the nth scan line SCL(n), a first terminal connected to the data line DL, and a second terminal connected to the first terminal of the second transistor T2.

[0084] Each of the first to third transistors T1 to T3 may include a semiconductor layer including an amorphous silicon material, a polycrystalline silicon material, or an oxide semiconductor material, and may be a P-type TFT including a semiconductor layer doped with a P-type impurity, but is not limited thereto, and may be an N-type TFT including a semiconductor layer doped with an N-type impurity. That is, in Figure 2 In FIG. 1 , a pixel driving circuit PDC including a plurality of P-type TFTs is shown, but the pixel driving circuit PDC may include a plurality of N-type TFTs. Figure 2 In FIG. 1 , a pixel driving circuit PDC including a plurality of P-type TFTs is shown, and the pixel driving circuit PDC may be configured with a plurality of N-type TFTs.

[0085] Polysilicon material may have good reliability in strong bias stress and may have high electron mobility. Therefore, each of the first to third transistors T1 to T3 according to the embodiment may include a P-type TFT including a semiconductor layer including a polysilicon material doped with P-type impurities.

[0086] Then, the first capacitor C1 may store an initialization voltage supplied through the initialization voltage line IVL. In addition, the first capacitor C1 may store a voltage compensating for a characteristic variation of the driving transistor Tdr together with the second capacitor C2.

[0087] The third electrode C1 a of the first capacitor C1 according to the embodiment may be connected to the second terminal of the third transistor T3 , the second electrode C2 b of the second capacitor C2 , and the first terminal of the second transistor T2 .

[0088] The fourth electrode C1 b of the first capacitor C1 may be connected to the second terminal of the fourth transistor T4 and the gate of the driving transistor Tdr.

[0089] In this case, the third electrode C1 a of the first capacitor C1 may be included in the first pixel circuit layer 110 , and the fourth electrode C1 b of the first capacitor C1 may be included in the second pixel circuit layer 120 .

[0090] That is, in the present disclosure, the first capacitor C1 may generate capacitance by using the third electrode C1a included in the first pixel circuit layer 110 and the fourth electrode C1b included in the second pixel circuit layer 120. Therefore, the first pixel circuit layer 110 or the second pixel circuit layer 120 may not require an additional area for the first capacitor C1.

[0091] To provide additional description, the proportion of the area of ​​the first capacitor C1 in the pixel driving circuit PDC may be large. Therefore, when the first capacitor C1 should be included in the first pixel circuit layer 110 or the second pixel circuit layer 120, a wider area of ​​the first capacitor C1 should be ensured, and therefore, for the pixel driving circuit PDC, the area of ​​the first pixel circuit layer 110 or the second pixel circuit layer 120 should be expanded.

[0092] However, in the present disclosure, as described above, the first capacitor C1 may be formed by the third electrode C1a included in the first pixel circuit layer 110 and the fourth electrode C1b included in the second pixel circuit layer 120. Therefore, the first pixel circuit layer 110 or the second pixel circuit layer 120 may not require an additional area for the first capacitor C1, and thus, the area of ​​the first pixel circuit layer 110 or the second pixel circuit layer 120 may be reduced.

[0093] In addition, since the fourth electrode C1b included in the second pixel circuit layer 120 may function as a blocking layer for blocking an electric field or light, parasitic capacitance may be reduced, and defects such as two-dimensional (2D) crosstalk may be prevented.

[0094] Finally, the second capacitor C2 can store the difference voltage between the driving gate and the source of the driving transistor Tdr. In addition, the second capacitor C2 can store a voltage for compensating for the characteristic change of the driving transistor Tdr together with the first capacitor C1. That is, by using the first capacitor C1 and the second capacitor C2, the data voltage supplied by the data line DL, the initialization voltage supplied by the initialization voltage line IVL, and the threshold voltage of the driving transistor Tdr can be stored in the first pixel circuit PC1 and the second pixel circuit PC2.

[0095] Therefore, the light emitting device ED can emit light having brightness corresponding to the data voltage regardless of the variation of the threshold voltage of the driving transistor Tdr.

[0096] According to an embodiment, a first electrode C2a of the second capacitor C2 may be connected to the first terminal of the first transistor T1, and a second electrode C2b of the second capacitor C2 may be connected to the second terminal of the third transistor T3, the third electrode C1a of the first capacitor C1, and the first terminal of the second transistor T2.

[0097] A second terminal of the first transistor T1 included in the first pixel circuit layer 110 may be electrically connected to a first terminal of the driving transistor Tdr included in the second pixel circuit layer 120 through a connection line CL1 .

[0098] The n-2nd scan control line SCL(n-2) included in the first pixel circuit layer 110 may be connected to the n-2nd scan control line SCL(n-2) included in the second pixel circuit layer 120 through the scan connection line CL2. In this case, the scan connection line CL2 may be arranged in the display area AA, and further, may be arranged in the non-display area IA. In addition, at least one scan connection line CL2 may be arranged only in the non-display area IA, or at least one scan connection line CL2 may be arranged only in the display area AA. Alternatively, at least two scan connection lines CL2 may be arranged in the display area AA and the non-display area IA.

[0099] Secondly, the second pixel circuit layer 120 may be disposed on a top surface (or surface) of the first pixel circuit layer 110 .

[0100] The second pixel circuit layer 120 according to an embodiment may include a second pixel circuit PC2, an initialization voltage line IVL for transmitting an initialization voltage to the second pixel circuit PC2, and an n-2 th scan control line SCL(n-2) for transmitting an n-2 th scan control signal to the second pixel circuit PC2.

[0101] The initialization voltage line IVL may be disposed in parallel with the data line DL in the pixel P. The initialization voltage supplied through the initialization voltage line IVL may initialize the first capacitor C1, the second capacitor C2, and the light emitting device ED.

[0102] The n-2nd scan control line SCL(n-2) may be disposed in the pixel P and may be parallel to and spaced apart from the light emission control line ECL. The n-2nd scan control line SCL(n-2) according to an embodiment may be disposed in the pixel P to one-dimensionally overlap or not overlap with the light emission control line ECL disposed in the first pixel circuit layer 110.

[0103] In addition, the n-2 th scan control line SCL(n-2) may be disposed in the pixel P to one-dimensionally overlap or not overlap with the n-2 th scan control line SCL(n-2) disposed in the first pixel circuit layer 110 .

[0104] The second pixel circuit PC2 may supply a current corresponding to a data voltage supplied through the data line DL to the light emitting device ED.

[0105] According to the embodiment, the second pixel circuit PC2 may include: a driving transistor Tdr, which includes a driving gate connected to the fourth electrode C1b, a first terminal connected to the second terminal of the first transistor T1, and a second terminal connected to the light emitting device ED; a fourth transistor T4, which includes a fourth gate connected to the n-2 scan control line SCL(n-2), a first terminal connected to the initialization voltage line IVL, and a second terminal connected to the fourth electrode C1b; and a fifth transistor T5, which includes a fifth gate connected to the n-2 scan control line SCL(n-2), a first terminal connected to the initialization voltage line IVL, and a second terminal connected to the second terminal of the driving transistor Tdr.

[0106] First, the driving transistor Tdr may transfer a current corresponding to a gate-source voltage based on a data voltage supplied from the first pixel circuit PC1 to the light emitting device ED.

[0107] The driving transistor Tdr according to the embodiment may include a first terminal connected to the second terminal of the first transistor T1 , a second terminal connected to the light emitting device ED, and a driving gate connected to the fourth electrode C1 b of the first capacitor C1 .

[0108] The first terminal of the driving transistor Tdr may be a source, and the second terminal of the driving transistor Tdr may be a drain. The driving transistor Tdr may be turned on based on the gate-source voltage, and thus, a current corresponding to the gate-source voltage based on the data voltage may flow in the first transistor T1, the driving transistor Tdr, and the light emitting device ED.

[0109] Subsequently, the fourth transistor T4 may be turned on or off based on the n-2 scan control signal supplied through the n-2 scan control line SCL(n-2). When the fourth transistor T4 is turned on, the initialization voltage supplied through the initialization voltage line IVL may be charged into at least one of the first capacitor C1 and the second capacitor C2.

[0110] The fourth transistor T4 according to the embodiment may include a fourth gate connected to the n-2 scan control line SCL (n-2), a first terminal connected to the initialization voltage line IVL, and a second terminal connected to the driving gate of the driving transistor Tdr. The second terminal of the fourth transistor T4 may be connected to the fourth electrode C1b of the first capacitor C1. That is, the fourth electrode C1b of the first capacitor C1 may be connected to the second terminal of the fourth transistor T4 and the driving gate of the driving transistor Tdr.

[0111] Subsequently, the fifth transistor T5 may be turned on or off based on the n-2 scan control signal supplied through the n-2 scan control line SCL(n-2). When the fifth transistor T5 is turned on, the initialization voltage supplied through the initialization voltage line IVL may be supplied to the light emitting device ED through the fifth transistor T5. Therefore, the light emitting device ED may be initialized to the initialization voltage.

[0112] The fifth transistor T5 according to the embodiment may include a fifth gate connected to the n-2 th scan control line SCL(n-2), a first terminal connected to the initialization voltage line IVL, and a second terminal connected to the second terminal of the driving transistor Tdr. The second terminal of the fifth transistor T5 may be connected to the second terminal of the driving transistor Tdr and the light emitting device ED.

[0113] Each of the driving transistor Tdr, the fourth transistor T4, and the fifth transistor T5 may include a semiconductor layer including an amorphous silicon material, a polycrystalline silicon material, or an oxide semiconductor material, and may be a P-type TFT including a semiconductor layer doped with P-type impurities, but is not limited thereto, and may be an N-type TFT including a semiconductor layer doped with N-type impurities. That is, in Figure 2 In FIG. 1 , a pixel driving circuit PDC including a plurality of P-type TFTs is shown, but the pixel driving circuit PDC may include a plurality of N-type TFTs. Figure 2 , a pixel driving circuit PDC including a plurality of P-type TFTs is shown, and the pixel driving circuit PDC may be configured with a plurality of N-type TFTs.

[0114] Polysilicon material may have good reliability in strong bias stress and may have high electron mobility. Therefore, each of the driving transistor Tdr, the fourth transistor T4, and the fifth transistor T5 according to the embodiment may include a P-type TFT including a semiconductor layer having a polysilicon material doped with P-type impurities.

[0115] Finally, as described above, the first capacitor C1 may store the initialization voltage supplied through the initialization voltage line IVL. In addition, the first capacitor C1 may store a voltage for compensating for a characteristic variation of the driving transistor Tdr together with the second capacitor C2.

[0116] The third electrode C1 a of the first capacitor C1 according to the embodiment may be connected to the second terminal of the third transistor T3 , the second electrode C2 b of the second capacitor C2 , and the first terminal of the second transistor T2 .

[0117] The fourth electrode C1 b of the first capacitor C1 may be connected to the second terminal of the fourth transistor T4 and the driving gate of the driving transistor Tdr.

[0118] In this case, the third electrode C1 a of the first capacitor C1 may be disposed in the first pixel circuit layer 110 , and the fourth electrode C1 b of the first capacitor C1 may be disposed in the second pixel circuit layer 120 .

[0119] That is, in the present disclosure, the first capacitor C1 may generate capacitance by using the third electrode C1a included in the first pixel circuit layer 110 and the fourth electrode C1b included in the second pixel circuit layer 120. Therefore, the first pixel circuit layer 110 or the second pixel circuit layer 120 may not require an additional area for the first capacitor C1.

[0120] The light emitting device layer 170 may include a light emitting device ED which is electrically connected to the second pixel circuit PC2 and emits light based on a current supplied from the second pixel circuit PC2 , and a bank pattern BNK.

[0121] The light emitting device ED according to the embodiment may include a pixel driving electrode AE ​​(referred to as an anode) connected to a pixel driving circuit PDC, a light emitting layer EL formed on the pixel driving electrode AE, and a common electrode layer CE (referred to as a cathode) electrically connected to the light emitting layer EL.

[0122] The pixel driving electrode AE ​​may be disposed in an opening region of the pixel P and may be electrically connected to a second terminal of the driving transistor Tdr included in the second pixel circuit PC2 .

[0123] The pixel driving electrode AE ​​according to the embodiment may include a metal material with high reflectivity. For example, the pixel driving electrode AE ​​may be formed as a laminated structure such as aluminum (Al) and titanium (Ti) (titanium / aluminum / titanium (Ti / Al / Ti)), a laminated structure of aluminum (Al) and indium tin oxide (ITO) (indium tin oxide / aluminum / indium tin oxide (ITO / Al / ITO)), an APC (silver / palladium / copper (Ag / Pd / Cu)) alloy, or a laminated structure of an APC alloy and ITO (ITO / APC / ITO) A multilayer structure, or may include a single-layer structure containing one material selected from Ag, Al, molybdenum (Mo), gold (Au), magnesium (Mg), calcium (Ca) and barium (Ba) or an alloy material of two or more materials.

[0124] The edge of the pixel driving electrode AE ​​may be covered by the bank pattern BNK. The bank pattern BNK may be provided in the pixel region except the opening region of the pixel P and may cover the edge of the pixel driving electrode AE. Therefore, the opening region of the pixel P may be defined.

[0125] The bank pattern BNK according to the embodiment may define an opening region of the pixel P as a Pentile structure or a stripe structure.

[0126] The light emitting layer EL according to the embodiment may be formed in the entire display area AA of the substrate 10 to cover the pixel driving electrode AE ​​and the bank pattern BNK.

[0127] The light-emitting layer EL according to the embodiment may include more than two light-emitting parts for emitting white light. For example, the light-emitting layer EL according to the embodiment may include a first light-emitting part and a second light-emitting part for emitting white light based on a combination of the first light and the second light. Here, the first light-emitting part may emit the first light and may include one of a blue light-emitting part, a green light-emitting part, a red light-emitting part, a yellow light-emitting part, and a yellow-green light-emitting part. The second light-emitting part may include a light-emitting part that emits a second light having a complementary color relationship with the first light among the blue light-emitting part, the green light-emitting part, the red light-emitting part, the yellow light-emitting part, and the yellow-green light-emitting part.

[0128] According to another embodiment, the light emitting layer EL may include one of a blue light emitting portion, a green light emitting portion, and a red light emitting portion for emitting colored light corresponding to the color set in the pixel P. For example, the light emitting layer EL according to another embodiment may include one of an organic light emitting layer, an inorganic light emitting layer, and a quantum dot light emitting layer, or may include a stacked structure or a combined structure of an organic light emitting layer (or an inorganic light emitting layer) and a quantum dot light emitting layer.

[0129] In addition, the light emitting device ED according to the embodiment may further include a functional layer for improving light emitting efficiency and / or lifetime of the light emitting layer EL.

[0130] The common electrode layer CE may be formed to be electrically connected to the light emitting layer EL. The common electrode layer CE may be formed in the entire display area AA of the substrate 10 and may be commonly connected to the light emitting layer EL provided in each pixel area PA.

[0131] The common electrode layer CE according to the embodiment may include a transparent conductive material, a transparent metal or a semi-transmissive conductive material that can transmit light. When the common electrode layer CE includes a semi-transmissive conductive material, the emission efficiency of light emitted from the light emitting device ED can be improved based on the microcavity. The semi-transmissive conductive material according to the embodiment may include Mg, Ag or an alloy of Mg and Ag. In addition, a cap layer for adjusting the refractive index of light emitted from the light emitting device ED to improve the emission efficiency of light may be further formed on the common electrode layer CE.

[0132] According to another embodiment, the light emitting layer EL may include a micro light emitting diode device implemented as an integrated circuit (IC) type. The micro light emitting diode device may include a first terminal electrically connected to the pixel driving electrode AE ​​and a second terminal electrically connected to the common electrode layer CE.

[0133] The pixel P according to the embodiment may further include a planarization layer 160 covering the second pixel circuit layer 120 and an encapsulation layer 190 covering the light emitting device layer 170 .

[0134] The planarization layer 160 may be disposed on the substrate 10 to cover the second pixel circuit layer 120 and may provide a planar surface on the second pixel circuit layer 120 .

[0135] The light emitting device layer 170 may be disposed on the planarization layer 160. In this case, the pixel driving electrode AE ​​of the light emitting device layer 170 may be electrically connected to the second terminal of the driving transistor Tdr of the second pixel circuit PC2 through an electrode contact hole disposed in the planarization layer 160.

[0136] The encapsulation layer 190 may be formed on the substrate 10 to surround the light emitting device layer 170. The encapsulation layer 190 may prevent oxygen or water from penetrating into the light emitting device ED.

[0137] According to an embodiment, encapsulation layer 190 may include at least one inorganic layer for preventing or minimizing the penetration of oxygen or water and an organic layer for covering particles occurring in the manufacturing process. For example, encapsulation layer 190 may include a first inorganic layer, an organic layer on the first inorganic layer, and a second inorganic layer on the organic layer.

[0138] In addition, the pixel P according to an embodiment of the present disclosure may further include a black matrix overlapping the bank pattern BNK and a wavelength conversion layer disposed in the opening region.

[0139] A black matrix may be disposed on the encapsulation layer 190 to overlap the bank pattern BNK.

[0140] The wavelength conversion layer according to the embodiment may include a color filter disposed on the encapsulation layer 190 overlapping the opening area of ​​the pixel P to transmit only the color wavelength of the white light incident from the light emitting device ED disposed in the pixel P. For example, the wavelength conversion layer may transmit only the wavelength of red, green, or blue. When the light emitting layer EL of the light emitting device ED includes a light emitting layer emitting red light, green light, and blue light, the wavelength conversion layer may be omitted.

[0141] The pixel P according to an embodiment of the present disclosure may further include a blocking film and a light path control layer.

[0142] The barrier film may be attached on the encapsulation layer 190 by using an adhesive layer. The barrier film may primarily prevent the penetration of oxygen or water and may include a material with a low water vapor transmission rate.

[0143] The light path control layer can control the path of incident light.

[0144] The light path control layer according to the embodiment may include a plurality of refractive layers. The plurality of refractive layers may have different refractive indices. The light path control layer may have a structure in which high refractive layers and low refractive layers are alternately stacked. The light path control layer according to the embodiment may change the path of the incident light to minimize the color shift phenomenon caused by the viewing angle.

[0145] According to another embodiment, the light path control layer may be a polarization layer. The polarization layer may change external light reflected by a TFT and / or a wire disposed in the pixel P into circularly polarized light, thereby improving visibility and contrast.

[0146] The operation of the pixel according to the embodiment of the present disclosure will be described below.

[0147] The pixel P according to the embodiment of the present disclosure can operate in the initialization period, the wiring period and the light-emitting period. For example, one frame of the light-emitting display device to which the light-emitting display panel according to the embodiment of the present disclosure is applied may include: an initialization period for initializing the driving gate of the driving transistor Tdr; a wiring period for storing a sampling voltage and a data voltage each corresponding to a characteristic value (e.g., a threshold voltage) of the driving transistor Tdr; and a light-emitting period for causing the light-emitting device ED to emit light through a current corresponding to the data voltage.

[0148] In the initialization / sampling period, a low voltage may be applied to the n-2 scan control line SCL (n-2), and therefore, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 may be turned on. In this case, the driving transistor Tdr may operate as a diode, and therefore, the voltage of the node (i.e., the first node n1) between the second terminal of the third transistor T3 and the first terminal of the second transistor T2 may be the sum voltage of the initialization voltage Vinit and the threshold voltage Vth of the driving transistor Tdr. Therefore, the threshold voltage Vth may be stored in the capacitor C1.

[0149] In the wiring period, a low voltage may be applied to the nth scan control line SCL(n), and thus the third transistor T3 may be turned on. In this case, the voltage of the first node n1 may be the data voltage Vdata supplied through the data line DL. In addition, the voltage of the node (i.e., the third node n3) connected to the driving gate of the driving transistor Tdr may be the difference voltage between the data voltage Vdata and the threshold voltage Vth.

[0150] In the light emitting period, a low voltage may be applied to the light emitting control line ECL, and thus, the first transistor T1 may be turned on. In this case, the current supplied to the light emitting device ED may be proportional to the square of the difference voltage between the gate-source voltage Vgs of the driving transistor Tdr and the threshold voltage Vth. In the light emitting period, the gate voltage of the driving transistor Tdr (i.e., the voltage of the third node n3) may be the difference voltage (=Vdata-Vth) between the data voltage Vdata and the threshold voltage Vth, and the source voltage of the driving transistor Tdr may be the pixel driving voltage Vdd applied through the pixel driving voltage line PL. Therefore, the current supplied to the light emitting device ED may be proportional to the square of the difference voltage (=Vdd-Vdata) between the data voltage Vdata and the pixel driving voltage Vdd.

[0151] That is, according to the present disclosure, the current supplied to the light emitting device ED may be independent of the threshold voltage Vth of the driving transistor Tdr, and may be determined only by the pixel driving voltage Vdd and the data voltage Vdata.

[0152] Therefore, according to the present disclosure, even when the driving transistor Tdr deteriorates so that the threshold voltage Vth of the driving transistor Tdr changes, the current supplied to the light emitting device ED may not be affected by the change in the threshold voltage Vth. Therefore, according to the present disclosure, the current may be controlled only by the data voltage Vdata regardless of the amount of change in the threshold voltage Vth of the driving transistor Tdr.

[0153] Figure 5 It is shown Figure 2 An exemplary diagram of a first pixel circuit shown in FIG. Figure 6 It is shown that Figure 5 An exemplary diagram of a layout of a first pixel circuit layer of a first pixel circuit shown in FIG. Figure 7 It is along Figure 6 The cross-sectional view is taken along the line AA' shown in FIG. That is, Figure 5 shows a first pixel circuit included in one pixel, Figure 6 shows the horizontal structure of the first pixel circuit layer in a pixel, Figure 7 The vertical structure of the first pixel circuit layer in one pixel is shown.

[0154] like Figures 5 to 7As shown, in the pixel P of the light-emitting display panel 100 according to the embodiment of the present disclosure, the first pixel circuit layer 110 may include a substrate 10, a first buffer layer 111, a first semiconductor layer 112 formed in a region of the substrate 10 corresponding to the first transistor T1 to the third transistor T3, a first gate insulating layer 113 covering the first semiconductor layer 112, a first gate layer 114 formed in an island shape in a region of the first gate insulating layer 113 corresponding to the first transistor T1 to the third transistor T3, a first passivation layer 115 covering the first gate layer 114, a first electrode C2a formed in an island shape on the first passivation layer 115, a second passivation layer 116 covering the first electrode C2a, a first layer electrode DCE formed in an island shape on the second passivation layer 116, a third passivation layer (hereinafter referred to as a lower passivation layer) 117 covering the first layer electrode DCE, and a first connection portion CL1a formed in an island shape on the lower passivation layer 117 and connected to the second pixel circuit layer 120. The first connection portion CL1a may be included in the first connection layer 118. The first layer electrode DCE may perform the function of configuring the third electrode C1a of the first capacitor C1 and the function of configuring the second electrode C2b of the second capacitor C2. That is, in the present disclosure, the first layer electrode DCE may be the second electrode C2b, or may be the third electrode C1a.

[0155] First, the substrate 10 may include a display area AA and a non-display area IA, and a plurality of pixels P may be disposed in the display area AA. Figures 5 to 7 One pixel is shown.

[0156] The first buffer layer 111 may be disposed on the substrate 10 to prevent water penetration or improve adhesion with the first semiconductor layer 112 .

[0157] The first buffer layer 111 may include an organic material or an inorganic material and may be formed of at least two layers.

[0158] The first semiconductor layer 112 may be disposed in a region where the first to third transistors T1 to T3 are disposed. The first semiconductor layer 112 may include a polysilicon material.

[0159] The first semiconductor layer 112 according to the embodiment may include first, second, and third channel regions CA1, CA2, and CA3 that are spaced apart from each other, and further may include a plurality of high-concentration doping regions respectively disposed at both ends of the first to third channel regions CA1 to CA3.

[0160] The first to third channel regions CA1 to CA3 may be used as semiconductor layers of the first to third transistors T1 to T3 , respectively.

[0161] The high-concentration doped region may include metal characteristics and may function as a first terminal or a second terminal of each of the first to third transistors T1 to T3 .

[0162] For example, in Figure 7 In the embodiment, the high-concentration doped region provided to the left side of the first channel region CA1 may be the first terminal of the first transistor T1, and the high-concentration doped region provided to the right side of the first channel region CA1 may be the second terminal of the first transistor T1.

[0163] In addition, Figure 7 In the embodiment, the high-concentration doped region provided to the left side of the second channel region CA2 may be the second terminal of the second transistor T2, and the high-concentration doped region provided to the right side of the second channel region CA2 may be the first terminal of the second transistor T2.

[0164] In addition, Figure 7 In the embodiment, the high-concentration doped region provided to the left side of the third channel region CA3 may be the second terminal of the third transistor T3, and the high-concentration doped region provided to the right side of the third channel region CA3 may be the first terminal of the third transistor T3.

[0165] That is to say, as mentioned above Figure 2 As described above, the first terminal of the first transistor T1 may be connected to the pixel driving voltage line PL, the second terminal of the first transistor T1 may be connected to the second terminal of the second transistor T2, and the first terminal of the second transistor T2 may be connected to the second terminal of the third transistor T3.

[0166] In particular, if Figure 2 , 5 As shown in FIG. 7 , the second terminal of the first transistor T1 may be connected to the second terminal of the second transistor T2, and the portion connecting the second terminal of the first transistor T1 to the second terminal of the second transistor T2 may be referred to as a second node n2.

[0167] The second node n2 may be connected to a first connection portion CL1 a for connecting the second node n2 to a first terminal of a driving transistor Tdr included in the second pixel circuit layer 120 .

[0168] Subsequently, a first gate insulating layer 113 may be formed on the entire substrate 10 to cover the first semiconductor layer 112. The first gate insulating layer 113 according to an embodiment may include silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

[0169] Subsequently, the first gate layer 114 may be provided in an independent pattern shape (e.g., an island shape) on the first gate insulating layer 113. The first gate layer 114 may include a first gate Gate1 provided in a region overlapping the first channel region CA1, a second gate Gate2 provided in a region overlapping the second channel region CA2, and a third gate Gate3 provided in a region overlapping the third channel region CA3.

[0170] The first gate Gate1, the high-concentration doping region set to the left side of the first channel region CA1, and the high-concentration doping region set to the right side of the first channel region CA1 may constitute a first transistor T1. The second gate Gate2, the high-concentration doping region set to the left side of the second channel region CA2, and the high-concentration doping region set to the right side of the second channel region CA2 may constitute a second transistor T2. The third gate Gate3, the high-concentration doping region set to the left side of the third channel region CA3, and the high-concentration doping region set to the right side of the third channel region CA3 may constitute a third transistor T3.

[0171] The first gate layer 114 may include one of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a single layer or multiple layers including an alloy thereof.

[0172] Subsequently, a first passivation layer 115 may be formed on the entire substrate 10 to cover the first gate layer 114. The first passivation layer 115 may include SiOx, SiNx, or a multilayer thereof.

[0173] Subsequently, the first electrode C2a of the second capacitor C2 may be provided in a pattern shape (e.g., an island shape) on the first passivation layer 115. The first electrode C2a may include one of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a single layer or multiple layers including an alloy thereof.

[0174] Subsequently, a second passivation layer 116 may be formed on the entire substrate 10 to cover the first electrode C2a. The second passivation layer 116 may include SiOx, SiNx, or a multilayer thereof.

[0175] Subsequently, the first layer electrode DCE may be provided in a pattern shape (e.g., an island shape) on the second passivation layer 116. The first layer electrode DCE may include one of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a single layer or multiple layers including alloys thereof.

[0176] The first layer electrode DCE may be connected to a high-concentration doped region of the first semiconductor layer 112 disposed between the second channel region CA2 and the third channel region CA3 through a third contact hole CH3 disposed in the first gate insulating layer 113, the first passivation layer 115, and the second passivation layer 116. The high-concentration doped region between the second channel region CA2 and the third channel region CA3 may be a first node n1. That is, the first node n1 may connect the first terminal of the second transistor T2 to the second terminal of the third transistor T3.

[0177] The first layer electrode DCE may constitute the second capacitor C2 together with the first electrode C2a and the second passivation layer 116. That is, the first layer electrode DCE may perform the function of the second electrode C2b constituting the second capacitor C2.

[0178] Subsequently, a third passivation layer 117 may be formed on the entire substrate 10 to cover the first layer electrode DCE. The third passivation layer 117 may include SiOx, SiNx, or a multilayer thereof.

[0179] Finally, the first connection layer 118 may be provided in a pattern shape (e.g., an island shape) on the third passivation layer 117. The first connection layer 118 may include one of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a single layer or multiple layers including alloys thereof.

[0180] The first connection layer 118 may include a first connection portion CL1 a electrically connecting the second node n2 to a first terminal of the driving transistor Tdr included in the second pixel circuit layer 120 , and a source / drain SD connected to a first terminal of the third transistor T3 .

[0181] The first connection portion CL1a may be connected to a high-concentration doped region disposed between the first channel region CA1 and the second channel region CA2 of the first semiconductor layer 112 through a first contact hole CH1 disposed in the first gate insulating layer 113, the first passivation layer 115, the second passivation layer 116, and the third passivation layer 117. The high-concentration doped region between the first channel region CA1 and the second channel region CA2 may be a second node n2.

[0182] The first terminal of the third transistor T3 may be connected to the source / drain SD through a fourth contact hole CH4 provided in the first gate insulating layer 113 , the first passivation layer 115 , the second passivation layer 116 , and the third passivation layer 117 .

[0183] Figure 8 It is shown Figure 2 An exemplary diagram of a second pixel circuit shown in FIG. Fig. 9 It is shown that Figure 8 An exemplary diagram of a layout of a second pixel circuit layer of a second pixel circuit shown in, Fig.10 It is along Fig. 9 The cross-sectional view is taken along the line BB' shown in FIG. That is, Figure 8 2 shows a second pixel circuit PC2 included in one pixel, Fig. 9 shows the horizontal structure of the second pixel circuit layer 120 in one pixel, Fig.10 The vertical structure of the second pixel circuit layer 120 in one pixel is shown.

[0184] like Figures 8 to 10 As shown, in the light-emitting display panel according to the embodiment of the present disclosure, the second pixel circuit layer 120 may include a fourth passivation layer (hereinafter referred to as an upper passivation layer) 121 covering the first connection layer 118, a second layer electrode UCE formed in an island shape on the upper passivation layer 121, a fifth passivation layer covering the second layer electrode UCE, a second semiconductor layer 123 provided in a region of the fifth passivation layer 122 corresponding to the fourth transistor T4 and the fifth transistor T5 and the driving transistor Tdr, a second gate insulating layer 124 covering the second semiconductor layer 123, a second gate layer 125 formed in an island shape in a region of the second gate insulating layer 124 corresponding to the fourth transistor T4 and the fifth transistor T5 and the driving transistor Tdr, a sixth passivation layer 126 covering the second gate layer 125, and a second connection portion CL1b formed in an island shape on the sixth passivation layer 126 and connected to the first pixel circuit layer 110. The second connection portion CL1b may be included in the second connection layer 127.

[0185] First, the fourth passivation layer 121 may be formed on the entire substrate 10 to cover the first connection layer 118 included in the first pixel circuit layer 110. The fourth passivation layer 121 may perform the function of a base substrate in the second pixel circuit layer 120. The fourth passivation layer 121 may include SiOx, SiNx, or a multilayer thereof.

[0186] Subsequently, the second layer electrode UCE may be provided in a pattern shape (e.g., an island shape) on the second passivation layer 116. The second layer electrode UCE may include one of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a single layer or multiple layers including alloys thereof.

[0187] The second layer electrode UCE may constitute a first capacitor C1 together with the first layer electrode DCE, the third passivation layer (lower passivation layer) 117 and the fourth passivation layer (upper passivation layer) 121 included in the first pixel circuit layer 110 .

[0188] That is, the second layer electrode UCE may be the fourth electrode C1 b of the first capacitor C1 .

[0189] In this case, the first layer electrode DCE may constitute the second capacitor C2 together with the first electrode C2a, and may constitute the first capacitor C1 together with the second layer electrode UCE.

[0190] To provide additional description, the first layer electrode DCE included in the first pixel circuit layer 110 may perform the function of the second electrode C2 b and may perform the function of the third electrode C1 a .

[0191] The second layer electrode UCE may be disposed under the driving transistor Tdr and may perform the function of a barrier layer. That is, the second layer electrode UCE may reduce parasitic capacitance between a metal line disposed under the second layer electrode UCE and the driving transistor Tdr disposed on the second layer electrode UCE.

[0192] Subsequently, a fifth passivation layer 122 may be formed on the entire substrate 10 to cover the second layer electrode UCE. The fifth passivation layer 122 may include SiOx, SiNx, or a multilayer thereof.

[0193] Subsequently, the second semiconductor layer 123 may be disposed in a region where the fourth transistor T4, the fifth transistor T5, and the driving transistor Tdr are disposed. The second semiconductor layer 123 may include a polysilicon material.

[0194] According to the embodiment, the second semiconductor layer 123 may include a plurality of high-concentration doped regions separated from each other and respectively arranged at both ends of the fourth channel region CA4, the fifth channel region, the driving channel region CAdr and the fourth channel region CA4. In addition, it may include a plurality of high-concentration doped regions respectively arranged at both ends of the fifth channel region and a plurality of high-concentration doped regions respectively arranged at both ends of the driving channel region CAdr.

[0195] The fourth channel region CA4 may be used as a semiconductor layer of the fourth transistor T4 , the fifth channel region may be used as a semiconductor layer of the fifth transistor T5 , and the driving channel region CAdr may be used as a semiconductor layer of the driving transistor Tdr.

[0196] The high-concentration doped region may include metal characteristics. Therefore, the plurality of high-concentration doped regions respectively disposed at both ends of the fourth transistor T4 may be used as the first terminal and the second terminal of the fourth transistor T4, the plurality of high-concentration doped regions respectively disposed at both ends of the fifth transistor T5 may be used as the first terminal and the second terminal of the fifth transistor T5, and the plurality of high-concentration doped regions respectively disposed at both ends of the driving transistor Tdr may be used as the first terminal and the second terminal of the driving transistor Tdr.

[0197] For example, in Fig.10 In the embodiment, the high-concentration doped region provided to the left of the driving channel region CAdr may be the first terminal of the driving transistor Tdr, and the high-concentration doped region provided to the right of the driving channel region CAdr may be the second terminal of the driving transistor Tdr.

[0198] In addition, Fig.10 In the embodiment, the high-concentration doped region disposed to the left side of the fourth channel region CA4 may be the second terminal of the fourth transistor T4, and the high-concentration doped region disposed to the right side of the fourth channel region CA4 may be the first terminal of the fourth transistor T4.

[0199] That is to say, as mentioned above Figure 2 As described above, the first terminal of the driving transistor Tdr may be connected to the second terminal of the first transistor T1 and the second terminal of the second transistor T2 , and the second terminal of the driving transistor Tdr may be connected to the second terminal of the fifth transistor T5 and the light emitting device ED.

[0200] In addition, a first terminal of the fourth transistor T4 may be connected to the initialization voltage line IVL, and a second terminal of the fourth transistor T4 may be connected to the driving gate Gatedr of the driving transistor Tdr.

[0201] In this case, because the second terminal of the fourth transistor T4 is connected to the driving gate Gatedr of the driving transistor Tdr, the fourth channel region CA4 may not be directly connected to the driving channel region CAdr.

[0202] The first terminal of the fifth transistor T5 can be electrically connected to the first terminal of the fourth transistor T4. Therefore, the high-concentration doped region forming the first terminal of the fifth channel region (forming the fifth transistor T5) can be connected to the high-concentration doped region forming the first terminal of the fourth channel region CA4 (forming the fourth transistor T4).

[0203] Subsequently, a second gate insulating layer 124 may be formed on the entire substrate 10 to cover the second semiconductor layer 123. The second gate insulating layer 124 according to an embodiment may include SiOx, SiNx, or a multilayer thereof.

[0204] Subsequently, the second gate layer 125 may be disposed in an independent pattern shape (e.g., an island shape) on the second gate insulating layer 124. The second gate layer 125 may include a driving gate Gatedr disposed in a region overlapping the driving channel region CAdr, a fourth gate Gate4 disposed in a region overlapping the fourth channel region CA4, and a fifth gate disposed in a region overlapping the fifth channel region.

[0205] The driving gate Gatedr, the driving channel region CAdr, and a plurality of high-concentration doped regions disposed to the right and left sides of the driving channel region CAdr may constitute a driving transistor Tdr. The fourth gate Gate4, the fourth channel region CA4, and a plurality of high-concentration doped regions disposed to the right and left sides of the fourth channel region CA4 may constitute a fourth transistor T4. The fifth gate, the fifth channel region, and a plurality of high-concentration doped regions disposed to the right and left sides of the fifth channel region may constitute a fifth transistor T5.

[0206] The second gate layer 125 may include one of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a single layer or multiple layers including an alloy thereof.

[0207] Subsequently, a sixth passivation layer 126 may be formed on the entire substrate 10 to cover the second gate layer 125. The sixth passivation layer 126 may include SiOx, SiNx, or a multilayer thereof.

[0208] Finally, the second connection layer 127 may be provided in a pattern shape (e.g., an island shape) on the sixth passivation layer 126. The second connection layer 127 may include one of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a single layer or multiple layers including alloys thereof.

[0209] The second connection layer 127 may include a second connection portion CL1b connecting a first terminal of the driving transistor Tdr to a first connection portion CL1a included in the first pixel circuit layer 110 and a third connection portion GSD connecting a driving gate Gatedr of the driving transistor Tdr to a second terminal of the fourth transistor T4.

[0210] The second connection portion CL1b may be connected to the first connection portion CL1a included in the first pixel circuit layer 110 through a second contact hole CH2 formed in the fourth passivation layer 121, the fifth passivation layer 122, the second gate insulating layer 124, and the sixth passivation layer 126. The first connection portion CL1a may be connected to the second terminal of the first transistor T1.

[0211] In addition, the second connection portion CL1b may be connected to the first terminal of the driving transistor Tdr, and the first connection portion CL1a may be connected to the second terminal of the first transistor T1 through the fifth contact hole CH5 formed in the second gate insulating layer 124 and the sixth passivation layer 126. Therefore, the first terminal of the driving transistor Tdr may be electrically connected to the second terminal of the first transistor T1 through the first connection portion CL1a and the second connection portion CL1b.

[0212] The third connection portion GSD can be connected to the driving gate Gatedr of the driving transistor Tdr through a sixth contact hole CH6 formed in the second gate insulating layer 124. In addition, it can be connected to the second layer electrode UCE and the second terminal of the fourth transistor T4 through a seventh contact hole CH7 formed in the fifth passivation layer 122, the second semiconductor layer 123, the second gate insulating layer 124 and the sixth passivation layer 126.

[0213] Therefore, the second terminal of the fourth transistor T4, the second layer electrode UCE, and the driving gate Gatedr of the driving transistor Tdr may be electrically connected to each other through the third connection portion GSD.

[0214] like Figure 3 As shown, the second connection layer 127 may be covered by a planarization layer 160 .

[0215] The light emitting device layer 170 may be included in the planarization layer 160. The light emitting device layer 170 may be covered by the encapsulation layer 190.

[0216] That is, the light-emitting display panel 100 according to the present disclosure may include a first pixel circuit layer 110, a second pixel circuit layer 120 and a light-emitting device layer 170. In this case, the planarization layer 160 may be disposed between the second pixel circuit layer 120 and the light-emitting device layer 170, and the light-emitting device layer 170 may be covered by the encapsulation layer 190.

[0217] Fig.11A and Fig. 11B are exploded cross-sectional views respectively showing a first pixel circuit layer and a second pixel circuit layer respectively constituting a light-emitting display panel according to an embodiment of the present disclosure, Fig.12 It shows that Fig.11A and Fig. 11B 2 is a cross-sectional view of an example in which the first pixel circuit layer and the second pixel circuit layer are coupled to each other. That is, Fig.11A shows a cross-sectional view of the first pixel circuit layer 110, Fig. 11B A cross-sectional view of the second pixel circuit layer 120 is shown.

[0218] As described above, the light-emitting display panel according to an embodiment of the present disclosure may include: a first pixel circuit layer 110, which includes a first pixel circuit PC1 including a first layer electrode DCE; a second pixel circuit layer 120, which includes a second pixel circuit PC2 including a second layer electrode UCE that together with the first layer electrode DCE constitutes a first capacitor C1; and a light-emitting device layer 170, which includes a light-emitting device ED electrically connected to a driving transistor Tdr included in the second pixel circuit layer 120.

[0219] A lower passivation layer (third passivation layer) 117 included in the first pixel circuit layer 110 and an upper passivation layer (fourth passivation layer) 121 included in the second pixel circuit layer 120 may be disposed between the first layer electrode DCE and the second layer electrode UCE.

[0220] The first layer electrode DCE may constitute a second capacitor C2 together with a first electrode C2 a included in the first pixel circuit layer 110 , and may constitute a first capacitor C1 together with a second layer electrode UCE included in the second pixel circuit layer 120 .

[0221] The first capacitor C1 and the second capacitor C2 may perform a function of storing a threshold voltage of the driving transistor Tdr for internal compensation.

[0222] The first transistor T1 connected to the pixel driving voltage line PL and included in the first pixel circuit layer 110 may be connected to the driving transistor Tdr connected to the light emitting device ED and included in the second pixel circuit layer 120 through the connection line CL1.

[0223] The connection line CL1 may include a first connection portion CL1a connected to the first transistor T1 through a first contact hole CH1 provided in the first pixel circuit layer 110, and a second connection portion CL1b connected to the driving transistor Tdr through a second contact hole CH2 provided in the second pixel circuit layer 120. The first connection portion CL1a may be connected to the second connection portion CL1b.

[0224] In this case, the driving transistor Tdr may transfer a current corresponding to the data voltage supplied from the first pixel circuit PC1 to the light emitting device ED.

[0225] The first pixel circuit PC1 may include a first layer electrode DCE; a first transistor T1 including a gate connected to the light emitting control line ECL and a first terminal connected to the pixel driving voltage line PL; a second transistor including a gate connected to the n-2th scanning control line SCL(n-2) and a first terminal connected to the first layer electrode DCE; a third transistor T3 including a gate connected to the nth scanning control line SCL(n), a first terminal connected to the data line DL and a second terminal connected to the first layer electrode DCE; and a second capacitor C2 including a first terminal connected to the first terminal of the first transistor T1 and a second terminal connected to the first layer electrode DCE.

[0226] The second pixel circuit PC2 may include a second layer electrode UCE; a driving transistor Tdr including a gate connected to the second layer electrode UCE, a first terminal connected to the second terminal of the first transistor T1, and a second terminal connected to the light emitting device ED; a fourth transistor T4 including a gate connected to the n-2th scanning control line SCL(n-2), a first terminal connected to the initialization voltage line IVL, and a second terminal connected to the second layer electrode UCE; and a fifth transistor T5 including a gate connected to the n-2th scanning control line SCL(n-2), a first terminal connected to the initialization voltage line IVL, and a second terminal connected to the second terminal of the driving transistor Tdr.

[0227] The first pixel circuit layer 110 may include a substrate 10, a first semiconductor layer 112 formed in an area corresponding to the first to third transistors T1 to T3, a first gate insulating layer 113 covering the first semiconductor layer 112, a first gate layer 114 formed in an island shape in an area of ​​the first gate insulating layer 113 corresponding to the first to third transistors T1 to T3, a first passivation layer 115 covering the first gate layer 114, a first electrode C2a formed in an island shape on the first passivation layer 115, a second passivation layer 116 covering the first electrode C2a, a first layer electrode DCE formed in an island shape on the second passivation layer 116, a lower passivation layer (third passivation layer) 117 covering the first layer electrode DCE, and a first connection portion CL1a formed in an island shape on the lower passivation layer 117 and connected to the second pixel circuit layer 120.

[0228] The second pixel circuit layer 120 may include an upper passivation layer (fourth passivation layer) 121 covering the first connection portion CL1a, a second layer electrode UCE formed in an island shape on the upper passivation layer 121, a fifth passivation layer 122 covering the second layer electrode UCE, a second semiconductor layer 123 arranged in an area of ​​the fifth passivation layer 122 corresponding to the fourth transistor T4 and the fifth transistor T5 and the driving transistor Tdr, a second gate insulating layer 124 covering the second semiconductor layer 123, a second gate layer 125 formed in an island shape in an area of ​​the second gate insulating layer 124 corresponding to the fourth transistor T4 and the fifth transistor T5 and the driving transistor Tdr, a sixth passivation layer 126 covering the second gate layer 125, and a second connection portion CL1b formed in an island shape on the sixth passivation layer 126 and connected to the first pixel circuit layer 110.

[0229] In the embodiment of the present disclosure, it is described that all transistors included in the pixel driving circuit PDC are implemented as P-type, but the present disclosure is not limited thereto. Therefore, without deviating from the technical feature of the present disclosure of realizing ultra-high resolution pixels by stacking two circuit layers, all transistors can be changed to N-type, or some transistors can be changed to N-type.

[0230] The light-emitting display device to which the present invention is applied can be applied to portable electronic devices requiring high resolution such as smartphones, mobile communication terminals, mobile phones, tablet personal computers (PCs), smart watches, watch phones, and wearable devices, home appliances such as televisions, laptops, monitors, and refrigerators, and various products such as virtual image display devices and head-mounted display devices.

[0231] In the light-emitting display panel according to the present disclosure, the pixel driving circuit included in each pixel can be implemented as a double-layer structure. Therefore, even in the case of reducing the size of each pixel by achieving high resolution, the pixel driving circuit can be fully set in each pixel, thereby realizing a high-resolution light-emitting display panel.

[0232] The above-mentioned features, structures and effects of the present disclosure are included in at least one embodiment of the present disclosure, but are not limited to one embodiment. In addition, those skilled in the art can realize the features, structures and effects described in at least one embodiment of the present disclosure by combining or modifying other embodiments. Therefore, the contents related to the combination and modification should be interpreted as being within the scope of the present disclosure.

[0233] It will be apparent to those skilled in the art that various modifications and variations may be made to the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting display panel, the light-emitting display panel comprising a plurality of pixels, in, Each of the plurality of pixels comprises: A first pixel circuit layer, the first pixel circuit layer comprising a first pixel circuit, the first pixel circuit having a first layer of electrodes; A second pixel circuit layer, the second pixel circuit layer comprising a second pixel circuit, the second pixel circuit comprising a driving transistor and a second layer electrode; a first capacitor having a first plate and a second plate, wherein the first plate includes the first layer of electrodes and the second plate includes the second layer of electrodes; and a light emitting device layer including a light emitting device electrically connected to the driving transistor provided in the second pixel circuit layer, The light-emitting display panel further includes a second capacitor having a third plate and a fourth plate, wherein the third plate includes the first layer electrode and the fourth plate includes the first electrode arranged in the first pixel circuit layer.

2. The light-emitting display panel according to claim 1, further comprising: A lower passivation layer, the lower passivation layer is arranged in the first pixel circuit layer and between the first layer electrode and the second layer electrode; as well as An upper passivation layer is disposed in the second pixel circuit layer and between the first layer electrode and the second layer electrode.

3. The light-emitting display panel according to claim 1, wherein: The first capacitor and the second capacitor store a threshold voltage of the driving transistor for internal compensation.

4. The light-emitting display panel according to claim 1, wherein: The first transistor connected to the pixel driving voltage line and disposed in the first pixel circuit layer is connected to the driving transistor connected to the light emitting device and disposed in the second pixel circuit layer through a connecting line.

5. The light emitting display panel according to claim 4, wherein: The connecting line comprises: a first connection portion connected to the first transistor through a first contact hole provided in the first pixel circuit layer; and a second connection portion, the second connection portion being connected to the driving transistor through a second contact hole provided in the second pixel circuit layer, and The first connection portion is connected to the second connection portion.

6. The light-emitting display panel according to claim 1, wherein: The driving transistor transmits a current corresponding to a data voltage supplied from the first pixel circuit to the light emitting device.

7. The light-emitting display panel according to claim 1, wherein: The first pixel circuit comprises: the first layer of electrodes; a first transistor including a gate connected to a light emitting control line and a first terminal connected to a pixel driving voltage line; a second transistor including a gate connected to an n-2 th scan control line and a first terminal connected to the first layer electrode; a third transistor including a gate connected to an nth scanning control line, a first terminal connected to a data line, and a second terminal connected to the first layer electrode; and A second capacitor including a first terminal connected to the first terminal of the first transistor and a second terminal connected to the first layer electrode.

8. The light emitting display panel according to claim 7, wherein: The second pixel circuit comprises: the second layer of electrodes; the driving transistor including a gate connected to the second layer electrode, a first terminal connected to the second terminal of the first transistor, and a second terminal connected to the light emitting device; a fourth transistor including a gate connected to the n-2 th scan control line, a first terminal connected to an initialization voltage line, and a second terminal connected to the second layer electrode; and A fifth transistor including a gate connected to the (n-2)th scan control line, a first terminal connected to the initialization voltage line, and a second terminal connected to the second terminal of the driving transistor.

9. The light emitting display panel according to claim 1, wherein: The first pixel circuit layer comprises: substrate; a first semiconductor layer formed in a region corresponding to the first to third transistors; a first gate insulating layer, wherein the first gate insulating layer at least partially covers the first semiconductor layer; a first gate layer, the first gate layer being formed in an island shape in a region of the first gate insulating layer corresponding to the first to third transistors; a first passivation layer, the first passivation layer at least partially covering the first gate layer; a first electrode, wherein the first electrode is formed in an island shape on the first passivation layer; a second passivation layer, wherein the second passivation layer at least partially covers the first electrode; The first layer electrode is formed in an island shape on the second passivation layer; a lower passivation layer, the lower passivation layer at least partially covering the first electrode layer; and A first connection portion is formed in an island shape on the lower passivation layer and connected to the second pixel circuit layer.

10. The light emitting display panel according to claim 9, wherein: The second pixel circuit layer includes: an upper passivation layer, wherein the upper passivation layer at least partially covers the first connecting portion; The second layer electrode is formed in an island shape on the upper passivation layer; a fifth passivation layer, wherein the fifth passivation layer at least partially covers the second electrode layer; a second semiconductor layer formed in a region of the fifth passivation layer corresponding to the fourth transistor, the fifth transistor and the driving transistor; a second gate insulating layer, wherein the second gate insulating layer at least partially covers the second semiconductor layer; a second gate layer, the second gate layer being formed in an island shape in a region of the second gate insulating layer corresponding to the fourth transistor, the fifth transistor, and the driving transistor; a sixth passivation layer, the sixth passivation layer at least partially covering the second gate layer; and A second connection portion is formed in an island shape on the sixth passivation layer and connected to the first pixel circuit layer.

11. A display device, comprising: A display panel, comprising a plurality of pixels, wherein each of the plurality of pixels comprises: A first pixel circuit layer, the first pixel circuit layer comprising a first pixel circuit, the first pixel circuit having a first layer of electrodes; a second pixel circuit layer, the second pixel circuit layer comprising a second pixel circuit, the second pixel circuit comprising a second layer electrode, the second layer electrode and the first layer electrode together forming a first capacitor; and a light emitting device layer including a light emitting device electrically connected to a driving transistor provided in the second pixel circuit layer, The first layer electrode and the first electrode arranged in the first pixel circuit layer together form a second capacitor.

12. The display device according to claim 11, wherein: The display panel further includes: a lower passivation layer, the lower passivation layer being disposed in the first pixel circuit layer and between the first layer electrode and the second layer electrode; and An upper passivation layer is disposed in the second pixel circuit layer and between the first layer electrode and the second layer electrode.

13. The display device according to claim 11, wherein: The first capacitor and the second capacitor store a threshold voltage of the driving transistor for internal compensation.

14. The display device according to claim 11, wherein: The first transistor connected to the pixel driving voltage line and disposed in the first pixel circuit layer is connected to the driving transistor connected to the light emitting device and disposed in the second pixel circuit layer through a connecting line.

15. The display device according to claim 14, wherein: The connecting line comprises: a first connection portion connected to the first transistor through a first contact hole provided in the first pixel circuit layer; and a second connection portion, the second connection portion being connected to the driving transistor through a second contact hole provided in the second pixel circuit layer, and The first connection portion is connected to the second connection portion.

16. The display device according to claim 11, wherein: The first pixel circuit comprises: the first layer of electrodes; a first transistor including a gate connected to a light emitting control line and a first terminal connected to a pixel driving voltage line; a second transistor including a gate connected to an n-2 th scan control line and a first terminal connected to the first layer electrode; a third transistor including a gate connected to an nth scanning control line, a first terminal connected to a data line, and a second terminal connected to the first layer electrode; and A second capacitor including a first terminal connected to the first terminal of the first transistor and a second terminal connected to the first layer electrode.

17. The display device according to claim 16, wherein: The second pixel circuit comprises: the second layer of electrodes; the driving transistor including a gate connected to the second layer electrode, a first terminal connected to the second terminal of the first transistor, and a second terminal connected to the light emitting device; a fourth transistor including a gate connected to the n-2 th scan control line, a first terminal connected to an initialization voltage line, and a second terminal connected to the second layer electrode; and A fifth transistor including a gate connected to the (n-2)th scan control line, a first terminal connected to the initialization voltage line, and a second terminal connected to the second terminal of the driving transistor.

18. The display device according to claim 15, wherein: The second pixel circuit comprises: an upper passivation layer, wherein the upper passivation layer at least partially covers the first connecting portion; A second layer of electrodes, the second layer of electrodes being formed in an island shape on the upper passivation layer; a fifth passivation layer, wherein the fifth passivation layer at least partially covers the second electrode layer; a second semiconductor layer formed in a region of the fifth passivation layer corresponding to the fourth transistor, the fifth transistor and the driving transistor; a second gate insulating layer, wherein the second gate insulating layer at least partially covers the second semiconductor layer; a second gate layer, the second gate layer being formed in an island shape in a region of the second gate insulating layer corresponding to the fourth transistor, the fifth transistor, and the driving transistor; a sixth passivation layer, the sixth passivation layer at least partially covering the second gate layer; and A second connection portion is formed in an island shape on the sixth passivation layer and connected to the first pixel circuit layer.

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