Array substrate and display device

Abstract

An array substrate and a display device. The array substrate includes a base substrate, a pixel driving layer, a flat layer, an organic light-emitting device, an encapsulation layer, a first retaining wall and a plurality of first channel lines; the first retaining wall is located in a peripheral area and includes a first retaining wall portion extending along a first direction; the plurality of first channel lines are located in the peripheral area and are located on a side of the encapsulation layer away from the base substrate; the encapsulation layer includes an organic encapsulation layer, the flat layer includes a first edge portion extending along a first direction, the first edge portion is located between the first retaining wall portion and the display area, the orthographic projection of the first edge portion on the base substrate is covered by the orthographic projection of the organic encapsulation layer on the base substrate, and the orthographic projection of at least one of the plurality of first channel lines on the base substrate is located on a side of the first edge portion away from the display area. The array substrate can reduce the width of the peripheral area, thereby realizing a narrow frame design of a display device using the array substrate.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an array substrate and a display device. Background Art

[0002] With the continuous development of touch technology, smart electronic products such as mobile phones and tablet computers are integrated with touch substrates with touch functions. On the other hand, with the rapid development of functional electronic products such as mobile phones and tablet computers, smart electronic products such as mobile phones and tablet computers gradually adopt narrow frame or even frameless design, that is, "full screen" design, so as to provide users with better experience. Summary of the invention

[0003] The embodiments of the present disclosure provide an array substrate and a display device. The array substrate can further reduce the width of the peripheral area by arranging at least part of the channel lines on the slope of the packaging layer, thereby realizing a narrow frame or even a frameless design of the display device using the array substrate.

[0004] At least one embodiment of the present disclosure provides an array substrate, comprising: a substrate, comprising a display area and a peripheral area located around the display area; a pixel driving layer located on the substrate; a planar layer located on a side of the pixel driving layer away from the substrate; an organic light emitting device located on a side of the planar layer away from the pixel driving layer; an encapsulation layer located on a side of the organic light emitting device away from the substrate; a first retaining wall located in the peripheral area and comprising a first retaining wall portion extending along a first direction; and a plurality of first channel lines located in the peripheral area and located on a side of the encapsulation layer away from the substrate, each of the plurality of first channel lines extending along the first direction, the plurality of first channel lines being arranged along a second direction, the second direction being substantially perpendicular to the first direction; the encapsulation layer comprising an organic encapsulation layer, the planar layer comprising a first edge portion extending along the first direction, the first edge portion being located between the first retaining wall portion and the display area, the orthographic projection of the first edge portion on the substrate substrate being covered by the orthographic projection of the organic encapsulation layer on the substrate substrate, and the orthographic projection of at least one of the plurality of first channel lines on the substrate substrate being located on a side of the first edge portion away from the display area.

[0005] For example, in an array substrate provided by an embodiment of the present disclosure, the organic encapsulation layer includes a second edge portion extending along the first direction, the second edge portion is located between the first edge portion and the first barrier wall portion, and the orthographic projection of at least one first channel line among the multiple first channel lines on the base substrate is located within the orthographic projection of the second edge portion on the base substrate.

[0006] For example, in an array substrate provided in an embodiment of the present disclosure, the plurality of first channel lines include a plurality of first flat channel lines located on a side of the first edge portion away from the base substrate and a plurality of first sloped channel lines located on a side of the second edge portion away from the base substrate, and a spacing between two adjacent first sloped channel lines is greater than a spacing between two adjacent first flat channel lines.

[0007] For example, in an array substrate provided by an embodiment of the present disclosure, a spacing between two adjacent first slope channel lines is 1.05-2 times a spacing between two adjacent first flat channel lines.

[0008] For example, in an array substrate provided by an embodiment of the present disclosure, among the plurality of first slope channel lines, a spacing between two adjacent first slope channel lines is 1.05-2 times of a width of the first slope channel line.

[0009] For example, in an array substrate provided by an embodiment of the present disclosure, a first channel line among the multiple first channel lines that is farthest from the display area is part of the ground line, and an orthographic projection of a first channel line among the multiple first channel lines that is farthest from the display area on the base substrate is located between the orthographic projection of the organic encapsulation layer on the base substrate and the orthographic projection of the first barrier wall portion on the base substrate.

[0010] For example, an array substrate provided by an embodiment of the present disclosure further includes: a plurality of touch drive electrodes, located in the display area and on a side of the packaging layer away from the base substrate; a plurality of touch sensing electrodes, located in the display area and on a side of the packaging layer away from the base substrate; a touch drive signal line, connected to each of the touch drive electrodes and extending to the peripheral area; and a touch sensing signal line, connected to each of the touch sensing electrodes and extending to the peripheral area, at least part of the plurality of first channel lines being a part of the touch drive signal line or the touch sensing signal line.

[0011] For example, in an array substrate provided by an embodiment of the present disclosure, the first retaining wall includes a second retaining wall portion extending along the second direction, and the array substrate also includes: a plurality of second channel lines extending along the second direction, the flat layer includes a third edge portion extending along the second direction, the third edge portion is located between the second retaining wall portion and the display area, the orthographic projection of the third edge portion on the base substrate is covered by the orthographic projection of the organic encapsulation layer on the base substrate, and the orthographic projection of at least one of the plurality of second channel lines on the base substrate is located on a side of the third edge portion away from the display area.

[0012] For example, an array substrate provided by an embodiment of the present disclosure further includes a plurality of touch drive electrodes located in the display area and on a side of the packaging layer away from the base substrate; a plurality of touch sensing electrodes located in the display area and on a side of the packaging layer away from the base substrate; a touch drive signal line connected to each of the touch drive electrodes and extending to the peripheral area; and a touch sensing signal line connected to each of the touch sensing electrodes and extending to the peripheral area, each of the plurality of touch sensing electrodes extending along the first direction, the plurality of touch sensing electrodes being arranged along the second direction, at least some of the plurality of first channel lines being a part of the touch sensing signal line, each of the plurality of touch drive electrodes extending along the second direction, the plurality of touch drive electrodes being arranged along the first direction, and at least some of the plurality of second channel lines being a part of the touch drive signal line.

[0013] For example, in an array substrate provided by an embodiment of the present disclosure, the organic encapsulation layer includes a fourth edge portion extending along the second direction, the fourth edge portion is located between the third edge portion and the second barrier wall portion, and the orthographic projection of at least one second channel line among the multiple second channel lines on the base substrate is located within the orthographic projection of the fourth edge portion on the base substrate.

[0014] For example, in an array substrate provided in an embodiment of the present disclosure, the plurality of second channel lines include a plurality of second flat channel lines located on a side of the third edge portion away from the base substrate and a plurality of second sloped channel lines located on a side of the fourth edge portion away from the base substrate, and a spacing between two adjacent second sloped channel lines is greater than a spacing between two adjacent second flat channel lines.

[0015] For example, in an array substrate provided by an embodiment of the present disclosure, a spacing between two adjacent second slope channel lines is 1.05-2 times a spacing between two adjacent second flat channel lines.

[0016] For example, in an array substrate provided by an embodiment of the present disclosure, among the plurality of second slope channel lines, a spacing between two adjacent second slope channel lines is greater than or equal to 1.05-2 times the width of the first slope channel line.

[0017] For example, an array substrate provided by an embodiment of the present disclosure also includes: a second retaining wall, which is arranged on the base substrate and located in the peripheral area, the second retaining wall is located between the first retaining wall and the display area, the second retaining wall includes a third retaining wall portion extending along the first direction, and the orthographic projection of at least one first channel line among the multiple first channel lines on the base substrate is located within the orthographic projection of the third retaining wall portion on the base substrate.

[0018] For example, an array substrate provided by an embodiment of the present disclosure also includes: a second retaining wall, which is arranged on the base substrate and located in the peripheral area, the second retaining wall is located between the first retaining wall and the display area, the second retaining wall includes a third retaining wall portion extending along the first direction, and the orthographic projections of the multiple first channel lines on the base substrate are located on the side of the orthographic projection of the third retaining wall portion on the base substrate close to the display area.

[0019] For example, in an array substrate provided in an embodiment of the present disclosure, the organic light-emitting device includes an anode, a light-emitting layer, and a cathode stacked in sequence in a direction away from the base substrate.

[0020] For example, in an array substrate provided in one embodiment of the present disclosure, the encapsulation layer also includes: a first inorganic encapsulation layer, located on a side of the organic light-emitting device away from the base substrate; and a second inorganic encapsulation layer, located on a side of the organic encapsulation layer away from the first inorganic encapsulation layer, the first inorganic encapsulation layer and the second inorganic encapsulation layer cover the first retaining wall, the organic encapsulation layer is sandwiched between the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the multiple first channel lines are located on a side of the second inorganic encapsulation layer away from the base substrate.

[0021] At least one embodiment of the present disclosure further provides an array substrate, which includes a substrate, including a display area and a peripheral area located around the display area; a pixel driving layer located on the substrate; an organic light-emitting device located on the pixel driving layer; an encapsulation layer located on the organic light-emitting device, the encapsulation layer including a first inorganic encapsulation layer and an organic encapsulation layer arranged in sequence; a plurality of first channel lines located in the peripheral area and on a side of the encapsulation layer away from the substrate, each of the plurality of first channel lines extending along a first direction, the plurality of first channel lines arranged along a second direction, the second direction being substantially perpendicular to the first direction; in the peripheral area, the first inorganic encapsulation layer, in a direction from the display area to the peripheral area, includes a first inorganic encapsulation portion, an inorganic encapsulation connecting portion, and a second inorganic encapsulation portion arranged continuously, the inorganic encapsulation connecting portion being configured to connect the first inorganic encapsulation portion and the second inorganic encapsulation portion. The encapsulation part, in the peripheral area, in the direction from the display area to the peripheral area, the organic encapsulation layer includes a first organic encapsulation part and a second organic encapsulation part which are continuously arranged, the edge of the second organic encapsulation part away from the display area is the edge of the organic encapsulation layer, the orthographic projection of the first organic encapsulation part on the substrate overlaps with the orthographic projection of the first inorganic encapsulation part and the inorganic encapsulation connecting part on the substrate, the orthographic projection of the second organic encapsulation part on the substrate overlaps with the orthographic projection of the second inorganic encapsulation part on the substrate, in the direction perpendicular to the substrate, the distance d1 between the first inorganic encapsulation part and the substrate substrate is greater than the distance d2 between the second inorganic encapsulation part and the substrate substrate, and the orthographic projection of at least one of the multiple first channel lines on the substrate substrate falls within the orthographic projection of the second inorganic encapsulation part on the substrate substrate.

[0022] For example, an array substrate provided by an embodiment of the present disclosure also includes: a first retaining wall, located in the peripheral area and including a first retaining wall portion extending along the first direction; and a flat layer, located on the side of the pixel driving layer away from the base substrate, the flat layer including a first edge portion extending along the first direction, the first edge portion being located between the first retaining wall portion and the display area, the orthographic projection of the first inorganic packaging portion on the base substrate overlaps with the orthographic projection of the first edge portion on the base substrate, and the difference between the distance d1 between the first inorganic packaging portion and the base substrate and the distance d2 between the second inorganic packaging portion and the base substrate is greater than or equal to the maximum thickness of the portion of the flat layer overlapping with the inorganic packaging connection portion in a direction perpendicular to the base substrate.

[0023] For example, in an array substrate provided in an embodiment of the present disclosure, the flat layer includes: a first sub-flat layer, located on a side of the pixel driving layer away from the base substrate; and a second sub-flat layer, located on a side of the first sub-flat layer away from the pixel driving layer, and the difference between the distance d1 between the first inorganic packaging part and the base substrate and the distance d2 between the second inorganic packaging part and the base substrate is greater than or equal to the sum of the maximum thickness of the first sub-flat layer overlapping with the inorganic packaging connection part in a direction perpendicular to the base substrate and the maximum thickness of the second sub-flat layer overlapping with the inorganic packaging connection part in a direction perpendicular to the base substrate.

[0024] For example, in an array substrate provided in an embodiment of the present disclosure, the plurality of first channel lines include a plurality of first flat channel lines located on a side of the first organic packaging portion away from the base substrate and a plurality of first slope channel lines located on a side of the second organic packaging portion away from the base substrate, and a spacing between two adjacent first slope channel lines is greater than a spacing between two adjacent first flat channel lines.

[0025] For example, in an array substrate provided by an embodiment of the present disclosure, a spacing between two adjacent first slope channel lines is 1.05-2 times a spacing between two adjacent first flat channel lines.

[0026] For example, in an array substrate provided by an embodiment of the present disclosure, among the plurality of first slope channel lines, a spacing between two adjacent first slope channel lines is 1.05-2 times of a width of the first slope channel line.

[0027] At least one embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned array substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0029] Figure 1 is a schematic cross-sectional view of a peripheral area of ​​an array substrate;

[0030] Figure 2 is a cross-sectional schematic diagram of a peripheral area of ​​another array substrate;

[0031] Figure 3 A schematic plan view of an array substrate provided according to an embodiment of the present disclosure;

[0032] Figure 4According to an embodiment of the present disclosure, an array substrate is provided along Figure 3 Schematic diagram of the cross section in the AA direction;

[0033] Figure 5 According to an embodiment of the present disclosure, an array substrate is provided along Figure 3 Schematic diagram of the cross section in the BB direction;

[0034] Figure 6 A schematic plan view of another array substrate provided according to an embodiment of the present disclosure;

[0035] Figure 7 According to an embodiment of the present disclosure, an array substrate is provided along Figure 6 Schematic diagram of the cross section in the CC direction;

[0036] Figure 8 According to an embodiment of the present disclosure, an array substrate is provided along Figure 6 Schematic diagram of the cross section in the middle DD direction;

[0037] Fig. 9 A schematic plan view of an array substrate provided according to an embodiment of the present disclosure;

[0038] Fig.10 According to an embodiment of the present disclosure, an array substrate is provided along Fig. 9 Schematic diagram of the cross section in the EE direction;

[0039] Fig.11 According to an embodiment of the present disclosure, an array substrate is provided along Fig. 9 Schematic diagram of the cross section in the FF direction;

[0040] Fig.12 A schematic plan view of another array substrate provided according to an embodiment of the present disclosure;

[0041] Fig.13 According to an embodiment of the present disclosure, an array substrate is provided along Figure 5 Schematic diagram of the cross section in the middle GG direction;

[0042] Fig.14 According to an embodiment of the present disclosure, an array substrate is provided along Figure 5 Schematic diagram of the cross section in the middle HH direction;

[0043] Fig.15 is a cross-sectional schematic diagram of an array substrate provided according to an embodiment of the present disclosure; and

[0044] Fig.16 The present invention is a schematic structural diagram of a display device provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0046] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0047] At present, in order to realize the lightweight design of display devices (for example, organic light-emitting diode display devices), the display panel and the touch structure can be integrated together. Therefore, FMLOC (Flexible Multiple Layer On Cell) touch technology came into being. FMLOC touch technology is to directly make various electrode layers and various wirings of the touch structure on the packaging layer, so as to integrate the touch structure on the display panel. Therefore, the display device using FMLOC touch technology can not only realize the lightweight design of the display device, but also realize flexible display and flexible touch.

[0048] In a display device using the FMLOC touch technology, a signal channel line connected to a touch driving electrode (Tx) and a touch sensing electrode (Rx) is disposed in a peripheral area of ​​the display device. Figure 1 FIG. 1 is a schematic cross-sectional view of a peripheral region of an array substrate. Figure 1As shown, an encapsulation layer 20 is provided on the base substrate 10; the encapsulation layer 20 includes two inorganic encapsulation layers 21 and an organic encapsulation layer 22 sandwiched between the two inorganic encapsulation layers 21; a signal trace 30 connected to a touch drive electrode (Tx) or a touch sensing electrode (Rx) is formed on the surface of the encapsulation layer 20 away from the base substrate 10. Since the organic encapsulation layer 22 undergoes a leveling process, a slope portion with a gradually decreasing thickness is formed in the peripheral area of ​​the array substrate. In order to avoid the influence of the slope on the signal trace 30, the above-mentioned signal trace 30 is usually formed at a position corresponding to the flat portion of the organic encapsulation layer 22, resulting in a larger width of the peripheral area, which is not conducive to realizing a narrow frame design of the display device.

[0049] Figure 2 FIG. 1 is a cross-sectional schematic diagram of another array substrate. Figure 2 As shown, the array substrate includes a base substrate 10, an encapsulation layer 20, a signal wiring 30, a pixel driving layer 40, a planar layer 50 and an organic light emitting device 60. The base substrate 10 includes a display area 11 and a peripheral area 12 around the display area 11; the pixel driving layer 40 is located on the base substrate 10 and is located in the display area 11 of the base substrate 10; the planar layer 50 is located on the side of the pixel driving layer 40 away from the base substrate 10; the organic light emitting device 60 is located on the side of the planar layer 50 away from the pixel driving layer 40; the encapsulation layer 20 is located on the side of the organic light emitting device 60 away from the base substrate 10; the encapsulation layer 20 includes two inorganic encapsulation layers 21 and an organic encapsulation layer 22 sandwiched between the two inorganic encapsulation layers 21; and a signal wiring 30 connected to a touch driving electrode (Tx) or a touch sensing electrode (Rx) is formed on the surface of the encapsulation layer 20 away from the base substrate 10. Since the flat layer 50 is not a whole layer, the distance between the encapsulation layer 20 on the flat layer 50 and the base substrate 10 will suddenly decrease at the edge of the flat layer 50, and the organic encapsulation layer 22 will undergo a leveling process, thereby forming a slope portion with a gradually decreasing thickness in the peripheral area of ​​the array substrate. In order to avoid the influence of the above-mentioned slope portion on the signal wiring 30, the above-mentioned signal wiring 30 is usually formed at a position corresponding to the flat portion of the organic encapsulation layer 22, that is, a position on the flat layer. Therefore, the width of the frame of the display device using the array substrate includes the width of the slope portion and the width of the flat portion, and the width of the flat portion is relatively large, which is not conducive to achieving a narrow frame design.

[0050] On the other hand, with the development of narrow frame design, the frame of display devices is getting narrower and narrower, and the space for the above-mentioned signal routing is getting smaller and smaller; at this time, simply reducing the line width and line spacing is not enough to solve the routing requirements of display devices with narrow frame design.

[0051] In view of this, an embodiment of the present disclosure provides an array substrate and a display device. The array substrate includes a base substrate, a pixel driving layer, a planar layer, an organic light-emitting device, an encapsulation layer, a first retaining wall and a plurality of first channel lines. The substrate includes a display area and a peripheral area located around the display area; a pixel driving layer is located on the substrate; a flat layer is located on a side of the pixel driving layer away from the substrate; an organic light-emitting device is located on a side of the flat layer away from the pixel driving layer; and a packaging layer is located on a side of the organic light-emitting device away from the substrate; a first retaining wall is located in the peripheral area and includes a first retaining wall portion extending along a first direction; a plurality of first channel lines are located in the peripheral area and on a side of the packaging layer away from the substrate, each of the plurality of first channel lines extends along the first direction, and the plurality of first channel lines are arranged along a second direction, and the second direction is substantially perpendicular to the first direction; the packaging layer includes an organic packaging layer, and the flat layer includes a first edge portion extending along the first direction, the first edge portion is located between the first retaining wall portion and the display area, an orthographic projection of the first edge portion on the substrate substrate is covered by an orthographic projection of the organic packaging layer on the substrate substrate, and an orthographic projection of at least one of the plurality of first channel lines on the substrate substrate is located on a side of the first edge portion away from the display area. Therefore, the array substrate can reduce the width of the peripheral area by setting at least one first channel line among the multiple first channel lines on the side of the first edge portion away from the display area (i.e., the slope portion of the packaging layer), thereby realizing a narrow frame or even a frameless design of the display device using the array substrate.

[0052] The array substrate and the display device provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0053] Figure 3 A schematic plan view of an array substrate provided according to an embodiment of the present disclosure; Figure 4 According to an embodiment of the present disclosure, an array substrate is provided along Figure 3 Schematic diagram of the cross section along the AA direction. Figure 3 and Figure 4As shown, the array substrate 100 includes a base substrate 110 , a pixel driving layer 150 , a planar layer 160 , an organic light emitting device 170 , an encapsulation layer 120 , a first barrier wall 130 and a plurality of first channel lines 140 . The base substrate 110 includes a display area 112 and a peripheral area 114 located around the display area 112; the pixel driving layer 150 is located on the base substrate 110; the planar layer 160 is located on a side of the pixel driving layer 150 away from the base substrate 110; the organic light-emitting device 170 is located on a side of the planar layer 160 away from the pixel driving layer 150; the encapsulation layer 120 is located on a side of the organic light-emitting device 170 away from the base substrate 110; the first retaining wall 130 is located in the peripheral area 114 and includes a first retaining wall portion 132 extending along a first direction; a plurality of first channel lines 140 are located in the peripheral area 114 and on a side of the encapsulation layer 120 away from the base substrate 110, each first channel line 140 extends along a first direction X, and the plurality of first channel lines 140 are arranged along a second direction Y, and the second direction is substantially perpendicular to the first direction. It should be noted that the above-mentioned pixel driving layer may include a pixel circuit for driving the corresponding organic light-emitting device to perform light-emitting display; in addition, the above-mentioned second direction is roughly perpendicular to the first direction, including the case where the angle between the first direction and the second direction is equal to 90 degrees and the case where the angle between the first direction and the second direction is greater than 80 degrees and less than 100 degrees.

[0054] like Figure 3 and Figure 4 As shown, the encapsulation layer 120 can be directly disposed on the base substrate 110 in a partial area, or other film structures can be disposed between the encapsulation layer 120 and the base substrate 110, such as the above-mentioned pixel driving layer 150, the flat layer 160, the organic light-emitting device 170, etc.; the encapsulation layer 120 can encapsulate the pixel driving layer 150 and the organic light-emitting device 170 formed on the base substrate 110 to prevent water and oxygen in the external environment from corroding the pixel driving layer 150 and the organic light-emitting device 170. The first retaining wall 130 is disposed on the base substrate 110 and is located in the peripheral area 114; the first retaining wall 130 can prevent the fluid material in the encapsulation layer 120 from flowing out of the first retaining wall 130 during the formation of the encapsulation layer 120.

[0055] like Figure 3 and Figure 4 As shown, the encapsulation layer 120 includes an organic encapsulation layer 124, the planar layer 160 includes a first edge portion 162 extending along a first direction X, the first edge portion 162 is located between the first retaining wall portion 132 and the display area 112, the orthographic projection of the first edge portion 162 on the base substrate 110 is covered by the orthographic projection of the organic encapsulation layer 124 on the base substrate 110, and the orthographic projection of at least one of the multiple first channel lines 140 on the base substrate 110 is located on a side of the first edge portion 162 away from the display area 112.

[0056] In the array substrate provided by the embodiment of the present disclosure, since the flat layer 160 is not provided as a whole layer, the distance between the encapsulation layer 120 and the base substrate 110 will suddenly decrease at the first edge portion 162, and the organic encapsulation layer 124 will undergo a leveling process, thereby forming a first slope portion 1243 with a gradually decreasing thickness in the peripheral area 114, and the portion of the organic encapsulation layer 124 above the first edge portion 162 is the first flat portion 1241. The array substrate can reduce the number of first channel lines 140 provided on the first flat portion 1241 by providing at least one first channel line 140 among the plurality of first channel lines 140 on the side of the first edge portion 162 away from the display area 112 (i.e., the first slope portion 1243 or the side of the first slope portion 1243 away from the display area 112), or even not provide a first channel line on the first flat portion 1241, thereby reducing the width of the first flat portion 1241, and further reducing the width of the peripheral area 114. Therefore, the array substrate is conducive to realizing a narrow frame or even a frameless design of a display device using the array substrate.

[0057] For example, the display area may be the image display area of ​​the array substrate, i.e., the light emitting area; the peripheral area may be the area of ​​the array substrate that does not display the image, i.e., the non-light emitting area. The peripheral area may surround the display area, or may be located at a part of the periphery of the display area.

[0058] For example, the base substrate 100 may be a flexible base substrate 100, such as polyimide (PI), to form a flexible display device. The material of the flexible base substrate 100 is not limited to polyimide.

[0059] In some examples, such as Figure 3 and Figure 4 As shown, the organic encapsulation layer 124 includes a second edge portion 1242 extending along the first direction, the second edge portion 1242 is located between the first edge portion 162 and the first barrier portion 132, and the orthographic projection of at least one of the plurality of first channel lines 140 on the base substrate 110 is located within the orthographic projection of the second edge portion 1242 on the base substrate 110. Therefore, the array substrate can reduce the number of first channel lines disposed on the first flat portion by disposing at least one of the plurality of first channel lines on the second edge portion, or even not disposing a first channel line on the first flat portion, thereby reducing the width of the first flat portion, and further reducing the width of the peripheral area.

[0060] In some examples, such as Figure 3 and Figure 4As shown, the plurality of first channel lines 140 include a plurality of first flat channel lines 142 located on the side of the first edge portion 162 away from the substrate 110 and a plurality of first sloped channel lines 144 located on the side of the second edge portion 1242 away from the substrate 110. Since the conventional channel lines are all arranged on the side of the first edge portion away from the substrate, that is, on the first flat portion, the width of the first flat portion in the second direction Y is relatively large, while the first flat channel lines in the array substrate provided in the embodiment of the present disclosure are formed on the side of the first edge portion away from the substrate, and the first sloped channel lines are formed on the side of the second edge portion away from the substrate, so that the number of first channel lines that the first flat portion needs to carry is reduced, thereby reducing the width of the first flat portion in the second direction Y, and further reducing the width of the peripheral area of ​​the array substrate in the second direction Y. Therefore, the display device using the array substrate can have a narrower frame.

[0061] In some examples, such as Figure 3 and Figure 4 As shown, the spacing between two adjacent first slope channel lines 144 is greater than the spacing between two adjacent first flat channel lines 142. Since the first slope channel lines are formed on the slope, in the process of patterning the conductive film layer to form the above-mentioned first flat channel lines and the first slope channel lines, when the performance of the exposure machine is limited, it is easy to cause insufficient exposure of the first slope channel lines on the slope, thereby causing a short circuit between the two adjacent first slope channel lines. In the array substrate provided in this example, by setting the spacing between the two adjacent first slope channel lines to be greater than the spacing between the two adjacent first flat channel lines, the array substrate can avoid various defects such as short circuits caused by insufficient exposure of the first slope channel lines.

[0062] In some examples, the spacing between two adjacent first sloped channel lines 144 is 1.05-2 times the spacing between two adjacent first flat channel lines 142. Thus, the array substrate can avoid exposure problems caused by forming the first sloped channel lines on the first sloped portion, thereby avoiding various defects caused by exposure problems.

[0063] For example, the spacing between two adjacent first slope channel lines 144 is 1.5 times the spacing between two adjacent first flat channel lines 142. On the one hand, the array substrate can avoid the exposure problem caused by forming the first slope channel lines on the first slope portion, and on the other hand, the array substrate can also make the spacing between two adjacent first slope channel lines smaller, so that more first slope channel lines are arranged on the first slope portion.

[0064] Of course, the embodiments of the present disclosure include but are not limited to this, and the spacing between two adjacent first slope channel lines may also be equal to the spacing between two adjacent first flat channel lines. For example, the spacing between two adjacent first slope channel lines may also be equal to the spacing between two adjacent first flat channel lines, but the line width of the first slope channel line is greater than the line width of the first flat channel line. In some examples, among the plurality of first slope channel lines 144, the spacing between two adjacent first slope channel lines 144 is 1.05-2 times the width of the first slope channel line 144. Since the spacing between two adjacent first slope channel lines is set larger, the array substrate can avoid the exposure problem caused by forming the first slope channel line on the first slope portion, thereby avoiding various defects caused by the exposure problem.

[0065] In some examples, such as Figure 3 and Figure 4 As shown, a first channel line 148 farthest from the display area 112 among the plurality of first channel lines 140 is a part of the ground line, and the orthographic projection of the first channel line 148 farthest from the display area 112 among the plurality of first channel lines 140 on the base substrate 110 is located between the orthographic projection of the organic encapsulation layer 124 on the base substrate 110 and the orthographic projection of the first retaining wall portion 132 on the base substrate 110. In other words, the outermost channel line among the plurality of first channel lines is a part of the ground line, and the ground line is arranged between the first retaining wall portion and the organic encapsulation layer. Thus, the array substrate can also use the space between the first retaining wall portion and the organic encapsulation layer to arrange the ground line, thereby further reducing the number of channel lines on the flat portion of the encapsulation layer, and further reducing the width of the peripheral area of ​​the array substrate.

[0066] In some examples, such as Figure 3 and Figure 4 As shown, the array substrate 100 further includes a plurality of touch driving electrodes 182, a plurality of touch sensing electrodes 184, a touch driving signal line 186 and a touch sensing signal line 188; the plurality of touch driving electrodes 182 and the plurality of touch sensing electrodes 184 are all located in the display area 112 and located on the side of the encapsulation layer 120 away from the base substrate 110; the touch driving signal line 186 is connected to each touch driving electrode 182 and extends to the peripheral area 114; the touch sensing signal line 188 is connected to each touch sensing electrode 184 and extends to the peripheral area 114; for example, the touch driving signal line 186 and the touch sensing signal line 188 can both extend to the binding area 115 in the peripheral area 114 to bind with an external circuit, thereby realizing touch driving, data reception and data processing. In the array substrate provided in this example, at least part of the plurality of first channel lines 140 is a part of the touch driving signal line 186 or the touch sensing signal line 188.

[0067] For example, the touch drive electrode and the touch sensing electrode may be a transparent electrode or a metal mesh. The touch drive electrode and the touch sensing electrode may form a capacitor at the overlapping position. When a finger touches, the coupling of the capacitor near the touch point is affected, thereby changing the capacitance of the capacitor near the touch point. Thus, the touch position can be determined by using the change in capacitance. The embodiments of the present disclosure are not limited to this. For example, the touch layer may include a mutual capacitance touch structure or a self-capacitance touch structure.

[0068] Figure 5 According to an embodiment of the present disclosure, an array substrate is provided along Figure 3 Schematic diagram of the cross section along the BB direction. Figure 3 , Figure 4 and Figure 5 As shown, the first retaining wall 130 includes a second retaining wall portion 134 extending along the second direction. For example, the second retaining wall portion 134 is connected to the first retaining wall portion 132 , and two first retaining wall portions 132 and two second retaining wall portions 134 are connected end to end to form a rectangular first retaining wall 134 surrounding the display area 112 .

[0069] In some examples, such as Figure 5 As shown, the array substrate 100 further includes a plurality of second channel lines 190; each second channel line 190 extends along the second direction; the flat layer 160 includes a third edge portion 164 extending along the second direction, the third edge portion 164 is located between the second retaining wall portion 134 and the display area 112, the orthographic projection of the third edge portion 164 on the base substrate 110 is covered by the orthographic projection of the organic encapsulation layer 124 on the base substrate 110, and the orthographic projection of at least one of the plurality of second channel lines 190 on the base substrate 110 is located on a side of the third edge portion 164 away from the display area 112. Since the flat layer 160 is not provided as a whole layer, the distance between the encapsulation layer 120 and the base substrate 110 will suddenly decrease at the third edge portion 164, and the organic encapsulation layer 124 will undergo a leveling process, thereby forming a second slope portion 1247 with a gradually decreasing thickness in the peripheral area 114, and the portion of the organic encapsulation layer 124 above the third edge portion 164 is a second flat portion 1246. The array substrate can reduce the number of second channel lines arranged on the second flat portion 1246 by arranging at least one of the plurality of second channel lines 190 on the side of the third edge portion 164 away from the display area 112 (i.e., the second slope portion 1247 or the side of the second slope portion 1247 away from the display area 112), or even not arrange any second channel line on the second flat portion 1246, thereby reducing the width of the second flat portion 1246 and further reducing the width of the peripheral area 114. Therefore, the array substrate is conducive to realizing a narrow frame or even a frameless design of a display device using the array substrate.

[0070] In some examples, such as Figure 3 , Figure 4 and Figure 5 As shown, the array substrate 100 further includes a plurality of touch driving electrodes 182, a plurality of touch sensing electrodes 184, a touch driving signal line 186 and a touch sensing signal line 188; the plurality of touch driving electrodes 182 and the plurality of touch sensing electrodes 184 are all located in the display area 112 and on the side of the packaging layer 120 away from the base substrate 110; the touch driving signal line 186 is connected to each touch driving electrode 182 and extends to the peripheral area 114; the touch sensing signal line 188 is connected to each touch sensing electrode 184 and extends to the peripheral area 114; for example, the touch driving signal line 186 and the touch sensing signal line 188 can both extend to the binding area 115 in the peripheral area 114 to be bound to an external circuit, thereby realizing touch driving, data reception and data processing. Each touch sensing electrode 184 extends along the first direction, and multiple touch sensing electrodes 184 are arranged along the second direction. At least some of the multiple first channel lines 140 are part of the touch sensing signal line 188. Each of the multiple touch driving electrodes 182 extends along the second direction, and the multiple touch driving electrodes 182 are arranged along the first direction. At least some of the multiple second channel lines 190 are part of the touch driving signal line 186.

[0071] For example, Figure 3 , Figure 4 and Figure 5 As shown, the touch driving signal line 186 includes a first portion 1861 extending along the extension direction of the touch driving electrode 182, a second portion 1862 extending along the arrangement direction of the plurality of touch driving electrodes 182, and a third portion 1863 extending along the extension direction of the touch driving electrode 182; the first portion 1861 is connected to the touch driving electrode 182, the second portion 1862 is connected to the first portion 1861, and the third portion 1863 is connected to the second portion 1862. At this time, the extension direction of each touch driving electrode 182 is the first direction X, and the arrangement direction of the plurality of touch driving electrodes 182 is the second direction Y. Each first channel line 140 may be the third portion 1863 of the touch driving signal line 186.

[0072] For example, Figure 3 , Figure 4 and Figure 5As shown, the touch sensing signal line 188 includes a fourth portion 1881 extending along the extension direction of the touch sensing electrode 184 and a fifth portion 1882 extending along the arrangement direction of the plurality of touch sensing electrodes 184; the fourth portion 1881 is connected to the touch sensing electrode 184, and the fifth portion 1882 is connected to the fourth portion 1881. At this time, the extension direction of each touch sensing electrode 184 is the second direction Y, and the arrangement direction of the plurality of touch sensing electrodes 184 is the first direction X. Each first channel line 140 may be the fifth portion 1882 of the touch sensing signal line 188. At this time, part of the first channel line 140 is part of the touch driving signal line 186, and part of the first channel line 140 is part of the touch sensing signal line 188.

[0073] In some examples, such as Figure 3 , Figure 4 and Figure 5 As shown, the organic encapsulation layer 124 includes a fourth edge portion 1245 extending along the second direction, the fourth edge portion 1245 is located between the third edge portion 164 and the second barrier wall portion 134, and the orthographic projection of at least one of the plurality of second channel lines 190 on the substrate 110 is located within the orthographic projection of the fourth edge portion 1245 on the substrate 110. The array substrate can reduce the number of second channel lines arranged on the second flat portion 1246 by arranging the orthographic projection of at least one of the plurality of second channel lines 190 on the substrate 110 within the orthographic projection of the fourth edge portion 1245 on the substrate 110 (i.e., arranging at least one of the plurality of second channel lines 190 on the fourth edge portion 1245), or even not arranging the second channel line on the second flat portion 1246, thereby reducing the width of the second flat portion 1246, and further reducing the width of the peripheral area 114. Therefore, the array substrate is conducive to realizing a narrow frame or even a frameless design of a display device using the array substrate.

[0074] In some examples, such as Figure 3 , Figure 4 and Figure 5As shown, the plurality of second channel lines 190 include a plurality of second flat channel lines 192 located on the side of the third edge portion 164 away from the substrate 110 and a plurality of second slope channel lines 194 located on the side of the fourth edge portion 1245 away from the substrate 110. Since the conventional channel lines are all arranged on the side of the third edge portion away from the substrate, that is, on the second flat portion, the width of the second flat portion in the first direction X is relatively large, while the second flat channel lines in the array substrate provided in the embodiment of the present disclosure are formed on the side of the third edge portion away from the substrate, and the second slope channel lines are formed on the side of the fourth edge portion away from the substrate, so that the number of second channel lines that the second flat portion needs to carry is reduced, thereby reducing the width of the second flat portion in the first direction X, and further reducing the width of the peripheral area of ​​the array substrate in the first direction X. As a result, the display device using the array substrate can have a narrower frame.

[0075] In some examples, such as Figure 3 and Figure 5 As shown, the spacing between two adjacent second slope channel lines 194 is greater than the spacing between two adjacent second flat channel lines 192. Since the second slope channel lines are formed on the slope, in the process of patterning the conductive film layer to form the above-mentioned second flat channel lines and second slope channel lines, when the performance of the exposure machine is limited, it is easy to cause insufficient exposure of the second slope channel lines on the slope, thereby causing short circuits and other undesirable phenomena between the two adjacent second slope channel lines. In the array substrate provided in this example, by setting the spacing between two adjacent second slope channel lines to be greater than the spacing between two adjacent second flat channel lines, the array substrate can avoid various undesirable phenomena such as short circuits caused by insufficient exposure of the second slope channel lines.

[0076] In some examples, the spacing between two adjacent second sloped channel lines 194 is 1.05-2 times the spacing between two adjacent second flat channel lines 192. Thus, the array substrate can avoid exposure problems caused by forming the second sloped channel lines on the second sloped portion, thereby avoiding various defects caused by exposure problems.

[0077] For example, the spacing between two adjacent second slope channel lines 194 is 1.5 times the spacing between two adjacent second flat channel lines 192. On the one hand, the array substrate can avoid the exposure problem caused by forming the second slope channel lines on the second slope portion, and on the other hand, the array substrate can also simultaneously make the spacing between two adjacent second slope channel lines smaller, so that more second slope channel lines are arranged on the second slope portion.

[0078] In some examples, among the plurality of second slope channel lines 194, the spacing between two adjacent second slope channel lines 194 is 1.05-2 times the width of the second slope channel line 194. Since the spacing between two adjacent second slope channel lines is set to be larger, the array substrate can avoid exposure problems caused by forming the second slope channel lines on the second slope portion, thereby avoiding various defects caused by exposure problems.

[0079] In some examples, such as Figure 3 , Figure 4 and Figure 5 As shown, the organic light emitting device 170 includes an anode 171, a light emitting layer 172 and a cathode 173 which are sequentially stacked in a direction away from the base substrate 110. Thus, the organic light emitting device 170 can emit light through the light emitting layer 172.

[0080] In some examples, such as Figure 3 , Figure 4 and Figure 5 As shown, the encapsulation layer 120 further includes: a first inorganic encapsulation layer 122 and a second inorganic encapsulation layer 126; the first inorganic encapsulation layer 122 is arranged on the side of the organic light-emitting device 170 away from the base substrate 110, and the second inorganic encapsulation layer 126 is arranged on the side of the first inorganic encapsulation layer 122 away from the base substrate 110; the organic encapsulation layer 124 is sandwiched between the first inorganic encapsulation layer 122 and the second inorganic encapsulation layer 124, and a plurality of first channel lines 140 are located on the side of the second inorganic encapsulation layer 126 away from the base substrate 110. Therefore, the encapsulation layer has a strong ability to isolate water and oxygen, thereby effectively preventing water and oxygen in the external environment from corroding the device encapsulated by the encapsulation layer.

[0081] For example, the materials of the first inorganic encapsulation layer and the second inorganic encapsulation layer may be selected from one or more of silicon oxide, silicon nitride or silicon oxynitride. Due to the high density of inorganic materials, water, oxygen, etc. can be prevented from invading and affecting the performance of the light-emitting element. The material of the organic encapsulation layer may include a polymer resin, such as polyimide, polyacrylate, etc. The organic encapsulation layer has the functions of planarization and stress relief.

[0082] In some examples, such as Figure 3 and Figure 4As shown, in the peripheral area 114, the first inorganic encapsulation layer 122 includes a first inorganic encapsulation part 1221, a second inorganic encapsulation part 1222, and an inorganic encapsulation connecting part 1223 connecting the first inorganic encapsulation part 1221 and the second inorganic encapsulation part 1222, and the orthographic projection of the first inorganic encapsulation part 1221 on the base substrate 110 overlaps with the orthographic projection of the first edge part 162 on the base substrate 110. In other words, the first inorganic encapsulation part 1221 is disposed on the first edge part 162, and the second inorganic encapsulation part 1222 is disposed on the base substrate 110 and is located on the side of the first edge part 162 away from the display area 112.

[0083] The organic encapsulation layer 124 includes a first organic encapsulation portion 1248 and a second organic encapsulation portion 1249 which are continuously arranged. The edge of the second organic encapsulation portion 1249 away from the display area 112 is the edge of the organic encapsulation layer 124. The orthographic projection of the first organic encapsulation portion 1248 on the base substrate 110 overlaps with the orthographic projection of the first inorganic encapsulation portion 1221 and the inorganic encapsulation connecting portion 1223 on the base substrate 110. The orthographic projection of the second organic encapsulation portion 1249 on the base substrate 110 overlaps with the orthographic projection of the second inorganic encapsulation portion 1222 on the base substrate 110. In a direction perpendicular to the base substrate 110 , a distance d1 between the first inorganic packaging part 1221 and the base substrate 110 is greater than a distance d2 between the second inorganic packaging part 1222 and the base substrate 110 , and a difference between d1 and d2 is greater than or equal to the thickness of the planar layer 160 , and an orthographic projection of at least one of the plurality of first channel lines 140 on the base substrate 110 falls within an orthographic projection of the second inorganic packaging part 1222 on the base substrate 110 .

[0084] In the array substrate provided in the embodiment of the present disclosure, since the distance d1 between the first inorganic encapsulation part 1221 and the base substrate 110 is greater than the distance d2 between the second inorganic encapsulation part 1222 and the base substrate 110, and the difference between d1 and d2 is greater than or equal to the thickness of the flat layer 160, the organic encapsulation layer 124 formed on the first inorganic encapsulation layer 122 will form a slope portion with a gradually decreasing thickness at the position of the second inorganic encapsulation part 1222, that is, the second organic encapsulation part 1249 is a slope portion, and the first organic encapsulation part 1248 is a flat portion. The array substrate can reduce the number of first channel lines arranged on the flat portion of the organic encapsulation layer 124, or even not arrange the first channel line on the flat portion of the organic encapsulation layer 124, by making the orthographic projection of at least one first channel line 140 among the plurality of first channel lines 140 on the base substrate 110 fall within the orthographic projection of the second inorganic encapsulation part 1222 on the base substrate 110 (i.e., the second organic encapsulation part 1249 or the side of the second organic encapsulation part 1249 away from the display area 112), thereby reducing the width of the flat portion of the organic encapsulation layer 124 and further reducing the width of the peripheral area 114. Therefore, the array substrate is conducive to realizing a narrow frame or even a frameless design of a display device using the array substrate.

[0085] In some examples, such as Figure 3 , Figure 4 and Figure 5 As shown, the array substrate 100 further includes a second retaining wall 230; the second retaining wall 230 is disposed on the base substrate 110 and is located in the peripheral area 114. The second retaining wall 230 is located between the first retaining wall 130 and the display area 112, and the second retaining wall 230 includes a third retaining wall portion 232 extending along the first direction, and the orthographic projection of the plurality of first channel lines 140 on the base substrate 110 is located on a side of the orthographic projection of the third retaining wall portion 232 on the base substrate 110 close to the display area 112. Of course, the embodiments of the present disclosure include but are not limited to this.

[0086] In some examples, such as Figure 3 , Figure 4 and Figure 5 As shown, the second edge portion 1242 of the organic encapsulation layer 124 may be located on a side of the second retaining wall 230 close to the display area 112; in this case, the orthographic projection of the first channel line 140 located on the second edge portion on the base substrate 110 is located on a side of the orthographic projection of the third retaining wall portion 232 on the base substrate 110 close to the display area 112. Of course, the present disclosure includes but is not limited to this, the second edge portion of the organic encapsulation layer may also extend beyond the second retaining wall and be located between the second retaining wall and the first retaining wall; in this case, the first channel line located on the second edge portion may also be located on the second retaining wall or between the second retaining wall and the first retaining wall.

[0087] In some examples, the pixel driving layer may include devices such as thin film transistors. For example, the pixel driving layer may include an active layer located on a substrate, a first gate insulating layer located on a side of the active layer away from the substrate, a gate located on a side of the first gate insulating layer away from the active layer, a second gate insulating layer located on a side of the gate away from the first gate insulating layer, and a source and a drain located on a side of the second gate insulating layer away from the gate. The active layer may include a source region, a channel region, and a drain region. The orthographic projection of the gate on the substrate at least partially overlaps with the orthographic projection of the channel region on the substrate; the source contacts the source region of the active layer, and the drain contacts the drain region of the active layer. Of course, the specific pixel structure in the pixel driving layer can refer to existing designs, such as 2T1C structure, 7T1C and other pixel driving structures, etc.

[0088] For example, the base substrate may be a glass substrate, a polyimide substrate, or other substrates.

[0089] For example, the materials of the first gate insulating layer and the second gate insulating layer may be selected from at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0090] For example, the first inorganic encapsulation layer 122 and the second inorganic encapsulation layer 126 cover the first retaining wall 130 and the second retaining wall 230 , thereby further enhancing the ability of the encapsulation layer to isolate water and oxygen. Figure 6 The diagram is a plan view of another array substrate provided according to an embodiment of the present disclosure. Figure 7 According to an embodiment of the present disclosure, an array substrate is provided along Figure 6 Schematic diagram of the cross section in the CC direction. Figure 6 and Figure 7 As shown, the array substrate 100 further includes a second retaining wall 230; the second retaining wall 230 is disposed on the base substrate 110 and is located in the peripheral area 114. The second retaining wall 230 is located between the first retaining wall 130 and the display area 112, and the second retaining wall 230 includes a third retaining wall portion 232 extending along the first direction, and the orthographic projection of at least one of the plurality of first channel lines 140 on the base substrate 110 is located within the orthographic projection of the third retaining wall portion 232 on the base substrate 110. In other words, at least one of the plurality of first channel lines 140 is disposed on the third retaining wall portion 232. At this time, by disposing at least one of the plurality of first channel lines on the third retaining wall portion, the array substrate can further reduce the width of the peripheral area, thereby further reducing the border width of the display device using the array substrate, thereby achieving a narrow border design.

[0091] It should be noted that when at least one of the multiple first channel lines is arranged on the third barrier wall portion, the first inorganic packaging layer and the second inorganic packaging layer of the packaging layer can be arranged on the side of the third barrier wall portion away from the base substrate, and the first channel line arranged on the third barrier wall can be arranged on the side of the second inorganic packaging layer away from the base substrate.

[0092] In some examples, such as Figure 7 As shown, the plurality of first channel lines 140 include a plurality of first barrier wall channel lines 146 located on the third barrier wall portion 232. That is to say, the orthographic projections of the plurality of first barrier wall channel lines 146 on the base substrate 110 fall within the orthographic projections of the third barrier wall portion 232 on the base substrate 110. Therefore, in a common design, since the plurality of first channel lines are all arranged on the first flat portion, the width of the first flat portion in the second direction Y is relatively large, while the first flat channel line in the array substrate provided in the embodiment of the present disclosure is formed on the first flat portion, the first slope channel line is formed on the first slope portion, and the first barrier wall channel line is formed on the third barrier wall portion, so that the number of first channel lines that the first flat portion needs to carry is greatly reduced, thereby reducing the width of the first flat portion in the second direction Y, and further reducing the width of the peripheral area of ​​the array substrate in the second direction Y. Therefore, the display device using the array substrate can have a narrower frame.

[0093] Figure 8 According to an embodiment of the present disclosure, an array substrate is provided along Figure 6 Schematic diagram of the cross section along the DD direction. Figure 8 As shown, the second retaining wall 230 includes a fourth retaining wall portion 234 extending along the second direction, and the orthographic projection of at least one of the plurality of second channel lines 190 on the base substrate 110 falls within the orthographic projection of the fourth retaining wall portion 234 on the base substrate 110. In other words, at least one of the plurality of second channel lines 190 is disposed on the fourth retaining wall portion 234. At this time, by disposing at least one of the plurality of second channel lines 190 on the fourth retaining wall portion, the array substrate can further reduce the width of the peripheral area, thereby further reducing the border width of the display device using the array substrate, thereby achieving a narrow border design.

[0094] In some examples, such as Figure 8As shown, the plurality of second channel lines 190 include a plurality of second barrier wall channel lines 196 located on the fourth barrier wall portion 234. That is, the orthographic projections of the plurality of second barrier wall channel lines 196 on the base substrate 110 fall within the orthographic projections of the fourth barrier wall portion 234 on the base substrate 110. Thus, the second flat channel lines in the array substrate provided by the embodiment of the present disclosure are formed on the second flat portion, the second slope channel lines are formed on the second slope portion, and the second barrier wall channel lines are formed on the fourth barrier wall portion, so that the number of second channel lines that the second flat portion needs to carry is greatly reduced, thereby reducing the width of the second flat portion in the first direction X, and further reducing the width of the peripheral area of ​​the array substrate in the first direction X. Thus, the display device using the array substrate can have a narrower frame.

[0095] Another embodiment of the present disclosure further provides an array substrate. Fig. 9 A schematic plan view of an array substrate provided according to an embodiment of the present disclosure; Fig.10 According to an embodiment of the present disclosure, an array substrate is provided along Fig. 9 Schematic diagram of the cross section along the EE direction. Fig. 9 and Fig.10 As shown, the array substrate 100 includes a base substrate 110, an encapsulation layer 120, a first retaining wall 130 and a plurality of first channel lines 140. The base substrate 110 includes a display area 112 and a peripheral area 114 located around the display area 112. At this time, the array substrate 100 can also be divided by the display area 112 and the peripheral area 114. The encapsulation layer 120 is arranged on the base substrate 110. For example, the encapsulation layer 120 can be directly arranged on the base substrate 110 in a part of the area, or other film layer structures, such as a light-emitting structure and a circuit structure for driving the light-emitting structure to emit light, can be arranged between the encapsulation layer 120 and the base substrate 110; the encapsulation layer 120 can encapsulate the light-emitting structure and the circuit structure formed on the base substrate 110 to prevent water and oxygen in the external environment from corroding the light-emitting structure and the circuit structure. The first retaining wall 130 is arranged on the base substrate 110 and located in the peripheral area 114; the first retaining wall 130 can prevent the fluid material in the encapsulation layer 120 from flowing out of the first retaining wall 130 during the formation of the encapsulation layer 120. The plurality of first channel lines 140 are located in the peripheral region 114 and on a side of the packaging layer 120 away from the base substrate 110 .

[0096] like Fig. 9 and Fig.10As shown, each first channel line 140 extends along the first direction X, and a plurality of first channel lines 140 are arranged along the second direction Y, and the first retaining wall 130 includes a first retaining wall portion 132 extending along the first direction X. The encapsulation layer 120 includes an organic encapsulation layer 124, and an edge portion of the organic encapsulation layer 124 extending along the first direction X is located between the first retaining wall portion 132 and the display area 112, and the edge portion includes a first flat portion 1241 and a first slope portion 1243; a plurality of first channel lines 140 are at least partially located on the first slope portion 1243. It should be noted that the slope of the first flat portion is less than 1 / 50, and the slope of the first slope portion is greater than 1 / 50; the plurality of first channel lines are at least partially located on the first slope portion, which means that the orthographic projections of the plurality of first channel lines on the substrate at least partially overlap with the orthographic projections of the first slope portion on the substrate.

[0097] In the array substrate provided by the embodiment of the present disclosure, since the organic encapsulation layer undergoes a leveling process, a first slope portion with a gradually decreasing thickness is formed in the peripheral area. By at least partially arranging a plurality of first channel lines on the first slope portion, the array substrate can reduce the width of the peripheral area, thereby reducing the frame width of a display device using the array substrate, thereby achieving a narrow frame design.

[0098] In some examples, such as Fig. 9 and Fig.10 As shown, the organic encapsulation layer 124 includes a second edge portion 1242 extending along the first direction, that is, the first slope portion 1243 mentioned above, the second edge portion 1242 is located between the first edge portion 162 and the first barrier portion 132, and the orthographic projection of at least one of the plurality of first channel lines 140 on the base substrate 110 is located within the orthographic projection of the second edge portion 1242 on the base substrate 110. Therefore, the array substrate can reduce the number of first channel lines disposed on the first flat portion by at least partially disposing the plurality of first channel lines on the second edge portion, or even not disposing the first channel line on the first flat portion, thereby reducing the width of the first flat portion, and further reducing the width of the peripheral area.

[0099] In some examples, such as Fig. 9 and Fig.10As shown, the plurality of first channel lines 140 include a plurality of first flat channel lines 142 located on the first flat portion 1241 and a plurality of first sloped channel lines 144 located on the first sloped portion 1243. That is, the orthographic projections of the plurality of first flat channel lines 142 on the base substrate 110 fall within the orthographic projections of the first flat portion 1241 on the base substrate 110, and the orthographic projections of the plurality of first sloped channel lines 144 on the base substrate 110 fall within the orthographic projections of the first sloped portion 1243 on the base substrate 110. Thus, in a conventional design, since the plurality of first channel lines are all arranged on the first flat portion, the width of the first flat portion in the second direction Y is relatively large, while the first flat channel lines in the array substrate provided in the embodiment of the present disclosure are formed on the first flat portion, and the first sloped channel lines are formed on the first sloped portion, so that the number of first channel lines that the first flat portion needs to carry is reduced, thereby reducing the width of the first flat portion in the second direction Y, and further reducing the width of the peripheral area of ​​the array substrate in the second direction Y. Therefore, a display device using the array substrate can have a narrower frame.

[0100] In some examples, such as Fig. 9 and Fig.10 As shown, the spacing between two adjacent first slope channel lines 144 is greater than the spacing between two adjacent first flat channel lines 142. Since the first slope channel lines are formed on the slope, in the process of patterning the conductive film layer to form the above-mentioned first flat channel lines and the first slope channel lines, when the performance of the exposure machine is limited, it is easy to cause insufficient exposure of the first slope channel lines on the slope, thereby causing a short circuit between the two adjacent first slope channel lines. In the array substrate provided in this example, by setting the spacing between the two adjacent first slope channel lines to be greater than the spacing between the two adjacent first flat channel lines, the array substrate can avoid various defects such as short circuits caused by insufficient exposure of the first slope channel lines.

[0101] In some examples, the spacing between two adjacent first sloped channel lines 144 is 1.05-2 times the spacing between two adjacent first flat channel lines 142. Thus, the array substrate can avoid exposure problems caused by forming the first sloped channel lines on the first sloped portion, thereby avoiding various defects caused by exposure problems.

[0102] In some examples, such as Fig. 9 and Fig.10As shown, the spacing between two adjacent first slope channel lines 144 is greater than or equal to 1.5 times the spacing between two adjacent first flat channel lines 142. By setting the spacing between two adjacent first slope channel lines to be greater than or equal to 1.5 times the spacing between two adjacent first flat channel lines, the array substrate can avoid exposure problems caused by forming the first slope channel lines on the first slope portion, thereby avoiding various defects caused by exposure problems.

[0103] For example, since the first slope channel line is formed on the first slope portion, in the process of patterning the conductive film layer to form the first flat channel line and the first slope channel line, when the performance of the exposure machine is limited, it is easy to cause insufficient exposure of the first slope channel line, thereby causing a short circuit phenomenon between two adjacent first slope channel lines. In the array substrate provided in this example, by setting the spacing between two adjacent first slope channel lines to be greater than or equal to 1.5 times the spacing between two adjacent first flat channel lines, the array substrate can avoid the short circuit phenomenon caused by insufficient exposure of the first slope channel line.

[0104] In some examples, among the plurality of first sloped channel lines 144, the spacing between two adjacent first sloped channel lines 144 is 1.05-2 times the width of the first sloped channel line 144. Since the spacing between two adjacent first sloped channel lines is set to be larger, the array substrate can avoid exposure problems caused by forming the first sloped channel lines on the first sloped portion, thereby avoiding various defects caused by the exposure problem.

[0105] In some examples, such as Fig. 9 and Fig.10 As shown, among the plurality of first slope channel lines, the spacing between two adjacent first slope channel lines 144 is 1.5 times the width (i.e., line width) of the first slope channel line 144. The array substrate can avoid exposure problems caused by forming the first slope channel lines on the first slope portion by setting the spacing between two adjacent first slope channel lines larger, thereby avoiding various defects caused by exposure problems.

[0106] In some examples, such as Fig. 9 and Fig.10 As shown, the first slope portion 1243 and the first flat portion 1241 are continuously arranged along the second direction Y, and the first slope portion 1243 is located on the side of the first flat portion 1241 close to the first barrier portion 132. That is, the first slope portion and the first flat portion are two continuous parts of the first edge portion extending along the first direction X formed by leveling the organic encapsulation layer.

[0107] In some examples, such as Fig. 9 and Fig.10As shown, the first channel line 140 farthest from the display area 112 among the plurality of first channel lines 140 is located at the edge of the first slope portion 1243 far away from the display area 112. In other words, the position above the first slope portion 1243 is used to set the above-mentioned first channel line 140 (i.e., the first slope channel line 144), so that the width of the peripheral area of ​​the array substrate can be greatly reduced, which is more conducive to realizing a narrow frame design.

[0108] In some examples, such as Fig.10 As shown, the encapsulation layer 120 further includes: a first inorganic encapsulation layer 122 and a second inorganic encapsulation layer 126; the first inorganic encapsulation layer 122 is disposed on the base substrate 110, and the second inorganic encapsulation layer 126 is disposed on a side of the first inorganic encapsulation layer 122 away from the base substrate 110; and the organic encapsulation layer 124 is sandwiched between the first inorganic encapsulation layer 122 and the second inorganic encapsulation layer 124. Thus, the encapsulation layer has a strong ability to isolate water and oxygen, thereby effectively preventing water and oxygen in the external environment from corroding the device encapsulated by the encapsulation layer.

[0109] For example, the material of the first inorganic encapsulation layer and the second inorganic encapsulation layer may be selected from one or more of silicon oxide, silicon nitride or silicon oxynitride. The material of the organic encapsulation layer may be organic resin.

[0110] In some examples, such as Fig. 9 and Fig.10 As shown, the array substrate 100 further includes a plurality of touch driving electrodes 182, a plurality of touch sensing electrodes 184, a touch driving signal line 186 and a touch sensing signal line 188; the plurality of touch driving electrodes 182 and the plurality of touch sensing electrodes 184 are all located in the display area 112 and located on the side of the encapsulation layer 120 away from the base substrate 110; the touch driving signal line 186 is connected to each touch driving electrode 182 and extends to the peripheral area 114; the touch sensing signal line 188 is connected to each touch sensing electrode 184 and extends to the peripheral area 114; for example, the touch driving signal line 186 and the touch sensing signal line 188 can both extend to the binding area 115 in the peripheral area 114 to bind with an external circuit, thereby realizing touch driving, data reception and data processing. In the array substrate provided in this example, each of the plurality of first channel lines 140 is a part of the touch driving signal line 186 or the touch sensing signal line 188.

[0111] For example, Fig. 9 and Fig.10As shown, the touch driving signal line 186 includes a first portion 1861 extending along the extension direction of the touch driving electrode 182, a second portion 1862 extending along the arrangement direction of the plurality of touch driving electrodes 182, and a third portion 1863 extending along the extension direction of the touch driving electrode 182; the first portion 1861 is connected to the touch driving electrode 182, the second portion 1862 is connected to the first portion 1861, and the third portion 1863 is connected to the second portion 1862. At this time, the extension direction of each touch driving electrode 182 is the first direction X, and the arrangement direction of the plurality of touch driving electrodes 182 is the second direction Y. Each first channel line 140 may be the third portion 1863 of the touch driving signal line 186.

[0112] For example, Fig. 9 and Fig.10 As shown, the touch sensing signal line 188 includes a fourth portion 1881 extending along the extension direction of the touch sensing electrode 184 and a fifth portion 1882 extending along the arrangement direction of the plurality of touch sensing electrodes 184; the fourth portion 1881 is connected to the touch sensing electrode 184, and the fifth portion 1882 is connected to the fourth portion 1881. At this time, the extension direction of each touch sensing electrode 184 is the second direction Y, and the arrangement direction of the plurality of touch sensing electrodes 184 is the first direction X. Each first channel line 140 may be the fifth portion 1882 of the touch sensing signal line 188. At this time, part of the first channel line 140 is part of the touch driving signal line 186, and part of the first channel line 140 is part of the touch sensing signal line 188.

[0113] Fig.11 According to an embodiment of the present disclosure, an array substrate is provided along Fig. 9 Schematic diagram of the cross section in the FF direction. Fig. 9 , Fig.10 and Fig.11 As shown, the first retaining wall 130 includes a second retaining wall portion 134 extending along the second direction. For example, the second retaining wall portion 134 is connected to the first retaining wall portion 132 , and two first retaining wall portions 132 and two second retaining wall portions 134 are connected end to end to form a rectangular first retaining wall 134 surrounding the display area 112 .

[0114] In some examples, such as Fig.11As shown, the array substrate 100 further includes a plurality of second channel lines 190; each second channel line 190 extends along the second direction; the edge portion of the organic encapsulation layer 124 extending along the second direction is located between the second retaining wall portion 134 and the display area 112. The edge portion includes a second flat portion 1246 and a second slope portion 1247, and the plurality of second channel lines 190 are at least partially located on the second slope portion 1247. In other words, the orthographic projections of the plurality of second channel lines 190 on the base substrate 110 overlap at least partially with the orthographic projections of the second slope portion 1247 on the base substrate 110. In the array substrate provided in this example, since the organic encapsulation layer undergoes a leveling process, the second slope portion mentioned above is formed in the peripheral area; by at least partially arranging the plurality of second channel lines on the second slope portion, the array substrate can reduce the width of the peripheral area in the first direction, thereby reducing the frame width of the display device using the array substrate, thereby realizing a narrow frame design.

[0115] In some examples, such as Fig.11 As shown, the plurality of second channel lines 190 include a plurality of second flat channel lines 192 located on the second flat portion 1246 and a plurality of second sloped channel lines 194 located on the second sloped portion 1247. That is, the orthographic projections of the plurality of second flat channel lines 192 on the substrate 110 fall within the orthographic projections of the second flat portion 1246 on the substrate 110, and the orthographic projections of the plurality of second sloped channel lines 194 on the substrate 110 fall within the orthographic projections of the second sloped portion 1247 on the substrate 110. Thus, in a conventional design, since the plurality of second channel lines are all arranged on the second flat portion, the width of the second flat portion in the first direction X is relatively large, while the second flat channel lines in the array substrate provided in this example are formed on the second flat portion, and the second sloped channel lines are formed on the second sloped portion, so that the number of second channel lines that the second flat portion needs to carry is reduced, thereby reducing the width of the second flat portion in the first direction, and further reducing the width of the peripheral area of ​​the array substrate in the first direction. Therefore, a display device using the array substrate can have a narrower frame.

[0116] In some examples, such as Fig.11 As shown, the spacing between two adjacent second slope channel lines 194 is greater than or equal to 1.5 times the spacing between two adjacent second flat channel lines 192. By setting the spacing between two adjacent second slope channel lines to be greater than or equal to 1.5 times the spacing between two adjacent second flat channel lines, the array substrate can avoid exposure problems caused by forming the second slope channel lines on the second slope portion, thereby avoiding various defects caused by exposure problems.

[0117] For example, since the second slope channel line is formed on the second slope portion, in the process of patterning the conductive film layer to form the second flat channel line and the second slope channel line, when the performance of the exposure machine is limited, it is easy to cause insufficient exposure of the second slope channel line, thereby causing a short circuit phenomenon between two adjacent second slope channel lines. In the array substrate provided in this example, by setting the spacing between two adjacent second slope channel lines to be greater than or equal to 1.5 times the spacing between two adjacent second flat channel lines, the array substrate can avoid the short circuit phenomenon caused by insufficient exposure of the second slope channel line.

[0118] In some examples, such as Fig.11 As shown, among the plurality of second sloped channel lines, the spacing between two adjacent second sloped channel lines 194 is 1.5 times the width (ie, line width) of the second sloped channel line 194 .

[0119] In some examples, such as Fig.11 As shown, the second slope portion 1247 and the second flat portion 1246 are continuously arranged along the first direction X, and the second slope portion 1247 is located on the side of the second flat portion 1246 close to the second retaining wall portion 134. In other words, the second slope portion and the second flat portion are two continuous parts of the second edge portion extending along the second direction formed by leveling the organic encapsulation layer.

[0120] In some examples, such as Fig.11 As shown, the second channel line 190 farthest from the display area 112 among the plurality of second channel lines 190 is located at the edge of the second slope portion 1247 farthest from the display area 112. In other words, the position above the second slope portion 1247 is used to set the above-mentioned second channel line 190 (i.e., the second slope channel line 194), so that the width of the peripheral area of ​​the array substrate can be greatly reduced, which is more conducive to realizing a narrow frame design.

[0121] In some examples, such as Fig. 9 and Fig.11 As shown, the touch driving signal line 186 includes a first portion 1861 extending along the extension direction of the touch driving electrode 182, a second portion 1862 extending along the arrangement direction of the plurality of touch driving electrodes 182, and a third portion 1863 extending along the extension direction of the touch driving electrode 182; the first portion 1861 is connected to the touch driving electrode 182, the second portion 1862 is connected to the first portion 1861, and the third portion 1863 is connected to the second portion 1862. At this time, the extension direction of each touch driving electrode 182 is the first direction X, and the arrangement direction of the plurality of touch driving electrodes 182 is the second direction Y. The second channel line 190 may be the second portion 1862 of the touch driving signal line 186.

[0122] It should be noted that in the above Fig. 9 , Fig.10 and Fig.11 In the array substrate shown in FIG. 1 , the extension direction of the first channel line (ie, the first direction) is the extension direction of the touch drive signal line, and the extension direction of the second channel line (ie, the second direction) is the extension direction of the touch sensing signal line. Fig. 9 , Fig.10 and Fig.11 This is only an example of an array substrate provided in an embodiment of the present disclosure, and the embodiments of the present disclosure include but are not limited to this. The extension direction of the first channel line (i.e., the first direction) may also be the extension direction of the touch sensing signal line, and the extension direction of the second channel line (i.e., the second direction) may also be the extension direction of the touch driving signal line. In addition, the array substrate may also include only the first channel line without the second channel line.

[0123] In some examples, such as Fig.10 and 11 As shown, the array substrate 100 further includes an organic light emitting structure 170; the organic light emitting device 170 is located in the display area 112 and between the encapsulation layer 120 and the base substrate 110. At this time, the encapsulation layer 120 can be used to encapsulate the organic light emitting device 170 to prevent the water and oxygen in the external environment from corroding the organic light emitting device 170.

[0124] For example, the organic light emitting device 170 may include an anode 171, an organic light emitting layer 172 and a cathode 173. Of course, the organic light emitting device 170 may also include other functional layers, such as a hole transport layer, an electron transport layer, etc., which will not be described in detail in the embodiments of the present disclosure.

[0125] Fig.12 The diagram is a plan view of another array substrate provided according to an embodiment of the present disclosure. Fig.13 According to an embodiment of the present disclosure, an array substrate is provided along Fig.12 Schematic diagram of the cross section along the GG direction. Fig.12 and Fig.13 As shown, the array substrate 100 further includes a second retaining wall 230; the second retaining wall 230 is disposed on the base substrate 110 and is located in the peripheral area 114. The second retaining wall 230 is located between the first retaining wall 130 and the display area 112, and the second retaining wall 230 includes a third retaining wall portion 232 extending along the first direction, and the orthographic projection of the plurality of first channel lines 140 on the base substrate 110 and the orthographic projection of the third retaining wall portion 232 on the base substrate 110 at least partially overlap. In other words, the plurality of first channel lines 140 are at least partially disposed on the third retaining wall portion 232. At this time, by at least partially disposing the plurality of first channel lines on the third retaining wall portion, the array substrate can further reduce the width of the peripheral area, thereby further reducing the border width of the display device using the array substrate, thereby realizing a narrow border design.

[0126] It should be noted that when multiple first channel lines are at least partially arranged on the third retaining wall portion, the first inorganic encapsulation layer and the second inorganic encapsulation layer of the encapsulation layer can be arranged on the side of the third retaining wall portion away from the base substrate, and the first channel line arranged on the third retaining wall can be arranged on the side of the second inorganic encapsulation layer away from the base substrate.

[0127] In some examples, such as Fig.13 As shown, the plurality of first channel lines 140 include a plurality of first barrier wall channel lines 146 located on the third barrier wall portion 232. That is to say, the orthographic projections of the plurality of first barrier wall channel lines 146 on the base substrate 110 fall within the orthographic projections of the third barrier wall portion 232 on the base substrate 110. Therefore, in a common design, since the plurality of first channel lines are all arranged on the first flat portion, the width of the first flat portion in the second direction Y is relatively large, while the first flat channel line in the array substrate provided in the embodiment of the present disclosure is formed on the first flat portion, the first slope channel line is formed on the first slope portion, and the first barrier wall channel line is formed on the third barrier wall portion, so that the number of first channel lines that the first flat portion needs to carry is greatly reduced, thereby reducing the width of the first flat portion in the second direction Y, and further reducing the width of the peripheral area of ​​the array substrate in the second direction Y. Therefore, the display device using the array substrate can have a narrower frame.

[0128] Fig.14 According to an embodiment of the present disclosure, an array substrate is provided along Fig.12 Schematic diagram of the cross section along the HH direction. Fig.14 As shown, the second retaining wall 230 includes a fourth retaining wall portion 234 extending along the second direction, and the orthographic projection of the plurality of second channel lines 190 on the base substrate 110 at least partially overlaps with the orthographic projection of the fourth retaining wall portion 234 on the base substrate 110. In other words, the plurality of second channel lines 190 are at least partially disposed on the fourth retaining wall portion 234. At this time, by at least partially disposing the plurality of second channel lines on the fourth retaining wall portion, the array substrate can further reduce the width of the peripheral area, thereby further reducing the border width of the display device using the array substrate, thereby achieving a narrow border design.

[0129] In some examples, such as Fig.14As shown, the plurality of second channel lines 190 include a plurality of second barrier wall channel lines 196 located on the fourth barrier wall portion 234. That is, the orthographic projections of the plurality of second barrier wall channel lines 196 on the base substrate 110 fall within the orthographic projections of the fourth barrier wall portion 234 on the base substrate 110. Thus, the second flat channel lines in the array substrate provided by the embodiment of the present disclosure are formed on the second flat portion, the second slope channel lines are formed on the second slope portion, and the second barrier wall channel lines are formed on the fourth barrier wall portion, so that the number of second channel lines that the second flat portion needs to carry is greatly reduced, thereby reducing the width of the second flat portion in the first direction X, and further reducing the width of the peripheral area of ​​the array substrate in the first direction X. Thus, the display device using the array substrate can have a narrower frame.

[0130] An embodiment of the present disclosure further provides an array substrate. Fig.15 FIG. 1 is a cross-sectional schematic diagram of an array substrate provided according to an embodiment of the present disclosure. Fig.15 As shown, the array substrate includes a base substrate 110, a pixel driving layer 150, an organic light emitting device 170, an encapsulation layer 120 and a plurality of first channel lines 140. The base substrate 110 includes a display area 112 and a peripheral area 114 located around the display area 112; the pixel driving layer 150 is located on the base substrate 110; the organic light emitting device 170 is located on a side of the flat layer 160 away from the pixel driving layer 150; the encapsulation layer 120 is located on a side of the organic light emitting device 170 away from the base substrate 110; a plurality of first channel lines 140 are located in the peripheral area 114 and on a side of the encapsulation layer 120 away from the base substrate 110, each first channel line 140 extends along a first direction X, and a plurality of first channel lines 140 are arranged along a second direction Y, and the second direction Y is substantially perpendicular to the first direction X. It should be noted that the above-mentioned pixel driving layer may include a pixel circuit for driving the corresponding organic light-emitting device to perform light-emitting display; in addition, the above-mentioned second direction is roughly perpendicular to the first direction, including the case where the angle between the first direction and the second direction is equal to 90 degrees and the case where the angle between the first direction and the second direction is greater than 80 degrees and less than 100 degrees.

[0131] like Fig.15As shown, the encapsulation layer 120 includes a first inorganic encapsulation layer 122 and an organic encapsulation layer 124 arranged in sequence. In the peripheral area 114, in the direction from the display area 112 to the peripheral area 114, the first inorganic encapsulation layer 122 includes a first inorganic encapsulation portion 1221, an inorganic encapsulation connection portion 1223, and a second inorganic encapsulation portion 1222 arranged in sequence; the inorganic encapsulation connection portion 1223 is used to connect the first inorganic encapsulation portion 1221 and the second inorganic encapsulation portion 1222. In the peripheral area 114, in the direction from the display area 112 to the peripheral area 114, the organic encapsulation layer 124 includes a first organic encapsulation part 1241 and a second organic encapsulation part 1242 which are continuously arranged, and the edge of the second organic encapsulation part 1242 away from the display area is the edge of the organic encapsulation layer 124; the orthographic projection of the first organic encapsulation part 1241 on the substrate 110 overlaps with the orthographic projection of the first inorganic encapsulation part 1221 and the inorganic encapsulation connection part 1223 on the substrate 110 and the orthographic projection of the second inorganic encapsulation part 1242 on the substrate 110. In the direction perpendicular to the substrate 110, the distance d1 between the first inorganic encapsulation part 1221 and the substrate 110 is greater than the distance d2 between the second inorganic encapsulation part 1222 and the substrate 110, and the orthographic projection of at least one of the plurality of first channel lines 140 on the substrate 110 falls within the orthographic projection of the second inorganic encapsulation part 1222 on the substrate 110.

[0132] In the array substrate provided in the embodiment of the present disclosure, since the distance d1 between the first inorganic encapsulation part 1221 and the base substrate 110 is greater than the distance d2 between the second inorganic encapsulation part 1222 and the base substrate 110, the distance between the first organic encapsulation part 1241 and the base substrate 110 will suddenly decrease, and the organic encapsulation layer 124 will undergo a leveling process, so that the second organic encapsulation part 1242 will form a first slope part 1243 with a gradually decreasing thickness in the peripheral area 114. The array substrate can reduce the number of first channel lines arranged on the relatively flat first organic encapsulation part 1241, or even not arrange the first channel line on the first organic encapsulation part 1241, by making the orthographic projection of at least one first channel line 140 among the plurality of first channel lines 140 on the base substrate 110 fall within the orthographic projection of the second inorganic encapsulation part 1222 on the base substrate 110 (i.e., the first slope part 1243 or the side of the first slope part 1243 away from the display area 112), thereby reducing the width of the first organic encapsulation part 1241 and further reducing the width of the peripheral area 114. Therefore, the array substrate is conducive to realizing a narrow frame or even a frameless design of a display device using the array substrate.

[0133] In some examples, such as Fig.15As shown, the array substrate further includes a first retaining wall 130 and a planar layer 160. The planar layer 160 is located on a side of the pixel driving layer 150 away from the base substrate 110; the organic light emitting device 170 is located on a side of the planar layer 160 away from the pixel driving layer 150; the first retaining wall 130 is located in the peripheral area 114 and includes a first retaining wall portion 132 extending along a first direction. The planar layer 160 includes a first edge portion 162 extending along the first direction, the first edge portion 162 is located between the first retaining wall portion 132 and the display area 112, the orthographic projection of the first inorganic encapsulation portion 1221 on the base substrate 110 overlaps with the orthographic projection of the first edge portion 162 on the base substrate 110, and the difference between the distance d1 between the first inorganic encapsulation portion 1221 and the base substrate 110 and the distance d2 between the second inorganic encapsulation portion 1222 and the base substrate 110 is greater than or equal to the maximum thickness of the portion of the planar layer 160 overlapping with the inorganic encapsulation connection portion 1223 in a direction perpendicular to the base substrate 110.

[0134] In some examples, such as Fig.15 As shown, the planarization layer 160 includes a first sub-planarization layer 1601 and a second sub-planarization layer 1602; the first sub-planarization layer 1601 is located on a side of the pixel driving layer 150 away from the base substrate 110; and the second sub-planarization layer 1602 is located on a side of the first sub-planarization layer 1601 away from the pixel driving layer 150. The difference between the distance d1 between the first inorganic encapsulation part 1221 and the base substrate 110 and the distance d2 between the second inorganic encapsulation part 1222 and the base substrate 110 is greater than or equal to the sum of the maximum thickness of the portion of the first sub-planarization layer 1601 overlapping with the inorganic encapsulation connection part 1223 in a direction perpendicular to the base substrate 110 and the maximum thickness of the portion of the second sub-planarization layer 1602 overlapping with the inorganic encapsulation connection part 1223 in a direction perpendicular to the base substrate 110.

[0135] In some examples, such as Fig.15As shown, the plurality of first channel lines 140 include a plurality of first flat channel lines 142 located on the side of the first organic encapsulation part 1241 away from the substrate substrate 110 and a plurality of first slope channel lines 144 located on the side of the first organic encapsulation part 1242 away from the substrate substrate 110. The spacing between two adjacent first slope channel lines 144 is greater than the spacing between two adjacent first flat channel lines 142. Since the first slope channel lines are formed on the slope, in the process of patterning the conductive film layer to form the above-mentioned first flat channel lines and first slope channel lines, when the performance of the exposure machine is limited, it is easy to cause insufficient exposure of the first slope channel lines on the slope, thereby causing a short circuit between two adjacent first slope channel lines. In the array substrate provided in this example, by setting the spacing between two adjacent first slope channel lines to be greater than the spacing between two adjacent first flat channel lines, the array substrate can avoid various defects such as short circuits caused by insufficient exposure of the first slope channel lines.

[0136] In some examples, the spacing between two adjacent first sloped channel lines 144 is 1.05-2 times the spacing between two adjacent first flat channel lines 142. Thus, the array substrate can avoid exposure problems caused by forming the first sloped channel lines on the first sloped portion, thereby avoiding various defects caused by exposure problems.

[0137] For example, the spacing between two adjacent first slope channel lines 144 is 1.5 times the spacing between two adjacent first flat channel lines 142. On the one hand, the array substrate can avoid the exposure problem caused by forming the first slope channel lines on the first slope portion, and on the other hand, the array substrate can also make the spacing between two adjacent first slope channel lines smaller, so that more first slope channel lines are arranged on the first slope portion.

[0138] Of course, the embodiments of the present disclosure include but are not limited to this, and the spacing between two adjacent first sloped channel lines may also be equal to the spacing between two adjacent first flat channel lines. For example, the spacing between two adjacent first sloped channel lines may also be equal to the spacing between two adjacent first flat channel lines, but the line width of the first sloped channel line is greater than the line width of the first flat channel line.

[0139] In some examples, among the plurality of first slope channel lines 144, the spacing between two adjacent first slope channel lines 144 is 1.05-2 times the width of the first slope channel line 144. Since the spacing between two adjacent first slope channel lines is set larger, the array substrate can avoid exposure problems caused by forming the first slope channel lines on the first slope portion, thereby avoiding various defects caused by exposure problems. Fig.15As shown, the array substrate also includes a connecting electrode 167 located between the first sub-flat layer 1601 and the second sub-flat layer 1602. The connecting electrode 167 is connected to the drain of a thin film transistor of the pixel driving layer 150 through a via hole in the first sub-flat layer 1601, and the anode of the organic light-emitting device 170 is connected to the connecting electrode 167 through a via hole in the second sub-flat layer 1602.

[0140] An embodiment of the present disclosure further provides a display device. Fig.16 FIG. 1 is a schematic diagram of a display device according to an embodiment of the present disclosure. Fig.16 As shown, the display device 300 includes the above-mentioned array substrate 100. Since the organic encapsulation layer forms a first slope portion with a gradually decreasing thickness in the peripheral area, the array substrate can reduce the number of first channel lines arranged on the first flat portion by arranging at least one of the plurality of first channel lines on the side of the first edge portion away from the display area (i.e., the first slope portion or the side of the first slope portion away from the display area), or even not arranging the first channel line on the first flat portion, thereby reducing the width of the first flat portion, and further reducing the width of the peripheral area. As a result, the display device can have a narrower frame, and can also realize flexible display and flexible touch. For details, please refer to the relevant description of the above embodiment, which will not be repeated here.

[0141] In some examples, the display device may be an electronic product with a display function, such as a mobile phone, a laptop computer, a tablet computer, a navigator, an electronic photo frame, etc.

[0142] There are a few points to note:

[0143] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0144] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0145] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An array substrate, include: A substrate, comprising a display area and a peripheral area located around the display area; A pixel driving layer, located on the substrate, comprising a thin film transistor; A planar layer, located on a side of the pixel driving layer away from the substrate; An organic light emitting device, located on a side of the planar layer away from the pixel driving layer; An encapsulation layer, located on a side of the organic light-emitting device away from the substrate; A first retaining wall, located in the peripheral area and comprising a first retaining wall portion extending along a first direction; as well as A plurality of first channel lines are located in the peripheral area and on a side of the packaging layer away from the substrate, each of the plurality of first channel lines extends along the first direction, and the plurality of first channel lines are arranged along a second direction, and the second direction is substantially perpendicular to the first direction; The encapsulation layer includes an organic encapsulation layer, the planar layer includes a first edge portion extending along the first direction, the first edge portion is located between the first retaining wall portion and the display area, an orthographic projection of the first edge portion on the base substrate is covered by an orthographic projection of the organic encapsulation layer on the base substrate, and an orthographic projection of at least one of the plurality of first channel lines on the base substrate is located on a side of the first edge portion away from the display area, The organic encapsulation layer includes a second edge portion extending along the first direction, the second edge portion is located between the first edge portion and the first barrier portion, the plurality of first channel lines include a plurality of first flat channel lines located on a side of the first edge portion away from the base substrate and a plurality of first sloped channel lines located on a side of the second edge portion away from the base substrate, The distance between two adjacent first slope channel lines is greater than the distance between two adjacent first flat channel lines.

2. The array substrate according to claim 1, in, An orthographic projection of at least one first channel line among the plurality of first channel lines on the base substrate is located within an orthographic projection of the second edge portion on the base substrate.

3. The array substrate according to claim 1, in, The distance between two adjacent first slope channel lines is 1.05-2 times the distance between two adjacent first flat channel lines.

4. The array substrate according to claim 1, in, Among the plurality of first sloping channel lines, a distance between two adjacent first sloping channel lines is 1.05-2 times of a width of the first sloping channel line.

5. The array substrate according to any one of claims 1 to 4, in, A first channel line among the multiple first channel lines that is farthest from the display area is part of the ground line, and an orthographic projection of a first channel line among the multiple first channel lines that is farthest from the display area on the base substrate is located between an orthographic projection of the organic encapsulation layer on the base substrate and an orthographic projection of the first barrier wall portion on the base substrate.

6. The array substrate according to any one of claims 1 to 4, further comprising: include: A plurality of touch driving electrodes are located in the display area and on a side of the packaging layer away from the base substrate; A plurality of touch sensing electrodes are located in the display area and on a side of the packaging layer away from the base substrate; A touch driving signal line connected to each of the touch driving electrodes and extending to the peripheral area; as well as A touch sensing signal line is connected to each of the touch sensing electrodes and extends to the peripheral area, At least part of the plurality of first channel lines is a part of the touch drive signal line or the touch sensing signal line.

7. The array substrate according to any one of claims 2 to 4, in, The first retaining wall includes a second retaining wall portion extending along the second direction, and the array substrate further includes: A plurality of second channel lines extending along the second direction, Wherein, the planar layer includes a third edge portion extending along the second direction, the third edge portion is located between the second retaining wall portion and the display area, the orthographic projection of the third edge portion on the base substrate is covered by the orthographic projection of the organic encapsulation layer on the base substrate, and the orthographic projection of at least one second channel line among the multiple second channel lines on the base substrate is located on a side of the third edge portion away from the display area.

8. The array substrate according to claim 7, further comprising: include: A plurality of touch driving electrodes are located in the display area and on a side of the packaging layer away from the base substrate; A plurality of touch sensing electrodes are located in the display area and on a side of the packaging layer away from the base substrate; A touch driving signal line connected to each of the touch driving electrodes and extending to the peripheral area; as well as A touch sensing signal line is connected to each of the touch sensing electrodes and extends to the peripheral area, Each of the plurality of touch sensing electrodes extends along the first direction, the plurality of touch sensing electrodes are arranged along the second direction, and at least some of the plurality of first channel lines are part of the touch sensing signal line. Each of the plurality of touch driving electrodes extends along the second direction, the plurality of touch driving electrodes are arranged along the first direction, and at least part of the plurality of second channel lines is a part of the touch driving signal line.

9. The array substrate according to claim 7, in, The organic encapsulation layer includes a fourth edge portion extending along the second direction, the fourth edge portion is located between the third edge portion and the second barrier wall portion, and the orthographic projection of at least one second channel line among the plurality of second channel lines on the base substrate is located within the orthographic projection of the fourth edge portion on the base substrate.

10. The array substrate according to claim 9, in, The plurality of second channel lines include a plurality of second flat channel lines located on a side of the third edge portion away from the substrate and a plurality of second sloped channel lines located on a side of the fourth edge portion away from the substrate. The distance between two adjacent second slope channel lines is greater than the distance between two adjacent second flat channel lines.

11. The array substrate according to claim 10, in, The distance between two adjacent second slope channel lines is 1.05-2 times the distance between two adjacent second flat channel lines.

12. The array substrate according to claim 10, in, Among the plurality of second sloping channel lines, a distance between two adjacent second sloping channel lines is greater than or equal to 1.05-2 times of a width of the first sloping channel line.

13. The array substrate according to any one of claims 1 to 4, further comprising: include: A second retaining wall is disposed on the base substrate and located in the peripheral area, The second retaining wall is located between the first retaining wall and the display area, and the second retaining wall includes a third retaining wall portion extending along the first direction. The orthographic projection of at least one first channel line among the plurality of first channel lines on the base substrate is located within the orthographic projection of the third retaining wall portion on the base substrate.

14. The array substrate according to any one of claims 1 to 4, further comprising: include: A second retaining wall is disposed on the base substrate and located in the peripheral area, The second retaining wall is located between the first retaining wall and the display area, and the second retaining wall includes a third retaining wall portion extending along the first direction. The orthographic projections of the plurality of first channel lines on the base substrate are located on a side of the orthographic projection of the third retaining wall portion on the base substrate close to the display area.

15. The array substrate according to any one of claims 1 to 4, in, The organic light emitting device includes an anode, a light emitting layer and a cathode which are sequentially stacked in a direction away from the base substrate.

16. The array substrate according to any one of claims 1 to 4, in, The encapsulation layer further comprises: A first inorganic encapsulation layer is located on a side of the organic light-emitting device away from the substrate; and a second inorganic encapsulation layer, located on a side of the organic encapsulation layer away from the first inorganic encapsulation layer; The first inorganic encapsulation layer and the second inorganic encapsulation layer cover the first retaining wall, the organic encapsulation layer is sandwiched between the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the plurality of first channel lines are located on a side of the second inorganic encapsulation layer away from the base substrate.

17. A display device comprising the array substrate according to any one of claims 1 to 16.

18. An array substrate, include: A substrate, comprising a display area and a peripheral area located around the display area; A pixel driving layer, located on the substrate, comprising a thin film transistor; An organic light emitting device, located on the pixel driving layer; An encapsulation layer, located on the organic light-emitting device, the encapsulation layer comprising a first inorganic encapsulation layer and an organic encapsulation layer arranged in sequence; A plurality of first channel lines are located in the peripheral area and on a side of the packaging layer away from the substrate, each of the plurality of first channel lines extends along a first direction, and the plurality of first channel lines are arranged along a second direction, and the second direction is substantially perpendicular to the first direction; In the peripheral area, the first inorganic encapsulation layer includes a first inorganic encapsulation portion, an inorganic encapsulation connecting portion, and a second inorganic encapsulation portion that are continuously arranged in a direction from the display area to the peripheral area, and the inorganic encapsulation connecting portion is configured to connect the first inorganic encapsulation portion and the second inorganic encapsulation portion; In the peripheral area, in the direction from the display area to the peripheral area, the organic encapsulation layer includes a first organic encapsulation portion and a second organic encapsulation portion that are continuously arranged, an edge of the second organic encapsulation portion away from the display area is an edge of the organic encapsulation layer, an orthographic projection of the first organic encapsulation portion on the base substrate overlaps with an orthographic projection of the first inorganic encapsulation portion and an inorganic encapsulation connecting portion on the base substrate, and an orthographic projection of the second organic encapsulation portion on the base substrate overlaps with an orthographic projection of the second inorganic encapsulation portion on the base substrate; In a direction perpendicular to the base substrate, a distance d1 between the first inorganic encapsulation portion and the base substrate is greater than a distance d2 between the second inorganic encapsulation portion and the base substrate, and an orthographic projection of at least one of the plurality of first channel lines on the base substrate falls within an orthographic projection of the second inorganic encapsulation portion on the base substrate. The plurality of first channel lines include a plurality of first flat channel lines located on a side of the first organic encapsulation portion away from the base substrate and a plurality of first sloped channel lines located on a side of the second organic encapsulation portion away from the base substrate. The spacing between two adjacent first sloping channel lines is greater than the spacing between two adjacent first flat channel lines. Among the plurality of first sloping channel lines, the spacing between two adjacent first sloping channel lines is greater than the width of the first sloping channel line.

19. The array substrate according to claim 18, further comprising: include: A first retaining wall, located in the peripheral area and comprising a first retaining wall portion extending along the first direction; as well as The planar layer is located on a side of the pixel driving layer away from the substrate. The planar layer includes a first edge portion extending along the first direction, the first edge portion is located between the first retaining wall portion and the display area, and the orthographic projections of the first inorganic encapsulation portion and the inorganic encapsulation connection portion on the base substrate overlap with the orthographic projection of the first edge portion on the base substrate. The difference between the distance d1 between the first inorganic encapsulation part and the base substrate and the distance d2 between the second inorganic encapsulation part and the base substrate is greater than or equal to the maximum thickness of the portion of the planar layer overlapping the inorganic encapsulation connection part in a direction perpendicular to the base substrate.

20. The array substrate according to claim 19, in, The planar layer comprises: A first sub-planar layer, located on a side of the pixel driving layer away from the substrate; and The second sub-planar layer is located on a side of the first sub-planar layer away from the pixel driving layer. Among them, the difference between the distance d1 between the first inorganic packaging part and the base substrate and the distance d2 between the second inorganic packaging part and the base substrate is greater than or equal to the sum of the maximum thickness of the part of the first sub-planar layer overlapping with the inorganic packaging connection part in the direction perpendicular to the base substrate and the maximum thickness of the part of the second sub-planar layer overlapping with the inorganic packaging connection part in the direction perpendicular to the base substrate.

21. The array substrate according to claim 18, in, The distance between two adjacent first slope channel lines is 1.05-2 times the distance between two adjacent first flat channel lines.

22. The array substrate according to claim 18, in, Among the plurality of first sloping channel lines, a distance between two adjacent first sloping channel lines is 1.05-2 times of a width of the first sloping channel line.

23. A display device comprising the array substrate according to any one of claims 18 to 22.

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