Display device

Abstract

An exemplary embodiment relates to a display device, the display device including: a pixel circuit; a first line disposed on the pixel circuit; and a second line disposed on the same layer as the first line. A light-emitting element is disposed on the first line and the second line. A connection pattern is disposed on the same layer as the first line and the second line and is disposed between the first line and the second line. The connection pattern connects the pixel circuit and the light-emitting element. The connection pattern has a polygonal shape including at least six sides. A first vertex of the connection pattern is located at the shortest distance from the first line to the connection pattern, and a portion of the connection pattern between the first vertex and an adjacent vertex is located farther from the first line than the first vertex.

Description

Technical Field

[0001] The inventive concept relates to a display device. Background Art

[0002] A display device may include a plurality of pixels for displaying an image. The display device may include lines for providing signals, power, etc. for driving the pixels.

[0003] Due to the increase in the size and resolution of the display device, recent developments of the display device have led to an increase in the number of pixels per unit area. Accordingly, due to the increase in the number of pixels per unit area, the gap between the lines for providing signals, power, etc. to the pixels is reduced. The reduction in the gap between the lines and the pixels may cause defects such as a short circuit between the lines. Summary of the Invention

[0004] Exemplary embodiments of the inventive concept provide a display device that prevents short - circuit defects.

[0005] According to an exemplary embodiment of the inventive concept, a display device includes: a pixel circuit; a first line disposed on the pixel circuit and extending in a first direction; and a second line disposed on the same layer as the first line and extending in the first direction. The second line is spaced apart from the first line in a second direction that intersects the first direction. A light - emitting element is disposed on the first line and the second line. A connection pattern is disposed on the same layer as the first line and the second line and is disposed between the first line and the second line in the second direction. The connection pattern is configured to connect the pixel circuit and the light - emitting element. The connection pattern has a polygonal shape including at least six sides. A first vertex of the connection pattern is located at the shortest distance from the first line to the connection pattern, and a portion of the connection pattern between the first vertex and an adjacent vertex is located farther from the first line than the first vertex.

[0006] In an exemplary embodiment, a second vertex of the connection pattern may be located at the shortest distance from the second line to the connection pattern.

[0007] In an exemplary embodiment, the connection pattern may include: a first connection portion connected to the light - emitting element; and a second connection portion connected to the pixel circuit, and the first connection portion may have a rhombus shape.

[0008] In an exemplary embodiment, the first vertex may be a vertex of the first connection portion.

[0009] In an exemplary embodiment, the second vertex may be a vertex of the first connection portion.

[0010] In an exemplary embodiment, the second connection part may have a rhombus shape.

[0011] In an exemplary embodiment, the second vertex may be a vertex of the second connection part.

[0012] In an exemplary embodiment, the second connection part may have a rectangular shape.

[0013] In an exemplary embodiment, the first line may be a data line that provides a data signal to the pixel circuit.

[0014] In an exemplary embodiment, the second line may be a power line that provides a power supply voltage to the pixel circuit.

[0015] In an exemplary embodiment, the display device may further include a first pixel and a second pixel spaced apart from the first pixel in a second direction that intersects the first direction. The first line may be connected to the first pixel, and the second line may be connected to the second pixel.

[0016] In an exemplary embodiment, the light-emitting element may include a first electrode, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer, and the connection pattern may be connected to the first electrode.

[0017] According to an exemplary embodiment of the inventive concept, a display device includes: a pixel circuit; a first line disposed on the pixel circuit, the first line extending in a first direction; and a second line disposed on the same layer as the first line and extending in the first direction. The second line is spaced apart from the first line in a second direction that intersects the first direction. A light-emitting element is disposed on the first line and the second line. A connection pattern is disposed on the same layer as the first line and the second line, and is disposed between the first line and the second line in the second direction. The connection pattern includes a first connection part configured to connect the light-emitting element and a second connection part configured to connect the pixel circuit. The first connection part has a rhombus shape.

[0018] In an exemplary embodiment, the vertex of the first connection part may be located at the shortest distance from the first line to the connection pattern.

[0019] In an exemplary embodiment, the vertex of the first connection part may be located at the shortest distance from the second line to the connection pattern.

[0020] In an exemplary embodiment, the second connection part may have a rhombus shape.

[0021] In an exemplary embodiment, a vertex of the second connection portion may be located at a shortest distance from the second line to the connection pattern.

[0022] In an exemplary embodiment, the second connection portion may have a rectangular shape.

[0023] In an exemplary embodiment, a length of a first side of the second connection portion extending in the first direction may be less than a distance in the first direction between a second side of the second connection portion extending in a second direction crossing the first direction and a vertex of the first connection portion.

[0024] In an exemplary embodiment, the length of the first side of the second connection portion may be greater than a width of a contact hole in the first direction, and the second connection portion and the pixel circuit are connected through the contact hole.

[0025] According to an exemplary embodiment of the inventive concept, a display device includes: a pixel circuit; a first line disposed on the pixel circuit and extending in a first direction; and a second line disposed on the same layer as the first line and extending in the first direction. The second line is spaced apart from the first line in a second direction crossing the first direction. A light-emitting element is disposed on the first line and the second line. A connection pattern is disposed on the same layer as the first line and the second line and is disposed between the first line and the second line in the second direction. The connection pattern includes a first connection portion configured to connect the light-emitting element and a second connection portion configured to connect the pixel circuit. The connection pattern has a shape in which the first connection portion or the second connection portion has a first vertex located at a shortest distance from the first line to the connection pattern, and all other portions of the connection pattern are located farther from the first line. The first connection portion or the second connection portion has a second vertex located at a shortest distance from the second line to the connection pattern, and all other portions of the connection pattern are located farther from the second line.

[0026] In the display device according to the exemplary embodiment of the inventive concept, the connection pattern may include the first connection portion connected to the light-emitting element and having a rhombus shape, and the first vertex of the connection pattern may be located at a shortest distance from the first line to the connection pattern. Accordingly, although a distance between the first line and the connection pattern decreases due to an increase in resolution of the display device, the first vertex of the connection pattern and a side of the first line may face each other, so that a short-circuit defect between the first line and the connection pattern may be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The following detailed description with reference to the accompanying drawings will enable a clearer understanding of the illustrative non - limiting embodiments.

[0028] Figure 1 is a circuit diagram of a pixel included in a display device according to an exemplary embodiment of the inventive concept.

[0029] Figure 2 is a plan view of a first pixel and a second pixel included in a display device according to an exemplary embodiment of the inventive concept.

[0030] Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 is a plan view of the layers of the first pixel and the second pixel shown in Figure 2 according to an exemplary embodiment of the inventive concept.

[0031] Figure 8 is a cross - sectional view taken along line I - I' in Figure 2 according to an exemplary embodiment of the inventive concept.

[0032] Figure 9 is an enlarged plan view of region II of Figure 6 according to an exemplary embodiment of the inventive concept.

[0033] Figure 10 is an enlarged plan view showing a first line, a second line, and a connection pattern according to an exemplary embodiment of the inventive concept.

[0034] Figure 11 is an enlarged plan view showing a first line, a second line, and a connection pattern according to an exemplary embodiment of the inventive concept. Detailed Description of the Embodiments

[0035] Hereinafter, a display device according to an exemplary embodiment of the inventive concept will be explained in detail with reference to the accompanying drawings.

[0036] Figure 1 is a circuit diagram of a pixel included in a display device according to an embodiment.

[0037] Referring to Figure 1 , a display device according to an exemplary embodiment of the inventive concept may include a plurality of pixels PX. Each pixel PX may emit light, and the display device may display an image formed by the light emitted from the pixels PX. Each pixel PX may include a light - emitting element EL and a pixel circuit PC.

[0038] The anode of the light-emitting element EL can be connected to the pixel circuit PC, and the cathode of the light-emitting element EL can receive a second voltage ELVSS. The light-emitting element EL can generate light having a predetermined luminance corresponding to the magnitude of the current I supplied from the pixel circuit PC EL and supplied to the anode of the light-emitting element EL. The first voltage ELVDD can be greater than the second voltage ELVSS to provide the current I flowing through the light-emitting element EL EL .

[0039] The pixel circuit PC can control the magnitude of the current I flowing through the light-emitting element EL from the first power supply that supplies the first voltage ELVDD in response to the data signal DT to the second power supply that supplies the second voltage ELVSS EL . To control the magnitude of the current I EL , the pixel circuit PC can include a plurality of transistors and at least one capacitor.

[0040] As Figure 1 shown in the exemplary embodiment of, the pixel circuit PC can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor CAP. However, the exemplary embodiment of the inventive concept is not limited thereto, and in other exemplary embodiments, the pixel circuit PC can include two to six or eight or more transistors and / or two or more capacitors.

[0041] The first transistor T1 can be a driving transistor that supplies the current I corresponding to the data signal DT EL to the light-emitting element EL. In the exemplary embodiment, the first transistor T1 can include a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3.

[0042] The second transistor T2 can be a switching transistor that supplies the data signal DT to the first transistor T1 in response to the first gate signal GW. In the exemplary embodiment, the second transistor T2 can include a gate electrode that receives the first gate signal GW, a first electrode that receives the data signal DT, and a second electrode connected to the second node N2.

[0043] The third transistor T3 can be a compensation transistor that diode-connects the first and second electrodes of the first transistor T1 in response to the first gate signal GW. In the exemplary embodiment, the third transistor T3 can include a gate electrode that receives the first gate signal GW, a first electrode connected to the first node N1, and a second electrode connected to the third node N3.

[0044] The fourth transistor T4 may be a first initialization transistor that provides an initialization voltage VINT to the first transistor T1 in response to a second gate signal GI. In an exemplary embodiment, the fourth transistor T4 may include a gate electrode that receives the second gate signal GI, a first electrode that receives the initialization voltage VINT, and a second electrode that is connected to the first node N1.

[0045] Each of the fifth transistor T5 and the sixth transistor T6 may be an emission control transistor that provides a first voltage ELVDD to the light-emitting element EL in response to an emission control signal EM. In an exemplary embodiment, the fifth transistor T5 may include a gate electrode that receives the emission control signal EM, a first electrode that receives the first voltage ELVDD, and a second electrode that is connected to the second node N2. The sixth transistor T6 may include a gate electrode that receives the emission control signal EM, a first electrode that is connected to the third node N3, and a second electrode that is connected to the anode of the light-emitting element EL.

[0046] The seventh transistor T7 may be a second initialization transistor that provides an initialization voltage VINT to the light-emitting element EL in response to a third gate signal GB. In an exemplary embodiment, the seventh transistor T7 may include a gate electrode that receives the third gate signal GB, a first electrode that receives the initialization voltage VINT, and a second electrode that is connected to the anode of the light-emitting element EL.

[0047] The capacitor CAP may store a voltage corresponding to the data signal DT and the threshold voltage of the first transistor T1. In an exemplary embodiment, the capacitor CAP may include a first capacitor electrode 124 that is connected to the first node N1 and a second capacitor electrode that receives the first voltage ELVDD.

[0048] In an exemplary embodiment, the first electrode of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be either a source electrode or a drain electrode, and the second electrode of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be an electrode different from the first electrode. For example, in an exemplary embodiment, the first electrode of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a source electrode, and the second electrode of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a drain electrode. Additionally, although in Figure 1The gate electrodes of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 shown in the exemplary embodiment are single gate electrodes, but the exemplary embodiments of the present inventive concept are not limited thereto. For example, in other exemplary embodiments, at least one gate electrode of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a double gate electrode, etc.

[0049] Figure 2 is a plan view illustrating a first pixel and a second pixel included in a display device according to an exemplary embodiment of the inventive concept. Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 is a diagram showing an exemplary embodiment according to the inventive concept Figure 2 A plan view of the layers of the first pixel and the second pixel shown in FIG. Figure 8 is an exemplary embodiment according to the inventive concept. Figure 2 A cross-sectional view taken along line II' in FIG.

[0050] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 In an exemplary embodiment, the display device may include a plurality of pixels PX including a first pixel PX1 and a second pixel PX2. In an exemplary embodiment, the plurality of pixels PX may be arranged in a substantially matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, in an exemplary embodiment, the first direction DR1 may be perpendicular to the second direction DR2. The first pixel PX1 may be any one of the plurality of pixels PX, and the second pixel PX2 may be located adjacent to the first pixel PX1 and may be spaced apart from the first pixel PX1, for example, in the second direction DR2. Each of the first pixel PX1 and the second pixel PX2 may include a pixel circuit PC and a light emitting element EL.

[0051] The active layer 110, including a first conductive layer of a first gate line 121, a second gate line 122, an emission control line 123, and a first capacitor electrode 124, a second conductive layer including a third gate line 131, an initialization voltage line 132, and a conductive pattern 133, a third conductive layer including a first line 141, a second line 142, a connection pattern 143, a gate connection pattern 144, and an initialization connection pattern 145, a first electrode 150, an emission layer 160, and a second electrode 170 may be sequentially disposed on the substrate 100 (e.g., in the thickness direction of the substrate 100). In an exemplary embodiment, the active layer 110, the first conductive layer, and the second conductive layer may form a pixel circuit PC including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor CAP. In addition, the first electrode 150, the emission layer 160, and the second electrode 170 may form a light-emitting element EL.

[0052] The substrate 100 may include a transparent insulating substrate. For example, the substrate 100 may be formed of a glass substrate, a quartz substrate, a plastic substrate, or the like. However, the exemplary embodiments of the inventive concept are not limited thereto. In an exemplary embodiment, the substrate 100 may include a structure in which an organic insulating layer and an inorganic insulating layer are alternately stacked. For example, the substrate 100 may be formed as a structure in which a first organic insulating layer including polyimide (PI), a first inorganic insulating layer including a silicon compound and / or amorphous silicon, a second organic insulating layer including polyimide, and a second inorganic insulating layer including a silicon compound are stacked.

[0053] As Figure 8 shown in the exemplary embodiment of, the active layer 110 may be disposed on the substrate 100 (e.g., in the thickness direction of the substrate 100). In an exemplary embodiment, a buffer layer may be inserted between the substrate 100 and the active layer 110 to provide insulation between the substrate 100 and the active layer 110. For example, the buffer layer may prevent impurities from dispersing from the substrate 100 and may control the rate of heat transfer during the crystallization process for forming the active layer 110. In an exemplary embodiment, the buffer layer may include a silicon compound or a metal oxide, etc. However, the exemplary embodiments of the inventive concept are not limited thereto. In some exemplary embodiments, the buffer layer may not be included in the display device. The active layer 110 may include a source region, a drain region, and a channel region of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0054] In an exemplary embodiment, the active layer 110 may be formed of polysilicon. For example, after an amorphous silicon layer is formed on the buffer layer, the amorphous silicon layer may be crystallized to form a polysilicon layer. The polysilicon layer may then be patterned to form the active layer 110. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the active layer 110 may be formed of an oxide semiconductor. For example, an oxide semiconductor layer is formed on the buffer layer, and the oxide semiconductor layer may be patterned to form the active layer 110.

[0055] The first conductive layer may be disposed on the active layer 110. For example, the first conductive layer may be directly or indirectly disposed above the active layer 110. As Figure 8 shown in the exemplary embodiment of, the first insulating layer 101 may be inserted (e.g., in the thickness direction of the substrate 100) between the active layer 110 and the first conductive layer to provide insulation between the active layer 110 and the first conductive layer. For example, the lower surface of the first insulating layer 101 may directly contact the upper surface and the side surface of the active layer 110, and the upper surface of the first insulating layer 101 may directly contact the lower surface of the first conductive layer, such as Figure 8 the emission control line 123 shown in. In an exemplary embodiment, the first insulating layer 101 may include at least one material selected from silicon compounds, metal oxides, and the like.

[0056] As Figure 4 shown in the exemplary embodiment of, the first gate line 121, the second gate line 122, and the emission control line 123 of the first conductive layer may be arranged (e.g., spaced apart) in the first direction DR1 and may extend in the second direction DR2. In an exemplary embodiment, the first gate line 121 may provide a first gate signal GW to the pixel circuit PC, the second gate line 122 may provide a second gate signal GI to the pixel circuit PC, and the third gate line including the emission control line 123 may provide an emission control signal EM to the pixel circuit PC. In an exemplary embodiment, the first conductive layer may be formed of at least one material selected from metals, alloys, conductive metal nitrides, conductive metal oxides, and transparent conductive materials, and the like. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0057] A portion of the first gate line 121 overlapping with the active layer 110 (e.g., in the thickness direction of the substrate 100) may be used as a gate electrode of the second transistor T2, and another portion of the first gate line 121 overlapping with the active layer 110 (e.g., in the thickness direction of the substrate 100) may be used as a gate electrode of the third transistor T3. Accordingly, the active layer 110 and the first gate line 121 may form the second transistor T2 and the third transistor T3. A portion of the second gate line 122 overlapping with the active layer 110 (e.g., in the thickness direction of the substrate 100) may be used as a gate electrode of the fourth transistor T4. Accordingly, the active layer 110 and the second gate line 122 may form the fourth transistor T4. A portion of the emission control line 123 overlapping with the active layer 110 (e.g., in the thickness direction of the substrate 100) may be used as a gate electrode of the fifth transistor T5, and another portion of the emission control line 123 overlapping with the active layer 110 (e.g., in the thickness direction of the substrate 100) may be used as a gate electrode of the sixth transistor T6. Accordingly, the active layer 110 and the emission control line 123 may form the fifth transistor T5 and the sixth transistor T6.

[0058] The second conductive layer may be disposed on the first conductive layer. For example, the second conductive layer may be directly or indirectly disposed above the first conductive layer. The second insulating layer 102 may be inserted (e.g., in the thickness direction of the substrate 100) between the first conductive layer and the second conductive layer to provide insulation between the first conductive layer and the second conductive layer. In an exemplary embodiment, the second insulating layer 102 may include a silicon compound or a metal oxide, etc.

[0059] As Figure 5 shown in the exemplary embodiment of, the third gate line 131, the initialization voltage line 132, and the conductive pattern 133 of the second conductive layer may be arranged (e.g., spaced apart in the first direction DR1) in the first direction DR1 and may extend in the second direction DR2. In an exemplary embodiment, the third gate line 131 may provide a third gate signal GB to the pixel circuit PC, and the initialization voltage line 132 may provide an initialization voltage VINT to the pixel circuit PC. In an exemplary embodiment, the third gate line 131, the initialization voltage line 132, and the conductive pattern 133 of the second conductive layer may be formed of a metal, an alloy, a conductive metal nitride, a conductive metal oxide, or a transparent conductive material, etc. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0060] A portion of the third gate line 131 overlapping with the active layer 110 (e.g., in the thickness direction of the substrate 100) may be used as a gate electrode of the seventh transistor T7. Accordingly, the active layer 110 and the third gate line 131 may form the seventh transistor T7. A portion of the conductive pattern 133 overlapping with the first capacitor electrode 124 (e.g., in the thickness direction of the substrate 100) may be used as a second capacitor electrode of the capacitor CAP. Accordingly, the first capacitor electrode 124 and the conductive pattern 133 may form the capacitor CAP.

[0061] The third conductive layer may be disposed on the second conductive layer. For example, the third conductive layer may be directly or indirectly disposed above the second conductive layer. The third insulating layer 103 may be inserted (e.g., in the thickness direction of the substrate 100) between the second conductive layer and the third conductive layer to provide insulation between the second conductive layer and the third conductive layer. The third insulating layer 103 may include a silicon compound or a metal oxide, etc.

[0062] As Figure 6 shown in the exemplary embodiment of, the first line 141 and the second line 142 of the third conductive layer may be arranged (e.g., spaced apart in the second direction DR2) in the second direction DR2 and may extend in the first direction DR1. In the exemplary embodiment, the first line 141 may provide a data signal DT to the pixel circuit PC, and the second line 142 may provide a power supply voltage to the pixel circuit PC. For example, the power supply voltage may be a first voltage ELVDD. In the exemplary embodiment, the third conductive layer may be formed of a metal, an alloy, a conductive metal nitride, a conductive metal oxide, or a transparent conductive material, etc. However, the exemplary embodiment of the inventive concept is not limited thereto.

[0063] The first line 141 may be connected to the active layer 110 through a first contact hole CH1 formed in the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. The second line 142 may be connected to the conductive pattern 133 through a second contact hole CH2 formed in the third insulating layer 103 and may be connected to the active layer 110 through a third contact hole CH3 formed in the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. As Figure 8As shown in the exemplary embodiment, the connection pattern 143 may be connected to the active layer 110 through a fourth contact hole CH4 formed in the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. The gate connection pattern 144 may be connected to the first capacitor electrode 124 through a fifth contact hole CH5 formed in the second insulating layer 102 and the third insulating layer 103, and may be connected to the active layer 110 through a sixth contact hole CH6 formed in the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. The initialization connection pattern 145 may be connected to the active layer 110 through a seventh contact hole CH7 and an eighth contact hole CH8 formed in the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103, and may be connected to the initialization voltage line 132 through a ninth contact hole CH9 formed in the third insulating layer 103.

[0064] The first electrode 150 may be disposed on the first line 141, the second line 142, the connection pattern 143, the gate connection pattern 144, and the initialization connection pattern 145 of the third conductive layer. For example, the first electrode 150 may be disposed directly or indirectly on the third conductive layer. The fourth insulating layer 104 may be inserted (e.g., in the thickness direction of the substrate 100) between the first line 141, the second line 142, the connection pattern 143, the gate connection pattern 144, and the initialization connection pattern 145 of the third conductive layer and the first electrode 150 to provide insulation between the first line 141, the second line 142, the connection pattern 143, the gate connection pattern 144, and the initialization connection pattern 145 of the third conductive layer and the first electrode 150. In the exemplary embodiment, the fourth insulating layer 104 may include polyimide or the like. However, the exemplary embodiment of the inventive concept is not limited thereto.

[0065] In the exemplary embodiment, the first electrode 150 may be formed of at least one material selected from metals, alloys, conductive metal nitrides, conductive metal oxides, and transparent conductive materials. For example, the first electrode 150 may include silver (Ag) or indium tin oxide (ITO). However, the exemplary embodiment of the inventive concept is not limited thereto. The first electrode 150 may be connected to the connection pattern 143 through a tenth contact hole CH10 formed in the fourth insulating layer 104.

[0066] The fifth insulating layer 105 may be disposed on the first electrode 150. For example, as Figure 8As shown in an exemplary embodiment, the fifth insulating layer 105 may directly contact the upper surface and the side surface of the first electrode 150. The fifth insulating layer 105 may cover the first electrode 150 and may be disposed on the fourth insulating layer 104. The fifth insulating layer 105 may have a pixel opening exposing at least a portion of the first electrode 150. In an exemplary embodiment, the pixel opening may expose a central portion of the first electrode 150 and may cover a peripheral portion of the first electrode 150. In an exemplary embodiment, the fifth insulating layer 105 may be formed of polyimide or the like. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0067] The emission layer 160 may be disposed on the first electrode 150. The emission layer 160 may be disposed on the first electrode 150 exposed by the pixel opening. For example, as Figure 8 shown in an exemplary embodiment, the lower surface of the emission layer 160 may directly contact the upper surface of the first electrode 150 exposed by the pixel opening. The lateral side surface of the emission layer 160 may directly contact a lower portion of the lateral side surface of the fifth insulating layer 105 forming the pixel opening. In an exemplary embodiment, the emission layer 160 may include at least one of an organic light-emitting material and a quantum dot. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0068] In an exemplary embodiment, the organic light-emitting material may include a low-molecular organic compound or a high-molecular organic compound. For example, the low-molecular organic compound may include at least one compound selected from copper phthalocyanine, diphenylbenzidine (N,N'-diphenylbenzidine), and tris(8-hydroxyquinoline) aluminum (tris-(8-hydroxyquinoline) aluminum). The high-molecular organic compound may include at least one compound selected from poly(3,4-ethylenedioxythiophene) (PEDOT), polyaniline, poly(phenylene vinylene), and polyfluorene.

[0069] In an exemplary embodiment, the quantum dot may include a core including a II-VI group compound, a III-V group compound, a IV-VI group compound, a group IV element, a group IV compound, and a combination thereof. In one exemplary embodiment, the quantum dot may have a core-shell structure including a core and a shell surrounding the core. The shell may prevent chemical denaturation of the core, and thus may serve as a protective layer for maintaining semiconductor characteristics and a charging layer for imparting electrophoretic characteristics to the quantum dot.

[0070] The second electrode 170 may be disposed on the emission layer 160. In an exemplary embodiment, the second electrode 170 may also be disposed on the fifth insulating layer 105. For example, as Figure 8As shown in the exemplary embodiment, the lower surface of the second electrode 170 may directly contact the upper surface of the emission layer 160, the upper surface of the fifth insulating layer 105, and the upper portion of the lateral side surface of the fifth insulating layer 105 that forms the pixel opening. In the exemplary embodiment, the second electrode 170 may include a conductive material, such as at least one material selected from metals, alloys, and transparent conductive oxides. For example, the second electrode 170 may include at least one compound selected from aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), and titanium (Ti). The first electrode 150, the emission layer 160, and the second electrode 170 may form a light-emitting element EL.

[0071] Figure 9 is an enlarged plan view showing a first line, a second line, and a connection pattern according to an exemplary embodiment of the inventive concept. For example, Figure 9 may show Figure 6 an example of region II in

[0072] Referring to Figures 1 to 9 the exemplary embodiment of , the first line 141, the second line 142, and the connection pattern 143 may be disposed (e.g., in the thickness direction of the substrate) between the pixel circuit PC and the light-emitting element EL. The first line 141, the second line 142, and the connection pattern 143 may be disposed on the pixel circuit PC. For example, the first line 141, the second line 142, and the connection pattern 143 may be directly or indirectly disposed above the pixel circuit PC. The light-emitting element EL may be disposed on the first line 141, the second line 142, and the connection pattern 143. For example, the light-emitting element EL may be directly or indirectly disposed above the first line 141, the second line 142, and the connection pattern 143. As Figure 6 and Figure 9 the exemplary embodiment of shows, the second line 142 may be disposed on the same layer as the first line 141, and may be spaced apart from the first line 141 in the second direction DR2 and may extend parallel to the first line 141. For example, the first line 141 and the second line 142 may both extend substantially parallel to the first direction DR1. The connection pattern 143 may be disposed on the same layer as the first line 141 and the second line 142, and may be disposed (e.g., in the second direction DR2) between the first line 141 and the second line 142.

[0073] In the exemplary embodiment, the first line 141 may be connected to the first pixel PXl, and the second line 142 may be connected to the second pixel PX2. In this embodiment, the connection pattern 143 may connect the pixel circuit PC of the second pixel PX2 and the light-emitting element EL.

[0074] As Figure 9As shown in the exemplary embodiment of, the connection pattern 143 may have a polygonal shape including at least six sides in a plan view (e.g., in a plan view defined by a first direction DR1 and a second direction DR2). In the exemplary embodiment, the connection pattern 143 may have a hexagonal shape. In this embodiment, the connection pattern 143 may have six vertices.

[0075] The connection pattern 143 may include a first connection portion 143a connected to the light-emitting element EL and a second connection portion 143b connected to the pixel circuit PC. The first connection portion 143a may be connected to the first electrode 150 of the light-emitting element EL through a tenth contact hole CH10, and the second connection portion 143b may be connected to the active layer 110 of the pixel circuit PC through a fourth contact hole CH4.

[0076] As Figure 9 shown in the exemplary embodiment of, the first connection portion 143a may have a rhombus shape in a plan view (e.g., in a plan view defined by a first direction DR1 and a second direction DR2). For example, the sides of the first connection portion 143a may extend in a direction that is not parallel to the first direction DR1 and the second direction DR2 between the first direction DR1 and the second direction DR2. The vertices of the first connection portion 143a may be spaced apart from the center of the first connection portion 143a in the first direction DR1 or the second direction DR2.

[0077] In the exemplary embodiment, the tenth contact hole CH10 may have a rhombus shape similar to the shape of the first connection portion 143a in a plan view. For example, the area of the tenth contact hole CH10 may be smaller than the area of the first connection portion 143a. As Figure 9 shown in the exemplary embodiment of, each side of the tenth contact hole CH10 (e.g., the side surface extending between the vertices of the tenth contact hole CH10) may be spaced apart from the adjacent side edges of the first connection portion 143a by the same distance. However, the exemplary embodiment of the inventive concept is not limited thereto.

[0078] The first vertex VX1 of the connection pattern 143 may be located at the shortest distance DS1 from the first line 141 to the connection pattern 143 (e.g., the length in the second direction DR2). The point closest to the first line 141 among the edges of the connection pattern 143 may be the first vertex VX1, and the edges of the connection pattern 143 between the first vertex VX1 and each adjacent vertex may be (e.g., in the second direction DR2) located farther from the first line 141 than the first vertex VX1. In Figure 9In the exemplary embodiment shown, the first vertex of the connection pattern 143 may face the edge 141a of the first line 141. For example, the edge 141a may extend substantially in the first direction DR1 and be the inner edge closest to the adjacent second line 142, and the connection pattern 143 (e.g., in the second direction DR2) is located between the edge 141a and the adjacent second line 142. The lower portion of the connection pattern 143 connected to the first connection portion 143a (e.g., in the first direction DR1) may be rectangular in shape and may have an edge adjacent to the first line 141, which extends substantially in the first direction DR1 and (e.g., in the second direction DR2) is located farther from the first line 141 than the first vertex VX1. However, in other exemplary embodiments, the lower portion of the connection pattern 143 may have other shapes with an edge adjacent to the first line 141 located farther from the first line 141 than the first vertex VX1.

[0079] In the comparative example, the connection pattern may have a rectangular shape in the plan view, and the rectangular shape is arranged such that the edge of the connection pattern extending in the first direction DR1 may face the adjacent edge of the first line extending in the first direction DR1 or the edge of the second line. In the comparative example, due to the increase in the resolution of the display device, the distance between the first line and the connection pattern and the distance between the second line and the connection pattern may decrease. Therefore, the distance between the adjacent edge of the first line and the entire edge of the connection pattern facing the first line and the distance between the edge of the second line facing each other and the entire edge of the connection pattern may decrease. In this comparative example, short-circuit defects may occur between the first line and the connection pattern and / or between the second line and the connection pattern, such as due to tolerances in the etching process for forming the first line, the second line, and the connection pattern provided on the same layer or particles generated in the etching process.

[0080] However, in Figure 9 the exemplary embodiment of the inventive concept shown, the first connection portion 143a of the connection pattern 143 may have a rhombus shape in the plan view, and the first vertex VX1 of the connection pattern 143 may be located at the shortest distance DS1 from the first line 141 to the connection pattern 143. Therefore, even when the distance between the first line 141 and the connection pattern 143 decreases due to the increase in the resolution of the display device, only the vertex VX1 of the connection pattern 143 and the edge 141a of the first line 141 face each other, and the side surface of the first connection pattern 143 extending between the vertex VX1 and the adjacent vertex is spaced farther apart from the adjacent side edge of the first line 141. Therefore, short-circuit defects between the first line 141 and the connection pattern 143 can be prevented.

[0081] Figure 10is an enlarged plan view showing a first line, a second line, and a connection pattern according to an exemplary embodiment of the inventive concept. For example, Figure 10 may show another exemplary embodiment according to the inventive concept Figure 6 another example of Region II in

[0082] Referring to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 10 of the exemplary embodiments, the first line 141, the second line 142, and the connection pattern 1143 may be disposed (e.g., in the thickness direction of the substrate 100) between the pixel circuit PC and the light-emitting element EL. The description of the first line 141, the second line 142, and the connection pattern 1143 that is substantially the same as or similar to the first line 141, the second line 142, and the connection pattern 143 described in the exemplary embodiment referring to Figure 9 will be omitted. Figure 10 of the exemplary embodiment referring to

[0083] The connection pattern 1143 may have a polygonal shape including at least six sides in a plan view. In an exemplary embodiment, the connection pattern 1143 may have a nonagon shape. In the present exemplary embodiment, the connection pattern 1143 may have nine vertices.

[0084] The connection pattern 1143 may include a first connection portion 1143a connected to the light-emitting element EL and a second connection portion 1143b connected to the pixel circuit PC.

[0085] As described in the exemplary embodiment regarding Figure 9 , the first connection portion 1143a may have a rhombus shape in a plan view (e.g., in a plane defined by a first direction DR1 and a second direction DR2). The second connection portion 1143b may have a rhombus shape in a plan view (e.g., in a plane defined by a first direction DR1 and a second direction DR2). For example, the sides of the second connection portion 1143b may extend in a direction between the first direction DR1 and the second direction DR2, and the vertices of the second connection portion 1143b may be spaced apart from the center of the second connection portion 1143b in the first direction DR1 or the second direction DR2.

[0086] In an exemplary embodiment, the fourth contact hole CH4 may have a diamond shape similar to the shape of the second connection part 1143b in a plan view (e.g., in a plane defined by a first direction DR1 and a second direction DR2). For example, the area of the fourth contact hole CH4 may be smaller than the area of the second connection part 1143b. As Figure 10 shown in the exemplary embodiment of

[0087] The second vertex VX2 of the first connection part 1143a (e.g., the vertex opposite the first vertex VX1 in the second direction DR2) may be (e.g., in the second direction DR2) located at the shortest distance DS2 from the second line 142 to the connection pattern 1143. The point on the edge of the connection pattern 1143 closest to the second line 142 may be the second vertex VX2. In the present exemplary embodiment, the second vertex VX2 of the connection pattern 1143 may face the side 142a of the second line 142. For example, the side 142a may be substantially extending in the first direction DR1 and the inner edge closest to the adjacent first line 141, and the connection pattern 1143 (e.g., in the second direction DR2) is located between the side 142a and the adjacent first line 141.

[0088] In an exemplary embodiment, the second vertex VX2 of the first connection part 1143a may be located at the shortest distance DS2 from the second line 142 to the connection pattern 1143.

[0089] In another exemplary embodiment, the third vertex VX3 of the second connection part 1143b may be located at the shortest distance DS3 (e.g., the length in the second direction DR2) from the second line 142 to the connection pattern 1143. However, in another exemplary embodiment, the distance between the third vertex VX3 of the second connection part 1143b and the second line 142 and the distance between the second vertex VX2 of the first connection part 1143a and the second line 142 may be the same, and the second vertex VX2 and the third vertex VX3 may both be located at the shortest distance from the second line 142. The portion of the connection pattern 1143 between the first connection part 1143a and the second connection part 1143b may be rectangular in shape and may have a side adjacent to the second line 142, which is substantially extending in the first direction DR1 and is located at a position farther from the second line 142 than the second vertex VX2 and / or the third vertex VX3 having the shortest distance from the second line 142.

[0090] In Figure 10In an exemplary embodiment, the second connection portion 1143b of the connection pattern 1143 may have a rhombus shape in a plan view, and the second vertex VX2 of the first connection portion 1143a and / or the third vertex VX3 of the second connection portion 1143b may be located at the shortest distances DS2 and / or DS3 from the second line 142 to the connection pattern 1143. Accordingly, although the distance between the second line 142 and the connection pattern 1143 decreases due to an increase in the resolution of the display device, since only the second vertex VX2 of the connection pattern 1143 and / or the third vertex VX3 of the connection pattern 1143 and the side 142a of the second line 142 face each other, and the side surfaces of the first connection portion 1143a extending between the second vertex VX2 and an adjacent vertex and / or between the third vertex VX3 and an adjacent vertex are located farther from the adjacent side 142a of the second line 142, a short-circuit defect between the second line 142 and the connection pattern 1143 can be prevented.

[0091] Figure 11 is an enlarged plan view showing a first line, a second line, and a connection pattern according to an exemplary embodiment of the inventive concept. For example, Figure 11 may show another Figure 6 example of region II in

[0092] Referring to Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 and Figure 11 of the exemplary embodiments, the first line 141, the second line 142, and the connection pattern 2143 may be disposed (e.g., in a thickness direction of the substrate 100) between the pixel circuit PC and the light-emitting element EL. The description of the first line 141, the second line 142, and the connection pattern 2143 described with reference to the exemplary embodiments of Figure 9 is substantially the same as or similar to the description of the first line 141, the second line 142, and the connection pattern 143 described with reference to the exemplary embodiments of Figure 11 and will be omitted.

[0093] The connection pattern 2143 may have a polygon shape including at least six sides in a plan view (e.g., in a plane defined by a first direction DR1 and a second direction DR2). In an exemplary embodiment, the connection pattern 2143 may have an eleven-sided shape. In the present exemplary embodiment, the connection pattern 2143 may have eleven vertices.

[0094] The connection pattern 2143 may include a first connection portion 2143a connected to the light-emitting element EL and a second connection portion 2143b connected to the pixel circuit PC.

[0095] The second connection portion 2143b may have a rectangular shape in a plan view (e.g., in a plane defined by a first direction DR1 and a second direction DR2). For example, the second connection portion 2143b may have a first side SD1 adjacent to the first line 141 and the second line 142 and extending in the first direction DR1, and a second side SD2 adjacent to the second side SD2 forming the bottom surface of the second connection portion 2143b extending in the second direction DR2.

[0096] In an exemplary embodiment, the fourth contact hole CH4 may have a rectangular shape similar to the shape of the second connection portion 2143b in a plan view. For example, the area of the fourth contact hole CH4 may be smaller than the area of the second connection portion 2143b. In another Figure 11 exemplary embodiment as shown in, the fourth contact hole CH4 may have a substantially square shape and be spaced apart from the central portion of the second connection portion 2143b (e.g., in the second direction DR2). For example, the fourth contact hole CH4 may be adjacent to the first side SD1 adjacent to the second line 142.

[0097] In an exemplary embodiment, the length LT of the first side SD1 of the second connection portion 2143b (e.g., in the first direction DR1) may be smaller than the distance DS4 in the first direction DR1 between the second side SD2 of the second connection portion 2143b and the second vertex VX2 of the first connection portion 2143a. The portion of the connection pattern 2143 between the first connection portion 2143a and the second connection portion 2143b may be rectangular in shape and may have a first side adjacent to the second line 142 and a second side adjacent to the first line 141. The first side and the second side extend substantially in the first direction DR1 and are respectively located farther from the first line 141 and the second line 142 than the first vertex VX1 and the second vertex VX2 (e.g., in the second direction DR2).

[0098] In an exemplary embodiment, the length LT of the first side SD1 of the second connection portion 2143b may be greater than the width WT of the fourth contact hole CH4 in the first direction DR1. Since the length LT of the first side SD1 of the second connection portion 2143b is greater than the width WT of the fourth contact hole CH4 in the first direction DR1, the second connection portion 2143b may fill the entire fourth contact hole CH4.

[0099] In Figure 11In the exemplary embodiment shown, the second connection portion 2143b of the connection pattern 2143 may have a rectangular shape in a plan view, and the length LT of the first side SD1 of the second connection portion 2143b may be less than the distance DS4 in the first direction DR1 between the second side SD2 of the second connection portion 2143b and the vertex of the first connection portion 2143a. Thus, although the distances between the first line 141 and the connection pattern 2143 and between the second line 142 and the connection pattern 2143 are reduced due to an increase in the resolution of the display device, since the length LT of the first side SD1 of the second connection portion 2143b facing the side 141a of the first line 141 and the side 142a of the second line 142 is reduced, short circuit defects between the first line 141 and the connection pattern 2143 and between the second line 142 and the connection pattern 2143 can be prevented.

[0100] Although Figures 9 to 11 The exemplary embodiments shown illustrate specific shapes of the connection patterns 143, 1143, 2143, such as the rhombus shape of the first connection portion, but the exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the connection pattern may have other shapes, in which the first connection portion and / or the second connection portion have vertices located at the shortest distance from the first line to the connection pattern and / or vertices located at the shortest distance from the second line to the connection pattern, and the portions of the connection pattern between the vertices having the shortest distance and the adjacent vertices are respectively located farther from the first line or the second line than the vertices having the shortest distance to the first line or the second line. For example, in an exemplary embodiment, all other portions of the connection pattern may be located farther from the first line than the vertex having the shortest distance to the first line, and all other portions of the connection pattern may be located farther from the second line than the vertex having the shortest distance to the second line.

[0101] In an exemplary embodiment of the inventive concept, the display device may be applied to an electronic device, such as a computer, a laptop computer, a mobile phone, a smart phone, a smart tablet, a PMP, a PDA, or an MP3 player, etc. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0102] Although the display device according to the exemplary embodiment has been described with reference to the drawings, the illustrated embodiments are examples and can be modified and changed by those of ordinary skill in the relevant art without departing from the inventive concept.

Claims

1. A display device, wherein, The display device includes: a pixel circuit; a first line disposed on the pixel circuit and extending in a first direction; a second line disposed on the same layer as the first line and extending in the first direction, the second line being spaced apart from the first line in a second direction intersecting the first direction; a light-emitting element disposed on the first line and the second line; and a connection pattern disposed on the same layer as the first line and the second line and disposed between the first line and the second line in the second direction, the connection pattern directly contacting the light-emitting element and configured to connect the pixel circuit and the light-emitting element, the connection pattern having a polygonal shape including at least six sides, wherein a single first vertex of the connection pattern is located at the shortest distance from the first line, and all other portions of the connection pattern except the first vertex are located farther from the first line than the first vertex.

2. The display device according to claim 1, wherein, A second vertex of the connection pattern is located at the shortest distance from the second line, and a portion of the connection pattern between the second vertex and an adjacent vertex is located farther from the second line than the second vertex.

3. The display device according to claim 2, wherein, The connection pattern includes: a first connection portion connected to the light-emitting element; and a second connection portion connected to the pixel circuit, wherein the first connection portion has a rhombus shape.

4. The display device according to claim 3, wherein, The first connection portion includes the first vertex.

5. The display device according to claim 3, wherein, The first connection portion includes the second vertex.

6. The display device according to claim 3, wherein, The second connection portion has a rhombus shape, and wherein the second connection portion includes the second vertex.

7. The display device according to claim 3, wherein, The second connection portion has a rectangular shape.

8. The display device according to claim 1, wherein, The display device further includes: a first pixel and a second pixel spaced apart from each other in the second direction, wherein the first line is connected to the first pixel, and wherein the second line is connected to the second pixel.

9. The display device according to claim 1, wherein: the light-emitting element includes a first electrode, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer; and the connection pattern is connected to the first electrode.

10. A display device, wherein, The display device includes: a pixel circuit; a first line disposed on the pixel circuit and extending in a first direction; a second line disposed on the same layer as the first line and extending in the first direction, the second line being spaced apart from the first line in a second direction intersecting the first direction; a light-emitting element disposed on the first line and the second line; and a connection pattern disposed on the same layer as the first line and the second line and disposed between the first line and the second line in the second direction, the connection pattern including a first connection portion configured to connect the light-emitting element and a second connection portion configured to connect the pixel circuit, the first connection portion directly contacting the light-emitting element, Wherein, the first connecting portion has a rhombic shape in a plane defined by the first direction and the second direction, and sides of the rhombic shape of the first connecting portion are not parallel to the first line and the second line.

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