Display device including blocking pattern

Abstract

A display device is provided. The display device includes a substrate on which an active area and an inactive area are defined. The inactive area at least partially surrounds the active area. A light-emitting element is disposed in the active area on the substrate. An encapsulation layer is disposed on the light-emitting element. A blocking pattern is disposed in the inactive area on the substrate and at least partially surrounds the active area. The inactive area includes a first inactive area positioned on a first side of the active area and a second inactive area positioned on a second side of the active area. A greater number of blocking patterns are disposed in the first inactive area than in the second inactive area.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2019-0159957 filed on December 4, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device including a blocking pattern. Background Art

[0003] Electronic devices such as smartphones, tablet computers, digital cameras, laptop computers, notebook computers, navigation devices, and smart televisions include a display device for displaying images. The display device includes a display panel configured to generate and display images. The display device may also include one or more input devices such as a touch panel, camera sensor, etc.

[0004] Recently, in order to reduce the thickness of a display device and allow the display device to be bent or folded, a thin film encapsulation structure including a thin and flexible material may be applied as an encapsulation structure for sealing a light emitting element of a display panel.

[0005] Meanwhile, when forming the thin film encapsulation structure, a barrier pattern may be formed to control the reflow of the flexible material. Although a large number of barrier patterns can help control the reflow, the additional barrier patterns may increase the dead space of the display panel. Summary of the Invention

[0006] A display device includes a substrate defining an active area and an inactive area disposed around the active area. A light-emitting element is disposed in the active area on the substrate. An encapsulation layer is disposed on the light-emitting element. A blocking pattern is disposed in the inactive area on the substrate and surrounds the active area in a plan view. The inactive area includes a first inactive area positioned on a first side of the active area and a second inactive area positioned on a second side of the active area. The number of blocking patterns disposed in the first inactive area is greater than the number of blocking patterns disposed in the second inactive area.

[0007] A planar shape of the barrier pattern may be a closed curve.

[0008] The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer. The organic encapsulation layer may be disposed inside the barrier pattern.

[0009] The blocking pattern disposed in the first inactive area may include: a first blocking pattern; a second blocking pattern spaced apart from the active area, the first blocking pattern being positioned between the second blocking pattern and the active area; and a third blocking pattern spaced apart from the first blocking pattern, the second blocking pattern being positioned between the third blocking pattern and the first blocking pattern.

[0010] The barrier pattern disposed in the second non-active area may include a fourth barrier pattern and a fifth barrier pattern. The fifth barrier pattern may be spaced apart from the active area, and the fourth barrier pattern may be interposed between the fifth barrier pattern and the active area.

[0011] The first barrier pattern may be physically connected to the fourth barrier pattern, and the third barrier pattern may be physically connected to the fifth barrier pattern.

[0012] The second barrier pattern may be physically connected to the fourth barrier pattern.

[0013] The planar shape of the active area may be a rectangle with rounded corners, a pair of short sides, and a pair of long sides. The first inactive area may be disposed adjacent to one short side of the active area, and the second inactive area may be disposed adjacent to one long side of the active area.

[0014] The inactive region may further include a third inactive region disposed between the first and second inactive regions and adjacent to a rounded corner of the active region. The second and fourth barrier patterns may be physically connected to each other in the first or third inactive regions.

[0015] The first non-active area may further include a bent area. In a plan view, the bent area may be spaced apart from the active area, and the third barrier pattern may be interposed between the bent area and the active area.

[0016] In the bending region, the display device may be bent in a thickness direction thereof.

[0017] The third barrier pattern may have a first stacked structure in which the first organic layer is stacked on the substrate, the second organic layer is stacked on the first organic layer, and the third organic layer is stacked on the second organic layer. The first and second barrier patterns may each have a second stacked structure in which the second organic layer and the third organic layer are stacked.

[0018] The display device may further include a fourth organic layer disposed in the bent region on the substrate. The fourth organic layer may contact the substrate and may include the same material as that of the first organic layer.

[0019] The second barrier pattern may be physically connected to the fifth barrier pattern.

[0020] A surface height of the third barrier pattern may be greater than each of a surface height of the first barrier pattern and a surface height of the second barrier pattern.A surface height of the fifth barrier pattern may be greater than a surface height of the fourth barrier pattern.

[0021] The organic encapsulating layer may be disposed inside the third barrier pattern and inside the fifth barrier pattern.The first inorganic encapsulating layer may be in direct contact with the first barrier pattern, the second barrier pattern, and the third barrier pattern.

[0022] A display device includes a substrate defining an active area and an inactive area surrounding the active area. A light-emitting element is disposed in the active area on the substrate. An encapsulation layer is disposed on the light-emitting element. A blocking pattern is disposed in the inactive area on the substrate and surrounds the active area in a plan view. The inactive area includes a first inactive area positioned on a first side of the active area and a second inactive area positioned on a second side of the active area. The blocking pattern has a closed curve shape that completely surrounds the active area in a plan view. The number of blocking patterns disposed in the first inactive area is greater than the number of blocking patterns disposed in the second inactive area.

[0023] The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer located on the first inorganic encapsulation layer, and a second inorganic encapsulation layer located on the organic encapsulation layer. The organic encapsulation layer may be disposed inside the barrier pattern. The barrier pattern disposed in the first inactive region may include: a first barrier pattern; a second barrier pattern spaced apart from the active region, the first barrier pattern being positioned between the second barrier pattern and the active region; and a third barrier pattern spaced apart from the first barrier pattern, the second barrier pattern being positioned between the third barrier pattern and the first barrier pattern.

[0024] The barrier pattern disposed in the second inactive region may include a fourth barrier pattern and a fifth barrier pattern spaced apart from the active region, the fourth barrier pattern being disposed between the active region and the fifth barrier pattern. The first barrier pattern may be physically connected to the fourth barrier pattern. The third barrier pattern may be physically connected to the fifth barrier pattern.

[0025] The second barrier pattern may be physically connected to the fourth barrier pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0027] Figure 1 is a plan view showing a display device according to an exemplary embodiment of the present disclosure;

[0028] Figure 2is a schematic partial cross-sectional view showing a display device according to an exemplary embodiment of the present disclosure;

[0029] Figure 3 is a schematic cross-sectional view illustrating an exemplary stacking structure of a display panel according to an exemplary embodiment of the present disclosure;

[0030] Figure 4 is a plan view showing a display panel according to an exemplary embodiment of the present disclosure;

[0031] Figure 5 is a plan view illustrating a display panel including a blocking pattern and an encapsulation organic layer according to an exemplary embodiment of the present disclosure;

[0032] Figure 6 yes Figure 5 An enlarged view of region A;

[0033] Figure 7 It is along Figure 6 A sectional view taken along line II';

[0034] Figure 8 It is along Figure 6 A sectional view taken along line II-II';

[0035] Figure 9 yes Figure 8 an enlarged view of a portion of;

[0036] Figure 10 yes Figure 7 an enlarged view of a portion of;

[0037] Figures 11 to 14 It shows Figure 9 A view of a modified example of

[0038] Figure 15 is a plan view illustrating a display panel showing a blocking pattern and an encapsulation organic layer according to an exemplary embodiment of the present disclosure;

[0039] Figure 16 It shows Figure 15 An enlarged view of region B;

[0040] Figure 17 is a partial plan view showing a display panel according to an exemplary embodiment of the present disclosure;

[0041] Figure 18 It is along Figure 17 a cross-sectional view taken along line III-III'; and

[0042] Figures 19 to 21 It shows Figure 9 A view of the modified example. DETAILED DESCRIPTION

[0043] The specific structural and functional descriptions of the embodiments of the invention disclosed herein are provided for illustrative purposes only. The invention may be implemented in many different forms without departing from the spirit and salient features of the invention. Therefore, the embodiments of the invention are disclosed for illustrative purposes only and should not be necessarily construed as limiting the invention.

[0044] It will be understood that when an element is referred to as being related to another element, such as being "coupled" or "connected" to another element, the element can be directly coupled or connected to the other element, or intervening elements may be present between the element and the other element. Other expressions explaining the relationship between elements, such as "between," "directly between," "adjacent," or "directly adjacent," should be interpreted in the same manner.

[0045] Throughout the specification, the same reference numerals may refer to the same or like parts.

[0046] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not necessarily be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings herein.

[0047] The terms used herein are for the purpose of describing specific embodiments and are not necessarily intended to be restrictive. As used herein, "one", "one (kind / person)", "said (the)" and "at least one (kind / person)" do not represent the limitation of quantity, and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. For example, "element" and "at least one element" have the same meaning, unless the context clearly indicates otherwise. "At least one (kind / person)" should not be interpreted as limiting "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when the term "comprising" and / or its variations or "including" and / or its variations are used in this specification, it is explained that there are stated features, regions, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0048] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device in one of the accompanying drawings is turned over, the element described as being on the "lower" side of the other element would then be oriented on the "upper" side of the other element. Thus, the exemplary term "lower" can encompass both "lower" and "upper" orientations, depending on the specific orientation of the accompanying drawings. Similarly, if the device in one of the accompanying drawings is turned over, the element described as being "below" or "beneath" the other element would then be oriented "above" the other element. Thus, the exemplary terms "below" or "under" can encompass both "upper" and "lower" orientations.

[0049] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0050] Exemplary embodiments of the present disclosure are described herein with reference to schematically illustrated cross-sectional views as idealized embodiments. As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are anticipated. Therefore, the embodiments described herein should not necessarily be construed as being limited to the specific shapes of the regions shown herein, but rather will include deviations in shape due to, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. Additionally, sharp angles shown may be rounded (rounded).

[0051] Hereinafter, embodiments of the invention will be described with reference to the accompanying drawings.

[0052] Figure 1 is a plan view showing a display device according to an exemplary embodiment of the present disclosure, Figure 2 is a schematic partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure.

[0053] In an exemplary embodiment of the present disclosure, the first direction DR1 and the second direction DR2 are different directions and intersect each other. Figure 1In the plan view of FIG, for ease of description, the first direction DR1 is defined as a vertical direction, and the second direction DR2 is defined as a horizontal direction. In the following exemplary embodiments of the present disclosure, one side direction of the first direction DR1 refers to the upper direction in the plan view, and the other side direction of the first direction DR1 refers to the lower direction in the plan view. One side direction of the second direction DR2 refers to the right direction in the plan view, and the other side direction of the second direction DR2 refers to the left direction in the plan view. However, the directions mentioned in the exemplary embodiments of the present disclosure should be understood to refer to relative directions, and the exemplary embodiments of the present disclosure are not necessarily limited to the mentioned directions.

[0054] Reference Figure 1 and Figure 2 The display device 1 may refer to any electronic device provided with a display screen. For example, the display device 1 may include a portable electronic device provided with a display screen, such as a mobile phone, a smartphone, a tablet computer, an electronic watch, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book (e-book) reader, a portable multimedia player (PMP), a navigation device, a game console, or a digital camera, and may also include a television, a laptop computer or notebook computer, a monitor, an electronic billboard, or a device for the Internet of Things (IoT).

[0055] The display device 1 may include a display area in which a screen is displayed and a non-display area in which the screen is not displayed. In terms of the display screen, an active area AAR including the display area and a non-active area NAR including the non-display area may be defined in the display device 1. The non-active area NAR may be positioned around the active area AAR. In a plan view, the non-active area NAR may at least partially surround the active area AAR. In an exemplary embodiment of the present disclosure, in a plan view, the non-active area NAR may completely surround the active area AAR.

[0056] The planar shape of the active area AAR may include a rectangle with rounded corners. For example, the outer contour of the active area AAR may include a short side positioned in one direction of the first direction DR1, another short side positioned in the other direction of the first direction DR1, a long side positioned in the one direction of the second direction DR2, and another long side positioned in the other direction of the second direction DR2. The rounded corners may be positioned between the short side and the long side, between the short side and the long side, between the short side and the long side, and between the short side and the long side. The short side of the active area AAR may extend primarily in the second direction DR2, and the long side of the active area AAR may extend primarily in the first direction DR1. In this specification, the phrase "rounded corners" should be understood to include not only corners having a constant or variable curvature, but also corners formed not by two intersecting straight lines, but instead by extending multiple straight lines having different inclinations (different extension directions).

[0057] However, the planar shape of the effective area AAR is not necessarily limited thereto. Hereinafter, a case where a rectangle with rounded corners is applied as the planar shape of the effective area AAR will be mainly described.

[0058] The non-active area NAR completely surrounding the active area AAR may surround short sides, long sides, and rounded corners of the active area AAR.

[0059] In some exemplary embodiments of the present disclosure, the active area AAR may include a touch area in which a touch input is sensed, and the non-active area NAR may include a non-touch area in which a touch is not sensed but which helps sense a touch.

[0060] In some exemplary embodiments of the present disclosure, the active area AAR may be the same area as the display area and the touch area, and the non-active area NAR may be the same area as the non-display area and the non-touch area.

[0061] In some exemplary embodiments of the present disclosure, the non-active region NAR may partially include the display region. For example, the non-active region NAR may be a region in which the display region and the non-display region are mixed.

[0062] A plurality of pixels may be defined in the active area AAR. Each of the plurality of pixels may include at least one thin film transistor and a light emitting element electrically connected to the thin film transistor. For example, the thin film transistor and the light emitting element may be disposed in the active area AAR.

[0063] A signal line and a signal pad (also referred to as a "pad") for applying an electrical signal to each pixel may be provided in the non-active region NAR. The signal pad is connected to the signal line, and an external device configured to apply an electrical signal is attached to the signal pad. A driving circuit may further be provided in the non-active region NAR.

[0064] The display device 1 includes a display panel 10 provided with a display screen. Examples of the display panel 10 may include an organic light-emitting diode (OLED) display panel, a micro-light-emitting diode (LED) display panel, a nano-LED display panel, a quantum dot light-emitting display panel, a liquid crystal display (LCD) panel, a plasma display panel, a field emission display panel, an electrophoretic display panel, an electrowetting display panel, and the like. Hereinafter, although an example in which an organic light-emitting display panel is applied as an example of the display panel 10 is described, the present disclosure is not necessarily limited thereto, and devices to which the same technical spirit is applicable may be applied to other display panels.

[0065] The display device 1 may further include a touch member for sensing touch input. The touch member may be provided as a panel or film that is separate from and attached to the display panel 10, or may be provided in the form of a touch layer inside the display panel 10. In the following exemplary embodiments of the present disclosure, a case where the touch member is provided inside the display panel so as to be included in the display panel 10 will be described, but the present disclosure is not necessarily limited thereto.

[0066] The display panel 10 may include a flexible substrate comprising a flexible polymer material such as polyimide. Thus, the display panel 10 may be flexible, bendable, foldable, or rollable. As used herein, the term "flexible" is understood to mean having the ability to bend to a non-trivial degree without breaking or rupturing, the term "bendable" is understood to mean having the ability to bend to a non-trivial degree without breaking or rupture, the term "foldable" is understood to mean having the ability to fold to a non-trivial degree without breaking or rupture, and the term "rollable" is understood to mean having the ability to curl to a non-trivial degree without breaking or rupture. As used herein, the term "non-trivial degree" is understood to mean a degree that can be easily observed with the naked eye and can be easily understood to constitute bending, bending, folding, curling, etc.

[0067] A bending region BR as a region where the panel is bent may be defined in the display panel 10. With respect to the bending region BR, a main region MR positioned at one side of the bending region BR and a sub-region SR positioned at the other side of the bending region BR may be further defined in the display panel 10.

[0068] The main region MR may have a shape substantially similar to the shape of the outside of the plane of the display device 1. The main region MR may be a flat region positioned on one surface. However, the present disclosure is not necessarily limited thereto, and in the main region MR, at least one of the remaining edges other than the edge (side) connected to the bending region BR may be bent to form a curved surface or may be bent in a vertical direction.

[0069] When at least one of the remaining edges of the main region MR, excluding the edge (side) connected to the bending region BR, forms a curved surface or is curved, the display area can even be provided at the corresponding edge. However, the present disclosure is not necessarily limited thereto, and the curved surface or curved edge may become a non-display area in which no pixels are provided and no image is displayed, or the display area and the non-display area may be mixed in the corresponding area.

[0070] The bending region BR is connected to one side of the main region MR in the first direction DR1. For example, the bending region BR may be connected via the lower short side of the main region MR. The width of the bending region BR may be smaller than the width of the main region MR (the width of the short side). The connection portion between the main region MR and the bending region BR may have an L-shaped cut shape.

[0071] In the bending region BR, the display panel 10 can be bent with a certain curvature facing downward in its thickness direction (for example, in the direction opposite to the display surface). The bending region BR can have a constant radius of curvature, but the present disclosure is not necessarily limited thereto. The bending region BR can have a different radius of curvature for each portion. When the display panel 10 is bent in the bending region BR, the surface of the display panel 10 can be reversed. For example, one surface of the display panel 10 facing upward can be changed to face outward and then face downward by the bending region BR.

[0072] The sub-region SR extends from the bending region BR. For example, the sub-region SR contacts the bending region BR. The sub-region SR may extend primarily in a direction parallel to the main region MR after the bending of the bending region BR is completed. The sub-region SR may at least partially overlap with the main region MR in the thickness direction of the display panel 10. The width of the sub-region SR (the width in the second direction DR2) may be the same as the width of the bending region BR, but the present disclosure is not necessarily limited to this.

[0073] The first pad part PA1 (see Figure 5 ) and the second pad portion PA2 (see Figure 5) may be disposed in the sub-region SR. The first pad portion PA1 may be positioned closer to the active area AAR than the second pad portion PA2. The first pad portion PA1 may be disposed between the active area AAR and the second pad portion PA2. The first driver chip 20 may be disposed in the first pad portion PA1. The first driver chip 20 may include an integrated circuit configured to drive the display panel 10. The integrated circuit may include an integrated circuit for driving / controlling the display and / or an integrated circuit for driving / controlling the touch unit. The integrated circuit for driving / controlling the display and the integrated circuit for driving / controlling the touch unit may be provided as separate chips or may be provided as parts of one chip.

[0074] The second pad portion PA2 may be provided at an end portion of the sub-region SR of the display panel 10. The second pad portion PA2 may include a plurality of display signal line pads and a plurality of touch signal line pads. The drive substrate 30 may be connected to the second pad portion PA2 at an end portion of the sub-region SR in the display panel 10. The drive substrate 30 may be a flexible printed circuit board or film. A second drive chip 35 may be provided on the drive substrate 30.

[0075] The main region MR may at least partially overlap the active area AAR and a portion of the non-active area NAR adjacent to the active area AAR. For example, the main region MR may include the active area AAR and a portion of the non-active area NAR adjacent to the active area AAR.

[0076] The non-active region NAR may at least partially overlap each of the bending region BR and the sub-region SR. For example, the non-active region NAR may include the bending region BR and the sub-region SR.

[0077] Figure 3 is a schematic cross-sectional view illustrating an exemplary stack structure of a display panel according to an exemplary embodiment of the present disclosure.

[0078] Reference Figure 3 The display panel 10 may include a substrate SUB (see Figure 7 The circuit driving layer DRL on the pixel 101 may include a circuit for driving the light emitting layer EML of the pixel. The circuit driving layer DRL may include a plurality of thin film transistors.

[0079] The light emitting layer EML may be disposed on the circuit driving layer DRL. The light emitting layer EML may include an organic light emitting layer. The light emitting layer EML may emit light at various levels of brightness according to a driving signal transmitted from the circuit driving layer DRL.

[0080] The encapsulation layer ENL may be provided on the light emitting layer EML. The encapsulation layer ENL may include an inorganic film or a stacked film of an inorganic film and an organic film. In an example, glass or an encapsulation film may be applied as the encapsulation layer ENL.

[0081] The touch layer TSL may be provided on the encapsulation layer ENL. The touch layer TSL may be a layer that senses touch input and may perform the function of a touch member. The touch layer TSL may include touch electrodes. For example, the touch electrodes may be in a grid pattern or a plane pattern. In the case where the touch electrodes are in a grid pattern, even when the touch electrodes include an opaque conductive material, the grid pattern may at least partially overlap with the non-emitting area (defined by the embankment layer), and therefore, the touch electrodes may not be visible. In the case where the touch electrodes are in a plane pattern, the touch electrodes may include a transparent conductive material.

[0082] The polarizing layer POL may be disposed on the touch layer TSL. The polarizing layer POL may be used to reduce external light reflection. The polarizing layer POL may be attached to the light blocking pattern layer (not shown) via an adhesive layer. The polarizing layer POL may be omitted.

[0083] The protective layer WDL may be disposed on the polarizing layer POL. The protective layer WDL may include, for example, a window member. The protective layer WDL may be attached to the polarizing layer POL by an optically transparent adhesive or the like.

[0084] In some exemplary embodiments of the present disclosure, the polarization layer POL may be omitted, and a color filter layer may be provided on the touch layer TSL. In this case, the color filter layer may be provided between the touch layer TSL and the protection layer WDL.

[0085] The following will refer to Figure 7 and Figure 8 Describe the detailed stacking structure of the display panel.

[0086] Figure 4 is a plan view illustrating a display panel according to an exemplary embodiment of the present disclosure.

[0087] Reference Figure 4 The short sides, long sides, and corners of the outer contour of the active area AAR may be demarcated by first to fourth reference lines CL1 to CL4. Each of the first and second reference lines CL1 and CL2 may extend primarily in the first direction DR1, and each of the third and fourth reference lines CL3 and CL4 may extend primarily in the second direction DR2. The first reference line CL1 may be located on the left side of the drawing, the second reference line CL2 may be located on the right side of the drawing, the third reference line CL3 may be located on the upper side of the drawing, and the fourth reference line CL4 may be located on the lower side of the drawing.

[0088] One short side of the outer contour of the active area AAR may be positioned between the first reference line CL1 and the second reference line CL2, and may be positioned above the third reference line CL3. The other short side of the outer contour of the active area AAR may be positioned between the first reference line CL1 and the second reference line CL2, and may be positioned below the fourth reference line CL4. One long side of the outer contour of the active area AAR may be positioned between the third reference line CL3 and the fourth reference line CL4, and may be positioned to the right of the second reference line CL2. The other long side of the outer contour of the active area AAR may be positioned between the third reference line CL3 and the fourth reference line CL4, and may be positioned to the left of the first reference line CL1.

[0089] The first corner of the active area AAR may be divided by the first reference line CL1 and the third reference line CL3 and may be positioned between the one short side and the other long side of the outer contour of the active area AAR. The second corner of the active area AAR may be divided by the second reference line CL2 and the third reference line CL3 and may be positioned between the one short side and the one long side of the outer contour of the active area AAR. The third corner of the active area AAR may be divided by the first reference line CL1 and the fourth reference line CL4 and may be positioned between the other short side and the other long side of the outer contour of the active area AAR. The fourth corner of the active area AAR may be divided by the second reference line CL2 and the fourth reference line CL4 and may be positioned between the other short side and the one long side of the outer contour of the active area AAR.

[0090] The non-active area NAR may include a plurality of areas divided according to positions relative to the active area AAR. The non-active area NAR may include first to eighth non-active areas NAR1 to NAR8.

[0091] The first non-active area NAR1 may be disposed adjacent to the one short side of the outer contour of the active area AAR, and the second non-active area NAR2 may be disposed adjacent to the other long side of the outer contour of the active area AAR. The third non-active area NAR3 may be disposed adjacent to the one long side of the outer contour of the active area AAR, and the fourth non-active area NAR4 may be disposed adjacent to the other short side of the outer contour of the active area AAR. The fifth non-active area NAR5 may be disposed adjacent to a first corner of the outer contour of the active area AAR, and the sixth non-active area NAR6 may be disposed adjacent to a second corner of the outer contour of the active area AAR. The seventh non-active area NAR7 may be disposed adjacent to a third corner of the outer contour of the active area AAR, and the eighth non-active area NAR8 may be disposed adjacent to a fourth corner of the outer contour of the active area AAR.

[0092] like Figure 4 As shown in , the width of the fourth non-active region NAR4 (the width in the first direction DR1) may be greater than each of the width of the first non-active region NAR1 (the width in the first direction DR1), the width of the second non-active region NAR2 (the width in the second direction DR2), and the width of the third non-active region NAR3 (the width in the second direction DR2). For example, the width of the fourth non-active region NAR4 (the width in the first direction DR1) may be designed to be greater than each of the width of the first non-active region NAR1 (the width in the first direction DR1), the width of the second non-active region NAR2 (the width in the second direction DR2), and the width of the third non-active region NAR3 (the width in the second direction DR2).

[0093] Figure 5 is a plan view illustrating a display panel showing a blocking pattern and an encapsulation organic layer according to an exemplary embodiment of the present disclosure, Figure 6 yes Figure 5 Magnified view of area A.

[0094] Reference Figure 5 and Figure 6 , the display panel 10 may include a plurality of blocking patterns and an encapsulation layer (see Figure 3 "ENL" and Figure 7 "180") of the encapsulation organic layer 182.

[0095] The encapsulation organic layer 182 may be provided in part of the non-active region NAR and the active region AAR. For example, the encapsulation organic layer 182 may be provided not only in the active region AAR but also in parts of the first to eighth non-active regions NAR1 to NAR8 adjacent to the active region AAR.

[0096] The plurality of barrier patterns may completely surround the active area AAR in a plan view. For example, the plurality of barrier patterns may form a closed curve completely surrounding the active area AAR in a plan view. For example, each of the plurality of barrier patterns may limit the active area AAR.

[0097] The plurality of barrier patterns forming a closed curve may completely surround the encapsulation organic layer 182 in a plan view. Figure 7 After forming the first encapsulation inorganic layer 181, an encapsulation organic layer material is formed on the first encapsulation inorganic layer 181. In this case, the encapsulation organic layer material can flow back in the outward direction of the display panel 10 (the direction from the active area AAR to the non-active area NAR). The plurality of barrier patterns can form a closed curve that completely surrounds the encapsulation organic layer material in a plan view, thereby reducing the outward flow of the encapsulation organic layer material in the display panel 10.

[0098] Increasing the number or height of the blocking patterns can appropriately mitigate the reflow of the encapsulated organic layer material. However, increasing the height of the blocking patterns to mitigate the reflow of the encapsulated organic layer material increases the overall thickness of the display device 1, which is detrimental to thinning the display device 1. Therefore, increasing the number of blocking patterns can be considered.

[0099] However, since the blocking patterns are arranged in the non-active region NAR, as the number of blocking patterns increases, the width of the non-active region NAR in which the corresponding blocking patterns are arranged increases. Therefore, the area in which the screen is not displayed increases significantly, resulting in an increase in ineffective space.

[0100] As mentioned above Figure 4 As described, according to an exemplary embodiment of the present disclosure, the width of the fourth non-active region NAR4 (the width in the first direction DR1) can be designed to be larger than each of the width of the first non-active region NAR1 (the width in the first direction DR1), the width of the second non-active region NAR2 (the width in the second direction DR2), and the width of the third non-active region NAR3 (the width in the second direction DR2).

[0101] Therefore, in terms of alleviating the backflow of the encapsulated organic layer material and in terms of reducing the invalid space, the following method may be first considered: further increasing the number of blocking patterns in the fourth non-active area NAR4 having a relatively wide free space for increasing the number of blocking patterns, thereby alleviating the backflow of the encapsulated organic layer material in at least the fourth non-active area NAR4.

[0102] In the display panel 10 according to an exemplary embodiment of the present disclosure, the number of blocking patterns provided in the fourth non-active area NAR4 may be different from the number of blocking patterns provided in the first to third non-active areas NAR1 to NAR3. The number of blocking patterns provided in the fourth non-active area NAR4 may be greater than the number of blocking patterns provided in the first to third non-active areas NAR1 to NAR3.

[0103] A first barrier pattern DAM1 closest to the encapsulation organic layer 182, a second barrier pattern DAM2 spaced apart from the active area AAR with the first barrier pattern DAM1 interposed therebetween, and a third barrier pattern DAM3 spaced apart from the first barrier pattern DAM1 with the second barrier pattern DAM2 interposed therebetween may be disposed in the fourth non-active area NAR4. The barrier patterns DAM1, DAM2, and DAM3 may have a substantially linear shape extending in the second direction DR2.

[0104] The fourth barrier pattern DAM4 closest to the encapsulation organic layer 182 and the fifth barrier pattern DAM5 spaced apart from the active area AAR with the fourth barrier pattern DAM4 interposed therebetween may be disposed in the first to third non-active areas NAR1 to NAR3. Each of the fourth barrier pattern DAM4 and the fifth barrier pattern DAM5 may extend along the first direction DR1 mainly in the second non-active area NAR2, extend along the second direction DR2 mainly in the first non-active area NAR1, and extend along the first direction DR1 again mainly in the third non-active area NAR3.

[0105] As described above, since the plurality of blocking patterns of the display panel 10 form a closed curve surrounding the active area AAR in a plan view, all of the first to third blocking patterns DAM1 to DAM3 of the fourth non-active area NAR4 should be connected to at least one of the fourth and fifth blocking patterns DAM4 and DAM5 of the first to third non-active areas NAR1 to NAR3.

[0106] According to an exemplary embodiment of the present disclosure, the first barrier pattern DAM1 may be physically connected to the fourth barrier pattern DAM4 , the second barrier pattern DAM2 may be physically connected to the fourth barrier pattern DAM4 , and the third barrier pattern DAM3 may be physically connected to the fifth barrier pattern DAM5 .

[0107] The connection between the second barrier pattern DAM2 and the fourth barrier pattern DAM4 of the third non-active region NAR3 may be formed in the fourth non-active region NAR4 or the eighth non-active region NAR8, and may not be formed in the third non-active region NAR3. As described above, this is because, since the invalid space of the third non-active region NAR3 is narrowly designed, when the connection between the second barrier pattern DAM2 and the fourth barrier pattern DAM4 is formed in the third non-active region NAR3, the narrowly designed invalid space of the third non-active region NAR3 may increase.

[0108] Similarly, the connection between the second barrier pattern DAM2 and the fourth barrier pattern DAM4 of the second non-active region NAR2 may be made in the fourth non-active region NAR4 or the seventh non-active region NAR7 , and may not be made in the second non-active region NAR2 .

[0109] When each of the connections between the second barrier pattern DAM2 and the fourth barrier pattern DAM4 of the third non-active area NAR3 and the connections between the second barrier pattern DAM2 and the fourth barrier pattern DAM4 of the second non-active area NAR2 are made in the fourth non-active area NAR4, it can be considered that the fourth barrier pattern DAM4 is further set in the entirety of the seventh non-active area NAR7 and the eighth non-active area NAR8 from the connection portion between the second barrier pattern DAM2 and the fourth barrier pattern DAM4 in the fourth non-active area NAR4.

[0110] When each of the connections between the second barrier pattern DAM2 and the fourth barrier pattern DAM4 of the third non-active area NAR3 and the connections between the second barrier pattern DAM2 and the fourth barrier pattern DAM4 of the second non-active area NAR2 are made in the seventh non-active area NAR7 and the eighth non-active area NAR8, it can be considered that the fourth barrier pattern DAM4 is further set in the remaining portion of the seventh non-active area NAR7 and the remaining portion of the eighth non-active area NAR8 from the connection portion between the second barrier pattern DAM2 and the fourth barrier pattern DAM4 in the seventh non-active area NAR7 and the eighth non-active area NAR8.

[0111] The above-described first pad portion PA1 and second pad portion PA2 may be disposed in the sub-region SR.

[0112] Hereinafter, a detailed cross-sectional structure of the display panel 10 will be described.

[0113] Figure 7 It is along Figure 6 A cross-sectional view taken along line II' of Figure 8 It is along Figure 6 A sectional view taken along line II-II'.

[0114] Reference Figure 7 and Figure 8 The display panel 10 may include a substrate 101, buffer layers 102 and 103, insulating layers GI1, GI2, IL1, VIA1, and VIA2, a bank layer PDL, a conductive layer, an organic layer OL, an encapsulation layer 180, and barrier patterns DAM1, DAM2, DAM3, DAM4, and DAM5.

[0115] The substrate 101 may include a flexible organic material. Although not shown, the substrate 101 may include a plurality of stacked films.

[0116] The first buffer layer 102 and the second buffer layer 103 may be sequentially disposed on the substrate 101. The buffer layers 102 and 103 may each include an inorganic material. Examples of the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, and the like. For example, the first buffer layer 102 may include silicon nitride, and the second buffer layer 103 may include silicon oxide, but the present disclosure is not necessarily limited thereto.

[0117] The semiconductor layer ACT may be disposed on the second buffer layer 103. The semiconductor layer ACT may be disposed in the active area AAR. In some exemplary embodiments of the present disclosure, the semiconductor layer ACT may also be disposed in the non-active area NAR3 (or see FIG. 1 ) in which the above-mentioned driving circuit is disposed. Figure 5 in "NAR2").

[0118] The first gate insulating layer GI1 may be disposed on the semiconductor layer ACT. The first gate insulating layer GI1 may at least partially cover the semiconductor layer ACT. The first gate insulating layer GI1 may include an inorganic material. Examples of the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, and the like.

[0119] The gate electrode or driving circuit of the thin film transistor can be disposed on the first gate insulating layer GI1. Figure 7 , the gate electrode GE of the thin film transistor is shown.

[0120] The semiconductor layer ACT may include a channel region at least partially overlapping the gate electrode GE.

[0121] A plurality of first data link lines DSL1 disposed in the fourth non-active region NAR4 may be disposed on the first gate insulating layer GI1. The first data link lines DSL1 may be disposed in the first pad portion PA1 and may be disposed between the bending region BR and the active region AAR. The first data link lines DSL1 disposed in the first pad portion PA1 may be electrically connected to the first data link lines DSL1 disposed between the bending region BR and the active region AAR. The first data link lines DSL1 disposed in the first pad portion PA1 may be electrically connected to the first pad PAD1.

[0122] The first data link line DSL1 and the gate electrode GE may be formed through the same process and may include the same material.

[0123] The gate electrode GE may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The gate electrode GE may be a single film made of at least one selected from the above materials. The present disclosure is not necessarily limited thereto, and the gate electrode GE may be a stacked film.

[0124] A second gate insulating layer GI2 may be disposed on the gate electrode GE. The second gate insulating layer GI2 may insulate the gate electrode GE from the source electrode SE and the drain electrode DE (described below). Furthermore, the second gate insulating layer GI2 may insulate the first data link line DSL1 from the second data link line DSL2. The second gate insulating layer GI2 may be exposed at the first pad portion PA1, so that the first data link line DSL1 and the first pad PAD1 may be in electrical contact with each other.

[0125] The second gate insulating layer GI2 may include at least one selected from among the above-mentioned materials of the first gate insulating layer GI1 .

[0126] The second data link line DSL2 may be disposed on the second gate insulating layer GI2. The second data link line DSL2 may be disposed between the bending region BR and the active region AAR. Although not shown, the second data link line DSL2 may be electrically connected to the first data link line DSL1 disposed in the first pad portion PA1.

[0127] The second data link line DSL2 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second data link line DSL2 may be a single film made of at least one selected from the above materials. The present disclosure is not necessarily limited to this, and the second data link line DSL2 may be a stacked film.

[0128] The first insulating layer IL1 may be disposed on the second data link line DSL2. The first insulating layer IL1 may expose an upper surface of the first data link line DSL1 in the first pad portion PA1 like the second gate insulating layer GI2.

[0129] The first insulating layer IL1 may include an inorganic material, and examples of the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, and the like.

[0130] The source electrode SE and the drain electrode DE may be disposed on the first insulating layer IL1. The source electrode SE and the drain electrode DE may be disposed in the active area AAR. The source electrode SE and the drain electrode DE may be electrically connected to the semiconductor layer ACT through the first insulating layer IL1 and the gate insulating layers GI1 and GI2 through exposed contact holes.

[0131] The source electrode SE, the drain electrode DE, the gate electrode GE, and the semiconductor layer ACT may together constitute a thin film transistor. The source electrode SE and the drain electrode DE may both be disposed in the active area AAR.

[0132] The low voltage supply line ELVSS and the high voltage supply line ELVDD may each be further disposed between the active area AAR and the bending area BR. The low voltage supply line ELVSS may also be disposed in the third non-active area NAR3. Each of the low voltage supply line ELVSS and the high voltage supply line ELVDD may be coplanar with the source electrode SE, may be formed by the same process as the source electrode SE, and may include the same material as the source electrode SE.

[0133] The first pad PAD1 may be disposed in each of the pad portions PA1 and PA2 . The first pad PAD1 may be coplanar with the source electrode SE, may be formed by the same process as that of the source electrode SE, and may include the same material as that of the source electrode SE.

[0134] The first pad PAD1 disposed in the first pad portion PA1 may be electrically connected to the first data link line DSL1 .

[0135] The source electrode SE and the drain electrode DE may each include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The source electrode SE and the drain electrode DE may each be a single film made of at least one selected from the above materials. The present disclosure is not necessarily limited thereto, and the source electrode SE and the drain electrode DE may each be a stacked film.

[0136] The first via layer VIA1 may be disposed on the source electrode SE, the drain electrode DE, the voltage supply lines ELVSS and ELVDD, and the first pad PAD1. The first via layer VIA1 disposed in the second pad portion PA2 may expose an upper surface of the first pad PAD1.

[0137] The first via layer VIA1 disposed in the fourth non-active region NAR4 between the bending region BR and the active region AAR may be directly disposed on the first insulating layer IL1 and may constitute a third barrier pattern DAM3.

[0138] In addition, the first via layer VIA1 disposed in the third non-active region NAR3 may constitute a fifth barrier pattern DAM5 .

[0139] Meanwhile, the first via layer VIA1 disposed in the bending region BR may be in direct contact with the substrate 101. For example, in the bending region BR, the first insulating layer IL1, the gate insulating layers GI1 and GI2, and the buffer layers 102 and 103 may all be removed, thereby exposing the upper surface of the substrate 101. The first via layer VIA1 may be in direct contact with the exposed upper surface of the substrate 101.

[0140] The first via layer VIA1 may include an organic insulating material such as polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0141] The first connection electrode CE1, the second connection electrode CE2, the fifth connection electrode CE5, the sixth connection electrode CE6, and the seventh connection electrode CE7 may be disposed on the first via layer VIA1. The first connection electrode CE1, the second connection electrode CE2, the fifth connection electrode CE5, the sixth connection electrode CE6, and the seventh connection electrode CE7 may all be disposed on the same layer, may all be formed by the same process, and may all include the same material.

[0142] The first connection electrode CE1 may be electrically connected to the drain electrode DE exposed by the first via layer VIA1 in the active area AAR.

[0143] The second link electrode CE2 may be electrically connected to the low voltage supply line ELVSS exposed by the first via layer VIA1 in the third non-active region NAR3 .

[0144] The fifth link electrode CE5 may be electrically connected to the high voltage supply line ELVDD and the sixth link electrode CE6 may be electrically connected to the low voltage supply line ELVSS exposed by the first via layer VIA1 between the bending region BR and the active region AAR.

[0145] The first via layer VIA1 may be exposed between the bending region BR and the active area AAR (e.g., between the third barrier pattern DAM3 and the low voltage supply line ELVSS, e.g., a region in which the first barrier pattern DAM1 and the second barrier pattern DAM2, which will be described below, are disposed). The sixth link electrode CE6 may be in direct contact with the first insulating layer IL1 in the region in which the first via layer VIA1 is exposed.

[0146] The seventh connection electrode CE7 may be disposed on the first via layer VIA1 in the bending region BR. Although not shown, the seventh connection electrode CE7 may be used to electrically connect the first data link line DSL1 in the first pad portion PA1 and the first data link line DSL1 or the second data link line DSL2 between the bending region BR and the active area AAR.

[0147] The second pad PAD2 may be further provided in the pad portions PA1 and PA2. The second pad PAD2 may be coplanar with the first connection electrode CE1, may be formed by the same process as that of the first connection electrode CE1, and may include the same material as that of the first connection electrode CE1.

[0148] The second pad PAD2 may be electrically connected to the first pad PAD1 in the pad portions PA1 and PA2 .

[0149] There may be a first connection electrode CE1, a second connection electrode CE2, a fifth connection electrode CE5, a sixth connection electrode CE6, and a seventh connection electrode CE7. The first connection electrode CE1, the second connection electrode CE2, the fifth connection electrode CE5, the sixth connection electrode CE6, and the seventh connection electrode CE7 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). There may be a first connection electrode CE1, a second connection electrode CE2, a fifth connection electrode CE5, a sixth connection electrode CE6, and a seventh connection electrode CE7. The first connection electrode CE1, the second connection electrode CE2, the fifth connection electrode CE5, the sixth connection electrode CE6, and the seventh connection electrode CE7 may each be a single film made of at least one selected from the above materials. The present disclosure is not necessarily limited thereto, and there may be first, second, fifth, sixth, and seventh connection electrodes CE1, CE2, CE5, CE6, and CE7. Each of the first, second, fifth, sixth, and seventh connection electrodes CE1, CE2, CE5, CE6, and CE7 may be a stacked film.

[0150] There may be first, second, fifth, sixth, and seventh connection electrodes CE1, CE2, CE5, CE6, and CE7. A second via layer VIA2 may be provided on the first, second, fifth, sixth, and seventh connection electrodes CE1, CE2, CE5, CE6, and CE7, and the second pad PAD2.

[0151] The second via layer VIA2 may expose an upper surface of the first link electrode CE1 in the active area AAR, and the exposed first link electrode CE1 may be electrically connected to an anode electrode ANO to be described below.

[0152] The second via layer VIA2 may be disposed on the second connection electrode CE2 in the third non-active region NAR3 and may at least partially overlap the second connection electrode CE2. The second via layer VIA2 at least partially overlapping the second connection electrode CE2 may constitute a fourth barrier pattern DAM4.

[0153] The second via layer VIA2 may be further disposed on the first via layer VIA1 constituting the fifth barrier pattern DAM5 in the third non-active area NAR3 to at least partially overlap the corresponding first via layer VIA1. The second via layer VIA2 at least partially overlapping the corresponding first via layer VIA1 may constitute the fifth barrier pattern DAM5.

[0154] The second via layer VIA2 may be further disposed on the first via layer VIA1 constituting the third barrier pattern DAM3 in the fourth non-active region NAR4 to at least partially overlap the corresponding first via layer VIA1. The corresponding second via layer VIA2 may constitute the third barrier pattern DAM3.

[0155] The second via layer VIA2 can form each of the first blocking pattern DAM1 and the second blocking pattern DAM2 on the sixth connection electrode CE6 that is in direct contact with the first insulating layer IL1 in an area of ​​the fourth non-active area NAR4 exposed between the bending area BR and the active area AAR (for example, between the third blocking pattern DAM3 and the low voltage supply line ELVSS, for example, an area in which the first blocking pattern DAM1 and the second blocking pattern DAM2 described below are provided).

[0156] The second via layer VIA2 constituting each of the barrier patterns DAM3 and DAM5 may cover not only an upper surface of the first via layer VIA1 at least partially overlapping the second via layer VIA2 , but also side surfaces of the first via layer VIA1 .

[0157] The second via layer VIA2 may expose an upper surface of the second pad PAD2 in the second pad portion PA2 .

[0158] In the bending region BR, the second via layer VIA2 may cover the seventh connection electrode CE7 and may be in direct contact with the first via layer VIA1 exposed by the seventh connection electrode CE7 .

[0159] The anode ANO can be arranged on the second via layer VIA2. The anode ANO can be a pixel electrode set for each pixel. The anode ANO can have a stacked film structure formed by stacking a material layer with a high work function and a reflective material layer, wherein the material layer with a high work function is made of one selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and indium oxide (In2O3), and the reflective material layer is made of one selected from silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) and a mixture thereof. The material layer with a high work function can be arranged on the reflective material layer and can be arranged close to the light-emitting layer EML. The anode ANO can have a multilayer structure of ITO / Mg, ITO / MgF2, ITO / Ag or ITO / Ag / ITO, but the present disclosure is not necessarily limited thereto.

[0160] The connection electrodes CE3 and CE4 may be further disposed on the second via layer VIA2 in the third non-active region NAR3 . The connection electrodes CE3 and CE4 may be coplanar with the anode ANO and may be formed by the same process and include the same material as that of the anode ANO.

[0161] The fourth connection electrode CE4 may be disposed between the fifth and fourth barrier patterns DAM5 and DAM4 and may partially cover upper surfaces of the fifth and fourth barrier patterns DAM5 and DAM4.

[0162] The third link electrode CE3 may be disposed between the fourth barrier pattern DAM4 and the adjacent second via layer VIA2. Each of the third and fourth link electrodes CE3 and CE4 may be in direct contact with an upper surface of the low voltage supply line ELVSS.

[0163] The bank layer PDL may be provided on the substrate 101. The bank layer PDL may be provided on the anode ANO and may have an opening exposing the anode ANO. The emission region and the non-emission region may be divided by the bank layer PDL and the opening of the bank layer PDL. The bank layer PDL may include an organic insulating material such as a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or BCB. The bank layer PDL may include an inorganic material.

[0164] The bank layer PDL may at least partially overlap the second via layer VIA2 constituting the fourth barrier pattern DAM4 to constitute the fourth barrier pattern DAM4.

[0165] The bank layer PDL may at least partially overlap the second via layer VIA2 constituting the fifth barrier pattern DAM5 to constitute the fifth barrier pattern DAM5 .

[0166] The bank layer PDL may at least partially overlap the second via layer VIA2 constituting the first to third barrier patterns DAM1 to DAM3 to constitute the first to third barrier patterns DAM1 to DAM3 .

[0167] The bank layer PDL may at least partially overlap the second via layer VIA2 in the bending region BR.

[0168] The spacer SPC may be disposed on the bank layer PDL.The spacer SPC may be disposed on the bank layer PDL constituting the fourth and fifth barrier patterns DAM4 and DAM5 to constitute each of the fourth and fifth barrier patterns DAM4 and DAM5.

[0169] The spacer SPC may at least partially overlap the bank layer PDL in the bending region BR.

[0170] The spacer SPC may include a material different from that of the underlying bank layer PDL. In some exemplary embodiments of the present disclosure, the spacer SPC and the underlying bank layer PDL may include the same material and may be formed using the same process. For example, after depositing the bank layer material, a slit mask or a halftone mask may be used to mask the bank layer material, and then exposure and development may be performed to form the bank layer PDL and the spacer SPC. A slit mask or a halftone mask may not be used, and exposure and development may be performed to form the bank layer PDL without the spacer SPC disposed thereon.

[0171] The first and second barrier patterns DAM1 and DAM2 may have a stacked structure of a second via layer VIA2 and a bank layer PDL. The third barrier pattern DAM3 may have a stacked structure of a first via layer VIA1, a second via layer VIA2, and a bank layer PDL. The fourth barrier pattern DAM4 may have a stacked structure of a second via layer VIA2, a bank layer PDL, and a spacer SPC. The fifth barrier pattern DAM5 may have a stacked structure of a first via layer VIA1, a second via layer VIA2, a bank layer PDL, and a spacer SPC.

[0172] A surface height of the third barrier pattern DAM3 may be greater than each of a surface height of the first barrier pattern DAM1 and a surface height of the second barrier pattern DAM2 . A surface height of the fifth barrier pattern DAM5 may be greater than or equal to a surface height of the fourth barrier pattern DAM4 .

[0173] The light emitting layer EML is disposed on the anode electrode ANO exposed by the bank layer PDL. The light emitting layer EML may include an organic layer OL. The organic layer OL may include an organic light emitting layer and may further include a hole injection / transport layer and / or an electron injection / transport layer.

[0174] The emission wavelength of light emitted by each light-emitting layer (EML) can vary depending on the color pixel. For example, the light-emitting layer (EML) may include a first color light-emitting layer disposed in an emission region of a first color pixel, a second color light-emitting layer disposed in an emission region of a second color pixel, and a third color light-emitting layer disposed in an emission region of a third color pixel. The first color light-emitting layer may emit light within a red wavelength range, the second color light-emitting layer may emit light within a blue wavelength range, and the third color light-emitting layer may emit light within a green wavelength range.

[0175] The cathode CAT may be disposed on the light-emitting layer EML. The cathode CAT may be a common electrode disposed in all pixels without distinguishing between the pixels (for example, a single cathode CAT may be continuous and pass through all pixels without interruption). The anode ANO, the light-emitting layer EML, and the cathode CAT may constitute an organic light-emitting element.

[0176] The cathode CAT may be in contact not only with the emission layer EML but also with the upper surface of the bank layer PDL. The cathode CAT may be conformally formed with respect to the lower structure to reflect the stepped portion of the lower structure.

[0177] The cathode CAT may include a layer of a material having a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF2, Ba, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). As used herein, the phrase "low work function" is understood to mean a work function that is the same as or lower than any of the aforementioned materials provided herein as examples of low work function materials. The cathode CAT may further include a transparent metal oxide layer disposed on the layer of material having a low work function.

[0178] The cathode electrode CAT may be electrically connected to the second connection electrode CE2 in the third non-active region NAR3.

[0179] An encapsulation layer 180 including a first encapsulation inorganic layer 181, an encapsulation organic layer 182, and a second encapsulation inorganic layer 183 is disposed on the cathode CAT. The first encapsulation inorganic layer 181 and the second encapsulation inorganic layer 183 may each include silicon nitride, silicon oxide, silicon oxynitride, or the like. The encapsulation organic layer 182 may include an organic insulating material such as a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or BCB.

[0180] The first encapsulating inorganic layer 181 may be disposed on the entire surface of the active area AAR and the non-active areas NAR3 and NAR4 . The first encapsulating inorganic layer 181 may be in direct contact with each of the barrier patterns DAM1 to DAM5 .

[0181] The encapsulation organic layer 182 may be disposed on the active area AAR and disposed inside the barrier pattern. Figure 7 , the encapsulation organic layer 182 is shown to be disposed inside the fourth and fifth barrier patterns DAM4 and DAM5.

[0182] Second encapsulating inorganic layer 183 may be disposed on encapsulating organic layer 182 and first encapsulating inorganic layer 181. Second encapsulating inorganic layer 183 may be in direct contact with encapsulating organic layer 182 at a portion where second encapsulating inorganic layer 183 at least partially overlaps encapsulating organic layer 182, and may be in direct contact with first encapsulating inorganic layer 181 at a portion where second encapsulating inorganic layer 183 does not overlap encapsulating organic layer 182. For example, encapsulating inorganic layers 181 and 183 may be disposed outwardly compared to encapsulating organic layer 182 and may at least partially surround encapsulating organic layer 182 in a plan view.

[0183] As described above, the plurality of barrier patterns forming a closed curve can completely surround the encapsulation organic layer 182 in a plan view. After forming the first encapsulation inorganic layer 181, an encapsulation organic layer material is formed on the first encapsulation inorganic layer 181, and the encapsulation organic layer material can flow back in an outward direction (from the active area AAR to the non-active area NAR) of the display panel 10. The plurality of barrier patterns can form a closed curve completely surrounding the encapsulation organic layer 182 in a plan view, thereby reducing the reflow of the encapsulation organic layer material in an outward direction of the display panel 10.

[0184] In addition, in the display panel 10 according to an exemplary embodiment of the present disclosure, the number of blocking patterns provided in the fourth non-active region NAR4 may be different from the number of blocking patterns provided in the first to third non-active regions NAR1 to NAR3. The number of blocking patterns provided in the fourth non-active region NAR4 may be greater than the number of blocking patterns provided in the first to third non-active regions NAR1 to NAR3.

[0185] Therefore, in order to increase the number of blocking patterns, the number of blocking patterns can be further increased in the fourth non-active area NAR4 having a relatively wide free space (compared with the free space of other non-active areas), thereby further reducing the backflow of the encapsulation organic layer material in at least the fourth non-active area NAR4.

[0186] Figure 9 yes Figure 8 Magnified view of part.

[0187] A surface height of the third barrier pattern DAM3 may be greater than surface heights of the first and second barrier patterns DAM1 and DAM2 .

[0188] A thickness t3 of the third barrier pattern DAM3 may be greater than a thickness t1 of the first barrier pattern DAM1 and a thickness t2 of the second barrier pattern DAM2 .

[0189] The first and second barrier patterns DAM1 and DAM2 may be spaced apart from each other with a first groove GR1 formed therebetween. The second and third barrier patterns DAM2 and DAM3 may be spaced apart from each other with a second groove GR2 formed therebetween.

[0190] Figure 10 yes Figure 7 Magnified view of part.

[0191] Reference Figure 10 , a surface height of the fifth barrier pattern DAM5 may be greater than or equal to a surface height of the fourth barrier pattern DAM4 .

[0192] When the surface height of the fifth barrier pattern DAM5 is equal to the surface height of the fourth barrier pattern DAM4, the thickness t5 of the fifth barrier pattern DAM5 may be greater than the thickness t4 of the fourth barrier pattern DAM4. When the surface height of the fifth barrier pattern DAM5 is greater than the surface height of the fourth barrier pattern DAM4, the thickness t5 of the fifth barrier pattern DAM5 may be greater than or equal to the thickness t4 of the fourth barrier pattern DAM4.

[0193] The fourth and fifth barrier patterns DAM4 and DAM5 may be spaced apart from each other, with the third groove GR3 formed therebetween.

[0194] Can constitute Figure 9 and Figure 10 The stacked films of the stacked structure of the barrier patterns DAM1 to DAM5 are variously modified.

[0195] In some exemplary embodiments of the present disclosure, the first and second barrier patterns DAM1 and DAM2 may have a stack structure of the first via layer VIA1 and the bank layer PDL or may have a stack structure of the first via layer VIA1 and the second via layer VIA2 .

[0196] In some exemplary embodiments of the present disclosure, the fourth blocking pattern DAM4 may have a stacked structure of the first via layer VIA1, the embankment layer PDL and the spacer SPC, may have a stacked structure of the first via layer VIA1, the second via layer VIA2 and the spacer SPC, or may have a stacked structure of the first via layer VIA1, the second via layer VIA2 and the embankment layer PDL.

[0197] In some exemplary embodiments of the present disclosure, the spacers SPC of the fourth and fifth barrier patterns DAM4 and DAM5 may be omitted.

[0198] In some exemplary embodiments of the present disclosure, spacers SPC may be further stacked in the first to third barrier patterns DAM1 to DAM3 .

[0199] Figures 11 to 14 It shows Figure 9 A view of the modified example.

[0200] Reference Figure 11 The encapsulation organic layer 182_1 of the encapsulation layer 180_1 may at least partially overlap the first barrier pattern DAM1 and may extend to a portion between the first barrier pattern DAM1 and the second barrier pattern DAM2.

[0201] Reference Figure 12 The encapsulation organic layer 182_2 of the encapsulation layer 180_2 may at least partially overlap the first and second barrier patterns DAM1 and DAM2 , and may extend to a portion between the second and third barrier patterns DAM2 and DAM3 .

[0202] Reference Figure 13 , the encapsulation organic layer 182_3 of the encapsulation layer 180_3 may overlap a portion of the first barrier pattern DAM1 and not overlap a remaining portion of the first barrier pattern DAM1 .

[0203] Reference Figure 14 , the encapsulation organic layer 182_4 of the encapsulation layer 180_4 may completely overlap the first barrier pattern DAM1 and may overlap a portion of the second barrier pattern DAM2 and not overlap the remaining portion of the second barrier pattern DAM2 .

[0204] Figure 15 is a plan view of the display panel 11, which shows a blocking pattern and an encapsulation organic layer 182 according to an exemplary embodiment of the present disclosure, Figure 16 yes Figure 15 Magnified view of area B.

[0205] Reference Figure 15 and Figure 16 , the display panel 11 according to this exemplary embodiment of the present disclosure is Figure 5 and Figure 6 The display panel 10 is different in that the second barrier pattern DAM2 is physically connected to the fifth barrier pattern DAM5.

[0206] For example, the connection between the second barrier pattern DAM2 and the fifth barrier pattern DAM5 of the third non-active region NAR3 may be formed in the fourth non-active region NAR4 or the eighth non-active region NAR8, and may not be formed in the third non-active region NAR3. As described above, this is because, since the invalid space of the third non-active region NAR3 is narrowly designed, when the connection between the second barrier pattern DAM2 and the fifth barrier pattern DAM5 is formed in the third non-active region NAR3, the narrowly designed invalid space of the third non-active region NAR3 may increase.

[0207] Similarly, the connection between the second barrier pattern DAM2 and the fifth barrier pattern DAM5 of the second non-active region NAR2 may be made in the fourth non-active region NAR4 or the seventh non-active region NAR7 , and may not be made in the second non-active region NAR2 .

[0208] When each of the connections between the second barrier pattern DAM2 and the fifth barrier pattern DAM5 of the third non-active area NAR3 and the connections between the second barrier pattern DAM2 and the fifth barrier pattern DAM5 of the second non-active area NAR2 are made in the fourth non-active area NAR4, it can be considered that the fifth barrier pattern DAM5 is further set in the entirety of the seventh non-active area NAR7 and the eighth non-active area NAR8 from the connection portion between the second barrier pattern DAM2 and the fifth barrier pattern DAM5 in the fourth non-active area NAR4.

[0209] When each of the connections between the second barrier pattern DAM2 and the fifth barrier pattern DAM5 of the third non-active area NAR3 and the connections between the second barrier pattern DAM2 and the fifth barrier pattern DAM5 of the second non-active area NAR2 are made in the seventh non-active area NAR7 and the eighth non-active area NAR8, it can be considered that the fifth barrier pattern DAM5 is further provided in the remaining portion of the seventh non-active area NAR7 and the remaining portion of the eighth non-active area NAR8 from the connection portion between the second barrier pattern DAM2 and the fifth barrier pattern DAM5 in the seventh non-active area NAR7 and the eighth non-active area NAR8.

[0210] Figure 17 is a partial plan view of a display panel according to an exemplary embodiment of the present disclosure, Figure 18 It is along Figure 17 A cross-sectional view taken along line III-III'.

[0211] Reference Figure 17 and Figure 18 , this exemplary embodiment of the present disclosure is Figure 15 and Figure 16 The exemplary embodiment of the present disclosure is different in that the second barrier pattern DAM2_1 has the same stack structure as the third barrier pattern DAM3 .

[0212] For example, the second barrier pattern DAM2_1 may have a stack structure of a first via layer VIA1 , a second via layer VIA2 on the first via layer VIA1 , and a bank layer PDL.

[0213] Figure 18 The sixth connection electrode CE6 is shown as being disposed between the second via layer VIA2 and the first via layer VIA1 of the second barrier pattern DAM2_1, and thus the second via layer VIA2 and the first via layer VIA1 do not contact each other, but the present disclosure is not necessarily limited thereto. The sixth connection electrode CE6 may not overlap the second barrier pattern DAM2_1, or may overlap only a portion of the upper surface of the first via layer VIA1. In this case, the second via layer VIA2 and the first via layer VIA1 of the second barrier pattern DAM2_1 may contact each other.

[0214] Figures 19 to 21 It shows Figure 9 A view of the modified example.

[0215] Reference Figure 19 , this exemplary embodiment of the present disclosure is Figure 9 The exemplary embodiment of the present disclosure is partially different in that the number of stacked films of the first barrier pattern DAM1_1 , the second barrier pattern DAM2_2 , and the third barrier pattern DAM3_1 is reduced.

[0216] For example, the first barrier pattern DAM1_1 may be formed of the bank layer PDL, the second barrier pattern DAM2_2 may be formed of the bank layer PDL, and the third barrier pattern DAM3_1 may be formed of the second via layer VIA2 and the bank layer PDL.

[0217] Reference Figure 20 , this exemplary embodiment of the present disclosure is Figure 19 The exemplary embodiment is different in that the third barrier pattern DAM3_2 has a stack structure of the first via layer VIA1 and the bank layer PDL, instead of the stack structure of the second via layer VIA2 and the bank layer PDL.

[0218] Reference Figure 21 , this exemplary embodiment of the present disclosure is Figure 9 The exemplary embodiment of the present invention differs in that the Figure 19 The first and second barrier patterns DAM1_1 and DAM2_2 are shown.

[0219] In a display device, according to an exemplary embodiment of the present disclosure, a greater number of barrier patterns are disposed at a lower side of the display device that is less sensitive to a dead space, thereby controlling a reflow of a thin film encapsulation structure.

[0220] The effects of the present disclosure are not limited to the exemplary embodiments of the present disclosure set forth herein, and more various effects are included in this specification.

[0221] Although the embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims

1. A display device, comprising: a substrate comprising an active area and a non-active area at least partially surrounding the active area; a light-emitting element, disposed on the substrate in the active area; an encapsulation layer, disposed on the light-emitting element; as well as a plurality of barrier patterns disposed in the non-active area on the substrate and at least partially surrounding the active area, wherein the non-active region comprises a first non-active region positioned at a first side of the active region and a second non-active region positioned at a second side of the active region, wherein more of the plurality of blocking patterns are disposed in the first inactive region than in the second inactive region, The blocking patterns in the first non-active area among the plurality of blocking patterns include: a first blocking pattern; a second blocking pattern spaced apart from the active area, the first blocking pattern being positioned between the second blocking pattern and the active area; and a third blocking pattern spaced apart from the first blocking pattern, the second blocking pattern being positioned between the third blocking pattern and the first blocking pattern. The barrier patterns disposed in the second non-active area among the plurality of barrier patterns include a fourth barrier pattern and a fifth barrier pattern, wherein the fifth barrier pattern is spaced apart from the active area, and the fourth barrier pattern is disposed between the fifth barrier pattern and the active area. The non-active region further includes a third non-active region disposed between the first non-active region and the second non-active region, and The second barrier pattern is physically connected to the fourth barrier pattern or the fifth barrier pattern in the first non-active region or the third non-active region.

2. The display device according to claim 1, wherein A planar shape of the plurality of barrier patterns includes a closed curve.

3. The display device according to claim 2, wherein: The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer disposed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer, and Wherein, the organic encapsulation layer is arranged inside the plurality of barrier patterns.

4. The display device according to claim 3, wherein The first barrier pattern is physically connected to the fourth barrier pattern, and Wherein, the third barrier pattern is physically connected to the fifth barrier pattern.

5. The display device according to claim 4, wherein The effective area has a rectangular shape with rounded corners, the rectangular shape having a pair of short sides and a pair of long sides, wherein the first inactive area is disposed adjacent to one of the pair of short sides of the active area, and The second inactive area is arranged adjacent to one of the pair of long sides of the active area. The display device according to claim 5 , wherein: The third non-active area is disposed adjacent to one of the rounded corners of the active area.

7. The display device according to claim 4, wherein The first inactive area also includes a curved area, and The bending area is spaced apart from the active area, and the third barrier pattern is placed between the bending area and the active area.

8. The display device according to claim 7, wherein: In the bending region, the display device is bent in a thickness direction of the display device.

9. The display device according to claim 8, wherein The third barrier pattern has a first stack structure in which a first organic layer is stacked on the substrate, a second organic layer is stacked on the first organic layer, and a third organic layer is stacked on the second organic layer, and The first barrier pattern and the second barrier pattern both have a second stacking structure, and in the second stacking structure, the second organic layer and the third organic layer are stacked.

10. The display device according to claim 9, further comprising a fourth organic layer disposed in the curved region on the substrate, in, The fourth organic layer contacts the substrate and includes the same material as that of the first organic layer.

11. The display device according to claim 3, wherein A surface height of the third barrier pattern is greater than each of a surface height of the first barrier pattern and a surface height of the second barrier pattern, and Wherein, a surface height of the fifth barrier pattern is greater than a surface height of the fourth barrier pattern.

12. The display device according to claim 3, wherein The organic encapsulation layer is disposed on an inner side of the third barrier pattern and an inner side of the fifth barrier pattern, and The first inorganic encapsulating layer is in direct contact with each of the first barrier pattern, the second barrier pattern, and the third barrier pattern.

13. A display device, comprising: a substrate comprising an active area and a non-active area at least partially surrounding the active area; a light-emitting element, disposed on the substrate in the active area; an encapsulation layer, disposed on the light-emitting element; as well as a plurality of barrier patterns disposed in the non-active area on the substrate and at least partially surrounding the active area, wherein the non-active region comprises a first non-active region positioned at a first side of the active region and a second non-active region positioned at a second side of the active region, wherein the plurality of blocking patterns have a closed curve shape surrounding the active area, wherein more of the plurality of blocking patterns are disposed in the first inactive region than in the second inactive region, The blocking patterns in the first non-active area among the plurality of blocking patterns include: a first blocking pattern; a second blocking pattern spaced apart from the active area, the first blocking pattern being positioned between the second blocking pattern and the active area; and a third blocking pattern spaced apart from the first blocking pattern, the second blocking pattern being positioned between the third blocking pattern and the first blocking pattern. The barrier patterns disposed in the second non-active area among the plurality of barrier patterns include a fourth barrier pattern and a fifth barrier pattern spaced apart from the active area, and the fourth barrier pattern is disposed between the fifth barrier pattern and the active area. The non-active region further includes a third non-active region disposed between the first non-active region and the second non-active region, and The second barrier pattern is physically connected to the fourth barrier pattern or the fifth barrier pattern in the first non-active region or the third non-active region.

14. The display device according to claim 13, wherein: The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer disposed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer, and Wherein, the organic encapsulation layer is arranged inside the plurality of barrier patterns.

15. The display device according to claim 14, in, The first barrier pattern is physically connected to the fourth barrier pattern, and Wherein, the third barrier pattern is physically connected to the fifth barrier pattern.

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