Access line management of memory cell array

Abstract

The present application relates to access line management of a memory cell array. Some memory devices may include a plate coupled to a memory cell that is associated with a plurality of digit lines and / or a plurality of word lines. Because the plate is coupled to a plurality of digit lines and / or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the effects of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Thus, the voltage of each unselected word line may be related to the voltage of the plate because plate voltage changes may occur.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 16 / 695,848, filed by Vimercati on November 26, 2019, entitled “ACCESS LINE MANAGEMENT FOR AN ARRAY OF MEMORY CELLS,” which is a continuation-in-part of U.S. patent application No. 15 / 971,639, filed by Vimercati on May 4, 2018, entitled “ACCESS LINE MANAGEMENT FOR AN ARRAY OF MEMORY CELLS,” each of which is assigned to the present assignee and expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to access line management of memory cell arrays. Background Art

[0004] The following relates generally to managing access to memory cells, and more specifically, to access line management for an array of memory cells.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, often represented by a logical "1" or a logical "0". In other systems, more than two states may be stored. To access the stored information, a component of the electronic device may read or sense the stored state in the memory device. To store information, a component of the electronic device may write or program a state in the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for an extended period of time even in the absence of an external power source. Volatile memory devices, such as DRAM, may lose their stored state over time unless the volatile memory device is periodically refreshed by an external power source. FeRAM may use a similar device architecture as volatile memory, but may have non-volatile properties due to the use of ferroelectric capacitors as storage devices. Therefore, FeRAM devices may have improved performance compared to other non-volatile and volatile memory devices.

[0007] Generally, improving a memory device may include increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Summary of the invention

[0008] A method is described. In some examples, the method may include: driving a plate coupled to a first memory cell of a memory cell array to a first voltage; identifying an access operation associated with a second memory cell of the memory cell array; floating a first access line coupled to the first memory cell for a duration based at least in part on the access operation associated with the second memory cell, wherein the floating is based at least in part on applying a first control signal having a first voltage swing and a second control signal having a second voltage swing different from the first voltage swing to a driver of the first access line, and driving the plate from the first voltage to a second voltage during the duration based at least in part on the access operation associated with the second memory cell.

[0009] An apparatus is described. In some examples, the apparatus may include: a memory cell coupled to an access line, a driver coupled to the access line, and a control circuit coupled to the driver and operable to generate a first control signal for the driver and a second control signal for the driver, the second control signal having a different voltage swing than the first control signal.

[0010] An apparatus is described. In some examples, the apparatus may include: a memory cell coupled to an access line; a driver coupled to the access line, wherein the driver includes a first transistor in a cascode configuration with a second transistor; and a control circuit coupled to the driver and operable to output a first control signal to the first transistor and a second control signal to a third transistor of the driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a memory array supporting access line management for an array of memory cells according to an example of the present invention is shown.

[0012] Figure 2 An example of circuitry supporting techniques for access line management according to an example of the present invention is shown.

[0013] Figure 3 An example of a memory device supporting techniques for access line management according to an example of the present disclosure is shown.

[0014] Figure 4A and 4BDepicted is an example of a memory device and a timing diagram supporting techniques for access line management in accordance with an example of the present disclosure.

[0015] Figure 5A and 5B Depicted is an example of a memory device and a timing diagram supporting techniques for access line management in accordance with an example of the present disclosure.

[0016] Figure 6 and 7 A block diagram of a device supporting techniques for access line management is shown according to an example of the disclosure.

[0017] Figures 8 to 10 A method for access line management of a memory cell array according to an example of the present invention is shown.

[0018] Fig.11 An example of a circuit supporting techniques for access line management of a memory cell array according to an example of the present invention is shown.

[0019] Figures 12A to 12D Depicted is an example timing diagram of a technique supporting access line management for an array of memory cells in accordance with an example of the present disclosure.

[0020] Fig.13 A block diagram of an access line manager supporting access line management of a memory cell array according to an example of the present invention is shown.

[0021] Fig.14 A diagram is shown of a system including devices supporting access line management of a memory cell array according to an example of the present invention.

[0022] Fig.15 An access line management method of a memory cell array according to an example of the present invention is illustrated. DETAILED DESCRIPTION

[0023] Some memory arrays may include a plate that is common to multiple memory cells that are also associated with multiple digit lines and / or multiple word lines. Because the voltage of the plate (and therefore the voltage of the associated plate lines) fluctuates (e.g., between a high voltage and a low voltage) in relation to access operations for selected memory cells, some memory devices may maintain each word line for unselected memory cells that are common to the plate (which may be referred to as an unselected word line) at a fixed voltage. This may generate leakage current and associated power losses due to capacitive (e.g., parasitic) cross-coupling associated with each unselected word line (e.g., between each unselected word line and the common plate or plate line). In the case where the plate is common to many memory cells, the amount of capacitance (e.g., parasitic capacitance) and unintended cross-coupling between the plate and the unselected word lines may be significant, and therefore, the amount of associated power losses may be significant. Parasitic signals due to such unintended cross-coupling, along with the additional power consumption of the memory array, may interfere with the logic states stored on the unselected memory cells. For example, parasitic signaling may result in errors being introduced into data by changing the state stored on a memory cell or by introducing errors into an access operation, among other effects.

[0024] Techniques for managing access lines (e.g., unselected access lines, unselected word lines) during access operations in a memory device are described herein, which may include a plate that is common to memory cells associated (directly or indirectly) with multiple digit lines and / or multiple word lines. For example, to reduce or mitigate the effects of unintended cross-coupling, the memory device may float multiple unselected access lines (e.g., word lines) while changing the voltage of the plate. Thus, the memory device may float the unselected word lines during one or more portions of an access operation for a selected memory cell, and in some cases for a duration before or after the access operation. Floating the unselected access lines may facilitate the voltage of each unselected access line to track the voltage of the plate and plate lines (e.g., maintain a constant or near-constant differential with the voltage of the plate and plate lines), resulting in lower power consumption of the memory array overall, as well as fewer errors associated with unselected memory cells. As used herein, floating a node may refer to electrically isolating the node from any defined voltage source.

[0025] Below is Figures 1 to 3 The features of the present invention introduced above are further described in the context of the present invention. Figures 4A to 4B , 5A-5B and 11 and 12A-12D describe specific examples. These and other features of the present invention are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flow charts related to techniques for access line management of memory cell arrays.

[0026] Figure 1 An example memory array 100 is depicted according to various embodiments of the present invention. The memory array 100 may also be referred to as an electronic memory device. The memory array 100 includes memory cells 105 that are programmable to store different states. Each memory cell 105 may be programmable to store two states, represented as logic 0 and logic 1. In some cases, the memory cell 105 is configured to store more than two logic states. The memory cell 105 may store charges representing programmable states in a capacitor; for example, a charged and uncharged capacitor may represent two logic states, respectively. DRAM architectures may typically use such designs, and the capacitors used may include dielectric materials having linear or paraelectric polarization properties as insulators. In contrast, a ferroelectric memory cell may include a capacitor having a ferroelectric as an insulating material. Different charge levels of a ferroelectric capacitor may represent different logic states. Ferroelectric materials have nonlinear polarization properties; some details and advantages of the ferroelectric memory cell 105 are discussed below.

[0027] The memory array 100 may be a three-dimensional (3D) memory array in which two-dimensional (2D) memory arrays are formed on top of each other. This may increase the number of memory cells that may be formed on a single die or substrate compared to a 2D array, which in turn may reduce production costs or increase the performance of the memory array, or both. Figure 1 , memory array 100 includes two levels of memory cells 105, and thus can be considered a three-dimensional memory array; however, the number of levels is not limited to two. Each level can be aligned or positioned so that memory cells 105 can be substantially aligned with each other across each level, forming memory cell stacks 145. In some cases, memory array 100 can be referred to as memory device 100.

[0028] Each row of memory cells 105 is connected to an access line 110, and each column of memory cells 105 is connected to a bit line 115. The access lines 110 and the bit lines 115 may be substantially perpendicular to each other to create an array. In addition, each row of memory cells 105 may be coupled to at least one plate line (not shown). As used herein, the terms plate node, plate line, or simply plate may be used interchangeably. Figure 1, each memory cell 105 in a memory cell stack 145 may be coupled to a separate conductive line, such as a bit line 115. In other examples (not shown), two memory cells 105 in a memory cell stack 145 may share a common conductive line, such as a bit line 115. That is, the bit line 115 may be in electronic communication with the bottom electrode of the upper memory cell 105 and the top electrode of the lower memory cell 105. Other configurations may be possible, for example, the third group may share the access line 110 with the lower group. In general, one memory cell 105 may be located at the intersection of two conductive lines, such as the access line 110 and the bit line 115. This intersection may be referred to as the address of the memory cell. The target memory cell 105 may be a memory cell 105 located at the intersection of the energized access line 110 and the bit line 115; that is, the access line 110 and the bit line 115 may be energized so that the memory cell 105 is read or written at their intersection. Other memory cells 105 that are in electronic communication with (eg, connected to) the same access line 110 or bit line 115 may be referred to as non-target memory cells 105 .

[0029] As discussed above, electrodes may be coupled to memory cells 105 and access lines 110 or bit lines 115. The term electrode may refer to an electrical conductor, and in some cases may serve as an electrical contact to memory cells 105. Electrodes may include traces, wires, conductive lines, conductive layers, or the like that provide a conductive path between elements or components of memory array 100.

[0030] Operations such as reading and writing can be performed on the memory cell 105 by activating or selecting the access line 110 and the digit line 115. The access line 110 may also be referred to as the word line 110, and the bit line 115 may also be referred to as the digit line 115. In general, the term access line may refer to a word line, a bit line, a digit line, or a plate line. References to word lines and bit lines, or the like, are interchangeable without loss of understanding or operation. Activating or selecting the word line 110 or the digit line 115 may include applying a voltage to the corresponding line. The word line 110 and the digit line 115 may be made of a conductive material such as a metal (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), etc.), a metal alloy, carbon, a conductive doped semiconductor, or other conductive material, alloy, compound, or the like.

[0031] In some architectures, the logic storage device of a cell (e.g., a capacitor) can be electrically isolated from a digit line by a selection component. A word line 110 can be connected to and can control the selection component. For example, the selection component can be a transistor, and the word line 110 can be connected to the gate of the transistor. Activating the word line 110 causes an electrical connection or closed circuit between the capacitor of the memory cell 105 and its corresponding digit line 115. The digit line can then be accessed to read or write the memory cell 105. After the memory cell 105 is selected, the resultant signal can be used to determine the stored logic state.

[0032] Access to the memory cells 105 may be controlled via the row decoder 120 and the column decoder 130. For example, the row decoder 120 may receive a row address from the memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, the column decoder 130 receives a column address from the memory controller 140 and activates the appropriate digit line 115. For example, the memory array 100 may include a plurality of word lines 110 and a plurality of digit lines 115. Thus, by activating the word lines 110 and the digit lines 115, the memory cells 105 at their intersections may be accessed. As described in more detail below, by floating unselected access lines (e.g., unselected word lines), the effects of unintended cross-coupling may be mitigated. For example, a plate may be coupled to a plurality of memory cells, which in turn may be coupled (directly or indirectly) to a plurality of word lines and a plurality of digit lines. During a period associated with an access operation of one memory cell, the word lines associated with the remaining unselected memory cells coupled to the plate may be floated. By floating the unselected word lines, the effects associated with cross coupling between the unselected word lines and the plate can be mitigated.

[0033] After access, the memory cell 105 may be read or sensed by the sensing component 125 to determine the stored state of the memory cell 105. For example, after accessing the memory cell 105, the capacitor of the memory cell 105 may be discharged onto its corresponding digit line 115. Discharging the capacitor may be caused by biasing or applying a voltage to the capacitor. The discharge may cause a voltage change on the digit line 115, which the sensing component 125 may compare to a reference voltage (not shown) in order to determine the stored state of the memory cell 105. Figures 4A to 4B 5A to 5B describe exemplary access operations.

[0034] The sensing component 125 may include various transistors or amplifiers in order to detect and amplify the difference in the signal, which may be referred to as latching. The detected logic state of the memory cell 105 may then be output as output 135 via the column decoder 130. In some cases, the sensing component 125 may be part of the column decoder 130 or the row decoder 120. Alternatively, the sensing component 125 may be connected to or in electronic communication with the column decoder 130 or the row decoder 120. As described in more detail below, unselected word lines may be floated during periods associated with access operations to mitigate effects associated with cross-coupling of the word lines.

[0035] In some memory architectures, accessing memory cell 105 may degrade or destroy the stored logical state, and a rewrite or refresh operation may be performed to return the original logical state to memory cell 105. In DRAM, for example, a capacitor may be partially or completely discharged during a sensing operation, thereby destroying the stored logical state. Therefore, the logical state may be rewritten after the sensing operation. In addition, activating a single word line 110 may cause all memory cells in a row to discharge; therefore, some or all memory cells 105 in the row may need to be rewritten. However, in non-volatile memories such as arrays using ferroelectrics, accessing memory cell 105 may not destroy the logical state, and therefore, memory cell 105 may not need to be rewritten after access. In some instances, multiple levels of memory cells may be coupled to the same plate. Such a plate configuration may result in a smaller amount of area used to connect higher level memory cells to the substrate.

[0036] Some memory architectures including DRAM may lose their stored state over time unless they are periodically refreshed by an external power source. For example, charged capacitors may discharge over time via leakage current, resulting in loss of stored information. The refresh rate of these so-called volatile memory devices may be relatively high, such as tens of refresh operations per second for DRAM arrays, which may result in significant power consumption. As memory arrays become larger, increased power consumption may inhibit the deployment or operation of memory arrays (e.g., power supply, heat generation, material limitations, etc.), especially for mobile devices that rely on limited power sources such as batteries.

[0037] The memory controller 140 may control the operation (e.g., reading, writing, rewriting, refreshing, discharging, etc.) of the memory cells 105 via various components (e.g., row decoder 120, column decoder 130, and sensing component 125). In some cases, one or more of the row decoder 120, column decoder 130, and sensing component 125 may be co-located with the memory controller 140. The memory controller 140 may generate row and column address signals in order to activate the desired word lines 110 and digit lines 115. The memory controller 140 may also generate and control various voltages or currents used during the operation of the memory array 100. For example, it may apply a discharge voltage to the word lines 110 or digit lines 115 after accessing one or more memory cells 105. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or varied and may be different for the various operations discussed when operating the memory array 100. Furthermore, one, multiple, or all memory cells 105 within memory array 100 may be accessed simultaneously; for example, multiple or all cells of memory array 100 may be accessed simultaneously during a reset operation in which all memory cells 105 or a group of memory cells 105 are set to a single logic state.

[0038] In some examples, the memory controller 140 may be configured to float one or more access lines (e.g., word lines 110) of the memory array 100 during one or more periods associated with an access operation. For example, the memory controller 140 may identify an access operation associated with a selected memory cell 104. Upon identifying the access operation, the memory controller 140 may initiate driving a plate (not shown) from a first voltage to a second voltage based at least in part on the access operation associated with the selected memory cell 105. In some examples, the memory controller 140 may initiate floating access lines (e.g., word lines 110) for unselected memory cells 105 based at least in part on the access operation associated with the selected memory cell 105. The memory controller 140 may be configured to initiate floating of the unselected access lines at the same time or prior to initiating driving of the plate to the second voltage. Thus, during an access operation, the memory controller 140 may select one access line while floating other access lines of the memory array 100 (e.g., other access lines associated with unselected memory cells 105 that share a plate with the selected memory cell 105). By floating the unselected access lines, undesirable effects associated with cross-coupling between the unselected access lines and other aspects of the memory array 100 (e.g., a plate that is common to a selected memory cell 105 and one or more unselected memory cells 105) may be avoided or mitigated.

[0039] Figure 2An example circuit 200 according to various embodiments of the present invention is shown. The circuit 200 includes a memory cell 105-a, a word line 110-a, a digit line 115-a, and a sensing element 125-a, which may be examples of a memory cell 105, a word line 110, a digit line 115, and a sensing element 125, respectively, as described in reference to Figure 1 Memory cell 105-a may include a logic storage component, such as capacitor 205, having a first plate, cell plate 230, and a second plate, cell bottom 215. Cell plate 230 and cell bottom 215 may be capacitively coupled via a material, such as a ferroelectric material, positioned between cell plate 230 and cell bottom 215. The orientation of cell plate 230 and cell bottom 215 may be flipped without changing the operation of memory cell 105-a. Circuit 200 also includes selection component 220 and reference line 225.

[0040] The cell plate 230 may be accessed via the plate line 210, and the cell bottom 215 may be accessed via the digit line 115-a. In some cases, some memory cells 105-a may share access lines (e.g., digit lines, word lines, plate lines) with other memory cells. For example, the digit line 115-a may be shared with the memory cells 105-a in the same column, the word line 110-a may be shared with the memory cells 105-a in the same row, and the plate line 210 (and the corresponding plate 230) may be shared with the memory cells 105-a in the same section, cell block, group, or even multiple groups. As described above, various states may be stored by charging or discharging the capacitor 205. In many examples, a connector or socket may be used to couple the digit line 115-a or plate line 210 of the memory cell of the upper level to the substrate positioned below the memory cell array. The size of the connector or socket may be modified based on the configuration of the plate lines in the memory array.

[0041] In some cases, a memory array 100 including a plate (not shown) coupled to a plurality of memory cells 105 associated with a plurality of different word lines 110 and / or digit lines 115 may have unique access operations as described herein. For example, if an unselected word line is maintained at a fixed voltage when the plate voltage is changed, the unselected word line may cause undesired leakage or power consumption due to capacitance between the unselected word line and the plate or between the unselected word line and one or more digit lines. Therefore, techniques are provided herein for mitigating or reducing the effects of such capacitance or cross-coupling during access operations of a memory array that includes a plate that is common to more than one memory cell 105, which may be referred to as a common plate.

[0042] The stored state of capacitor 205 may be read or sensed by operating various elements represented in circuit 200. Capacitor 205 may be in electronic communication with digital line 115-a. For example, when selection component 220 is deactivated, capacitor 205 may be isolated from digital line 115-a, and when selection component 220 is activated, capacitor 205 may be connected to digital line 115-a. Activating selection component 220 may be referred to as selecting memory cell 105-a. In some cases, selection component 220 is a transistor, and its operation is controlled by applying a voltage to the transistor gate, where the voltage magnitude is greater than the threshold magnitude of the transistor. Word line 110-a may activate selection component 220; for example, a voltage applied to word line 110-a is applied to the transistor gate, thereby connecting capacitor 205 to digital line 115-a. As described in more detail below, access operations (e.g., read operations or write operations) may be performed based on the plate configuration of the memory array. For example, one or more unselected access lines (eg, unselected word lines; not shown) may be floated. By floating the unselected access lines, negative cross-coupling effects may be prevented or mitigated.

[0043] In other examples, the positions of select component 220 and capacitor 205 may be switched so that select component 220 is connected between plate line 210 and cell plate 230, and so that capacitor 205 is between digit line 115-a and another terminal of select component 220. In this embodiment, select component 220 may remain in electronic communication with digit line 115-a via capacitor 205. This configuration may be associated with alternative timing and biasing for read and write operations.

[0044] In some cases, due to the ferroelectric material between the plates of capacitor 205, capacitor 205 may not discharge immediately after being connected to digit line 115-a. In one approach, to sense the logic state stored by ferroelectric capacitor 205, word line 110-a may be biased to select memory cell 105-a, and a voltage may be applied to plate line 210. In some cases, digit line 115-a is virtually grounded and then isolated from the virtual ground before plate line 210 and word line 110-a are biased. Biasing plate line 210 may produce a voltage difference across capacitor 205 (e.g., plate line 210 voltage minus digit line 115-a voltage). The voltage difference may cause a change in the stored charge on capacitor 205, where the magnitude of the stored charge change may depend on the initial state of capacitor 205—e.g., whether the initial state stores a logic 1 or a logic 0. This may cause a voltage change in digit line 115-a based on the charge stored on capacitor 205. Operating the memory cell 105-a by varying the voltage of the cell plate 230 may be referred to as “moving the cell plate.” As described in more detail below, some aspects of access operations (eg, read operations or write operations) may be modified based on the plate configuration of the memory array.

[0045] The voltage change of digit line 115-a may depend on its intrinsic capacitance. That is, as charge flows through digit line 115-a, some finite charge may be stored in digit line 115-a, and the resulting voltage depends on the intrinsic capacitance. The intrinsic capacitance may depend on the physical properties of digit line 115-a, including size. Digit line 115-a may connect many memory cells 105, so digit line 115-a may have a length that produces a non-negligible capacitance (e.g., on the order of pico-farads (pF)). The resulting voltage of digit line 115-a may then be compared to a reference (e.g., the voltage of reference line 225) by sensing component 125-a in order to determine the stored logic state in memory cell 105-a. Other sensing processes may be used.

[0046] The sensing component 125-a may include various transistors or amplifiers to detect and amplify the difference in signals, which may be referred to as latching. The sensing component 125-a may include a sense amplifier that receives and compares the voltages of the digital line 115-a and the reference line 225, which may be a reference voltage. The sense amplifier output may be driven to a higher (e.g., positive) or lower (e.g., negative or ground) supply voltage based on the comparison. For example, if the digital line 115-a has a higher voltage than the reference line 225, the sense amplifier output may be driven to the positive supply voltage.

[0047] In some cases, the sense amplifier may additionally drive the digit line 115-a to a supply voltage. The sensing component 125-a may then latch the output of the sense amplifier and / or the voltage of the digit line 115-a, which may be used to determine the stored state in the memory cell 105-a, such as a logical 1. Alternatively, if the digit line 115-a has a lower voltage than the reference line 225, the sense amplifier output may be driven to a negative or ground voltage. The sensing component 125-a may similarly latch the sense amplifier output to determine the stored state in the memory cell 105-a, such as a logical 0. Reference Figure 1 , the latched logic state of memory cell 105 - a may then be output as output 135 , for example, via column decoder 130 .

[0048] To write to memory cell 105-a, a voltage may be applied across capacitor 205. Various methods may be used. In one example, select component 220 may be activated via word line 110-a so as to electrically connect capacitor 205 to digit line 115-a. A voltage may be applied across capacitor 205 by controlling the voltage of cell plate 230 (via plate line 210) and cell bottom 215 (via digit line 115-a). To write a logical 0, cell plate 230 may be taken high, i.e., a positive voltage may be applied to plate line 210, and cell bottom 215 may be taken low, such as virtually grounding digit line 115-a or applying a negative voltage to digit line 115-a. The reverse process is performed to write a logical 1, where cell plate 230 is taken low and cell bottom 215 is taken high.

[0049] Figure 3 An example of a memory device 300 supporting techniques for access line management of an array of memory cells according to an example of the present disclosure is depicted. The memory device 300 may include a plurality of memory cells 305 coupled with one or more word lines 310 and one or more digit lines 315 to form an array 320. The memory device 300 may include a plate 325 coupled with one or more memory cells 305 associated with the plurality of word lines 310 or the plurality of digit lines 315 in the array 320. In some examples, the memory array 320 may include a plurality of ferroelectric memory cells or other capacitor-based memory cells.

[0050] For example, the plate 325 can be coupled to the memory cells 305 associated with the first word line 310-a and the second word line 310-b, and / or the memory cells 305 associated with the first digit line 315-a, the second digit line 315-b, and the third digit line 315-c. In some cases, a single plate 325 can be coupled to (e.g., coupled to) the memory cells 305 associated with any number of word lines 310 or digit lines. The memory device 300 can be a reference Figure 1 Examples of memory array 100 are described or included in memory array 100 .

[0051] In some examples, by having one or more plates that are each common to multiple memory cells, the number of plate nodes in the memory cell array can be reduced relative to alternative architectures. This may result in more efficient use of die area in the memory array, and / or more efficient use of power during access operations. In some cases, the plate drivers associated with plate 325 can be located outside of memory array 320, thereby providing more space for other components of array 320. Additionally, by reducing the number of plates, memory device 300 can be configured to reduce the number of plate drivers in the memory cell array relative to alternative architectures.

[0052] In some cases, a single plate 325 may be coupled to different groups of memory cells 305. In some such cases, a single plate 325 may be coupled to a first group of memory cells and a second group of memory cells. Such an arrangement may result in even more reductions in the plates and plate drivers in array 320.

[0053] Having a plate 325 that is common to multiple memory cells may create an associated risk of undesirable coupling between different components of the array 320. During access operations of selected memory cells, unselected access lines (e.g., unselected word lines) may be susceptible to cross-coupling with one or more digit lines 315 and the plate 325 during access operations. In some cases, the cross-coupling may generate parasitic signals (e.g., leakage currents) between each unselected word line 310 and the corresponding digit line 315 and between each unselected word line 310 and the plate 325. Because such parasitic effects may occur at each unselected word line 310, the impact of such effects may be significant in a memory array containing multiple word lines and multiple digit lines. In some examples, such cross-coupling and related effects may "disturb" the logic states stored on the unselected memory cells. For example, the parasitic signals may cause charge to be stored on the middle electrode of the unselected memory cell 305. In some cases, such accumulation or other parasitic effects may result in additional power consumption of the memory device 300.

[0054] During an access operation, typically only a small number of memory cells (e.g., one or more) are accessed in a given segment of array 320. Figure 3In the illustrative example of , memory cell 305-b may be a selected memory cell for access operations (e.g., read, write, and / or precharge), and memory cells 305-a, 305-c, 305-d, 305-e, and 305-f may be unselected memory cells. Each of these memory cells 305 is coupled to a common plate 325. In such an example, parasitic signals (e.g., due to unintended capacitive cross-coupling) may develop between the unselected word line 310-b and the unselected digit lines (e.g., 315-b, 315-c) and between each of the unselected word lines and the plate 325.

[0055] In some cases, parasitic signals may occur between several components when the plate 325 is biased from a first state to a second state (e.g., driven from a first voltage to a second voltage). For example, biasing the plate 325 to a first voltage while maintaining the unselected word lines 315-b, 315-c at a fixed voltage may cause parasitic signals due to the capacitance between each unselected word line and a corresponding digit line and between each unselected word line and the plate 325. To avoid or mitigate such undesirable effects, the unselected word lines 315-b, 315-c may be floated relative to the plate 325. For example, if the plate 325 is biased from a first voltage to a second voltage as part of an access operation for a selected memory cell 305-b, the unselected digit lines 315-b, 315-c may be floated as the voltage of the plate 325 changes, and the unselected digit lines 315-b, 315-c may in turn track the voltage of the plate 325 (e.g., maintain a common differential with the voltage of the plate 325).

[0056] Such operations may be performed on any combination of unselected word lines. For example, a memory array may include a plurality of word lines (e.g., 1024 word lines) and a plurality of digit lines (e.g., 1024 digit lines). During a single access operation, a large number of word lines may be unselected (e.g., 1023 unselected word lines). Floating any combination of unselected word lines (e.g., any of the 1023 unselected word lines) during a period associated with an access operation associated with a selected word line may result in performance improvements (e.g., reduced power consumption, increased reliability) for the entire memory device 300.

[0057] Memory cell 305 may be a reference Figure 1 1. The memory cell 305 is an example of a memory cell 105 described. In some cases, the memory cell 305 can be a ferroelectric memory cell, a DRAM memory cell, a NAND memory cell, a phase change memory cell, or any other type of memory cell. The word line 310 can be a reference Figure 1 An example of a word line 110 is depicted. A digit line 315 may be referenced Figure 1 An example of a digital line 115 is described. Plate 325 may be referenced Figure 2 Examples of plates 230 and / or plate lines 210 are described and may relate to plates 230 and / or plate lines 210 .

[0058] As an example, Figure 3 A memory array 320 including a first memory cell 305-a and a second memory cell 305-f may be depicted. As described above, the memory array 320 may include a plate 325 coupled to the first memory cell 305-a and the second memory cell 305-f, and may include a plate line driver (not shown) coupled to the plate 325. In some examples, a first access line 310-a may be coupled to the first memory cell 305-a, and an access line driver (not shown) may be coupled to the first access line 310-a. In some examples, the access line driver may be configured to float the first access line 310-a for a duration based at least in part on an access operation associated with the second memory cell 305-f. In some examples, each of the memory cells 305-a, 305-b, 305-c, 305-d, and 305-e may be floated for a duration based at least in part on an access operation associated with the memory cell 305-f. In some examples, the plate line driver may be configured to drive the plate 325 to a first voltage prior to the duration and may be configured to drive the plate 325 to a second voltage during the duration based at least in part on an access operation associated with the second memory cell 305 - f .

[0059] Figure 4A An example of a memory device 400-a supporting techniques for access line management of a memory cell array according to an example of the present disclosure is shown. In some examples, the memory device 400-a may include a driver 405, which may be referred to as a memory driver 405. The memory driver 405 may be coupled to any number of access lines and may facilitate one or more memory cells (e.g., as described in reference Figure 3 Memory driver 405 may be coupled to, for example, access line 420, access line 425, access line 430, and access line 435. Each of access lines 420, 425, 430, and 435 may be a word line of a memory array (e.g., as described in reference to FIG. 1 ). Figure 3 Memory driver 405 may include various subcomponents, such as driver component 410 and driver component 415. In other examples (not shown), memory driver 405 may contain any number of subcomponents (such as any number of driver components).

[0060] As described above, each of the access lines 420, 425, 430, and 435 can be a memory array (e.g., as described in reference Figure 3 4. For example, access line 420 may be referred to as a first access line 420, and access line 425 may be referred to as a second access line 425. Additionally or alternatively, access line 430 and access line 435 may be examples of access lines representing a total number of access lines associated with memory device 400-a.

[0061] For example, access line 435 may be referred to as access line "AL n ”, where “n” is the total number of access lines associated with the memory array, and access line 430 may be referred to as access line “AL”. n-1 ”. In some examples, a memory array associated with driver 405 may include 1024 access lines (e.g., word lines), so access line 430 may represent the 1023rd access line of the memory array, and access line 435 may represent the 1024th access line of the memory array. Each of access lines 420, 425, 430, and 435 may be associated with a respective individual memory cell—e.g., no memory cells 105 may be common across access lines 420, 425, 430, and 435, regardless of whether any of access lines 420, 425, 430, and 435 are associated with a single memory cell 105 or a plurality of memory cells 105.

[0062] In some examples, the memory driver 405 can facilitate access operations to a memory cell coupled to one of the access lines 420, 425, 430, or 435. For example, an access operation can be performed on a memory cell coupled to the access line 425, which can be referred to as a second memory cell. A memory controller (e.g., as described in reference Figure 1 The memory controller 140 described above may identify an access operation associated with the second memory cell. The driver 405 may then float the first access line 420 (e.g., for a duration). In some examples, the driver 405 may float each of the access lines 420-435 except for the access line 425. In other words, the driver 405 may float each unselected access line associated with the memory cell 105 that has a common plate with the selected memory cell. Floating the unselected access lines may cause the voltage of each unselected access line to track the voltage of the associated plate (e.g., as described above). Figure 3 The voltage of the plate 325) described.

[0063] In the examples described above, memory driver 405 may include any number of subcomponents, and each subcomponent may be coupled with any number of access lines. For example, memory driver 405 may include a separate driver component for each access line, may include a separate driver component for each unique subset of access lines.

[0064] Figure 4B An example timing diagram 400-b is shown that supports techniques for access line management for a memory cell array according to an example of the present invention. In some examples, the timing diagram 400-b may be similar to the timing diagram described above with reference to Figure 4A In some examples, the timing diagram 400-b may be depicted as described above with reference to the access operation associated with the memory device 400-a. Figure 4A Depicted are the voltages of plate line 440, unselected access lines 445, 445-a, and selected access line 450. Timing diagram 400-b may depict the voltages of plate line 440, unselected access lines 445, 445-a, and selected access line 450 during intervals 455, 458, 460, 462, and 465.

[0065] As described above, a memory array may include a plurality of corresponding access lines for a plurality of memory cells (e.g., as described above with reference to Figure 4A 420, 425, 430, and 435), each memory cell has a common plate. Each access line may be referred to as a word line, and may be selected or unselected (e.g., by a driver) based on a particular access operation. Any one access line may be selected during a particular access operation, and the remaining number of access lines associated with the plate may remain unselected during that operation. For example, the memory cells common to a plate may be associated with 1024 access lines (e.g., word lines). Thus, during an access operation, one access line associated with the memory cell to be accessed may be selected (e.g., selected access line 450), and the remaining number of access lines may remain unselected (e.g., unselected access lines 445, 445-a). As described above with reference to Figure 3 As depicted, a plate, such as plate line 440, may be coupled to a memory array.

[0066] An access operation associated with a memory cell may be identified (e.g., by referring to Figure 1 1. In the example of FIG. 1 , the memory controller 140 is shown as initially being driven to a first voltage (e.g., a high voltage, such as 1.5V) at interval 455. Selected access line 450 is shown as being driven to a high voltage (e.g., 3V), and unselected access lines 445 are shown as being driven to a different voltage (e.g., 0V). Unselected access lines 445 may be referred to as being at different voltages (e.g., 0V) because the unselected lines may be at different voltages. Figure 4B During the intervals shown in , the voltage (eg, 0 V) ​​transitions between a negative voltage.

[0067] At interval 458, plate line 440 may transition from a first voltage (e.g., a high voltage) to a second voltage (e.g., a low voltage, such as 0V). Selected access line 450 may remain at a high value (e.g., 3V), and unselected access lines 445 may be floated. In some examples, unselected access lines 445 may be floated simultaneously with plate line 440 transitioning to the second voltage, or may begin floating unselected access lines 445 at some protection period before plate line 440 transitions to the second voltage to ensure that unselected access lines 445 are floating as the voltage of plate line 440 begins transitioning.

[0068] Due to the capacitive coupling between the unselected access line 445 and the plate line 440, floating the unselected access line 445 may cause the voltage of the unselected access line 445 to track the voltage of the plate line 440. In other words, as the voltage of the plate line 440 decreases during the interval 458, it may pull down the voltage of the floating unselected access line 445 by an equal or substantially similar amount. For example, if the voltage of the plate line 440 decreases from 1.5V to 0V, the voltage of the unselected access line 445 may decrease from 0V to or approximately to -1.5V. By allowing the voltage of the unselected access line 445 to track the voltage of the plate line 440 as the voltage of the plate line 440 changes, the voltage differential between the plate line 440 and the unselected access line 445 may remain constant or substantially constant. Thus, as the voltage of plate line 440 changes, leakage current (eg, due to capacitive coupling between plate line 440 and unselected access lines 445) may be reduced or eliminated, and power consumption associated with access operations may be reduced.

[0069] During interval 460, plate line 440 may remain at a second voltage (e.g., a low voltage such as 0V), and selected access line 450 may remain at a high voltage (e.g., 3V). In some examples, unselected access line 445 may continue to float during the entire interval 460, and the voltage of unselected access line 445 may thus remain at the level achieved at the end of interval 458. In such examples, the difference between the voltage of unselected access line 445 and the voltage of plate line 440 during interval 460 may not be exactly the difference during interval 455. For example, if the voltage of plate line 440 decreases from 1.5V to 0V, the voltage of unselected access line 445 may decrease from 0V to some level that is close to, but not exactly equal to, -1.5V (e.g., -1.4V) during interval 458, and the voltage of unselected access line 445 may remain at that approximate level (e.g., -1.4V) during the entire interval 460.

[0070] In some examples, after floating, the unselected access line 445 may be driven to a desired low voltage based on and compatible with the voltage change of the plate line 440 during the interval 458, as in Figure 4B4. The unselected access line 445-a may be driven to a desired voltage based on the plate voltage swing, e.g., such that a subsequent voltage differential between plate line 440 and unselected access line 445-a is ensured to be the same as during interval 455 (e.g., if the voltage of the plate changes from 1.5V to 0V during interval 458, and the voltage of unselected access line 445 was 0V during interval 455, the voltage of unselected access line 445 may be driven to -1.5V to ensure a voltage differential of 1.5V).

[0071] In some examples, the unselected access line 445-a may be driven to the desired voltage at the beginning of the interval 460 (e.g., once the plate line 440 reaches the second voltage) or at some later time during the interval 460 (e.g., at time t'). In other examples, the unselected access line 445-a may be driven to the desired voltage at the beginning of the interval 460. Driving the unselected access line 445 to the desired voltage in order to ensure a desired voltage differential relative to the voltage of the plate line 440 (e.g., a voltage differential that is equal to the voltage differential during the interval 455) may introduce a certain amount of additional complexity as opposed to continuing to float the unselected access line 445 during the entire interval 460, but may further reduce leakage current and associated power consumption due to the changing voltage of the plate line 440, and may provide greater control over the voltage of the unselected access line 445 during the interval 460. Thus, the voltage of the unselected access line 445 may track the voltage of the plate line 440.

[0072] In interval 462, plate line 440 may be driven from a second voltage (e.g., from a low voltage) to a first voltage (e.g., to a high voltage). Selected access line 450 may remain at a high voltage (e.g., at 3V), and unselected access line 445 may be floated (either in the case where it floats during the entire interval 460, or in the case of unselected access line 445-a, at or before the plate line 440 voltage begins to transition, at some protection period). Floating unselected access line 445 may cause the voltage of unselected access line 445 to track (e.g., substantially track) the voltage of plate line 440 due to capacitive coupling between unselected access line 445 and plate line 440. Thus, as the voltage of plate line 440 increases, the voltage of unselected access line 445 may increase. By tracking the voltage of plate line 440, the voltage differential between the voltage of plate line 440 and the voltage of unselected access line 445 may remain constant or substantially constant. Thus, leakage current associated with plate line 440 and unselected access line 445 may be mitigated, and power consumption of the associated memory device may be reduced.

[0073] At interval 465, the selected access line 450 may remain at a high voltage (e.g., 3V). The plate line 440 may return to the first voltage (e.g., high voltage), as described at interval 455, and the unselected access lines 445 may be driven to a high voltage (e.g., 0V). As described above, the unselected access lines 445 may be referred to as being at a high voltage (e.g., 0V) due to transitioning between a high voltage (e.g., 0V) and a negative voltage.

[0074] Despite Figure 4B 4. In the example of , the plate line 440 is shown as transitioning from a high voltage to a low voltage and back to a high voltage, but in some examples, the techniques described herein may be applied when the plate line 440 transitions from a low voltage to a high voltage and back to a low voltage. When the plate line 440 transitions from a low voltage to a high voltage or from a high voltage to a low voltage, this may be referred to as switching or toggling the voltage of the plate line 440. Regardless of the direction of the switching, when the voltage of the plate line 440 is switched, the unselected access lines 445, 445-a may be floated.

[0075] In various examples, plate switching can occur and thus the unselected access lines 445, 445-a can be floated at any time associated with an access operation. For example, the unselected access lines 445, 445-a can be floated before, during, or after accessing (e.g., reading from or writing to) a selected memory cell.

[0076] In some of the examples described herein, operations supporting techniques for access line management are described in the context of a memory cell array having one common plate (i.e., common to all memory cells of the array). It should be understood that the same techniques described herein may be supported by a memory cell array that includes more than one common plate, where each plate may be common to a subset of memory cells of the array. Thus, the techniques described herein may be applied in the context of a memory array having any number of plates.

[0077] In the examples described herein, the absolute voltage levels described (eg, 3V, 0V, -1.5V, etc.) are for illustrative purposes only. Thus, any absolute voltage levels different from those described herein may be used.

[0078] Figure 5A An example of a memory device 500-a supporting techniques for access line management of a memory cell array according to an example of the present invention is shown. In some examples, the memory device 500-a may include a driver 505, which may be referred to as a memory driver 505. The memory driver 505 may be coupled to any number of access lines and may facilitate one or more memory cells (e.g., as described in reference Figure 3Memory driver 505 may be coupled to, for example, access line 520, access line 525, access line 530, access line 535, and access line 537. Each of access lines 520, 525, 530, 535, and 537 may be a word line of a memory array (e.g., as described in reference to FIG. 1 ). Figure 3 Memory driver 505 may include various subcomponents, such as driver component 510 and driver component 515. In other examples (not shown), memory driver 505 may contain any number of subcomponents (such as any number of driver components).

[0079] As described above, each of the access lines 520, 525, 530, 535, and 537 can be a memory array (e.g., as described in reference Figure 3 For example, access line 520 may be or may be referred to as a first access line 520, access line 525 may be or may be referred to as a second access line 525, and access line 530 may be or may be referred to as a third access line 530.

[0080] Additionally or alternatively, access line 430 and access line 435 may be examples of access lines representing a total number of access lines associated with memory device 500-a. For example, access line 537 may be referred to as access line "AL". n ”, where “n” is the total number of access lines associated with the memory array, and access line 535 may be referred to as access line “AL”. n-1 ”. In some examples, a memory array associated with driver 505 may include 1024 access lines (e.g., word lines), so access line 535 may represent the 1023rd access line of the memory array, and access line 537 may represent the 1024th access line of the memory array. Each of access lines 520, 525, 530, 535, and 537 may be associated with an individual memory cell—e.g., no memory cells 105 may be common across access lines 520, 525, 530, 535, and 537, regardless of whether any of access lines 520, 525, 530, 535, and 537 are associated with a single memory cell 105 or a plurality of memory cells 105.

[0081] In some examples, the memory driver 505 can facilitate access operations to memory cells coupled to one of the access lines 520, 525, 530, 535, and 537. For example, an access operation can be performed on a memory cell coupled to the access line 525, which can be referred to as a second memory cell. In some examples, a memory controller (e.g., as described in reference Figure 1105 ) may identify an access operation associated with the second memory cell. The driver 505 may then float the first access line 520 (e.g., for a duration). In other examples, the driver 505 may float each of the access lines 520-537 except for the access line 525. In other words, the driver 505 may float each unselected access line associated with the memory cell 105 that has a common plate with the selected memory cell. By floating the unselected access lines, the voltage of each unselected access line may track the voltage of the associated plate (e.g., as described with reference to FIG. 105 ). Figure 3 The voltage of the plate 325) described.

[0082] In some examples, the driver 505 may float the unselected access lines using multiple floating operations and / or using multiple subcomponents. For example, a first subset of unselected access lines may be floated using a first floating operation and / or a first combination of subcomponents of the driver 505, and a second subset of unselected access lines may be floated using a second floating operation and / or a second combination of subcomponents of the driver 505. Because the driver 505 may be coupled to all access lines except one unselected access line (e.g., to 1023 unselected access lines out of 1024 unselected access lines) depending on the size of the memory array, the first subset of unselected access lines floated using the first floating operation and / or the first combination of subcomponents and the second subset of unselected access lines floated using the second floating operation and / or the second combination of subcomponents may total 1023 access lines.

[0083] In some cases, a subcomponent of driver 505 (e.g., driver component 510) may be common to a selected access line (e.g., access line 520) and one or more unselected access lines (e.g., access lines 525, 530), while one or more other subcomponents of driver 505 (e.g., driver component 515) may be common to a plurality of other unselected access lines (e.g., access lines 535, 537). In such examples, driver component 510 may operate unselected access lines 525, 530 differently than driver component 515 may operate unselected access lines 535, 537. For example, driver component 515 may operate unselected access lines 535, 537 substantially as described with reference to FIG. 4, while driver component 510 may drive (rather than float) unselected access lines 525, 530 to voltages configured to minimize voltage stress on components (e.g., transistors) within driver component 510 because driver component 510 is common to selected access line 520.

[0084] In the examples described above, memory driver 505 may include any number of subcomponents, and each subcomponent may be coupled with any number of access lines. For example, memory driver 505 may include a separate driver component for each access line, or may include a separate driver component for each unique subset of access lines.

[0085] Figure 5B An example timing diagram 500-b is shown that supports techniques for access line management for a memory cell array according to an example of the present invention. In some examples, the timing diagram 500-b may be shown similar to the timing diagram described above with reference to Figure 5A 500 - a. In some examples, timing diagram 500 - b may depict voltages of plate line 540, unselected access lines 545, 545 - a, selected access line 550, and a subset of unselected access lines 552. Timing diagram 500 - b may depict voltages of plate line 540, unselected access lines 545, 545 - a, selected access line 550, and a subset of unselected access lines 552 during intervals 555, 558, 560, 562, and 565. In some examples, the subset of unselected access lines 552 may be or may refer to a subset of unselected access lines 552 that share one or more drivers or driver components with selected access line 550 (e.g., as described above with reference to FIG. 1 ). Figure 5A The unselected access lines of the driver assembly 510) are depicted.

[0086] As described above, a memory array may include a plurality of corresponding access lines for a plurality of memory cells (e.g., as described above with reference to Figure 5A 520, 525, 530, 535, and 537), each memory cell having a common plate. Each access line may be referred to as a word line, and may be selected or unselected (e.g., by a driver) based on a particular access operation. Any one access line may be selected during a particular access operation, and the remaining number of access lines associated with the plate may remain unselected during that operation. For example, the memory cells common to a plate may be associated with 1024 access lines (e.g., word lines). Thus, during an access operation, one access line associated with a memory cell to be accessed may be selected (e.g., selected access line 550), and the remaining number of access lines may remain unselected (e.g., unselected access lines 545, 545-a). As described above with reference to Figure 3 As depicted, a plate (eg, plate line 540) can be coupled to a memory array.

[0087] An access operation associated with a memory cell may be identified (e.g., by reference to Figure 1140 is shown as initially driven to a first voltage (e.g., a high voltage) at interval 555. Selected access line 550 is shown as being driven to a high voltage (e.g., 3V), and unselected lines 445, 552 are shown as being driven to a different voltage (e.g., 0V). Unselected access line 445 may be referred to as being at a different voltage (e.g., 0V) because the unselected lines may transition between that voltage (e.g., 0V) and a negative voltage.

[0088] At interval 558, plate line 540 may transition from a first voltage (e.g., a high voltage) to a second voltage (e.g., a low voltage). Selected access line 550 may remain at a high value (e.g., 3V), and unselected access line 545 may be floated. In some examples, floating unselected access line 545 may begin simultaneously with plate line 540 transitioning to the second voltage, or may begin before plate line 540 transitions to the second voltage. Floating unselected access line 545 may cause the voltage of unselected access line 545 to track the voltage of plate line 540 due to capacitive coupling between the unselected access line and plate line 540. In other words, as the voltage of plate line 540 decreases during interval 558, it may pull the voltage of floating unselected access line 545 down by an equal or substantially similar amount.

[0089] For example, if the voltage of plate line 540 is reduced from 1.5 V to 0 V, the voltage of unselected access line 545 may be reduced from 0 V to or approximately to -1.5 V. By allowing the voltage of unselected access line 545 to track the voltage of plate line 540 as the voltage of plate line 540 changes, the voltage differential between plate line 540 and unselected access line 545 may be kept constant or substantially constant. Thus, as the voltage of plate line 540 changes, leakage current (e.g., due to capacitive coupling between plate line 540 and unselected access line 545) may be reduced or eliminated, and power consumption associated with access operations may be reduced.

[0090] During interval 560, plate line 540 may remain at a second voltage (e.g., a low voltage), and selected access line 550 may remain at a high voltage (e.g., 3V). In some examples, unselected access line 545 may continue to float during the entire interval 560, and the voltage of unselected access line 545 may thus remain at the level achieved at the end of interval 558. In such examples, the difference between the voltage of unselected access line 545 and the voltage of plate line 540 during interval 560 may not be exactly the difference during interval 555. For example, if the voltage of plate line 540 decreases from 1.5V to 0V, the voltage of unselected access line 545 may decrease from 0V to some level that is close to, but not exactly equal to, -1.5V (e.g., -1.4V) during interval 558, and the voltage of unselected access line 545 may remain at that approximate level (e.g., -1.4V) during the entire interval 560.

[0091] In some examples, after floating, the unselected access line 545 may be driven to a desired low voltage based on and compatible with the voltage change of the plate line 540 during the interval 458, as in Figure 5B 558 is shown by unselected access line 545-a. Unselected access line 545-a may be driven to a desired voltage based on the plate voltage swing, e.g., such that a subsequent voltage differential between plate line 540 and unselected access line 545-a is ensured to be the same as during interval 555 (e.g., if the voltage of the plate changes from 1.5V to 0V during interval 558, and the voltage of unselected access line 545 was 0V during interval 555, the voltage of unselected access line 545 may be driven to -1.5V to ensure a voltage differential of 1.5V).

[0092] In some examples, the unselected access line 545-a may be driven to the desired voltage at the beginning of the interval 560 (e.g., once the plate line 540 reaches the second voltage) or at some later time during the interval 560 (e.g., at time t'). In other examples, the unselected access line 545-a may be driven to the desired voltage at the beginning of the interval 560. Driving the unselected access line 545 to the desired voltage in order to ensure a desired voltage differential relative to the voltage of the plate line 540 (e.g., a voltage differential that is equal to the voltage differential during the interval 555) may introduce a certain amount of additional complexity as opposed to continuing to float the unselected access line 545 during the entire interval 560, but may further reduce leakage current and associated power consumption due to the changing voltage of the plate line 540, and may provide greater control over the voltage of the unselected access line 545 during the interval 560. Thus, the voltage of the unselected access line 545 may track the voltage of the plate line 540.

[0093] At interval 562, plate line 540 may be driven from a second voltage (e.g., from a low voltage) to a first voltage (e.g., to a high voltage). Selected access line 550 may remain at a high voltage (e.g., at 3V), and unselected access line 545 may be floated (either remaining floating in the case where it floats during the entire interval 460, or beginning to float at some protection period before or when the plate line 540 voltage begins to transition in the case of unselected access line 545-a). Floating unselected access line 545 may cause the voltage of unselected access line 545 to track (e.g., substantially track) the voltage of plate line 540 due to capacitive coupling between unselected access line 545 and plate line 540. Thus, as the voltage of plate line 540 increases, the voltage of unselected access line 545 may increase. By tracking the voltage of plate line 540, the voltage differential between the voltage of plate line 540 and the voltage of unselected access line 545 may be limited. Thus, leakage current associated with plate line 540 and unselected access line 545 may be mitigated, and power consumption of the associated memory device may be reduced.

[0094] At interval 565, selected access line 550 may remain at a high voltage (e.g., 3V). Plate line 540 may return to a first voltage (e.g., a high voltage), as described at interval 555, and unselected access lines 545 may be driven to a high voltage (e.g., 0V). As described above, unselected access lines 545 may be referred to as being at a high voltage (e.g., 0V) due to transitioning between a high voltage (e.g., 0V) and a negative voltage.

[0095] As described above, the subset of unselected access lines 552 may be maintained at a constant voltage (e.g., 0V) throughout intervals 555, 558, 560, 562, and 565. Because the subset of unselected access lines 552 may be or may refer to a plurality of driver components that share one or more driver components with the selected access line 550 (e.g., as described above with reference to Figure 5A 510) described above, such a configuration may provide unselected access lines to a memory device (e.g., as described in reference Figure 5A The memory device 500-a described in reference Figure 4A However, in some examples, such a configuration can reduce voltage stress and thus reduce the necessary voltage tolerance of one or more transistors (e.g., one or more transistors located within a driver component) that are common between unselected access lines 545, 545-a and selected access line 550.

[0096] Additionally or alternatively, the voltage differential between the selected access line 550 and the subset of unselected access lines 552 may be less than that described above with reference to Figure 4BThe voltage differential between the selected access line 450 and the unselected access lines 445, 445-a is described. For example, as described above with reference to Figure 4B As described, the voltage differential between the selected access line 450 and the unselected access lines 445, 445-a can be 4.5V (eg, the unselected access lines 445, 445-a are at -1.5V; the selected access line is at 3V). Figure 5B As described, the voltage differential between the selected access line 450 and the subset of unselected access lines 552 may be 3V (e.g., the subset of unselected access lines 552 is at 0V; the selected access line is at 3V). It should be understood that where the driver 505 includes multiple driver components 510, each driver component may support operating any one corresponding access line as described with reference to the selected access line 550, while operating any other corresponding access line as described with reference to the subset of unselected access lines 552, and operating all corresponding access lines as described with reference to the unselected access lines 545, depending on whether any access line corresponding to the driver component 510 is selected.

[0097] Despite Figure 5B , but in some examples, the techniques described herein may be applied when plate line 540 transitions from a low voltage to a high voltage or from a high voltage to a low voltage, which may be referred to as switching or toggling the voltage of plate line 540. Regardless of the direction of switching, when the voltage of plate line 540 is switched, unselected access lines 545, 545-a, and / or a subset of unselected access lines 552 may be floated.

[0098] In various examples, plate switching can occur and thus the unselected access lines 545, 545-a, and / or a subset of the unselected access lines 552 can be floated at any time associated with an access operation. For example, the unselected access lines 545, 545-a, and / or a subset of the unselected access lines 552 can be floated before, during, or after accessing (e.g., reading from or writing to) a selected memory cell.

[0099] In some of the examples described herein, operations supporting techniques for access line management are described in the context of a memory cell array having one common plate (i.e., common to all memory cells of the array). It should be understood that the same techniques described herein may be supported by a memory cell array that includes more than one common plate, where each plate may be common to a subset of memory cells of the array. Thus, the techniques described herein may be applied in the context of a memory array having any number of plates.

[0100] In the examples described herein, the absolute voltage levels described (eg, 3V, 0V, -1.5V, etc.) are for illustrative purposes only. Thus, any absolute voltage levels different from those described herein may be used.

[0101] Figure 6 A block diagram 600 is shown of an access line manager 615 that supports access line management for a memory cell array in accordance with an embodiment of the present invention. The access line manager 615 may be a reference Figure 7 An example of aspects of the described access line manager 715. The access line manager 615 may include a bias component 620, a timing component 625, a drive component 630, an identification component 635, a float component 640, and an initiation component 645. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0102] The driving component 630 may drive a plate coupled to at least a first memory cell of the memory cell array to a first voltage. In some examples, the driving component 630 may drive the plate from the first voltage to the second voltage based on an access operation associated with the second memory cell during the duration. In other examples, the driving component 630 may drive the first access line to a desired voltage after the duration based at least in part on a difference between the first voltage and the second voltage. Additionally or alternatively, the driving component 630 may drive the plate from the second voltage to the first voltage. In some examples, the driving component 630 may drive a second access line coupled to the second memory cell to a third voltage during the duration. In other examples, the driving component 630 may drive a third access line coupled to the third memory cell to a fourth voltage during the duration while driving the plate from the first voltage to the second voltage.

[0103] The identification component 635 can identify an access operation associated with a second memory cell of the memory cell array.

[0104] The floating component 640 may float a first access line coupled to a first memory cell of the memory cell array for a duration based on an access operation associated with the second memory cell. In other examples, the floating component 640 may float the first access line after driving the first access line to a desired voltage while driving the plate from the second voltage to the first voltage. In other examples, the floating component 640 may float the first access line for a second duration immediately following the duration. Additionally or alternatively, the floating component 640 may simultaneously float the first access line and drive the plate to the second voltage.

[0105] The start component 645 may initiate driving the third access line to a fifth voltage. The fifth voltage may be associated with the second logic value of the third memory cell. In some examples, the start component 645 may initiate driving the plate from the first voltage to the second voltage based on an access operation associated with the second memory cell. In some examples, the start component 645 may initiate floating the first access line based on an access operation associated with the second memory cell. Additionally or alternatively, the start component 645 may initiate driving a third access line associated with a third memory cell of the set of memory cells to a third voltage based on an access operation associated with the second memory cell.

[0106] It should be understood that in some cases, one or more components of access line manager 615 (eg, bias component 620, drive component 630, and float component 640) may be combined.

[0107] Figure 7 A diagram of a system 700 including a device 705 supporting access line management for a memory cell array according to an embodiment of the present invention is shown. The device 705 may be as described above, for example with reference to Figure 1 Examples of or including components of the memory array 100 are described. Device 705 may include components for two-way voice and data communications, including components for transmit and receive communications, including access line manager 715, memory unit 720, basic input / output system (BIOS) component 725, processor 730, I / O controller 735, and peripheral components 740. These components may communicate electronically via one or more buses, such as bus 710.

[0108] Memory cell 720 can store information (ie, in the form of logic states) as described herein.

[0109] BIOS component 725 is a software component including BIOS operating as firmware that can initialize and run various hardware components. BIOS component 725 can also manage the data flow between the processor and various other components (such as peripheral components, input / output control components, etc.). BIOS component 725 can include a program or software stored in a read-only memory (ROM), flash memory, or any other non-volatile memory.

[0110] The processor 730 may include an intelligent hardware device such as a general purpose processor, a DSP, a central processing unit (CPU), a microcontroller, an ASIC, an FPGA, a programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof. In some cases, the processor 730 may be configured to operate the memory array using a memory controller. In other cases, the memory controller may be integrated into the processor 730. The processor 730 may be configured to execute computer readable instructions stored in the memory to perform various functions such as functions or tasks that support access line management for the memory cell array.

[0111] I / O controller 735 can manage input and output signals for device 705. I / O controller 735 can also manage peripherals that are not integrated into device 705. In some cases, I / O controller 735 can represent a physical connection or port to an external peripheral. In some cases, I / O controller 735 can utilize, for example, or another known operating system. In other cases, I / O controller 735 may represent or interact with a modem, keyboard, mouse, touch screen, or similar device. In some cases, I / O controller 735 may be implemented as part of a processor. In some cases, a user may interact with device 705 via I / O controller 735 or via hardware components controlled by I / O controller 735.

[0112] Peripheral components 740 may include any input or output device, or an interface for such a device. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot.

[0113] Input 745 may represent a device or signal external to device 705 that provides input to device 705 or its components. This may include a user interface, or an interface with or between other devices. In some cases, input 745 may be managed by I / O controller 735 and may interact with device 705 via peripheral components 740.

[0114] Output 750 may also represent a device or signal external to device 705 that is configured to receive output from device 705 or any component thereof. Examples of output 750 may include a display, an audio speaker, a printing device, another processor or printed circuit board, etc. In some cases, output 750 may be a peripheral element that interfaces with device 705 via peripheral component 740. In some cases, output 750 may be managed by I / O controller 735.

[0115] The components of device 705 may include circuitry designed to perform its functions. This may include various circuit elements, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to perform the functions described herein. Device 705 may be a computer, server, laptop, notebook, tablet, mobile phone, wearable electronic device, personal electronic device, or the like. Alternatively, device 705 may be a portion or aspect of such a device.

[0116] Figure 8 A flow chart illustrating a method 800 for access line management of a memory cell array according to an example of the present invention is shown. The operations of the method 800 may be implemented by a memory controller or components thereof as described herein. For example, the operations of the method 800 may be implemented by a memory controller or components thereof as described herein. Figure 6 The described access line manager is executed.

[0117] At 805, a plate coupled to at least a first memory cell of an array of memory cells may be driven to a first voltage. The operations of 805 may be performed according to methods described herein. In some examples, aspects of the operations of 805 may be described as described in reference to Figure 6 The described drive components execute.

[0118] At 810, an access operation associated with a second memory cell of the memory cell array may be identified. The operations of 810 may be performed according to the methods described herein. In some examples, aspects of the operations of 810 may be described in detail with reference to Figure 6 The described identification component performs.

[0119] At 815, a first access line coupled to a first memory cell of the memory cell array may be floated for a duration based at least in part on an access operation associated with a second memory cell. The operations of 815 may be performed according to methods described herein. In some examples, aspects of the operations of 815 may be described as described with reference to Figure 6 The described floating component is implemented.

[0120] At 820, the plate may be driven from the first voltage to the second voltage during the duration based at least in part on the access operation associated with the second memory cell. The operations of 820 may be performed according to the methods described herein. In some examples, aspects of the operations of 820 may be described as described in reference to Figure 6 The described drive components execute.

[0121] Fig. 9A flow chart illustrating a method 900 for access line management of a memory cell array according to an example of the present invention is shown. The operations of the method 900 may be implemented by a memory controller or components thereof as described herein. For example, the operations of the method 900 may be implemented by a memory controller or components thereof as described herein. Figure 6 The described access line manager is executed.

[0122] At 905, a plate coupled to at least a first memory cell of an array of memory cells may be driven to a first voltage. The operations of 905 may be performed according to methods described herein. In some examples, aspects of the operations of 905 may be described as described in reference to Figure 6 The described drive components execute.

[0123] At 910, an access operation associated with a second memory cell of the memory cell array may be identified. The operations of 910 may be performed according to the methods described herein. In some examples, aspects of the operations of 910 may be described in detail with reference to Figure 6 The described identification component performs.

[0124] At 915, a first access line coupled to a first memory cell of the memory cell array may be floated for a duration based at least in part on an access operation associated with a second memory cell. The operations of 915 may be performed according to methods described herein. In some examples, aspects of the operations of 915 may be described as described with reference to Figure 6 The described floating component is implemented.

[0125] At 920, the plate may be driven from the first voltage to the second voltage during the duration based at least in part on the access operation associated with the second memory cell. The operations of 920 may be performed according to the methods described herein. In some examples, aspects of the operations of 920 may be described as described in reference to Figure 6 The described drive components execute.

[0126] At 925, the first access line may be driven to a desired voltage after the duration based at least in part on the difference between the first voltage and the second voltage. The operations of 925 may be performed according to the methods described herein. In some examples, aspects of the operations of 925 may be described as described with reference to Figure 6 The described drive components execute.

[0127] Fig.10 A flow chart illustrating a method 1000 for access line management of a memory cell array according to an example of the present invention is shown. The operations of the method 1000 may be implemented by a memory controller or components thereof as described herein. For example, the operations of the method 1000 may be implemented by a memory controller or components thereof as described herein. Figure 6 The described access line manager is executed.

[0128] At 1005, a plate coupled to at least a first memory cell of a memory cell array may be driven to a first voltage. The operations of 1005 may be performed according to methods described herein. In some examples, aspects of the operations of 1005 may be described as described with reference to Figure 6 The described drive components execute.

[0129] At 1010, an access operation associated with a second memory cell of the memory cell array may be identified. The operations of 1010 may be performed according to the methods described herein. In some examples, aspects of the operations of 1010 may be described with reference to Figure 6 The described identification component performs.

[0130] At 1015, a first access line coupled to a first memory cell of the memory cell array may be floated for a duration based at least in part on an access operation associated with a second memory cell. The operations of 1015 may be performed according to methods described herein. In some examples, aspects of the operations of 1015 may be described as in reference to Figure 6 The described floating component is implemented.

[0131] At 1020, the plate may be driven from the first voltage to the second voltage during the duration based at least in part on an access operation associated with the second memory cell. The operations of 1020 may be performed according to the methods described herein. In some examples, aspects of the operations of 1020 may be described as described with reference to Figure 6 The described drive components execute.

[0132] At 1025, the first access line may be floated for a second duration immediately following the duration. The operations of 1025 may be performed according to the methods described herein. In some examples, aspects of the operations of 1025 may be described as described with reference to Figure 6 The described floating component is implemented.

[0133] In some cases, the method may include driving a plate coupled to at least a first memory cell of the memory cell array to a first voltage. In some examples, floating the first access line and driving the plate to a second voltage may occur simultaneously. In other examples, the method may include floating a first access line coupled to a first memory cell of the memory cell array for a duration based at least in part on an access operation associated with the second memory cell.

[0134] In some cases, the method may include driving the plate from the first voltage to the second voltage during the duration based at least in part on an access operation associated with the second memory cell. In some examples, the method may include driving the first access line to a desired voltage after the duration based at least in part on a difference between the first voltage and the second voltage. Additionally or alternatively, the method may include driving the plate from the second voltage to the first voltage. In other cases, the method may include identifying an access operation associated with a second memory cell of the memory cell array.

[0135] In some cases, the method may include driving a second access line coupled to a second memory cell to a third voltage during the duration. In some examples, the method may include driving a third access line coupled to a third memory cell to a fourth voltage during the duration when the plate is driven from the first voltage to the second voltage. In some cases, the method may include floating the first access line for a second duration immediately following the duration. Additionally or alternatively, the plate may be coupled to a plurality of memory cells of the memory cell array. The plurality of memory cells may include a first memory cell and a second memory cell.

[0136] In some cases, the plate may be coupled to a first set of rows or columns of memory cells of the memory cell array and to a second set of rows or columns of memory cells of the memory cell array. In other cases, the method may include floating the first access line after driving the plate to the second voltage when driving the plate from the second voltage to the first voltage.

[0137] Fig.11 An example of a circuit 1100 supporting techniques for access line management of a memory cell array according to an example of the present invention is shown. In some examples, the circuit 1100 may include a driver 1105, which in some cases may be an example of a word line driver. The driver 1105 may be coupled to an access line 1110, which in some cases may be an example of a word line as discussed herein. The driver 1105 may facilitate access operations of one or more memory cells coupled to the access line 1110. In some examples, the circuit 1100 may be coupled to or included in an access line decoder, such as a word line decoder (or row decoder) or a digit line decoder (or column decoder), as described herein.

[0138] Driver 1105 may be coupled to various control circuits, such as control circuit 1115, control circuit 1120, and control circuit 1125. Operation of driver 1105 and / or control circuits 1115, 1120, and / or 1125 may facilitate access operations of one or more memory cells as described herein. It should be understood that in some cases, one or more structural or functional aspects of control circuits 1115, control circuits 1120, and control circuits 1125 may alternatively be integrated into driver 1105 or otherwise considered part of driver 1105.

[0139] In some examples, driver 1105 may represent one of a plurality of word line drivers of a memory device. For example, driver 1105 may represent one of 1,024 word line drivers of a memory device. It should be understood that here and elsewhere, specific numbers are for clarity of description only, and the claims are not limited thereto. Each driver 1105 may include one or more transistors. For example, driver 1105 may include a transistor 1130 (e.g., a first transistor 1130) and a transistor 1135 (e.g., a second transistor 1135). The first transistor 1130 and the second transistor 1135 may be arranged in a common source and common gate configuration. Driver 1105 may also include a transistor 1140 (e.g., a third transistor 1140) and a transistor 1145 (e.g., a fourth transistor 1145). In some examples, the first transistor 1130 and the second transistor 1135 may be PMOS transistors, and the third transistor 1140 and the fourth transistor 1145 may be NMOS transistors.

[0140] In some examples, driver 1105 can include node 1180, which can be referred to as an output node of driver 1105 and can be coupled to access line 1110. Node 180 can also be coupled to a drain terminal of second transistor 1135, a source terminal of fourth transistor 1145, and a source terminal of third transistor 1140.

[0141] The driver 1105 may also include one or more nodes configured to receive control signals from the control circuits 1115, 1120, and / or 1125. For example, the driver 1105 may include a node 1170 (e.g., a first node 1170) configured to receive a control signal 1160 from the control circuit 1125. The node 1170 may refer to a terminal (e.g., a source terminal) of the first transistor 1130. In some instances, the control signal 1160 may be referred to as ARFX. The driver 1105 may also include a node 1185 (e.g., a third node) configured to receive a control signal 1167 from the control circuit 1125. The node 1185 may refer to a gate of the third transistor 1140. In some instances, the control signal 1185 may be referred to as ARFX' and may be inverted relative to the control signal 1160.

[0142] The word line driver may also include a node 1175 (e.g., a second node) configured to receive a control signal 1165 from the control circuit 1120. The node 1175 may refer to a terminal (e.g., a source terminal) of the third transistor 1140 and a terminal (e.g., a source terminal) of the fourth transistor 1145, which may be coupled to each other. In some examples, the state of the control signal 1165 may be based on a setting of the control circuit 1120.

[0143] In some examples, the driver 1105 can be configured to receive two control signals from the control circuit 1115. The first control signal 1150 generated by the control circuit 115 can be referred to as MWLF_H and can be received at the gate of the transistor 1130. In addition, the gate of the fourth transistor 1145 can be configured to receive a second control signal 1155 from the control circuit 1115. The control signal 1155 can be referred to as MWLF_L. In some examples, the control signal 1150 can have a different (e.g., higher) voltage swing than the control signal 1155.

[0144] Fig.11 The control circuit 1115 shown in can be one of a plurality of control circuits 1115 of a memory device. For example, the control circuit 1115 can represent one of sixty-four (64) control circuits 1115 of a memory device. That is, continuing with the above example, where 1,024 drivers 1105 are each coupled to a corresponding access line 1110, a single control circuit 1115 can be coupled to sixteen (16) drivers 1105. Thus, for each control circuit 1115, the control signal 1150 and the control signal 1155 generated and output by the control circuit 1115 can be common to (received by each of) the sixteen (16) drivers 1105.

[0145] In some examples, as explained above, control signal 1150 may be applied to the gate of transistor 1130 of driver 1105. For example, applying control signal 1150 to the gate of transistor 1130 may cause transistor 1130 to be activated (e.g., turned on) when the control signal is in a low state (low voltage) or to be deactivated (e.g., turned off) when the control signal is in a high state (high voltage) because transistor 1130 may be a PMOS device. Similarly, applying control signal 1155 to the gate of transistor 1145 may cause transistor 1145 to be activated (e.g., turned on) when the control signal is in a high state (high voltage) or to be deactivated when the control signal is in a low state (low voltage) because transistor 1145 may be an NMOS device.

[0146] Control signals 1150 and 1155 may have different voltage swings from each other. For example, the voltage swing of control signal 1155 may be less than the voltage swing of control signal 1150, or vice versa. In some examples, each of control signals 1150 and 1155 may be associated with the same lower limit (e.g., 0V), but may have different upper limits. For example, the upper limit of control signal 1150 may be 3V, while the upper limit of control signal 1155 may be 1.5V. In some examples, different control circuits 1115 in multiple control circuits within the same device may apply different control signals to different corresponding drivers 1105 during various stages of an access operation.

[0147] In some cases, configuring the control circuit 1115 to generate and output two different control signals 1150 and 1155 to the driver 1105 and further that the two control signals 1150 and 1155 have different voltage swings can avoid placing undue stress (e.g., excessive voltage) on one or more components (e.g., transistors) of the driver 1105, which can support the use of low voltage tolerant devices, which can provide space, switching speed, and efficiency benefits, as well as other benefits that can be understood by those skilled in the art. Additionally or alternatively, including the transistor 1135 in a cascode configuration with the transistor 1130 can avoid placing undue stress (e.g., excessive voltage) on one or more components (e.g., transistors) of the driver 1105, which can support the use of low voltage tolerant devices, which can provide space, switching speed, and efficiency benefits, as well as other benefits that can be understood by those skilled in the art.

[0148] Fig.11 The control circuit 1120 shown in can be one of a plurality of control circuits 1120 of a memory device. For example, the control circuit 1120 can represent one of sixteen (16) control circuits 1120 of a memory device. That is, following the above example, where 1,024 drivers 1105 are each coupled to a corresponding access line 1110, a single control circuit 1120 can be coupled to sixty-four (64) drivers 1105. Thus, for each control circuit 1120, the control signal 1165 generated and output by the control circuit 1120 can be common to (received by each of) the sixty-four (64) drivers 1105. The control circuit 1120 can be configured to apply the control signal 1165 to a corresponding node 1175 of each driver 1105 coupled to the control circuit 1120.

[0149] In some examples, at different times during an access operation of one or more memory cells within a memory device, the control signal 1165 may drive the node 1175 to a relatively high voltage, which may be referred to as VNWL (e.g., 0V), may drive the node 1175 to a relatively low voltage, which may be referred to as VNNWL (e.g., -1.5V, VNNWL), or may cause the node 1175 to electrically float (e.g., FLOAT). The state of the control signal 1165 may be based on one or more control signals received by the control circuit 1120 (e.g., from a controller). The voltage swing between the possible voltages of the control signal 1165 may be the same as the voltage variation of the plate of the memory device during the access operation. That is, the voltage swing between the relatively high voltage and the relatively low voltage may be 1.5V, which may be the same as the voltage variation of the plate during the access operation (e.g., if the plate changes from 1.5V to 0V). In some examples, different control circuits 1120 of multiple control circuits within the same device may apply different control signals to different corresponding drivers 1105 during various stages of the access operation.

[0150] Fig.11 The control circuit 1125 shown in can be one of a plurality of control circuits 1125 of a memory device. For example, the control circuit 1125 can represent one of sixteen (16) control circuits 1125 of a memory device. That is, following the above example, where 1,024 drivers 1105 are each coupled to a corresponding access line 1110, a single control circuit 1125 can be coupled to sixty-four (64) drivers 1105. Thus, for each control circuit 1125, the control signals 1160 and 1167 generated and output by the control circuit 1125 can be common to (received by each of) the sixty-four (64) drivers 1105. Each control circuit 1125 can be configured to apply the control signal 1160 to a corresponding node 1170 of each driver 1105 coupled to the control circuit 1125 and / or to a corresponding node 1185. In some cases, the control circuit 1125 can be associated with the corresponding control circuit 1120 so that both the control circuit 1125 and the corresponding control circuit 1120 can be coupled to the same set of drivers 1105, that is, if two or more drivers 1105 are coupled to the same control circuit 1125, then they can also be coupled to the same control circuit 1120.

[0151] In some examples, the control circuit 1125 may include transistors 1190, 1192, and 1194. Transistors 1190 and 1192 may be NMOS transistors, and transistor 1194 may be a PMOS transistor. In some examples, transistor 1190 may be arranged in a common source and common gate configuration with transistor 1192. In some examples, a terminal (e.g., a source terminal) of transistor 1194 may be coupled to a first voltage source (e.g., VCCP), and a terminal (e.g., a source terminal) of transistor 1190 may be coupled to a different voltage source (e.g., VSS). Transistors 1190, 1192, and 1194 may include (implement) an inverter, but the number of transistors on the two legs of the inverter is asymmetric. In addition, the control circuit 1125 may also include a second inverter 1196, which may be coupled to the gate of transistor 1194 and / or transistor 1190.

[0152] The control circuit 1125 may be configured to output (e.g., generate) a control signal 1160 and a control signal 1167. The control signals 1160 and 1167 may have opposite logic to each other (e.g., due to an inverter formed between the respective output nodes of the control signals 1160 and 1167 by transistors 1190, 1192, and 1194). That is, when one is high, the other is low.

[0153] In some examples, the control circuit 1125 may also be configured to float the node 1170 based on the FLOAT2 control signal. The FLOAT2 control signal may be received by the control circuit 1125 (e.g., from a controller) and may electrically float the control signal 1160 when valid. In some examples, FLOAT2 may be active low, and when FLOAT2 is high, transistors 1190, 1192, and 1194 may act as inverters in series with the inverter 1196. However, if FLOAT2 is low when the output of the inverter 1196 is high, the control signal 1160 may float, and thus the node 1170 may float. For example, since the transistor 1194 is deactivated (e.g., turned off) because the output of the inverter 1196 is high and the transistor 1192 is deactivated (e.g., turned off) because the FLOAT2 is low, the node 1170 may float. In some examples, different control circuits 1125 of multiple control circuits within the same device may apply different control signals to different corresponding drivers 1105 during various stages of an access operation.

[0154] Fig. 12A An example timing diagram 1200-a is shown that supports techniques for access line management for a memory cell array according to an example of the present invention. In some examples, the timing diagram 1200-a may be similar to the timing diagram 1200-a described above with reference to FIG. Fig.11The access operation associated with (e.g., performed using) the described circuit 1100. In some examples, the timing diagram 1200-a can depict the voltages of the board line 1205, the word line 1110-a, the node 1170-a, and the node 1175-a. The voltages of the word line 1110-a, the node 1170-a, and the node 1175-a can illustrate the voltages applied to the reference Fig.11 The voltages of access line 1110, node 1170, and node 1175 are depicted. Timing diagram 1200-a may depict the voltages of plate line 1205, word line 1110-a, and nodes 1170-a and 1175-a during intervals 1210, 1215, 1220, 1225, and 1230.

[0155] As described herein, a memory array may include a plurality of corresponding access lines (e.g., a plurality of word lines) for a plurality of memory cells, each memory cell having a common plate. Each access line may be selected or unselected (e.g., by reference to a cell coupled to the access line) based on whether the cell is the target of (accessed by) a particular access operation. Fig.11 1105 described above). In some cases, any one access line of a given type may be selected during a particular access operation, while a remaining number of access lines of the same type associated with the board may remain unselected during that operation.

[0156] Timing diagram 1200-a may illustrate the timing of a selected access line (eg, a selected word line) similar to that described above with reference to Fig.11 The access operations associated with the described circuit 1100 may be Fig. 12A Memory cells associated with a selected access line are accessed during one or more intervals shown in .

[0157] During interval 1210, the voltage of plate line 1205 is shown as initially driven to a first voltage (e.g., a high voltage such as 1.5V). When the plate is driven to the first voltage, prior to interval 1210, word line 1110-a may be selected. Figures 12A to 12DIn some examples, the examples are described with respect to word lines, but it should be understood that the teachings can be used for any type of access line. In some examples, the word line that has been selected can be represented as the voltage of word line 1110-a being at a high voltage, such as 3V, at the beginning of interval 1210. To select word line 1110-a, control circuit 1125 can apply a high control signal 1160 to node 1170 (e.g., by activating transistor 1194), which can be based on the logic high signal received at the input of inverter 1196, and can cause the voltage of node 1170-a to be driven to a high voltage, such as 3V. When node 1170-a is at a high voltage, control circuit 1115 can apply a low control signal 1150 to transistor 1130. Low control signal 1150 can be, for example, 0V. Applying control signals 1160 and 1150 to driver 1105 can cause transistors 1130 and 1135 to be activated (e.g., turned on). Therefore, the voltage of word line 1110 - a can be driven to 3V.

[0158] In some examples, control circuit 1120 may apply a high control signal 1165 (e.g., VNWL) to node 1175. Thus, the voltage of node 1175-a may be at 0V. When node 1175 is at 0V, control circuit 1115 may apply a low control signal 1155 to transistor 1145, and control circuit 1125 may apply a low control signal 1167 to transistor 1140. Low control signals 1155 and 1167 may be, for example, 0V. Thus, applying control signals 1155 and 1167 to driver 1105 may cause transistors 1140 and 1145 to be deactivated (e.g., turned off). Thus, word line 1110-a may be isolated from node 1175.

[0159] During interval 1215, the voltage of plate line 1205 may transition from a first voltage (e.g., a high voltage) to a second voltage (e.g., a low voltage, such as 0 V). The voltage of selected word line 1110-a and the voltage of node 1170-a may remain high (e.g., 3 V), and the voltage of node 1175-a may remain low (e.g., 0 V).

[0160] During interval 1220, the voltage of plate line 1205 may remain at a second voltage (e.g., a low voltage such as 0V). The voltage of word line 1110-a and the voltage of node 1170-a may remain high (e.g., 3V), and the voltage of node 1175-a may remain low (e.g., 0V).

[0161] During interval 1225, the voltage of plate line 1205 may be driven from the second voltage (e.g., from a low voltage) to the first voltage (e.g., a high voltage). The voltage of selected word line 1110-a and the voltage of node 1170-a may remain high (e.g., 3V), and the voltage of node 1175-a may remain low (e.g., 0V).

[0162] During interval 1230, the voltage of plate line 1205 may remain at a first voltage (e.g., a high voltage). The voltage of word line 1110-a and the voltage of node 1170-a may remain high (e.g., 3V), and the voltage of node 1175-a may remain low (e.g., 0V). In the examples described herein, the absolute voltage levels described (e.g., 3V, 0V, -1.5V, etc.) are for illustrative purposes only. Therefore, any absolute voltage levels different from those described herein may be used.

[0163] In some examples, each of transistors 1130, 1135, 1140, and 1145 within driver 1105 of selected word line 1110-a may have a relatively low gate-source voltage (eg, V gs ) and / or drain-source voltage (e.g., V ds ). For example, throughout the access operation, transistors 1130, 1135, 1140, and 1145 do not have a Vgs and / or Vds greater than the voltage swing of control signal 1150 (eg, MWLF_H, which may be 3V).

[0164] Fig. 12B An example timing diagram 1200-b is shown that supports techniques for access line management for a memory cell array according to an example of the present invention. In some examples, the timing diagram 1200-b may be similar to the timing diagram 1200-b described above with reference to FIG. Fig.11 The access operation associated with (e.g., performed using) the described circuit 1100. In some examples, the timing diagram 1200-b can depict the voltages of the board line 1205, the word line 1110-b, the node 1170-b, and the node 1175-b. The voltages of the word line 1110-b, the node 1170-b, and the node 1175-b can illustrate the voltages applied to the reference Fig.11 The voltages of access line 1110, node 1170, and node 1175 are depicted. Timing diagram 1200-b may depict the voltages of plate line 1205, word line 1110-b, and nodes 1170-b and 1175-b during intervals 1210, 1215, 1220, 1225, and 1230.

[0165] As described herein, a memory array may include a plurality of corresponding access lines (e.g., a plurality of word lines) for a plurality of memory cells, each memory cell having a common plate. Each access line may be selected or unselected (e.g., by reference to a cell coupled to the access line) based on whether the cell is the target of (accessed by) a particular access operation. Fig.11 In some cases, any one access line may be selected during a particular access operation, while the remaining number of access lines of the same type associated with the board may remain unselected during that operation.

[0166] Timing diagram 1200-b may illustrate the timing of a first subset of unselected access lines as described above with reference to Fig.11 The access operations associated with the described circuit 1100 are described. For example, the timing diagram 1200-b may illustrate the shared and selected word lines (eg, as shown in reference Fig. 12A 110-b) that share the same control circuit 1120 and control circuit 1125 as the driver 1105 for the selected word line 1110-a discussed above. Thus, continuing with the above example, where 1,024 drivers 1105 are each coupled to a respective word line 1110, the voltage of the unselected word line 1110-b may illustrate the voltage of the 63 unselected word lines 1110 that share the same control circuit 1120 and control circuit 1125 as the driver 1105 for the selected word line.

[0167] During interval 1210, the voltage of plate line 1205 is shown as initially being driven to a first voltage (e.g., a high voltage, such as 1.5V). When the plate is driven to the first voltage, prior to interval 1210, one word line 1110-a may be selected, and a subset of word lines 1110 may remain unselected. In some examples, the subset of word lines remaining unselected may be represented by the voltage of word line 1110-b remaining at a low voltage, such as 0V. When the subset of word lines 1110-b is unselected but shares common control circuit 1125 with the selected word line 1110-a, control circuit 1125 may apply a high control signal 1160 to node 1170, which may cause the voltage of node 1170-b to be driven to a high voltage, such as 3V. When node 1170-b is at a high voltage, control circuit 1115, which may not be common to selected word line 1110-a and a first subset of unselected word lines 1110-b, may apply a high control signal 1150 to transistor 1130. High control signal 1150 may be, for example, 3V. Thus, applying control signals 1160 and 1150 to driver 1105 may cause transistors 1130 and 1135 to be deactivated (e.g., turned off). Thus, unselected word line 1110-b may be isolated from node 1170.

[0168] In some examples (e.g., when a subset of word lines 1110-b are not selected but share common control circuit 1120 with selected word line 1110-a), control circuit 1120 may apply a high control signal 1165 (e.g., VNWL) to node 1175. For example, the voltage of node 1175-a may be 0V. When control signal 1165 is applied to node 1175, control circuit 1115 may apply a high control signal 1155 to transistor 1145, and control circuit 1125 may apply a low control signal 1167 to transistor 1140. High control signal 1155 may be, for example, 1.5V, and low control signal 1167 may be 0V. Thus, applying control signals 1155 and 1167 to driver 1105 may cause transistor 1145 to be activated (e.g., turned on) and transistor 1140 to be deactivated (e.g., turned off). Thus, the unselected word lines may be coupled to the node 1175 via the transistor 1145, which may cause the node 1175 and the unselected word lines to have the same voltage (eg, 0 V).

[0169] During interval 1215, the voltage of plate line 1205 may transition from a first voltage (e.g., a high voltage) to a second voltage (e.g., a low voltage such as 0 V). The voltage of unselected word line 1110-b may remain low (e.g., 0 V), the voltage of node 1170-a may remain high (e.g., 3 V), and the voltage of node 1175-a may remain low (e.g., 0 V).

[0170] During interval 1220, the voltage of plate line 1205 may remain at a second voltage (e.g., a low voltage such as 0 V). The voltage of unselected word line 1110-b may remain low (e.g., 0 V), the voltage of node 1170-a may remain high (e.g., 3 V), and the voltage of node 1175-a may remain low (e.g., 0 V).

[0171] During interval 1225, the voltage of plate line 1205 may be driven from a second voltage (e.g., a low voltage) to a first voltage (e.g., a high voltage). The voltage of unselected word line 1110-b may remain low (e.g., 0V), the voltage of node 1170-a may remain high (e.g., 3V), and the voltage of node 1175-a may remain low (e.g., 0V).

[0172] During interval 1230, the voltage of plate line 1205 may remain at a first voltage (e.g., a high voltage). The voltage of unselected word line 1110-b may remain low (e.g., 0V), the voltage of node 1170-a may remain high (e.g., 3V), and the voltage of node 1175-a may remain low (e.g., 0V). In the examples described herein, the absolute voltage levels described (e.g., 3V, 0V, -1.5V, etc.) are for illustrative purposes only. Thus, any absolute voltage levels different from those described herein may be used.

[0173] In some examples, each of transistors 1130, 1135, 1140, and 1145 within driver 1105 of unselected word lines 1110-b may have a relatively low gate-source voltage (eg, V gs ) and / or drain-source voltage (e.g., V ds ). For example, throughout the access operation, transistors 1130, 1135, 1140, and 1145 do not have a Vgs and / or Vds greater than the voltage swing of control signal 1150 (eg, MWLF_H, which may be 3V).

[0174] Fig. 12C An example timing diagram 1200-c is shown that supports techniques for access line management for a memory cell array according to an example of the present invention. In some examples, the timing diagram 1200-c may be similar to the timing diagram 1200-c described above with reference to FIG. Fig.11 The access operations associated with (e.g., performed using) the described circuit 1100. In some examples, the timing diagram 1200-c can depict the voltages of the board line 1205, the word line 1110-c, the node 1170-c, and the node 1175-c. The timing diagram 1200-c can also depict alternative voltages for the word line 1110-c, as shown by the voltage trace denoted as 1110-c'. The voltages of the word line 1110-c, the node 1170-c, and the node 1175-c can illustrate the voltages applied to the reference Fig.11 Depicted are the voltages of word line 1110, node 1170, and node 1175. Timing diagram 1200-c may depict the voltages of plate line 1205, word line 1110-c, and nodes 1170-c and 1175-c during intervals 1210, 1215, 1220, 1225, and 1230.

[0175] As described herein, a memory array may include a plurality of corresponding access lines (e.g., a plurality of word lines) for a plurality of memory cells, each memory cell having a common plate. Each access line may be selected or unselected (e.g., by reference to a cell coupled to the access line) based on whether the cell is the target of (accessed by) a particular access operation. Fig.11In some cases, any one access line may be selected during a particular access operation, while the remaining number of access lines of the same type associated with the board may remain unselected during that operation.

[0176] Timing diagram 1200-c may illustrate the timing of the unselected access line subset as described above. Fig.11 The access operations associated with the described circuit 1100 are described in detail. For example, the timing diagram 1200-c may illustrate shared and selected access lines (eg, as shown in reference Fig. 12A The voltages of the word lines 1110-c discussed above for the selected word lines 1110-a) are different from the driver 1105 for the different control circuits 1115, different control circuits 1120, and different control circuits 1125. Thus, continuing with the above example, where 1,024 drivers 1105 are each coupled to a respective word line 1110, the voltage of the unselected word lines 1110-c may describe the voltages of the 945 unselected word lines 1110.

[0177] During interval 1210, the voltage of plate line 1205 is shown as initially driven to a first voltage (e.g., a high voltage, such as 1.5V). When the plate is driven to the first voltage, prior to interval 1210, a subset of word lines 1110-c may remain unselected. In some examples, word lines 1110-c remaining unselected may be represented as the voltage of word lines 1110-c remaining at a low voltage, such as 0V. When the subset of word lines is unselected and does not share a common control circuit 1125 with the selected word line 1110-a, control circuit 1125 may apply a low control signal 1160 to node 1170, which may cause the voltage of node 1170-c to be driven to a low voltage, such as 0V. When node 1170-c is at a low voltage, control circuit 1115 may apply a high control signal 1150 to transistor 1130. High control signal 1150 may be, for example, 3V. Thus, applying control signals 1160 and 1150 to driver 1105 may cause transistors 1130 and 1135 to be deactivated (eg, turned off). Thus, unselected word lines may be isolated from node 1170.

[0178] In some examples, control circuit 1115 may apply a high control signal 1155 to transistor 1145, and control circuit 1125 may apply a high control signal 1167 to node 1185. In some examples, high control signal 1155 may be 1.5V, and high control signal 1167 may be 1.5V. Thus, transistor 1145 may be activated (e.g., turned on) and transistor 1140 may be activated (e.g., turned on). Thus, unselected word line 1110-c may be coupled to node 1175 via transistor 1140 and transistor 1145, and may be the same voltage as the output of control circuit 1120 (e.g., the same voltage as the voltage of control signal 1165). During interval 1210, control circuit 1120 may output control signal 1165 corresponding to VNWL, which may be, for example, 0V. Thus, during interval 1210, the voltage of node 1175-c and the voltage of unselected word line 1110-c may be 0V.

[0179] During interval 1215, the voltage of plate line 1205 may transition from a first voltage (e.g., a high voltage) to a second voltage (e.g., a low voltage such as 0V). In some cases, during interval 1215, node 1170 may also float, which may cause the voltage of node 1170-c to float. For example, control circuit 1125 may receive a FLOAT2 control signal at the gate of transistor 1192, which may be low when the input of inverter 1196 is low, which may cause control signal 1160 to float, and thus cause node 1170 to float. Node 1170 may float due to transistor 1194 being deactivated (e.g., turned off) due to the output of inverter 1196 being high and transistor 1192 being deactivated (e.g., turned off) due to FLOAT2 being low.

[0180] Control circuit 1120 may float control signal 1165, and thus node 1175, during interval 1215. Unselected word lines 1110-c may float due to isolation from node 1170 and the floating of node 1175. And due to capacitive coupling between unselected word lines 1110 and plate line 1205, the floating of unselected word lines 1110 may cause the voltage of unselected word lines 1110 to track the voltage of plate line 1205. In other words, when the voltage of plate line 1205 decreases during interval 1215, it may pull down the voltage of floating unselected word lines 1110 by an equal or substantially similar amount. For example, if the voltage of plate line 1205 decreases from 1.5V to 0V, the voltage of unselected access lines 1105 may decrease from 0V to -1.5V or approximately to -1.5V.

[0181] Thus, during interval 1215, unselected access line 1105 may be floated by adjusting control signal 1165 applied to node 1175. For example, control circuit 1120 may output FLOAT control signal 1165, which may float unselected word line 1110. Thus, the voltage of unselected word line 1110-c may be reduced to, for example, -1.4V.

[0182] During interval 1220 , the voltage of plate line 1205 may remain at a second voltage (eg, a low voltage such as 0 V). In some examples, based on control signal 1165 being applied to node 1175 , unselected word lines 1110 - c may remain floating.

[0183] In other examples, the unselected word line 1110-c may be driven to a desired voltage during the interval 1220 (e.g., may be driven to a voltage such that the voltage difference between the unselected word line 1110-c during the interval 1220 and the unselected word line 1110-c during the interval 1210 is equal to the voltage difference between the plate during the interval 1220 and the plate during the interval 1210). For example, during the interval 1220 (e.g., at time t', which may be before, at, or after the start of the interval 1220), a different control signal 1165 may be applied to the node 1175. The control signal 1165 may be VNNWL, which may be -1.5V. Thus, because the unselected word line 1110-c is coupled to the node 1175, the voltage of the unselected word line 1110-c may be driven to -1.5V, which may be slightly different from the voltage of the unselected word line 1110-c floating throughout the interval 1220 in some cases, such as Fig. 12C is shown by the alternative voltage trace associated with 1110-c'.

[0184] In some cases, during interval 1220, node 1170 may continue to float as it did during interval 1215. In other examples, node 1170 may be driven to a low voltage, such as 0 V, during interval 1220. Due to potential capacitive coupling between unselected word line 1110 and plate 1205, the voltage of node 1170-c may change (drift) slightly during interval 1215 (e.g., decrease to a voltage slightly below 0 V), and based on the expected drift during interval 1215, node 1170 may be driven to 0 V or a different voltage during interval 1220.

[0185] During interval 1225, the voltage of plate line 1205 can be driven from a second voltage (e.g., a low voltage) to a first voltage (e.g., a high voltage). Control circuit 1120 can output FLOAT control signal 1165, which can float unselected word line 1110, as described above with reference to interval 1215. Thus, the voltage of unselected word line 1110-c can increase to, for example, -0.1V. In addition, control circuit 1125 can float node 1170 (e.g., continue to float), as described with reference to interval 1215.

[0186] During the interval 1230, the voltage of the plate line 1205 may be maintained at a first voltage (e.g., a high voltage). The control circuit 1120 may output a high control signal 1165 (e.g., VNWL), which may be, for example, 0V. Thus, during the interval 1230, the voltage of the node 1175-c and the voltage of the unselected word line 1110-c may be 0V. Additionally or alternatively, during the interval 1230, the node 1170-c may be driven to 0V. In the examples described herein, the absolute voltage levels described (e.g., -1.4V, -1.5V, 3V, 0V, etc.) are for illustrative purposes only. Thus, any absolute voltage levels different from those described herein may be used.

[0187] In some examples, each of transistors 1130, 1135, 1140, and 1145 within driver 1105 of unselected word lines 1110-c may have a relatively low gate-source voltage (eg, V gs ) and / or drain-source voltage (e.g., V ds ). For example, throughout the access operation, transistors 1130, 1135, 1140, and 1145 do not have a Vgs and / or Vds greater than the voltage swing of control signal 1150 (eg, MWLF_H, which may be 3V).

[0188] Additionally or alternatively, the cascode configuration of transistors 1130 and 1135 may be such that when plate line 1205 is at a low voltage (e.g., 0V) and unselected access line 1105 is at a low voltage (e.g., -1.4V), transistor 1130 has a relatively low gate-source voltage (e.g., V gs ). In addition, because control signals 1167 and 1155 can have relatively low voltage swings, transistor 1145 can avoid excessive V gs .

[0189] Fig.12DAn example timing diagram 1200-d is shown that supports techniques for access line management for a memory cell array according to an example of the present invention. In some examples, the timing diagram 1200-d may be similar to the timing diagram 1200-d shown in the reference numeral 1200-d above. Fig.11 The access operations associated with (e.g., performed using) the described circuit 1100. In some examples, the timing diagram 1200-d can depict the voltages of the board line 1205, the word line 1110-d, the node 1170-d, and the node 1175-d. The timing diagram 1200-d can also depict alternative voltages for the word line 1110-d, as shown by the voltage trace denoted as 1110-d'. The voltages of the word lines 1110-d and 1110-d', the node 1170-d, and the node 1175-d can illustrate the voltages applied to the reference Fig.11 Depicted are the voltages of word line 1110, node 1170, and node 1175. Timing diagram 1200-d may depict the voltages of plate line 1205, word line 1110-d (and word line 1110-d'), and nodes 1170-d and 1175-d during intervals 1210, 1215, 1220, 1225, and 1230.

[0190] As described herein, a memory array may include a plurality of corresponding access lines (e.g., a plurality of word lines) for a plurality of memory cells, each memory cell having a common plate. Each access line may be selected or unselected (e.g., by reference to a cell coupled to the access line) based on whether the cell is the target of (accessed by) a particular access operation. Fig.11 Any one access line may be selected during a particular access operation, while the remaining number of access lines of the same type associated with the board may remain unselected during that operation.

[0191] Timing diagram 1200-d may illustrate the timing of the unselected access line subset as described above. Fig.11 The access operations associated with the described circuit 1100. For example, the timing diagram 1200-d may illustrate shared and selected access lines (eg, as shown in reference Fig. 12A The voltage of word line 1110-d (and / or 1110-d') of the same control circuit 1115 as the driver 1105 for the selected word line 1110-a) discussed above. Thus, following the above example, where 1,024 drivers 1105 are each coupled to a respective word line 1110, the voltage of unselected word line 1110-d may illustrate the voltages of fifteen (15) unselected word lines 1110.

[0192] During interval 1210, the voltage of plate line 1205 is shown as initially driven to a first voltage (e.g., a high voltage such as 1.5V). When the plate is driven to the first voltage, prior to interval 1210, a subset of word lines 1110 may remain unselected. In some examples, the unselected word lines 1110-d remaining unselected may be represented by the voltage of word lines 1110-d remaining at a low voltage, such as 0V. When the subset of word lines 1110-d is unselected and does not share control circuit 1125 with selected word line 1110-a, control circuit 1125 may apply a low control signal 1160 to node 1170, which may cause the voltage of node 1170-d to be driven to a low voltage, such as 0V. When node 1170-d is at a low voltage, when a subset of word lines 1110-d are unselected and share control circuit 1115 with selected word line 1110-a, control circuit 1115 may apply a low control signal 1150 to transistor 1130. Low control signal 1150 may be, for example, 0V. Thus, applying control signals 1160 and 1150 to driver 1105 may cause transistors 1130 and 1135 to be deactivated (e.g., turned off). Thus, the unselected word lines may be isolated from node 1170.

[0193] In some examples, when a subset of word lines 1110-d are unselected and share control circuit 1115 with selected word line 1110-a, control circuit 1115 may apply a low control signal 1155 to transistor 1145, and control circuit 1125 may apply a high control signal 1167 to node 1185. In some examples, low control signal 1155 may be 0V, and high control signal 1167 may be 1.5V. Thus, transistor 1145 may be deactivated (e.g., turned off), and transistor 1140 may be activated (e.g., turned on). Thus, unselected word lines 1110-d may be coupled to node 1175 via transistor 1140, and may be the same voltage as the output of control circuit 1120 (e.g., the same voltage as the voltage of control signal 1165). During interval 1210, control circuit 1120 may output control signal 1165 corresponding to VNWL, which may be, for example, 0V. Thus, during interval 1210, the voltage of node 1175-d and the voltage of unselected word lines 1110-d may be 0V.

[0194] During the interval 1215, the voltage of the plate line 1205 may transition from a first voltage (e.g., a high voltage) to a second voltage (e.g., a low voltage, such as 0V). Due to the capacitive coupling between the unselected word lines 1110 and the plate line 1205, floating the unselected word lines 1110 may cause the voltage of the unselected word lines 1110 to track the voltage of the plate line 1205. In other words, when the voltage of the plate line 1205 decreases during the interval 1215, it may pull down the voltage of the floating unselected word lines 1110 by an equal or substantially similar amount. For example, if the voltage of the plate line 1205 decreases from 1.5V to 0V, the voltage of the unselected access lines 1105 may decrease from 0V to -1.5V or approximately to -1.5V.

[0195] Thus, during interval 1215, unselected access lines 1105 may be floated by applying a different control signal 1165 to node 1175. For example, control circuit 1120 may output FLOAT control signal 1165, which may float unselected word lines 1110. Thus, the voltage of unselected word lines 1110-d may be reduced to, for example, -1.4V.

[0196] In some cases, node 1170 may also float during interval 1215. For example, control circuit 1125 may receive a FLOAT2 control signal at the gate of transistor 1192, which may be low when the input of inverter 1196 is low, which may float control signal 1160 and, therefore, node 1170. Node 1170 may float due to transistor 1194 being deactivated (e.g., turned off) due to the output of inverter 1196 being high and transistor 1192 being deactivated (e.g., turned off) due to FLOAT2 being low.

[0197] During the interval 1220, the voltage of the plate line 1205 can remain at a second voltage (e.g., a low voltage such as 0V). In some examples, the unselected word lines 1110-d can remain floating based on the control signal 1165 being applied to the node 1175. In other examples, the unselected word lines 1110 can be driven to a desired voltage during the interval 1220. For example, during the interval 1220 (e.g., at time t'), a different control signal 1165 can be applied to the node 1175. The control signal 1165 can be VNNWL, which can be -1.5V.

[0198] In some cases, during interval 1220, node 1170 may continue to float as it did during interval 1215. In other examples, node 1170 may be driven to a low voltage, such as 0 V, during interval 1220. Due to potential capacitive coupling between unselected word line 1110 and plate 1205, the voltage of node 1170-d may change (drift) slightly during interval 1215 (e.g., decrease to a voltage slightly below 0 V), and based on the expected drift during interval 1215, node 1170 may be driven to 0 V or a different voltage during interval 1220.

[0199] During interval 1225, the voltage of plate line 1205 can be driven from a second voltage (e.g., a low voltage) to a first voltage (e.g., a high voltage). Control circuit 1120 can output FLOAT control signal 1165, which can float unselected word line 1110. In addition, control circuit 1125 can float node 1170 (e.g., continue to float) as described with reference to interval 1215. During interval 1225, the voltage of unselected word line 1110-d (or 1110-d') can increase to, for example, -0.1V.

[0200] During the interval 1230, the voltage of the plate line 1205 may be maintained at a first voltage (e.g., a high voltage). The control circuit 1120 may output a high control signal 1165 (e.g., VNWL), which may be, for example, 0V. Thus, during the interval 1230, the voltage of the node 1175-d and the voltage of the unselected word line 1110-d (and 1110-d') may be 0V. Additionally or alternatively, during the interval 1230, the node 1170-d may be driven to 0V. In the examples described herein, the absolute voltage levels described (e.g., -1.4V, -1.5V, 3V, 0V, etc.) are for illustrative purposes only. Thus, any absolute voltage levels different from those described herein may be used.

[0201] In some examples, each of transistors 1130, 1135, 1140, and 1145 within driver 1105 of unselected word lines 1110-d may have a relatively low gate-source voltage (eg, V gs ) and / or drain-source voltage (e.g., V ds ). For example, throughout the access operation, transistors 1130, 1135, 1140, and 1145 do not have a Vgs and / or Vds greater than the voltage swing of control signal 1150 (eg, MWLF_H, which may be 3V).

[0202] Additionally or alternatively, the cascode configuration of transistors 1130 and 1135 may be such that when plate line 1205 is at a low voltage (e.g., 0V) and unselected access line 1105 is at a low voltage (e.g., -1.4V), transistor 1130 has a relatively low gate-source voltage (e.g., V gs ). In addition, because control signals 1167 and 1155 can have relatively low voltage swings, transistor 1145 can avoid excessive V gs .

[0203] Fig.13 A block diagram 1300 is shown of an access line manager 1315 supporting access line management of a memory cell array according to an example of the present invention. The access line manager 1315 may be a reference Fig.14 An example of aspects of the described access line manager 1415. The access line manager 1315 can include a bias component 1320, a timing component 1325, a drive component 1330, an identification component 1335, a float component 1340, and an apply component 1345. Each of these modules can communicate with each other directly or indirectly (e.g., via one or more buses).

[0204] The driving component 1330 can drive a plate coupled to at least a first memory cell of the memory cell array to a first voltage. In some examples, the driving component 1330 can drive the plate from the first voltage to a second voltage during a duration based on an access operation associated with a second memory cell.

[0205] The identification component 1335 can identify an access operation associated with a second memory cell of the memory cell array.

[0206] The floating component 1340 can float a first access line coupled to a first memory cell of the memory cell array for a duration based on an access operation associated with the second memory cell. In other examples, the floating component 1340 can float the first access line based on applying a first control signal having a first voltage swing and a second control signal having a second voltage swing different from the first voltage swing to a driver of the first access line.

[0207] In some examples, the floating component 1340 can float a second node of the driver for at least a portion of the duration. The second node can include a source or a drain of a fourth transistor included in the driver. Floating the first access line can be based on floating the second node.

[0208] The applying component 1345 may apply a fourth control signal to a third transistor included in the driver. The fourth control signal may be inverted relative to the third control signal and have a different voltage swing than the third control signal.

[0209] It should be appreciated that in some examples, one or more components of access line manager 1315 may be combined (eg, bias component 1320, drive component 1330, and float component 1340).

[0210] Fig.14 A diagram of a system 1400 including an apparatus 1405 supporting access line management of a memory cell array according to an example of the present invention is shown. The apparatus 1405 may be as described above, for example with reference to Figure 1 The device 1405 may include components for two-way voice and data communications, components for transmitting and receiving communications, including an access line manager 1415, a memory unit 1420, a basic input / output system (BIOS) component 1425, a processor 1430, an I / O controller 1435, and peripheral components 1440. The access line manager 1415 may be a reference Fig.13 An example of an access line manager 1315 is depicted. These components may be in electronic communication via one or more buses (eg, bus 1410).

[0211] Memory cell 1420 can store information (ie, in the form of logic states) as described herein.

[0212] BIOS component 1425 may be a software component including BIOS operating as firmware that can initialize and run various hardware components. BIOS component 1425 may also manage data flow between the processor and various other components (e.g., peripheral components, input / output control components, etc.). BIOS component 1425 may include a program or software stored in a read-only memory (ROM), flash memory, or any other non-volatile memory.

[0213] The processor 1430 may include an intelligent hardware device (e.g., a general purpose processor, a DSP, a central processing unit (CPU), a microcontroller, an ASIC, an FPGA, a programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof). In some cases, the processor 1430 may be configured to operate the memory array using a memory controller. In other cases, the memory controller may be integrated into the processor 1430. The processor 1430 may be configured to execute computer readable instructions stored in the memory to perform various functions (e.g., functions or tasks that support access line management of the memory cell array).

[0214] I / O controller 1435 can manage input and output signals of device 1405. I / O controller 1435 can also manage peripheral devices that are not integrated into device 1405. In some cases, I / O controller 1435 can represent a physical connection or port for an external peripheral device. In some cases, I / O controller 1435 can utilize an operating system, such as or another known operating system. In other cases, I / O controller 1435 may represent or interact with a modem, keyboard, mouse, touch screen, or similar device. In some cases, I / O controller 1435 may be implemented as part of a processor. In some cases, a user may interact with device 1405 via I / O controller 1435 or via hardware components controlled by I / O controller 1435.

[0215] Peripheral components 1440 may include any input or output device, or an interface for such a device. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral device card slot, such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot.

[0216] Input 1445 may represent a device or signal external to device 1405 that provides input to device 1405 or its components. This may include a user interface or an interface with other devices or an interface between other devices. In some cases, input 1445 may be managed by I / O controller 1435 and may interact with device 1405 via peripheral components 1440.

[0217] Output 1450 may also represent a device or signal external to device 1405 that is configured to receive output from device 1405 or any of its components. Examples of output 1450 may include a display, an audio speaker, a printing device, another processor or printed circuit board, etc. In some cases, output 1450 may be a peripheral element that interfaces with device 1405 through peripheral component 1440. In some cases, output 1450 may be managed by I / O controller 1435.

[0218] The components of device 1405 may include circuitry designed to perform their functions. This may include various circuit elements, such as conductive wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or non-active elements, which are configured to perform the functions described herein. Device 1405 may be a computer, server, laptop, notebook, tablet computer, mobile phone, wearable electronic device, personal electronic device, etc. Alternatively, device 1405 may be a portion or aspect of such a device.

[0219] Fig.15 A flow chart of a method 1500 for managing access lines of a memory cell array according to an example of the present invention is shown. The operations of the method 1500 may be implemented by a memory controller or a component thereof, as described herein. For example, the operations of the method 1500 may be implemented by reference to Figure 6 The described access line manager is executed.

[0220] At 1505, a plate coupled to at least a first memory cell of a memory cell array may be driven to a first voltage. The operations of 1505 may be performed according to the methods described herein. In some examples, aspects of the operations of 1505 may be described with reference to Figure 6 The described drive components execute.

[0221] At 1510, an access operation associated with a second memory cell of the memory cell array may be identified. The operations of 1510 may be performed according to the methods described herein. In some examples, aspects of the operations of 1510 may be described with reference to Figure 6 The described identification component performs.

[0222] At 1515, a first access line coupled to a first memory cell of the memory cell array can be floated for a duration based at least in part on an access operation associated with a second memory cell. In some examples, the floating can be based on applying a first control signal having a first voltage swing and a second control signal having a second voltage swing different from the first voltage swing to a driver of the first access line. The operations of 1515 can be performed according to the methods described herein. In some examples, aspects of the operations of 1515 can be described with reference to Figure 6 The described floating component is implemented.

[0223] At 1520, the plate can be driven from the first voltage to the second voltage during the duration based at least in part on the access operation associated with the second memory cell. The operations of 1520 can be performed according to the methods described herein. In some examples, aspects of the operations of 1520 can be described with reference to Figure 6 The described drive components execute.

[0224] In some examples, the method may include floating a first node of a word line driver for at least a portion of the duration. The first node of the word line driver may be configured to receive a third control signal, and floating the first access line may be based on floating the first node. In some examples, the first control signal may be applied to a gate of a transistor included in the driver, and the first node may include a source or a drain of the transistor. In some examples, the transistor may be in a cascode configuration with a second transistor included in the driver.

[0225] In some examples, a fourth control signal may be applied to a third transistor included in the driver. The fourth control signal may be inverted relative to the third control signal and have a different voltage swing than the third control signal.

[0226] In some examples, the method may include floating a second node of the driver for at least a portion of the duration. The second node may include a source or a drain of a fourth transistor included in the driver. In some examples, floating the first access line may be based on floating the second node. In some examples, the second control signal may be applied to a gate of the fourth transistor.

[0227] An apparatus is described. In some examples, the apparatus may include: a memory cell coupled to an access line, a driver coupled to the access line, and a control circuit coupled to the driver and operable to generate a first control signal for the driver and a second control signal for the driver. In some examples, the second control signal may have a different voltage swing than the first control signal.

[0228] The apparatus may include a second control circuit coupled to the driver and operable to float a first node of the driver. In some examples, the driver may be operable to float the access line based on the first node being floated. The apparatus may include a third control circuit coupled to the driver and operable to float a second node of the driver. In some examples, the driver may be operable to float the access line based on the second node being floated.

[0229] In some examples, the driver is one of a subset of a set of drivers, and each driver in the set can be coupled to a corresponding access line of a memory array including the memory cell. In some examples, the control circuit can be coupled to each driver in the subset, and the first control signal and the second control signal can be common to the drivers in the subset. In some examples, the apparatus can include a control circuit coupled to a second subset of the set of drivers. The third control circuit can be used to generate a third control signal common to the drivers in the second subset.

[0230] In some examples, the third control circuit may be further configured to generate a fourth control signal common to the drivers in the second subset. The fourth control signal may be inverted relative to the third control signal and have a different voltage swing than the third control signal.

[0231] The device may include a controller coupled to the control circuit, the second control circuit, and the third control circuit. The controller may be configured to identify an access operation associated with a second memory cell of the memory array and cause the second control circuit to float a first node of the driver during a portion of the access operation associated with the second memory cell based on the second subset not including the driver. In some examples, the second memory cell may be coupled to a second access line that is coupled to a second driver in the set. The second subset may not include the second driver. In some examples, the driver may be configured to float the access line based at least in part on the first node floating.

[0232] The controller may be configured to identify a second access operation associated with a third memory cell of the memory array and cause the second control circuit to drive the node of the driver to a first voltage during the access operation associated with the third memory cell based on the second driver being coupled to the second control circuit. The third memory cell may be coupled to a third access line coupled to a third driver in the set. In some examples, the third driver may be coupled to the second control circuit.

[0233] The device may include a controller coupled to the control circuit, the second control circuit, and the third control circuit. The controller may be configured to identify an access operation associated with a second memory cell of the memory array and cause the third control circuit to float a second node of the driver during at least a portion of the access operation associated with the second memory cell based on the second driver being coupled to the control circuit. In some examples, the second driver may be coupled to the control circuit. The driver may be configured to float the access line based on the second node being floated.

[0234] In some examples, the controller may be further operable to identify a second access operation associated with a third memory cell of the memory array and cause the third control circuit to drive the second node of the driver to a first voltage or a second voltage during the access operation associated with the third memory cell based on the subset not including the third driver. In some examples, the subset may not include the third driver.

[0235] An apparatus is described. In some examples, the apparatus may include: a memory cell coupled to an access line; a driver coupled to the access line, wherein the driver may include a first transistor in a cascode configuration with a second transistor; and a control circuit coupled to the driver and operable to output a first control signal to the first transistor and a second control signal to a third transistor of the driver.

[0236] In some examples, the apparatus may include a second memory cell. A source of the first transistor and a source of the third transistor may be used to float simultaneously with an access operation of the second memory cell. In some examples, the driver may be used to float the access line based on one or more of the source of the first transistor or the source of the third transistor floating.

[0237] An apparatus is described. In some examples, the apparatus may include: means for driving a plate coupled to a first memory cell of a memory cell array to a first voltage; means for identifying an access operation associated with a second memory cell of the memory cell array; means for floating a first access line coupled to the first memory cell for a duration based at least in part on the access operation associated with the second memory cell, wherein the floating is based at least in part on applying a first control signal having a first voltage swing and a second control signal having a second voltage swing different from the first voltage swing to a driver of the first access line; and means for driving the plate from the first voltage to a second voltage during the duration based at least in part on the access operation associated with the second memory cell.

[0238] In some examples, the apparatus may include means for floating a first node of the word line driver for at least a portion of the duration, wherein the first node of the word line driver is configured to receive a third control signal, and wherein floating the first access line is based at least in part on floating the first node. In such an example, the apparatus may include means for applying a fourth control signal to a third transistor included in the driver, wherein the fourth control signal is inverted relative to the third control signal and has a different voltage swing than the third control signal. In some examples, the apparatus may include means for floating a second node of the driver for at least a portion of the duration, wherein the second node comprises a source or a drain of a fourth transistor included in the driver, and wherein floating the first access line is based at least in part on floating the second node.

[0239] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. In addition, examples from two or more than two of the methods may be combined.

[0240] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. Some diagrams may depict a signal as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a bus of signals, where the bus may have various bit widths.

[0241] The terms "electronic communication" and "coupling" refer to a relationship between components that supports the flow of electrons between the components. This may include a direct connection between the components, or may include intermediate components. Components that are in electronic communication or coupled to each other may actively exchange electrons or signals (e.g., in an energized circuit), or may not actively exchange electrons or signals (e.g., in a de-energized circuit), but may be configured and operable to exchange electrons or signals once the circuit is energized. As an example, two components that are physically connected via a switch (e.g., a transistor) are in electronic communication, or may be coupled regardless of the state of the switch (i.e., open or closed).

[0242] As used herein, the term "substantially" means that the modified characteristic (such as a verb or adjective modified by the term substantially) need not be absolute, but is close enough so that the advantage of the characteristic is achieved.

[0243] The term "isolation" refers to a relationship between components where electrons are currently unable to flow between the components; if there is an open circuit between the components, the components are isolated from each other. For example, two components physically connected by a switch may be isolated from each other when the switch is open.

[0244] The devices discussed herein, including the memory array 100, may be formed on a semiconductor substrate such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0245] One or more transistors discussed herein may represent a field effect transistor (FET) and include a three-terminal device, including a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include a heavily doped (e.g., degenerate) semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0246] The description set forth herein describes example configurations in conjunction with the accompanying drawings, and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "used as an example, instance, or illustration," and does not mean "preferred" or "better than other examples." For the purpose of providing an understanding of the described techniques, the detailed description includes specific details. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form in order to avoid confusing the concepts of the described examples.

[0247] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar components. If only the first reference label is used in this specification, the description applies to any of the similar components with the same first reference label, regardless of the second reference label.

[0248] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0249] Thus, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0250] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present invention and the appended claims. For example, due to the nature of the software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features of the implementation functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations. In addition, as used herein (included in the claims), as used in a list of items (e.g., a list of items followed by a phrase such as "at least one of" or "one or more of"), "or" indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be considered as a reference to a closed set of conditions. For example, the exemplary steps described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present invention. In other words, as used herein, the phrase "based on" should be considered in the same manner as the phrase "based at least in part on".

[0251] Computer-readable media include both non-transitory computer storage media and communication media, and communication media include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. As an example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage device, magnetic disk storage device or other magnetic storage device, or any other non-transitory media that can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. In addition, any connection can be properly referred to as a computer-readable medium. For example, if a coaxial cable, optical cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave is used to transmit software from a website, server or other remote source, then coaxial cable, optical cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave are all included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0252] The description herein is provided to enable one skilled in the art to make or use the invention. Various modifications to the invention will be readily apparent to those skilled in the art without departing from the scope of the invention, and the general principles defined herein may be applied to other variations. Therefore, the invention is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: driving a plate coupled to a first memory cell of the memory cell array to a first voltage; identifying an access operation associated with a second memory cell of the memory cell array; floating a first access line coupled to the first memory cell for a duration based at least in part on the access operation associated with the second memory cell, wherein the floating is based at least in part on applying a first control signal having a first voltage swing and a second control signal having a second voltage swing different from the first voltage swing to a driver of the first access line; as well as The plate is driven from the first voltage to a second voltage during the duration based at least in part on the access operation associated with the second memory cell.

2. The method according to claim 1, further comprising: A first node of the driver is floated for at least a portion of the duration, wherein the first node of the driver is configured to receive a third control signal, and wherein floating the first access line is based at least in part on floating the first node.

3. The method according to claim 2, wherein: The first control signal is applied to a gate of a transistor included in the driver; and The first node includes a source or a drain of the transistor. 4 . The method of claim 3 , wherein the transistor is in a cascode configuration with a second transistor included in the driver.

5. The method according to claim 2, further comprising: A fourth control signal is applied to a third transistor included in the driver, wherein the fourth control signal is inverted with respect to the third control signal and has a different voltage swing than the third control signal.

6. The method according to claim 1, further comprising: A second node of the driver is floated for at least a portion of the duration, wherein the second node comprises a source or a drain of a fourth transistor included in the driver, and wherein floating the first access line is based at least in part on floating the second node. The method of claim 6 , wherein the second control signal is applied to a gate of the fourth transistor.

8. A device comprising: a memory cell coupled to the access line; a driver coupled to the access line; a control circuit coupled to the driver and operable to generate a first control signal for the driver and a second control signal for the driver, the second control signal having a different voltage swing than the first control signal; as well as A second control circuit is coupled to the driver and operable to float a first node of the driver, wherein the driver is operable to float the access line based at least in part on floating the first node.

9. The apparatus of claim 8, further comprising: A third control circuit is coupled to the driver and operable to float a second node of the driver, wherein the driver is operable to float the access line based at least in part on the second node floating.

10. The apparatus of claim 8, wherein: The driver is one of a subset of a set of drivers, each driver in the set coupled to a respective access line of a memory array including the memory cell; The control circuit is coupled to each driver in the subset; and The first control signal and the second control signal are common to the drivers in the subset.

11. The apparatus of claim 10, further comprising: A second control circuit is coupled to a second subset of the set of drivers, wherein the driver is one of the second subset, and wherein the second subset includes more drivers than the first subset.

12. The apparatus of claim 11, further comprising: A third control circuit is coupled to the second subset of the set of drivers, wherein the third control circuit is operable to generate a third control signal common to the drivers in the second subset.

13. The apparatus of claim 12, wherein the third control circuit is further operable to generate a fourth control signal common to the drivers in the second subset, and wherein the fourth control signal is inverted relative to the third control signal and has a different voltage swing than the third control signal.

14. The apparatus of claim 12, further comprising: a controller coupled to the control circuit, the second control circuit, and the third control circuit, wherein the controller is configured to: identifying an access operation associated with a second memory cell of the memory array, wherein the second memory cell is coupled to a second access line, the second access line is coupled to a second driver in the set, and wherein the second subset does not include the second driver; as well as The second control circuit is caused to float a first node of the driver during at least a portion of the access operation associated with the second memory cell based at least in part on the second subset not including the second driver, wherein the driver is operable to float the access line based at least in part on the first node floating.

15. The apparatus of claim 14, wherein the controller is further configured to: identifying a second access operation associated with a third memory cell of the memory array, wherein the third memory cell is coupled to a third access line, the third access line is coupled to a third driver in the set, and wherein the third driver is coupled to the second control circuit; and The second control circuit is caused to drive the first node of the driver to a first voltage during the access operation associated with the third memory cell based at least in part on the second driver being coupled to the second control circuit.

16. The apparatus of claim 12, further comprising: a controller coupled to the control circuit, the second control circuit, and the third control circuit, wherein the controller is configured to: identifying an access operation associated with a second memory cell of the memory array, wherein the second memory cell is coupled to a second access line, the second access line is coupled to a second driver in the set, and wherein the second driver is coupled to the control circuit; as well as The third control circuit is coupled to the control circuit based at least in part on the second driver to float a second node of the driver during at least a portion of the access operation associated with the second memory cell, wherein the driver is operable to float the access line based at least in part on the second node floating.

17. The apparatus of claim 16, wherein the controller is further configured to: identifying a second access operation associated with a third memory cell of the memory array, wherein the third memory cell is coupled to a third access line, the third access line is coupled to a third driver in the set, and wherein the subset does not include the third driver; and The third control circuit is caused to drive the second node of the driver to a first voltage or a second voltage during the access operation associated with the third memory cell based at least in part on the subset not including the third driver.

18. An apparatus comprising: a memory cell coupled to the access line; a driver coupled to the access line, wherein the driver comprises a first transistor in a cascode configuration with a second transistor; a control circuit coupled to the driver and operable to output a first control signal to the first transistor and a second control signal to a third transistor of the driver; as well as A second memory cell, wherein the source of the first transistor and the source of the third transistor are capable of floating simultaneously with an access operation of the second memory cell, and wherein the driver is capable of floating the access line based at least in part on floating one or more of the source of the first transistor or the source of the third transistor.

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