Hemt transistor comprising a field plate region and a manufacturing process thereof

Abstract

A HEMT transistor includes a semiconductor body having a semiconductor heterostructure. A gate region of conductive material is disposed on and in contact with the semiconductor body. A first insulating layer laterally extends over the semiconductor body to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region of conductive material extends between the first and second insulating layers, laterally separated from the conductive gate region along a first direction. A second field plate region of conductive material extends over the second insulating layer, and the second field plate region covers and is vertically aligned with the first field plate region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a high electron mobility transistor (HEMT) comprising a field plate region and a manufacturing process thereof. BACKGROUND

[0002] It is known that HEMT transistors (also known as heterostructure field effect transistors (HFETs)) are being widely spread due to the operating possibilities at high voltages and high breakdown voltages.

[0003] In each HEMT transistor, a semiconductor heterostructure allows generating in an electronically controllable manner a so-called two-dimensional electron gas (2deg) forming a channel region of the HEMT transistor. Further, each HEMT transistor comprises a gate region; the HEMT transistor channel is modulated by a voltage on the gate region.

[0004] For example, Figure 1 A HEMT transistor is shown, comprising a semiconductor body 2, here formed by a first layer 4 and a second layer 6, which will also be referred to as lower layer 4 and upper layer 6 in the following text.

[0005] The lower layer 4 is formed by a first semiconductor material, such as for example a first semiconductor alloy of elements of group III and group V of the periodic table; for example, the lower layer 4 can be formed by gallium nitride (GaN).

[0006] The upper layer 6 is overlaid on the lower layer 4 and in direct contact therewith, and is formed by a second semiconductor material of elements of group III to group V of the periodic table, such as for example a second semiconductor alloy different from the first semiconductor alloy. For example, the upper layer 6 can be formed by aluminum gallium nitride (AlGaN). The lower layer 4 and the upper layer 6 are for example N-type. Although not shown, the semiconductor body 2 further comprises a substrate, usually formed by silicon, on which the lower layer 4 is formed.

[0007] The HEMT transistor 1 further comprises a source metallization 20 and a drain metallization 22, which are arranged on the upper layer 6 at a distance from each other. The source metallization 20 and the drain metallization 22 can be in direct ohmic contact with the respective source and drain regions, for example as taught in US 2020 / 0168718 (corresponding to EP 3 660 923 A1). In particular, the source metallization 20 and the drain metallization 22 have a respective lower portion 20A, 22A directly overlaid on the upper layer 6 and adjoining the upper layer, and a respective upper portion 20B, 22B adjoining and connected to the respective lower portion 20A, 22A. The source metallization 20 and the drain metallization 22 are for example titanium and aluminum or a multilayer stack.

[0008] A first insulating layer 8, for example of silicon nitride, extends over the upper layer 6 and over portions of the source metallization 20 and of the drain metallization 22, lower portions 20A, 22A.

[0009] The gate region 10 of conductive material extends partially within the opening 11 (with a lower gate portion 10A) and partially over the first insulating layer 8 (with an upper gate portion 10B). The gate region 10 is for example formed by a stack of materials such as nickel (Ni), gold (Au), platinum (Pt) and palladium (Pd), with the nickel layer being in direct contact with the upper layer 6 and forming with it a Schottky-type (i.e. rectifying) metal-semiconductor junction.

[0010] A second insulating layer 12, for example of silicon nitride, extends over the first insulating layer 8 and around the upper gate portion 10A. In fact, the second insulating layer 12 and the first insulating layer 8 form an insulating structure 13 that seals the gate region 10.

[0011] The field plate region 14 extends over the second insulating layer 12, partially vertically overlapping the gate region 10 and partially laterally offset towards the drain metallization region 22. The field plate region 14, for example of aluminum, aims at modifying the existing electric field during operation of the HEMT transistor 1. The field plate region 14 is electrically coupled to the source metallization 20 in a manner not shown.

[0012] A passivation layer 16, for example of silicon oxide, surrounds the upper portions 20B, 22B of the source metallization 20 and of the drain metallization 22 and the field plate region 14, and covers the entire structure.

[0013] Another embodiment of a HEMT transistor is described in the Italian patent application No. 102018000011065 filed in the name of the Applicant on 13 December 2018 and allows to reduce the drain leakage current. This solution is shown in Figure 2 with slight modifications with respect to what is shown in the aforementioned patent application, highlighting the differences with respect to the HEMT transistor 1.

[0014] Figure 2 A HEMT transistor 30 is shown having a general structure similar to one of the HEMT transistors in Figure 1 ; therefore similar components are identified with the same reference numbers and will not be described again.

[0015] In Figure 2In the HEMT transistor 30, the insulating structure 13 comprises, in addition to the first insulating layer 8 and the second insulating layer 12, a dielectric layer 32 extending between them and partially within the gate region 10. The dielectric layer 32 can also be silicon nitride. In this way, the gate region 10 has, in addition to the lower gate portion 10A and the upper gate portion 10B, a first intermediate gate portion 10C and a second intermediate gate portion 10D arranged between the lower gate portion 10A and the upper gate portion 10B.

[0016] In detail, the first intermediate gate portion 10C is contiguous to the lower gate portion 10A, extends above the first insulating layer 8 and has an area (in cross section perpendicular to the plane of the drawing) approximately equal to that of the upper gate portion 10B. The second intermediate gate portion 10D is arranged between the physically contiguous first intermediate gate portion 10C and the upper gate portion 10B (physically contiguous thereto) and has an area (in cross section perpendicular to the plane of the drawing) smaller than that of the first intermediate gate portion 10C and of the upper gate portion 10B. The thickness of the second intermediate gate portion 10D is approximately equal to the thickness of the dielectric layer 32.

[0017] In fact, the dielectric layer 32 partially extends laterally to the first intermediate gate portion 10C and partially (with its substantially annular portion) between the first intermediate gate portion 10C and the second intermediate gate portion 10D and has an opening (called second opening 33) which accommodates the second intermediate portion 10D.

[0018] This allows the gate region 10 to be made of three different alloys (not shown); in particular, the lower gate portion 10A and the first intermediate portion 10C can be a first metal (for example, nickel Ni) which forms a Schottky contact with the body 2; the upper gate portion 10B can be a second metal (for example, aluminum Al) with low electrical resistance; and the second intermediate portion 10D can be a third material (for example, tungsten nitride WN or tantalum nitride TaN or TiN) which acts as a barrier and prevents the aluminum of the upper gate portion 10B from diffusing downwards to the upper layer 6 of the body 2 through the first intermediate portion 10C and the lower gate portion 10A, thus causing the Schottky junction to be destroyed.

[0019] in terms of frequency, from frequencies less than 6 GHz to frequencies in the range 30-50 GHz (millimeter waves), Figure 1 and Figure 2 The structure shown in the figures has very good performance and has very good switching capacitance, but can be improved in terms of gain and electrical field uniformity when a high voltage is applied to the gate region. SUMMARY

[0020] In various embodiments, the present disclosure provides an improved HEMT transistor and a manufacturing process thereof.

[0021] In at least one embodiment of the present disclosure, a HEMT transistor is provided that includes a semiconductor body having a semiconductor heterostructure. A gate region of conductive material is disposed on and in contact with the semiconductor body. A first insulating layer laterally extends over the semiconductor body to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region of conductive material extends between the first and second insulating layers laterally separated from the conductive gate region along a first direction. A second field plate region of conductive material extends over the second insulating layer and the second field plate region overlies the first field plate region.

[0022] In at least one embodiment, a process is provided that includes forming a semiconductor heterostructure in a semiconductor body; forming a first insulating layer having a first opening on the semiconductor body; forming a gate region of conductive material on the semiconductor body and in contact with the semiconductor body, the gate region extending into the opening; forming a first field plate region of conductive material on the first insulating layer, the first field plate region laterally separated from the conductive gate region; forming a second insulating layer over the gate region, the first field plate region, and the first dielectric layer; and forming a second field plate region of conductive material over the second insulating layer, the second field plate region overlying and vertically aligned with the first field plate region.

[0023] In at least one embodiment, an apparatus is provided that includes a semiconductor body having a semiconductor heterostructure. A conductive gate region is disposed on the semiconductor body. A first insulating layer is disposed on the semiconductor body and at least a portion of the conductive gate region extends through an opening in the first insulating layer. A second insulating layer is disposed on the first insulating layer and the conductive gate region. A first conductive field plate extends between and in contact with the first and second insulating layers and the first conductive field plate is laterally separated from the conductive gate region along a first direction. A second conductive field plate is disposed on the second insulating layer and the second conductive field plate overlies the first conductive field plate along a second direction that is transverse to the first direction. The second insulating layer extends directly between the first and second conductive field plates along the second direction. BRIEF DESCRIPTION OF DRAWINGS

[0024] For a better understanding of the present disclosure, some of the embodiments thereof will now be described, by way of non-limiting examples only, reference being made to the accompanying drawings in which:

[0025] Figure 1 A cross-section of a known HEMT transistor is schematically illustrated;

[0026] Figure 2 A cross-section of another HEMT transistor is schematically illustrated;

[0027] Figure 3 A cross-section of an embodiment of the present HEMT transistor is schematically illustrated;

[0028] Figure 4 Cross-sections of different embodiments of the present HEMT transistor are schematically illustrated;

[0029] Figure 5 A cross-section of another embodiment of the present HEMT transistor is schematically illustrated;

[0030] Figures 6A to 6D A cross-section similar to Figure 3 is shown in subsequent manufacturing steps;

[0031] Figures 7A to 7D A cross-section similar to Figure 4 is shown in subsequent manufacturing steps;

[0032] Figure 8 Results of simulations performed by the applicant on the structure of Figure 1 , Figure 2 , Figure 3 and Figure 4 are shown;

[0033] Figure 9 is a cross-section of another embodiment of the present HEMT transistor;

[0034] Figure 10 and Figure 11 are top plan views of different embodiments of the present HEMT transistor;

[0035] Figures 12A to 12C is a top plan view of the HEMT transistor of Figure 5 in subsequent manufacturing steps according to an embodiment; and

[0036] Figures 13 to 17 are cross-sections of other embodiments of the present HEMT transistor. DETAILED DESCRIPTION

[0037] Figure 3 A HEMT transistor 50 according to one embodiment is shown.

[0038] The HEMT transistor 50 has a general structure similar to the HEMT transistor 30 of Figure 2 and is therefore briefly described hereinafter; its regions are identified by numbers increased by 50.

[0039] The HEMT transistor 50 comprises a semiconductor body 52, which here is formed, for example, by a lower layer 54 of gallium nitride (GaN) and an upper layer 56 of, for example, aluminum gallium nitride (AlGaN). The upper layer 56 forms a surface 52A of the semiconductor body 52. In a not shown manner, the semiconductor body 52 can further comprise a silicon substrate, and / or the upper layer 56 can be a multi-layer comprising AlGaN layers with different aluminum percentages (for example, an AlGaN layer with 20% aluminum and another AlGaN layer with 40% aluminum).

[0040] The source metallization 70 and the drain metallization 72 extend above the body 52 at a distance from each other. Also here, the source metallization 70 and the drain metallization 72 comprise a lower part 70A, 72A and an upper part 70B, 72B, and are, for example, aluminum. The source metallization 70 and the drain metallization 72 form a source electrode and a drain electrode, and are electrically coupled to a respective source terminal S and drain terminal D.

[0041] A first insulating layer 58 of, for example, silicon nitride extends above the upper layer 56 and parts of the lower parts 70A, 72A of the source metallization 70 and the drain metallization 72.

[0042] A gate region 60 of electrically conductive material extends above the semiconductor body 52, and comprises a lower gate part 60A (extending into an opening of the first insulating layer 58, referred to as first opening 61, and being in direct contact with the upper layer 56 of the semiconductor body 52), an upper gate part 60B, a first intermediate gate part 60C and a second intermediate gate part 60D, which are arranged between the lower gate part 60A and the upper gate part 60B. Here, the gate region 60 can again be formed by a stack of materials, which are, for example, nickel (Ni), aluminum (Al) and tungsten nitride (WN) or tantalum nitride (TaN).

[0043] The gate region 60 is electrically coupled to a gate terminal G.

[0044] A dielectric layer 82 of, for example, silicon nitride extends above the first insulating layer 58, and partly within the gate region 60. The dielectric layer 82 thus has an opening (also referred to as second opening 83), in which the second intermediate part 60D of the gate region 60 extends.

[0045] A second insulating layer 62 of, for example, silicon nitride extends above the dielectric layer 82, and on top of and laterally surrounding the upper gate part 60B. In effect, the second insulating layer 62 forms, together with the first insulating layer 58 and the dielectric layer 82, an insulating structure 63 that seals the gate region 60.

[0046] A passivation layer 66, for example of silicon oxide, surrounds the source metallization 70 and the upper parts 70B, 72B of the drain metallization 72 and covers the whole structure.

[0047] Figure 3 The transistor 50 has a first field plate region 84 and a second field plate region 85 of electrically conductive material, such as a metal, for example aluminum.

[0048] The first field plate region 84 extends between the gate region 60 and the drain metallization 72 over the dielectric layer 82 and is covered by the second insulating layer 62. In the illustrated embodiment, the first field plate region 84 is arranged closer to the gate region 60 than to the drain metallization 72. For example, in a direction parallel to the first Cartesian axis X in the plane of the structure, the first field plate region 84 can have a width LI depending on the breakdown voltage, for example between 0.1 pm and 3 pm, for example 1 pm, and can be arranged at a distance d of 0.1 pm to 3 pm, for example 1 pm, from the gate region 60 (the distance d is calculated approximately from the edge of the upper gate part 60B facing the first field plate region 84). Figure 3

[0049] As discussed in detail below with reference to Figures 6A to 6D The first field plate region 84 can be of the same electrically conductive material, in particular the same metal layer, as the upper gate part 60B and be manufactured in the same manufacturing step, as discussed in detail below with reference to

[0050] The second field plate region 85 extends over the second insulating layer 62, vertically covering (with respect to the second Cartesian axis Z) the first field plate region 84 and is covered by the passivation layer 66. The second field plate region 85 has a width L2 at least equal to, but generally greater than, the width LI of the first field plate region 84. For example, the width L2 of the second field plate region 85 can be between 0.1 pm and 5 pm.

[0051] The field plate regions 84, 85 are electrically coupled to the source metallization 70 as illustrated by the line 75. In particular, the second field plate region 85 can be co-formed and use the same metal layer as the upper parts 70B and 72B of the source and drain regions 70, 72.

[0052] The field plate regions 84, 85 have the effect of modifying the existing electric field and in particular of making the electric field more uniform during operation of the HEMT transistor 50. Furthermore, the presence of the first field plate region 84 allows a significant increase in the gain of the HEMT transistor 50. Indeed, as discussed in detail below with reference to Figure 8 ​As discussed, the first field plate region 84, acting as a shield between the gate region 60 and the drain metallization 72, has the effect of reducing the gate-drain capacitance, the gain being inversely related to this gate-drain capacitance, in case of an increase of the drain voltage.

[0053] Figure 4 A different embodiment of a HEMT transistor is shown, here indicated with 100.

[0054] The HEMT transistor 100 has a general structure similar to the HEMT transistor 50 of Figure 3 Therefore, the components in common have been provided with the same reference numerals and will not be further described.

[0055] In the HEMT transistor 100, the first field plate region, here indicated with 84', comprises a lower plate portion 84A' and an upper plate portion 84B'.

[0056] The upper plate portion 84B' of the first field plate region 84' generally corresponds to Figure 3 the first field plate region 84 of the HEMT transistor 50, and thus extends laterally between the gate region 60 and the drain metallization 72 over the second insulating layer 62. The lower plate portion 84A' of the first field plate region 84' extends continuously from the upper plate portion 84B', through an opening, here indicated with 86, of a dielectric layer, here indicated with 82', and partly through the first insulating layer, here indicated with 58', in its cavity 87, towards the surface 52A of the semiconductor body 52. However, the lower plate portion 84A' does not extend completely through the first insulating layer 58', a thinner portion of the first insulating layer, hereinafter referred to as thinned portion 58A', extending between the surface 52A of the semiconductor body 52 and the first field plate region 84', electrically separates the first field plate region from the semiconductor body 52.

[0057] As discussed below with reference to Figure 8 This embodiment is characterized by a significant increase of the gain and a particularly uniform electric field.

[0058] Figure 5 A further embodiment of a HEMT transistor is shown, here indicated with 150.

[0059] Apart from the shape of the gate region (similar to the HEMT transistor 1 of Figure 1 The HEMT transistor 150 has a general structure similar to the HEMT transistor 50 of Figure 3 Therefore, the components in common with the HEMT transistor 50 of Figure 3 have been provided with the same reference numerals and will not be further described.

[0060] In detail, the HEMT transistor 150 comprises a gate region 60" having a lower gate portion 60A" and an upper gate portion 60B". Further, the HEMT transistor 150 comprises a first insulating layer, indicated with 58", having an opening 61" accommodating the lower gate portion 60A", and a first field plate region 84" extending above the insulating layer 58" and being laterally and on top covered by a second insulating layer 62.

[0061] In this embodiment, the lower gate portion 60A" and the upper gate portion 60B" can be formed from a single deposited (e.g. "sputtered") metal layer or a single evaporated layer or by a stack of multiple separately deposited layers. In the latter case, the first field plate region 84" can be formed with one of the layers of the gate region 60".

[0062] Here, the second field plate region 85 in turn extends vertically (in the direction of the second Cartesian axis Z) above the first field plate region 84".

[0063] Due to the simple shape of the gate region 60", this embodiment allows to simplify the manufacturing process.

[0064] The manufacturing process of the HEMT transistors 50 and 100 will now be described with reference to Figures 6A to 6D and with reference to Figures 7A to 7D respectively. Figure 3 and Figure 4 In detail, the manufacturing process of the HEMT transistor 50 comprises the following steps: Figure 6A A cross section similar to Figure 3 is shown in an intermediate manufacturing step of the HEMT transistor 50.

[0065] In particular, Figure 6A An intermediate structure is shown, in which, above the semiconductor body 52, a lower portion 70A of the source metallization 70, a lower portion 72A of the drain metallization 72 and the first insulating layer 58 have been formed in a manner known per se; further, the first insulating layer 58 has been etched to form the first opening 61; the lower gate portion 60A and a first intermediate gate portion 60C above the lower gate portion 60A in the first opening 61 have been formed (e.g. the lower gate portion 60A and the first intermediate gate portion 60C can be formed at the same time by physical vapor deposition (PVD) of a nickel layer within a cavity formed in a temporary structure and having an opening of small dimensions, relative to the area of the first intermediate gate portion 60C), and, after removal of the temporary structure, the dielectric layer 82 has been deposited, e.g. by PECVD deposition.

[0066] Next, as shown in Figure 6B , a portion of the dielectric layer 82 above the first intermediate gate portion 60C is removed, e.g. by dry etching, forming the second opening 83.

[0067] Then, as Figure 6C As shown, two sputtering processes are performed consecutively; specifically, a first sputtering process with tungsten nitride (WN) or tantalum nitride (TaN) forms a thinner first metal layer, filling the second opening 83, and is intended to subsequently form the second intermediate gate portion 60D; and a second sputtering process, for example, with aluminum, forms a thicker second metal layer. The layers formed by the first and second metal layers are in... Figure 6C The designation is 200. Alternatively, a range of sputtered metal layers can be used, including tungsten nitride (WN), aluminum (Al), and titanium nitride (TiN).

[0068] Next, as Figure 6D As shown, for example using a resist mask (not shown), some portions of the metal layer 200 (also called the gate metal layer) are selectively removed to form the second intermediate gate portion 60D and the upper portion 60B of the gate region 60, as well as the first field plate region 84.

[0069] The known steps include: depositing a second insulating layer 62; depositing a third metal layer, such as an aluminum substrate (e.g., an Al, AlSiCu, or AlCu bilayer and a Ti, TiN metal layer) by sputtering; and subsequent selective removal to form the upper portions 70B and 72B of the source metallization 70 and the drain metallization 72, as well as the second field plate region 85. Finally, a passivation layer 66 is deposited.

[0070] In this way, relative to Figure 2 In the manufacturing process of the HEMT transistor 30, the first field plate region 84 can be formed simply by modifying the etch mask of the gate metal layer 200 without adding process steps, and therefore no additional cost is required.

[0071] Figure 7A This illustrates the intermediate manufacturing steps of the HEMT transistor 100. Figure 4 Similar cross-sections.

[0072] In particular, Figure 7A An intermediate structure is shown, in which, above the semiconductor body 52, the lower portion 70A of the source metallization 70, the lower portion 72A of the drain metallization 72, and the first insulating layer 58ʹ have been formed in a manner known per se; furthermore, the first insulating layer 58ʹ has been etched to form a first opening 61, in which the lower gate portion 60A and the first intermediate gate portion 60C above the lower gate portion 60A have been formed (e.g., the lower gate portion 60A and the first intermediate gate portion 60C can be formed as described above for the HEMT transistor 50), and the dielectric layer 82ʹ has been deposited, for example, by PECVD deposition. Therefore... Figure 7A intermediate structure and Figure 6A The intermediate structure is the same.

[0073] Next, Figure 7B A portion of the dielectric layer 82' is removed over the first intermediate gate portion 60C to form a second opening 83. In addition, a portion of the dielectric layer 82' and an underlying portion of the first insulating layer 58' are selectively removed laterally to the second opening 83 to form a third opening 86, where it is desired to form a first field plate region 84'.

[0074] Then, Figure 7C The gate metal layer 200' is deposited, for example, in the manner described above with reference to Figure 6C A first sputtering process of tungsten nitride (WN) or tantalum nitride (TaN) is performed in succession to form a first metal layer (which is thinner and is intended to form subsequently the second intermediate gate portion 60D and the lower portion 84A of the first field plate region 84), and a second sputtering process of, for example, aluminum is performed to form a second metal layer which is thicker.

[0075] Next, Figure 7D Some portions of the gate metal layer 200' are selectively removed, for example, using a resist mask not shown, to complete the gate region 60' and the first field plate region 84'.

[0076] The known steps are as follows, including: deposition of the second insulating layer 62; deposition of a third metal layer, for example, an aluminum-based layer by sputtering (as shown above); and subsequent selective removal to form the source metallization 70 and the upper portions 70B and 72B of the drain metallization 72 and the second field plate region 85. This is followed finally by deposition of the passivation layer 66.

[0077] Thus in this case, with respect to the manufacturing process of the HEMT transistor 30 of Figure 2 , the first field plate region 84 can be formed by a modification of the etch mask to the gate metal layer 200' without adding process steps, and thus without additional cost.

[0078] Similarly, with respect to the steps foreseen to form the HEMT transistor 1 of Figure 1 , the manufacturing process of the HEMT transistor 150 does not require additional steps, and in some embodiments, only some modifications of the mask can be used to define the gate region 60" to form the first field plate region 84". Figures 3 to 5 The HEMT devices shown in the figures have many advantages. As shown, the HEMT devices described have a high gain due to the presence of the additional shielding region (the first field plate region 84, 84', 84") as shown in Figure 8 .

[0079] In particular, Figure 8The Applicant shows the results of simulations performed by it, which concern the variation curve of the gain G obtainable with a HEMT transistor as a function of the frequency f in the range from 2 GHz to 10 GHz, respectively for Figure 1 a HEMT transistor 1 (curve A) of the type shown in Figure 2 a HEMT transistor 30 (curve B) of the type shown in Figure 3 a HEMT transistor 50 (curve C) of the type shown in Figure 4 a HEMT transistor 100 (curve D) of the type shown in. It can be seen that the HEMT transistors 50 and 100 have a considerable gain with respect to similar structures lacking the first field plate region 84, 84'.

[0080] In a manner not shown, Figures 3 to 5 the HEMT device shown in allows to obtain a non-negligible improvement in terms of electric field uniformity, thus increasing its robustness at high voltages.

[0081] It is finally clear that modifications and changes can be made to the HEMT transistors and to the manufacturing processes thereof described and illustrated herein without departing from the scope of the present disclosure. For example, the different embodiments described can be combined to provide further solutions.

[0082] For example, the second field plate 85 and the first field plate 84, 84', 84" can be connected to the source metallization 70 in various ways; Figure 5 the first field plate 84" and the gate region 60" in can be positioned differently with respect to the insulating layer 58"; and Figure 5 the gate region 60" in can be defined in different ways, as discussed in detail below.

[0083] Connection of the second field plate 85:

[0084] The second field plate 85 can be connected to the source metallization 70 through a connection region extending over the active region (where the two-dimensional electron gas - 2deg - forms the channel region of the HEMT transistor and conducts the current) or over the passive region surrounding the active region, as described below.

[0085] For example, Figure 9 Embodiments are shown in which Figure 5 the HEMT transistor 150 of the type shown in has a second field plate 85 connected to the source metallization 70 through a connection portion formed in a third metal layer which also forms the upper portion 70B of the source metallization 70, the upper portion 72B of the drain metallization 72 and the second field plate region 85, thus being defined in the same etching step.

[0086] In particular, in Figure 9In this case, the biasing metal portion 88 of the third metal layer extends on the second insulating layer 62 between the upper portion 70B of the source metallization 70 and the second field plate region 85 and forms a single region with the upper portion and the second field plate region.

[0087] According to different embodiments, the second field plate 85 is connected to the source metallization 70 via a connection region extending over the passive region of the HEMT transistor 150, as illustrated hereafter with reference to Figure 10 It shows, in plan view, the structure of a basic cell of the HEMT transistor 150. Figure 5

[0088] It is intended here that the HEMT transistor 150 can comprise a plurality of basic cells each having at least one source metallization 70, at least one drain metallization 72, at least one first field plate 84 and at least one second field plate 85 (extending as a finger along one direction (vertical direction) of the basic cell). Figure 10

[0089] Figure 10 A portion of the intermediate structure of the HEMT transistor 150 after deposition and definition of the second insulating layer 62 (not visible in Figure 10 ) and deposition and definition of the third metal layer (indicated with 98) to form the upper portions 70B and 72B of the source and drain metallizations 70 and 72 and the second field plate region 85 is illustrated. In particular, Figure 10 An active region 90 (which accommodates 2-deg of high mobility conducting electrons) surrounded by a passive region 91 not participating in the conduction behavior is illustrated. The passive region 91 is usually doped to avoid current flow when the HEMT transistor 150 is turned off.

[0090] In Figure 10 , the lines 93 indicate the boundaries of the active region 90.

[0091] Here, the third metal layer 98 is also defined to form a second field plate connection region 97 extending over the passive region 91 between the upper portion 70B of the source metallization 70 and the second field plate region 85, thereby electrically connecting the upper portion and the second field plate region 85.

[0092] According to different embodiments, as illustrated in Figure 11 , the second field plate 85 is connected to the source metallization 70 via a plurality of clamping portions or bridge portions 105 extending over the active region 90 at a certain spacing from each other and formed by the second metal layer 200". In this case, in cross-section, the clamping portions 105 are not visible (as illustrated in Figure 5 ) or have a shape as illustrated in Figure 9 ​​a similar shape as the biasing metal portion 88, depending on whether the cross section through the HEMT transistor 150 is drawn in the region between two adjacent clamping portions 105 or through one of the clamping portions 105.

[0093] According to yet another embodiment, the second field plate 85 is connected to the source metallization 70 through Figure 10 a second field plate connection region of the second field plate and Figure 11 a clamping portion 105 of the HEMT transistor 150.

[0094] Connection of the first field plate 84, 84', 84":

[0095] The first field plate 84, 84', 84" can be connected to the source metallization 70 through a connection region extending over the passive region 91 or through the second field plate 85, as described below.

[0096] For example, as shown in Figures 12A to 12C Figs. 6A to 6C, the first field plate 84, 84', 84" can be connected to the source metallization 70, which figures show the structure of a basic cell of the HEMT transistor 150 (connection over the passive region 91) in three intermediate manufacturing steps. Figure 5

[0097] Furthermore, here, the HEMT transistor 150 can comprise a plurality of basic cells, each basic cell having at least one source metallization 70, at least one drain metallization 72, at least one first field plate 84 and at least one second field plate 85 (extending as a finger along one direction (vertical direction) of the HEMT transistor 150). Figures 12A to 12C

[0098] A portion of the intermediate structure of the HEMT transistor 150 is shown after forming the source metallization 70 and the lower portion 70A, 72A of the drain metallization 72, and after forming and defining the insulating layer 58" (58''). Figure 12A Figure 5 In , the source metallization 70 and the lower portion 70A, 72A of the drain metallization 72 extend mainly over the active region 90 and have end portions 70A1, 72A1 extending over the passive region 91. The line 93 indicates the boundary of the active region 90; the line 94 indicates the boundary of the insulating layer 58" (not visible) and the line 95 indicates the first opening 61" in

[0099] Figure 12A Figure 5

[0100] Figure 12B A portion of the intermediate structure of the HEMT transistor 150 is shown after depositing and defining a metal layer (with Figure 7C ​​​​The same portion of the intermediate structure of the HEMT transistor 150 (similar to the gate metal layer 200') forms the gate region 60″, the first field plate 84″, and the first connection region 96. The first connection region 96 is integral with and connected to the first field plate 84″, extends from the end of the first field plate 84″ onto the passive region 91, and ends at the enlarged portion 96A.

[0101] Figure 12C This shows the deposition and definition of the second insulating layer 62 ( Figure 12C (Not visible in the middle) and after the deposition and definition of the third metal layer (again indicated by 98) Figure 12A and Figure 12B The same parts are used to form the upper portions 70B and 72B of the source metallization section 70 and the drain metallization section 72, as well as the second field plate region 85.

[0102] exist Figure 12C In the middle, the second insulating layer 62 ( Figure 5 A via 99 has been defined to form on the amplified portion 96A of the first connection region 96.

[0103] Here, the third metal layer 98 extends over the passive region 91, particularly over the amplification portion 96A, and fills the via 99 to form a connection channel (indicated by the same number 99 because it has the same shape as the via). The connection channel 99 electrically connects the upper portion 70B of the source metallization portion 70 to the amplification portion 96A of the first connection region 96 (at a lower level), thereby connecting to the first field plate 84″.

[0104] Here, in addition, the third metal layer 98 is also used to form a second field plate connection region 97, which extends over the passive region 91 between the upper portion 70B of the source metallization portion 70 and the second field plate region 85.

[0105] Therefore, the first connecting region 96, the connecting channel 99, and the second connecting region 97 are formed. Figure 3 Line 75 directly connects the source metallization section 70, the first field plate 84″, and the second field plate region 85.

[0106] According to different implementations, such as Figure 13 As shown, the first field plates 84, 84ʹ, and 84″ can be connected to the source metallization section 70 via the second field plate 85.

[0107] In detail, Figure 13In particular, the second insulating layer 62 has a via, which is referred to as field plate connection opening 89 and extends over the first field plate 84". Thus, during deposition of the third metal layer 98, metal enters and fills the field plate connection opening 89, forming a field plate via, also indicated by 89, as it has the same shape and is defined by the field plate connection opening 89. The field plate connection via 89 electrically connects the first field plate 84" to the second field plate region 85, thereby connecting to the source metallization 70 through one of the solutions in the partial connection of the second field plate 85 discussed above.

[0108] According to another embodiment, in combination with the solution of Figures 12A to 12C and Figure 13 the first field plate 84, 84', 84" can be connected to the source metallization 70 over the passive region 91 (through the first connection region 96, the amplification portion 96A and the connection via 99, as shown in Figures 12A to 12C and also over the active region 90 (through the field plate connection via 89, as shown in Figure 13 .

[0109] Arrangement of the first field plate 84":

[0110] The first field plate 84" can be arranged differently with respect to the insulating layer 58".

[0111] In particular, as an alternative to the arrangement shown in Figure 5 , in which the first field plate 84" is formed completely over the insulating layer 58", the first field plate 84" can be formed with its lower portion within the insulating layer 58", as shown in Figure 14 .

[0112] In this case, process steps similar to those described with reference to Figures 7B to 7D are performed. In particular, after deposition of the insulating layer 58", the first opening 61 is formed and the cavity 87' (corresponding to the third opening 86 and the cavity 87 of Figure 4 ) is formed in a separate etching step. Then, a gate metal layer (similar to the gate metal layer 200" of Figure 7C ) is deposited and defined to form the gate region 60" and the first field plate region 84". Thereafter, the second insulating layer 62 and the third metal layer are deposited and defined and covered by the passivation layer 66.

[0113] According to a different embodiment, the first field plate 84" can be formed to contact the semiconductor body 52. In this case, the insulating layer 58" can only be partially removed, as shown in Figure 15 .

[0114] In detail, in Figure 15In this case, the third opening in the insulating layer 58" (here indicated with 86') is a via, so that the bottom of the first field region 4" directly contacts the semiconductor body 52.

[0115] Arrangement of the gate region 60":

[0116] The gate region 60" can extend directly on the semiconductor body 52 and in contact with the semiconductor body 52, as shown in Figure 9 , Fig. 12, Figures 13 to 15 , or can enter a recess in the semiconductor body, as shown in Figure 16 .

[0117] In Figure 16 , the lower gate portion 60A" of the gate 60" extends in the recess 79 past the portion of the upper layer 56 of the semiconductor body 52.

[0118] This solution can be used when the first field plate 84" is in direct contact with the semiconductor body 52.

[0119] Definition of the gate region 60" and the first field plate 84":

[0120] The gate region 60" and the first field plate 84" can be defined through known masking and etching steps, in which case, due to the etching process as shown in Figure 9 , Figures 13 to 17 or using a lift-off process, the insulating layer 58" is slightly recessed. In this case, as shown in Figure 17 , the insulating layer 58" has a planar upper surface that is not recessed.

[0121] The various embodiments described above can be combined to provide further embodiments. These and other alterations can be made to the embodiments described above in light of the detailed description. In general, the terms used in the following claims should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. The claims are not to be limited to the embodiments disclosed in this disclosure.

Claims

1. A HEMT transistor, comprising: The semiconductor substrate has a semiconductor heterostructure; A gate region of conductive material is disposed on and in contact with the semiconductor body; A first insulating layer extends laterally over the semiconductor body to the conductive gate region; A second insulating layer extends over the first insulating layer and the gate region; A first field plate region of conductive material extends between the first insulating layer and the second insulating layer, and is laterally separated from the conductive gate region along a first direction; A second field plate region of conductive material extends over the second insulating layer along the first direction, the second field plate region covering the first field plate region, wherein the gate region includes a lower gate portion and an upper gate portion, the lower gate portion extending into a first opening in the first insulating layer and contacting the semiconductor body; as well as A dielectric layer extending between a first insulating layer and a second insulating layer, wherein the dielectric layer has a second opening and a third opening, the gate region has an intermediate gate portion extending between the upper gate portion and the lower gate portion into the second opening, and wherein the first field plate region has a lower plate portion extending through the third opening of the dielectric layer and into a cavity of the first insulating layer, and a thickness-reduced portion of the first insulating layer extending between the lower plate portion and the semiconductor body.

2. The HEMT transistor according to claim 1, wherein the first field plate region and the second field plate region are metal regions.

3. The HEMT transistor of claim 1, wherein the upper gate portion is formed of the same material as the first field plate region.

4. The HEMT transistor of claim 3, wherein the upper gate portion and the first field plate region are made of aluminum.

5. The HEMT transistor of claim 1, further comprising a drain contact region and a source contact region of conductive material, the drain contact region and the source contact region extending over the semiconductor body via the first insulating layer and the second insulating layer on opposite sides of the gate region and in electrical contact with the semiconductor body, wherein the first field plate region is disposed between the gate region and the drain contact region.

6. The HEMT transistor of claim 5, wherein the first field plate region is electrically coupled to the source contact region.

7. The HEMT transistor of claim 1, wherein the first field plate region has a first width along the first direction, and the second field plate region has a second width along the first direction, wherein the second width is greater than the first width.

8. The HEMT transistor of claim 1, wherein the semiconductor body comprises at least a first semiconductor layer comprising gallium aluminum nitride and a second semiconductor layer comprising gallium nitride, wherein the second semiconductor layer is adjacent to the first insulating layer.

9. The HEMT transistor of claim 1, further comprising a drain contact region and a source contact region of conductive material, the drain contact region and the source contact region extending over the semiconductor body via the first insulating layer and the second insulating layer on opposite sides of the gate region and in electrical contact with the semiconductor body. The semiconductor body includes an active region and a passive region, and the gate region, the first field plate region, and the second field plate region extend over the active region. The first field plate region is electrically connected to the source contact region via the field plate contact region and the connecting channel. The field plate contact region extends from the first field plate region to the passive region. The connecting channel extends between the upper portion of the field plate contact region and the source contact region.

10. The HEMT transistor of claim 1, further comprising a drain contact region and a source contact region of conductive material, the drain contact region and the source contact region extending over the semiconductor body via the first insulating layer and the second insulating layer on opposite sides of the gate region and in electrical contact with the semiconductor body. The semiconductor body includes an active region and a passive region, and the gate region, the first field plate region, and the second field plate region extend over the active region. The first field plate region is electrically connected to the second field plate region through a field plate connection channel, and the field plate connection channel extends over the active region through the second insulating layer.

11. The HEMT transistor of claim 1, further comprising a drain contact region and a source contact region of conductive material, the drain contact region and the source contact region extending over the semiconductor body via the first insulating layer and the second insulating layer on opposite sides of the gate region and in electrical contact with the semiconductor body. The semiconductor body includes an active region and a passive region, and the gate region, the first field plate region, and the second field plate region extend over the active region. The metal portion extends on the second insulating layer between the source contact region and the second field plate region.

12. A process for manufacturing HEMT transistors, comprising: Forming semiconductor heterostructures within a semiconductor substrate; A first insulating layer having a first opening is formed on the semiconductor body; A gate region of conductive material is formed on the semiconductor body and in contact with the semiconductor body, the gate region extending into the opening; A first field plate region of conductive material is formed on the first insulating layer, and the first field plate region is laterally separated from the conductive gate region along a first direction; A second insulating layer is formed over the gate region, the first field plate region, and the first insulating layer; as well as A second field plate region of conductive material is formed on the second insulating layer along the first direction, the second field plate region covering the first field plate region; A lower gate portion of conductive material is formed in the first opening; A dielectric layer is formed over the first insulating layer and over the lower gate portion; as well as Selectively removing the dielectric layer over the lower gate portion, including removing the portion of the dielectric layer that is adjacent to but not adjacent to the lower gate portion, the process further includes: A cavity is formed in the first insulating layer below the removed portion of the dielectric layer, the cavity covering the thinned portion of the first insulating layer, such that a metal layer fills the cavity and the removed portion of the dielectric layer.

13. The process of claim 12, wherein forming the gate region and forming the first field plate region comprises depositing and defining the same metal layer.

14. The process of claim 13, wherein the metal layer forms the upper gate portion and the first field plate region.

15. The process according to claim 13, wherein the metal layer is aluminum.

16. A HEMT device, comprising: The semiconductor substrate has a semiconductor heterostructure; A conductive gate region is located on the semiconductor body; A first insulating layer is provided on the semiconductor body, and at least a portion of the conductive gate region extends through a first opening in the first insulating layer. A second insulating layer is provided on the first insulating layer and the conductive gate region; A first conductive field plate extends between and contacts the first insulating layer and the second insulating layer, and the first conductive field plate is laterally separated from the conductive gate region along a first direction; The second conductive field plate covers the first conductive field plate along a second direction transverse to the first direction on the second insulating layer, and the second insulating layer extends directly between the first conductive field plate and the second conductive field plate along the second direction. as well as A dielectric layer extending between a first insulating layer and a second insulating layer, wherein the dielectric layer has a second opening, the conductive gate region including a lower gate portion in the first opening and in contact with the semiconductor body, a first intermediate gate portion between the first insulating layer and the dielectric layer, a second intermediate gate portion in the second opening above the first intermediate gate portion, and an upper gate portion above the second opening, wherein the first intermediate gate portion is wider than the second intermediate gate portion in the first direction.

17. The HEMT device of claim 16, wherein at least a portion of the conductive gate region is formed of the same material as the first conductive field plate.

18. The HEMT device of claim 17, wherein at least a portion of the conductive gate region and the first conductive field plate are formed of aluminum.

19. The HEMT apparatus of claim 16, further comprising: Drain contact, on the semiconductor body and in contact with the semiconductor body; as well as The source contact is located on and in contact with the semiconductor body. Each of the drain contact and the source contact extends through the first insulating layer and the second insulating layer on opposite sides of the conductive gate region, wherein the first conductive field plate is disposed between the gate region and the drain contact along the first direction.

20. The HEMT device of claim 19, wherein the first conductive field plate is electrically coupled to the source contact.

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