Migration of partially completed instructions

Abstract

Migration of partially completed instructions. Determining that processing of an operation of an instruction executed on a processor was interrupted before completion. Re-executing the instruction on a selected processor to resume forward processing of the instruction. The re-executing includes determining whether model-dependent metadata will be used by the selected processor when re-executing the instruction. Based on determining that the model-dependent metadata will be used, using the model-dependent metadata when re-executing the instruction. Based on determining that the model-dependent metadata will not be used, continuing to re-execute the instruction without using the model-dependent metadata.

Description

Technical Field

[0001] One or more aspects relate generally to facilitating processing within a computing environment, and more particularly to facilitating instruction processing. Background Art

[0002] Instructions executed within a computing environment may require a significant number of execution cycles to complete. When an instruction requires a significant number of execution cycles to complete, the instruction is defined as interruptible. Therefore, additional processing must be performed in order to ultimately complete the instruction. Summary of the Invention

[0003] The shortcomings of the prior art are overcome and additional advantages are provided by providing a computer program product for facilitating processing within a computing environment. The computer program product includes a computer-readable storage medium readable by processing circuitry and storing instructions for performing a method. The method includes determining that processing of an operation of an instruction executed on a processor has been interrupted before completion, and re-executing the instruction on a selected processor to resume forward processing of the instruction. The re-executing includes determining whether model-related metadata will be used by the selected processor when re-executing the instruction. Based on determining that the model-related metadata will be used, the model-related metadata is used when re-executing the instruction. Based on determining that the model-related metadata will not be used, the re-executing of the instruction continues without using the model-related metadata. With the model-related metadata, storage accesses are reduced, which saves time and improves the performance of the processor operating and executing the instruction.

[0004] In one embodiment, determining whether to use the model-related metadata includes comparing a model version indicator of the interrupted processor with a model version indicator of a selected processor, wherein the model-related metadata is to be used when re-executing the instruction based on a predefined relationship between the model version indicator of the processor and the model version indicator of the selected processor, for example, the predefined relationship being equality.

[0005] In one embodiment, the processor's model version indication is a model version number stored in a location specified by the instruction. The location includes a parameter block in a memory. Further, the parameter block in the memory includes the model-related metadata.

[0006] For example, the re-execution further includes checking a continuation indicator to determine whether the operation is partially completed. Based on the continuation indicator being set to indicate that the operation is partially completed, the determination of whether to use the model-related metadata is performed. The continuation indicator is, for example, stored in the parameter block in the memory.

[0007] In one embodiment, using the model-related metadata includes extracting the model-related metadata from a location specified by the instruction and loading the model-related metadata extracted from the location into one or more selected locations of the selected processor, wherein the model-related metadata is provided to the selected processor without repeating one or more tasks to generate the model-related metadata. For example, the location specified by the instruction includes a continuation state buffer of a parameter block in a memory specified by the instruction.

[0008] Computer-implemented methods and systems related to one or more aspects are also described and claimed herein. Further, services related to one or more aspects are also described and may be claimed herein.

[0009] Additional features and advantages are realized through the techniques described herein.Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and objects, features, and advantages of one or more aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1A An example of a computing environment is shown to incorporate and use one or more aspects of the present invention;

[0012] Figure 1B According to one or more aspects of the present invention Figure 1A Further details of the processor;

[0013] Figure 2 Another example of a computing environment that includes and uses one or more aspects of the present invention is shown;

[0014] Figure 3A A format of a Sort Lists instruction according to one aspect of the present invention is shown;

[0015] Figure 3B shows an example of the fields of an implicit register (general register 0) used by a list sort instruction according to an aspect of the present invention;

[0016] Figure 3C An example of a function code for a list sorting instruction according to one aspect of the present invention is shown;

[0017] Figure 3Dshows an example of the fields of an implicit register (general register 1) used by a list sort instruction according to an aspect of the present invention;

[0018] Figure 3E An example of the contents of register R1 specified by a list sort instruction according to an aspect of the present invention is described;

[0019] Figure 3F shows an example of the contents of register R1+1 used by a list sort instruction according to an aspect of the present invention;

[0020] Figure 3G shows an example of the contents of register R2 specified by a list sort instruction according to one aspect of the present invention;

[0021] Figure 3H shows an example of the contents of register R2+1 used by a list sort instruction according to an aspect of the present invention;

[0022] Figure 3I shows an example of the contents of a parameter block used by the SORTL-QAF functionality of a sort list instruction according to an aspect of the present invention;

[0023] Figure 3J shows an example of a fixed-length record format used by a list sort instruction according to an aspect of the present invention;

[0024] Figure 3K shows an example of the contents of a parameter block used by the SORTL-SFLR functionality of a list sort instruction according to an aspect of the present invention;

[0025] Figures 4A-4B shows a SORTL-SFLR example according to one or more aspects of the present invention;

[0026] Figure 5A An example of summarization of values of inputs to a SORTL-SFLR function according to an aspect of the present invention is described;

[0027] Figure 5B An example of limitations on modification of the input list address and length fields of the SORTL-SFLR function according to an aspect of the present invention is shown;

[0028] Figure 6A shows an example of a first operand position / first operand before performing a SORTL with a merge mode indication set to zero according to an aspect of the present invention;

[0029] Figure 6Bshows an example of a first operand position / first operand after performing a SORTL with a merge mode indication set to zero according to an aspect of the present invention;

[0030] Figure 6C shows an example of a second operand position / second operand before performing a SORTL with a merge mode indication set to zero according to an aspect of the present invention;

[0031] Figure 6D shows an example of a second operand position / second operand after performing a SORTL with a merge mode indication set to zero according to an aspect of the present invention;

[0032] Figure 7A shows an example of a first operand position / first operand before executing SORTL with the merge mode indication set to 1 according to an aspect of the present invention;

[0033] Figure 7B shows an example of a first operand position / first operand after executing SORTL with the merge mode indication set to 1 according to an aspect of the present invention;

[0034] Figure 8 shows an example of certain fields of a parameter block used in accordance with an aspect of the present invention;

[0035] Figure 9 shows an example of a variable length record format used by a list sort instruction according to an aspect of the present invention;

[0036] Figures 10A-10B An example of processing associated with interruption of instructions and re-execution of instructions according to an aspect of the present invention is shown;

[0037] Figures 11A-11B An example of facilitating processing within a computing environment according to an aspect of the present invention is shown;

[0038] Figure 12A Another example of a computing environment that includes and uses one or more aspects of the present invention is shown;

[0039] Figure 12B Show Figure 12A Further details of the memory;

[0040] Figure 13 illustrates one embodiment of a cloud computing environment; and

[0041] Figure 14 An example of an abstract model layer is shown. DETAILED DESCRIPTION

[0042] According to one aspect of the present invention, a capability is provided to facilitate processing within a computing environment. As an example, a single instruction (e.g., a single architectural hardware machine instruction at a hardware / software interface) is provided to perform an operation, such as sorting and / or merging data records. The instruction is executed, for example, on a general-purpose processor.

[0043] When executing an instruction, a large number of execution cycles may be required to complete the operation. Therefore, in one aspect, the instruction is defined as interruptible. When the instruction is interrupted, the operation (e.g., sorting and / or merging) is only partially completed. The execution of the instruction ends by setting the condition code to a value that notifies the program (e.g., the program that issued the instruction) that the operation is partially completed. The program can then re-execute the instruction to resume processing.

[0044] In one embodiment, an instruction takes multiple (e.g., a significant number) execution cycles to provide metadata to the processor before generating a result. Each time an instruction is executed or re-executed, the processor is booted with the metadata. Thus, according to one aspect of the present invention, previously generated metadata is stored and used so that the previously generated metadata does not need to be regenerated when the instruction is re-executed.

[0045] In one example, the instruction is a sort instruction that sorts and / or merges records of one or more input lists input to the instruction. For such an example, the metadata includes an internal state of the processor, including, for example, information about the input lists, such as information about previous comparisons of records of the input lists to determine a next comparison to be performed.

[0046] The processor extracts the metadata and stores it in a location provided by the program. Then, when the instruction is re-executed after an interruption, the metadata is extracted from this location and loaded into the processor without using a task to regenerate the metadata. This saves the time that would otherwise be required to generate metadata for the operation.

[0047] In one instance, metadata is model-dependent metadata accumulated during execution of an instruction (e.g., a sort instruction) being executed in a computing environment that may include machines or processors of different models. As an example, the model-dependent metadata includes information about an input list, such as information about previous comparisons of records of the input list in order to determine a next comparison to be performed; the metadata is model-dependent because, for example, it can be stored differently for each processor (e.g., in a different format). The model-dependent metadata is not necessary to re-execute the instruction, but is used in certain circumstances to minimize overhead when resuming partially completed operation of the instruction. For example, the model-dependent metadata is used when the processor resuming the operation is capable of interpreting the captured model-dependent metadata.

[0048] Reference Figure 1A One embodiment of a computing environment that includes and uses one or more aspects of the present invention is described. Computing environment 100 includes, for example, a processor 102 (e.g., a central processing unit), a memory 104 (e.g., main memory; also known as system memory, primary storage, central storage, storage), and one or more input / output (I / O) devices and / or interfaces 106 coupled to each other via, for example, one or more buses 108 and / or other connections.

[0049] In one example, processor 102 is based on a processor provided by International Business Machines Corporation of Armonk, New York. Hardware architecture, and is such as IBM A portion of a server such as a server, also provided by International Business Machines Corporation, that implements the z / Architecture hardware architecture. One embodiment of the z / Architecture hardware architecture is described in a publication entitled "z / Architecture Principles of Operation" (IBM Publication No. SA22-7832-11, 12th Edition, September 2017), which is hereby incorporated by reference in its entirety. However, the z / Architecture hardware architecture is only one example architecture; other architectures and / or other types of computing environments may include and / or use one or more aspects of the present invention. In one example, a processor executes an operating system, such as an . operating system.

[0050] The processor 102 includes multiple functional components for executing instructions. Figure 1BAs depicted in , these functional components include, for example, an instruction fetch component 120 for fetching instructions to be executed; an instruction decode unit 122 for decoding the fetched instructions and obtaining operands of the decoded instructions; an instruction execution component 124 for executing the decoded instructions; a memory access component 126 for accessing memory for instruction execution when necessary; and a write-back component 130 for providing the results of the executed instructions. According to one or more aspects of the present invention, one or more of these components may include at least a portion of one or more other components that provide sort / merge processing (or other processing that may use one or more aspects of the present invention) or be able to access one or more other components. The one or more other components include, for example, a sort / merge component (or other component) 136. The functionality provided by component 136 is described in further detail below.

[0051] See Figure 2 Another example of a computing environment for incorporating and using one or more aspects of the present invention is described below. In one example, the computing environment is based on the z / Architecture hardware architecture; however, the computing environment may be based on other architectures provided by International Business Machines Corporation or other companies.

[0052] Reference Figure 2 In one example, a computing environment includes a central electronic complex (CEC) 200. The CEC 200 includes multiple components, such as a memory 202 (also known as system memory, main memory, main storage, central storage, storage) coupled to one or more processors (also known as central processing units (CPUs)) 204 and an input / output subsystem 206.

[0053] The memory 202 includes, for example, one or more logical partitions 208, a hypervisor 210 that manages the logical partitions, and processor firmware 212. An example of the hypervisor 210 is the Processor Resource / System Manager (PR / SM) provided by International Business Machines Corporation of Armonk, New York. TM ) hypervisor. As used herein, firmware includes, for example, the microcode of a processor. It includes, for example, hardware-level instructions and / or data structures used in the implementation of higher-level machine code. In one embodiment, it includes, for example, proprietary code typically delivered as microcode, including trusted software or microcode specific to the underlying hardware, and controlling operating system access to the system hardware.

[0054] Each logical partition 208 is capable of functioning as a separate system. That is, each logical partition can be independently reconfigured, run a guest operating system 220 such as the z / OS operating system or another operating system, and operate with different programs 222. An operating system or application running in a logical partition appears to have access to the entire system, but in reality, only a portion of it is available.

[0055] Memory 202 is coupled to processors (e.g., CPUs) 204, which are physical processor resources that can be assigned to logical partitions. For example, logical partition 208 includes one or more logical processors, each of which represents all or a share of physical processor resources 204 that can be dynamically assigned to a logical partition.

[0056] Further, the memory 202 is coupled to an I / O subsystem 206. The I / O subsystem 206 may be part of the central electronic complex or separate therefrom. It directs the flow of information between the main memory 202 and an input / output control unit 230 and input / output (I / O) devices 240 coupled to the central electronic complex.

[0057] Many types of I / O devices can be used. One particular type is a data storage device 250. The data storage device 250 can store one or more programs 252, one or more computer-readable program instructions 254, and / or data, etc. The computer-readable program instructions can be configured to perform the functions of embodiments of various aspects of the present invention.

[0058] In one example, processor 204 includes a sort / merge component (or other component) 260 for performing one or more sorts and / or merges (or other operations that may utilize one or more aspects of the present invention). In different examples, there may be one or more components that perform these tasks. Many variations are possible.

[0059] The central electronic complex 200 may include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, it may include and / or be coupled to non-removable non-volatile magnetic media (commonly referred to as a "hard drive"), a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and / or an optical disk drive for reading from or writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media). It should be understood that other hardware and / or software components may be used in conjunction with the central electronic complex 200. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems.

[0060] Furthermore, the central electronic complex 200 can operate with numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations that may be suitable for use with the central electronic complex 200 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, among others.

[0061] Although various examples of computing environments are described herein, one or more aspects of the present invention may be used with many types of environments. The computing environments provided herein are merely examples. Furthermore, although one or more aspects of the present invention are described with reference to sorting instructions, one or more aspects are applicable to other processes and / or instructions that utilize a large number of execution cycles and are interruptible. Sorting instructions are merely one example.

[0062] According to one aspect of the present invention, processor (for example processor 102 or 204) adopts a kind of enhanced sorting facility that is provided for the mechanism that multiple unsorted input data lists are sorted into the output data lists of one or more sorts.In one example, when facility indicator is set to for example 1, this enhanced sorting facility is installed in system.As a specific example of z / Architecture hardware framework, when the enhanced sorting facility is installed with z / Architecture framework pattern, facility bit 150 is set to (for example) 1.In one embodiment, this facility also provides the mechanism that is used for multiple sorted input data lists are merged into the output data list of single sort.This facility comprises for example list sort instruction, and its embodiment is described below.

[0063] Reference Figures 3A-3K An embodiment of details related to a list sort instruction is described. In one example, the instruction is executed on a general-purpose processor (e.g., processor 102 or 204). In the description herein, specific locations, specific fields, and / or specific sizes of fields (e.g., specific bytes and / or bits) are indicated. However, other locations, fields, and / or sizes may be provided. Further, while a bit is specified to be set to a specific value (e.g., 1 or 0), this is merely an example. In other examples, the bit may be set to a different value, such as an opposite value or another value. Many variations are possible.

[0064] Reference Figure 3AIn one example, the format of the sort list (SORTL) instruction 300 is an RRE format representing register and register operations with extended opcodes. As an example, the instruction includes an opcode field 302 (e.g., bits 0-15) with an opcode indicating a sort and / or merge operation, a first register field (R1) 304 (e.g., bits 24-27) specifying a first pair of general registers, and a second register field (R2) 306 (e.g., bits 28-31) specifying a second pair of general registers. The contents of the register specified by the R1 field 304 specify the location of the first operand (in storage), and the contents of the register specified by the R2 field 306 specify the location of the second operand (in storage). The contents of R1+1 specify the length of the first operand, and the contents of R2+1 specify the length of the second operand. In one example, bits 16-23 of the instruction are reserved and should contain zeros; otherwise, the program may operate incompatible in the future. As used herein, a program is a program that issues a sort list instruction. It can be a user program, an operating system, or another type of program.

[0065] In one embodiment, execution of an instruction includes the use of one or more implicit general registers (i.e., registers not explicitly specified by the instruction). For example, general registers 0 and 1 are used to execute a list sort instruction, as described herein. In one example, general register 0 is used to specify whether a merge is to be performed and to specify the sorting function to be performed by the instruction, and general register 1 is used to provide the location of a parameter block used by the instruction. In another example, general register 0 is not used to specify whether a merge is to be performed; instead, the merge is set / unset by the machine (e.g., processor) and cannot be changed by a mode indicator. Other variations are possible.

[0066] As an example, see Figure 3B , general register 0 (308) contains a merge mode field 310 (described below) and a function code field 312. In one particular example, bit positions 57-63 of general register 0 contain the function code; however, in other embodiments, other bits may be used to contain the function code. In one example, a designated exception is recognized when bits 57-63 of general register 0 specify an unassigned or uninstalled function code.

[0067] Example of list sorting instruction assigned function code in Figure 3C, including, for example: function code 0 (313) indicating the SORTL-QAF (Query Available Function) function; function code 1 (315) indicating the SORTL-SFLR (Fixed Length Record Sorting) function; and function code 2 (317) indicating the SORTL-SVLR (Variable Length Record Sorting) function. Each code uses a parameter block, and in one example, the size of the parameter block depends on the function. For example, for the SORTL-QAF function, the parameter block is 32 bytes; for SORTL-SFLR and SORTL-SVLR, the parameter block is 576+16xN IS , where N IS is the number of input lists specified by the interface size. In this example, no other function codes are assigned. Although example functions and function codes are described, other functions and / or function codes may be used.

[0068] As previously indicated, general register 0 also contains a merge mode field 310. In one example, bit 56 of general register 0 specifies an operating mode (merge mode) that applies to, for example, SORTL-SFLR and SORLT-SVLR functions. In one example, when the specified function is SORTL-QAF, bit 56 of general register 0 is ignored. Further, in one example, bit positions 0-55 of general register 0 are ignored.

[0069] See Figure 3D Further details are described regarding another implicit register used by the list sort instructions, general register 1. The contents of general register 1 (314), for example, specify the logical address 316 of the leftmost byte of a parameter block in storage. In one example, the parameter block is specified on a doubleword boundary; otherwise, a specified exception is recognized. Further details regarding the parameter block are described further below.

[0070] For a specified function (e.g., SORTL-QAF, SORTL-SFLR, SORTL-SVLR), the contents of general registers 0 and 1 are not modified. Further, in one example, the R1 field 304 specifies an even-odd pair of general registers. To specify an even register, do not specify general register 0; otherwise, a specified exception is recognized. When the specified function is SORTL-SFLR or SORTL-SVLR, as shown in FIG. Figures 3E-3FAs shown, the contents of general register R1 318 specify, for example, the logical address 320 of the leftmost byte of the first operand, while the contents of general register R1+1 (322) specify the length 324 of the first operand, for example, in bytes. When the specified function is SORTL-SFLR or SORTL-SVLR, for example, the first operand is specified on a doubleword boundary; otherwise, a specified exception is recognized. Data in record form is selected from the set of input lists and stored at the first operand location (for example, starting at the address specified by R1). When the SORTL-QAF function is specified, the contents of general registers R1 and R1+1 are ignored.

[0071] Additionally, for a specified function (e.g., SORTL-QAF, SORTL-SFLR, SORTL-SVLR), in one example, the R2 field 306 specifies an even-odd pair of general registers. To specify an even register, do not specify general register 0; otherwise, a specified exception is recognized. When the specified function is SORTL-SFLR or SORTL-SVLR, and the merge mode (MM) is zero, as shown in FIG. Figures 3G-3H As shown, the contents of general register R2 326 specify, for example, the logical address 328 of the leftmost byte of the second operand, and the contents of general register R2+1 (330) specify the length 332 of the second operand, for example, in bytes. In one example, when the specified function is SORTL-SFLR or SORTL-SVLR and the merge mode (MM) is zero, the second operand is specified on a doubleword boundary; otherwise, a specified exception is recognized. When MM is zero, the starting address and length of each output list (referred to as the output list description (OLD)) are stored at the second operand location (e.g., starting at the address specified by R2). When the SORTL-QAF function is specified or MM is 1, the contents of general registers R2 and R2+1 are ignored.

[0072] During execution, in one embodiment, the function specified by the function code in general register 0 is performed. In one embodiment, as part of the operation when the specified function is SORTL-SFLR or SORTL-SVLR, the following operations occur:

[0073] The address in general register R1 is incremented by the number of bytes stored at the first operand location, and the length in general register R1+1 is decremented by the same number.

[0074] When MM is 0, the address in general register R2 is incremented by the number of bytes stored at the second operand location, and the length in general register R2+1 is decremented by the same number.

[0075] In one example, the formation and updating of the address and length depend on the addressing mode.

[0076] In 24-bit addressing mode, in one embodiment, the following applies:

[0077] The contents of bit positions 40-63 of general register 1, R1 and R2 constitute the addresses of the parameter block, first operand and second operand respectively, and the contents of bit positions 0-39 are ignored.

[0078] Bits 40-63 of the updated first and second operand addresses replace the corresponding bits in general registers R1 and R2, respectively. A carry from bit position 40 of the updated address is ignored, and the contents of bit positions 32-39 of general registers R1 and R2 are set to 0. The contents of bit positions 0 through 31 of general registers R1 and R2 remain unchanged.

[0079] The contents of bit positions 32-63 of general registers R1+1 and R2+1 form a 32-bit unsigned binary integer specifying the number of bytes in the first and second operands, respectively. The contents of bit positions 0 through 31 of general registers R1+1 and R2+1 are ignored.

[0080] Bits 32-63 of the updated first and second operand lengths replace the corresponding bits in general registers R1+1 and R2+1, respectively. The contents of bit positions 0 to 31 of general registers R1+1 and R2+1 remain unchanged.

[0081] In 31-bit addressing mode, in one embodiment, the following applies:

[0082] The contents of bit positions 33-63 of general register 1, R1 and R2 constitute the addresses of the parameter block, first operand and second operand respectively, and the contents of bit positions 0-32 are ignored.

[0083] Bits 33-63 of the updated first and second operand addresses replace the corresponding bits in general registers R1 and R2, respectively. A carry from bit position 33 of the updated address is ignored, and the contents of bit position 32 of general registers R1 and R2 are set to 0. The contents of bit positions 0-31 of general registers R1 and R2 remain unchanged.

[0084] The contents of bit positions 32-63 of general registers R1+1 and R2+1 form a 32-bit unsigned binary integer specifying the number of bytes in the first and second operands, respectively. The contents of bit positions 0-31 of general registers R1+1 and R2+1 are ignored.

[0085] Bits 32-63 of the updated first and second operand lengths replace the corresponding bits in general registers R1+1 and R2+1, respectively. The contents of bit positions 0-31 of general registers R1+1 and R2+1 remain unchanged.

[0086] In 64-bit addressing mode, in one embodiment, the following applies:

[0087] The contents of bit positions 0-63 of general register 1, R1 and R2 constitute the addresses of the parameter block, the first operand and the second operand, respectively.

[0088] Bits 0-63 of the updated first and second operand addresses replace the corresponding bits in general registers R1 and R2, respectively. Carries from bit position 0 of the updated addresses are ignored.

[0089] The contents of bit positions 0-63 of general registers R1+1 and R2+1 form a 64-bit unsigned binary integer specifying the number of bytes in the first and second operands, respectively.

[0090] Bits 0-63 of the updated first operand and second operand lengths replace the corresponding bits in general registers R1+1 and R2+1, respectively.

[0091] In access register mode, access registers 1, R1, and R2 specify the address space containing the parameter block, the first operand, and the second operand, respectively.

[0092] Further details about the different features are described below:

[0093] Function Code 0: SORTL-QAF (Query Available Functions)

[0094] The SORTL-QAF (query) function provides a mechanism to indicate the availability of all installed functions, the installed parameter block formats, and the available interface sizes. The interface size is the number of input lists available to a program. The size of the parameter blocks for the SORT-SFLR and SORT-SVLR functions is proportional to the interface size specified by the program.

[0095] Reference Figure 3I An example format of a parameter block describing a SORTL-QAF function. In one example, a parameter block 340 for a SORTL-QAF function (e.g., function code 0) includes an installed functions vector 342, an installed interface size vector 344, and an installed parameter block format vector 346. In one specific example, these vectors are stored in bytes 0 to 15, byte 16, and bytes 24 to 25 of the parameter block, respectively. Each of these vectors is further described below.

[0096] As an example, bits 0-127 of the installed function vector 342 correspond to function codes 0-127 of the list sorting instruction, respectively. If a bit is 1, for example, the corresponding function is installed; otherwise, the function is not installed.

[0097] Furthermore, in one example, bits 0-7 of installed interface size vector 344 indicate the interface size available to the program. The interface size is the number of input lists specified by the program for the SORT-SFLR and SORTL-SVLR functions. In one example, bits 0-7 of installed interface size vector 344 correspond to the following interface sizes: bits 0, 1, 5-7 are reserved; bit 2 – 32 input lists; bit 3 – 64 input lists; and bit 4 – 128 input lists. Other examples are possible.

[0098] When a bit of installed interface size vector 344 is, for example, 1, the corresponding interface size is available to the program. One or more bits may be stored as 1. For example, the binary value 00101000 indicates that interface sizes for 32 and 128 input lists are available. In one example, bits 0-1 and 5-7 are reserved bits and are stored as 0. Furthermore, in one example, when the enhanced sort facility is installed, an interface size for 32 input lists is available. Therefore, bit 2 is stored as 1. Other examples are also possible.

[0099] In addition to the above, in one example, bits 0-15 of the installed parameter block format vector 346 correspond to parameter block formats 0 to 15, respectively. When a bit is 1, the corresponding parameter block format is installed; otherwise, the parameter block format is not installed. In one example, 0s are stored in reserved bytes 17-23 and 26-31 of the parameter block.

[0100] The SORT-QAF function ignores the contents of general registers R1, R2, R1+1, and R2+1.

[0101] When applicable, PER (Program Event Recording) storage change events are identified for parameter blocks. When applicable, PER zero address detection events are identified for parameter blocks.

[0102] Condition code 0 is set when execution of the SORTL-QAF function is complete; in one example, condition codes 1, 2, and 3 are not applicable to the query function.

[0103] Function Code 1: SORTL-SFLR (Sort Fixed-Length Records)

[0104] In one example, the input list set is sorted and stored as the output list set at the first operand position. Each list is a set of records, referenced Figure 3J , each record 350 includes a key 352 (eg, a fixed-length key) and a payload 354 (eg, a fixed-length payload).

[0105] Sorts the records from the input list based on the value of the key. As described below, the records can be sorted in ascending or descending order, as specified in the Sort Order (SO) field of the parameter block associated with function code 1. The records of the input list can be listed in sorted order or not.

[0106] The records of an output list can originate from multiple input lists and are stored in sorted order. The number of output lists stored in the first operand position depends on the input data. In one example, only one output list is generated when each active input list contains records listed in the same order as specified in the SO field.

[0107] As indicated above, bit 56 of general register 0 specifies the operating mode (referred to as merge mode (MM)) applicable to the SORTL-SFLR function. When merge mode is (e.g.) 0, for each output list stored at the first operand location, a corresponding output list description (OLD) is stored at the second operand location. Each OLD comprises, for example, an 8-byte OLD-address that specifies the position of the first record in the corresponding output list and an 8-byte OLD-length that specifies the length, e.g., in bytes, of the corresponding output list. When merge mode is 1, the input lists are considered pre-sorted. That is, each active input list is considered to contain records in the same order as specified by the SO field of the parameter block.

[0108] When MM is 1 and each input list is pre-sorted, the result stored at the first operand position is a single output record list in sorted order. When MM is 1 and each input list is not pre-sorted, the result is unpredictable.

[0109] When MM is, for example, 1, the contents of general registers R2 and R2+1 are ignored, and no information is stored in the second operand location. When MM is 1, the routine for distinguishing between output lists may not be executed, thereby potentially improving the performance of the operation. When MM is 1, no data is stored in the continuation record recall buffer described below.

[0110] In one example, to generate a single list of records in sorted order from a collection of records in random order, a program may perform the following process:

[0111] 1. Evenly divide the set of records among an initial set of lists, where each list contains records in random order. Execute the list sort instruction with the initial set of lists as input lists and merge mode equal to 0 to generate a set of intermediate lists (where each list contains records in sorted order), as well as the storage location and length of each list in the intermediate set of lists.

[0112] 2. Execute the list sort command with the intermediate list set as input list and merge mode equal to 1 to produce a final and single list containing the records in sorted order.

[0113] Figure 4A An example of SORTL-SFLR with merge mode equal to 0 is illustrated in FIG. The example includes inputs and result outputs. As shown in the figure, there are three input lists 400: input list0, input list1, and input list2. Further, an example of the result first operand 402 and the second operand 404 is shown. In one example, the first operand 402 ( Figure 4A ), and as shown in 404 in the second operand, one starts at address 1000 and has a length of 18; another starts at address 1018 and has a length of 28; and the third starts at address 1040 and has a length of 20.

[0114] In one example, when two operations perform the same SORTL-SFLR function on the same set of unsorted input records with merge mode equal to 0 and the only difference between the two operations is the number of input lists used to specify the input data, the operation with the larger number of input lists results in a smaller number of output lists. Figure 4B The use of six input lists 450 is shown in contrast to the use of three input lists. Figure 4A Also shown is a result first operand 452 having two output lists instead of three and a second operand 454 providing a description of the two output lists.

[0115] As indicated, the SORTL-SFLR function uses parameter blocks, an example of which is given in Figure 3K In the example parameter blocks described herein, specific locations (e.g., specific bytes and / or bits) within the parameter blocks are indicated for specific fields and specific sizes of fields. However, other locations and / or sizes may be provided for one or more fields. Further, while bits are specified as being set to specific values (e.g., 1 or 0), this is merely an example. In other examples, bits may be set to different values, such as the opposite value or another value. Many variations are possible.

[0116] In one example, the parameter block 360 of the SORTL-SFLR function contains the following:

[0117] Parameter Block Version Number (PBVN) 362: Bytes 0-1 of the parameter block specify the version and size of the parameter block. Bits 0-7 of the PBVN have the same format and definition as bits 0-7 of the Interface Size List Vector (byte 16) of the parameter block used for the SORTL-QAF (query) function. Bits 0-7 specify the number N of input lists described in the parameter block. IS By evaluating the formula (576+16xN IS ) determines the size of the parameter block in bytes. One of bits 0-7 shall have the value 1; otherwise, a general operand data exception is recognized. Bits 8-11 of the PBVN are reserved and should contain 0; otherwise, the program may not operate compatibly in the future. Bits 12-15 of the PBVN contain an unsigned binary integer that specifies the format of the parameter block. The SORTL-QAF function provides a mechanism to indicate the available parameter block formats. A general operand data exception is recognized when the size or format of the specified parameter block is not supported by the model. The PBVN is specified by the program and is not modified during the execution of the instruction.

[0118] Model Version Number (MVN) 364: Byte 2 of the parameter block is an unsigned binary integer that identifies the model on which the instruction is executed. The MVN is updated during execution of the instruction by, for example, a processor. The value stored in the MVN is model-dependent.

[0119] When the continue flag (CF) 368, described below, is 1, the MVN is input to the operation. When CF is 1 and the MVN identifies the same model as the currently executing instruction, data from the continuation state buffer (CSB) 390, described below, can be used to resume the operation. When CF is 1 and the MVN identifies a different model than the currently executing instruction, some or all of the CSB field may be ignored.

[0120] In one example, the program initializes MVN to zero. It is expected that the program does not modify MVN when instructions are re-executed for the purpose of recovery operation; otherwise, the results are unpredictable.

[0121] Sort Order (SO) 366: Bit 56 of the parameter block specifies ascending sort order when 0 and descending sort order when 1. When ascending sort order is specified, each record in the output list contains a key that is greater than or equal to the key of the adjacent record in the same output list (e.g., to the left). When descending sort order is specified, each record in the output list contains a key that is less than or equal to the key of the adjacent record in the same output list (e.g., to the left). SO is not updated during execution of the instruction.

[0122] Continue Flag (CF) 368: Bit 63 of the parameter block, when set to 1, indicates that the operation is partially completed and the contents of the status buffer 390 are continued. When the merge mode (MM) is 0, the operation can be resumed using the contents of the resume record recall buffer. The program will initialize the Continue Flag (CF) to zero and not modify it if the instruction is re-executed for the purpose of resuming the operation; otherwise, the results are unpredictable. In one example, the processor modifies the CF if the instruction is to be re-executed.

[0123] Record Key Length 370: Bytes 10-11 of the parameter block contain an unsigned binary integer that specifies the size in bytes of the key in the record processed during the operation. In one example, a general operand data exception is recognized for any of the following conditions:

[0124] Specifies a key size of zero bytes.

[0125] Specify a key size that is not a multiple of 8.

[0126] Specify a key size larger than 4096 bytes.

[0127] The record key length is not updated during the execution of the instruction.

[0128] Record Payload Length 372: When the SORTL-SFLR function is specified, bytes 14-15 of the parameter block contain an unsigned binary integer that specifies the size, in bytes, of the payload in the record processed during the operation. In one example, a general operand data exception is recognized for any of the following conditions:

[0129] A payload size was specified that is not a multiple of 8.

[0130] The sum of the specified key and payload size is greater than 4096 bytes.

[0131] A payload size of zero is valid.

[0132] When the SORTL-SVLR function is specified, the record payload length field of the parameter block is ignored. The record payload length is not updated during the execution of the instruction.

[0133] Operand Access Intent (OAI) 374: Bits 0-1 of byte 32 of the parameter block indicate to the CPU future access intentions for the input list and the first operand. The provided access intentions can be used to modify cache line installation and replacement policies for corresponding storage locations at different levels of cache in the storage hierarchy.

[0134] When bit 0 of the OAI field is 1, the storage location designated as containing data for any active input list will be referenced as one or more operands of subsequent instructions. When bit 0 of the OAI field is 0, the storage location designated as containing data for any active input list will not be referenced as one or more operands of subsequent instructions.

[0135] When bit 1 of the OAI field is 1, the storage location designated as containing the first operand will be referenced as one or more operands of subsequent instructions. When bit 1 of the OAI field is 0, the storage location designated as containing the first operand will not be referenced as one or more operands of subsequent instructions.

[0136] There is no guarantee that the CPU will use this information. The duration for which it can use this information is undefined, but finite.

[0137] When the next sequential instruction after the Next Instruction Access Intent (NIAI) is a sort list (SORTL), the execution of SORTL is not affected by the NIAI.

[0138] The OAI is not updated during the execution of the instruction.

[0139] Active Input Lists Count Code (AILCC) 376: Bits 1-7 of byte 33 of the parameter block are a 7-bit unsigned integer that specifies the number of input lists indicating the boundary between active and inactive input lists. Input lists with list numbers that are, for example, less than or equal to the value of the AILCC field are active. Input lists with list numbers that are, for example, greater than the value of the AILCC field are inactive. The number of active input lists is one more than the value in the AILCC field.

[0140] Active input lists participate in the operation. Inactive input lists do not participate in the operation.

[0141] Bit 0 of byte 33 of the parameter block is reserved and should contain zero; otherwise, the program may operate incompatible in the future.

[0142] In one example, a general operand data exception is recognized when the value of the AILCC field plus one is greater than the number of input lists described in the parameter block (as specified by bits 0 through 7 of the PBVN field).

[0143] The value specified in the AILCC field does not affect the size of the parameter block. Access exceptions apply to references to fields of a parameter block that specify the input list address or length corresponding to an inactive input list.

[0144] The AILCC is not updated during the execution of an instruction.

[0145] Empty Input Lists Control (EILCL) 378: When bit 0 of byte 40 of the parameter block is 1, when the length of input list0 becomes zero during the operation, the operation ends. When bit 0 of byte 40 of the parameter block is zero, when the length of input list0 becomes zero during the operation, the operation continues. When bit 1 of byte 40 of the parameter block is 1, when the length of the active input list other than input list0 becomes zero during the operation, the operation ends. When bit 1 of byte 40 of the parameter block is zero, when the length of the active input list other than input list0 becomes zero during the operation, the operation continues.

[0146] When the length of the active input list is initially zero before executing an instruction, the corresponding bit of EILCL does not apply.

[0147] EILCL is not updated during the execution of an instruction.

[0148] It is expected that the program does not modify EILCL when re-executing instructions for the purpose of recovery; otherwise, the results are unpredictable.

[0149] Empty Input List Flag (EILF) 380: When EILCL is binary 11 and the operation ends because the updated length of the active input list is equal to zero, and condition code 2 is set, then the value 1 is stored by the processor, for example, in bit 2 of byte 40 of the parameter block; otherwise, the value 0 is stored in bit 2 of byte 40 of the parameter block. When EILF contains a value of 1, the input list number of the input list that became empty during the operation is placed in the EILN field of the parameter block. In one example, the program initializes EILF to zero.

[0150] When resuming an operation, the EILF may be referenced at the start of execution of an instruction. It is expected that the program does not modify the EILF when re-executing instructions for the purpose of resuming an operation; otherwise, the results are unpredictable.

[0151] Empty Input List Number (EILN) 382: When the condition is such that a value of 1 is stored in the EILF field, the input list number of the input list that becomes empty during operation is stored by the processor, for example, in byte 41 of the parameter block; otherwise, a value of 0 is stored in byte 41 of the parameter block.

[0152] EILN is ignored at the beginning of the operation. In one example, the program initializes EILN to zero.

[0153] Incomplete Input List Flag (IILF) 384: When the operation ends due to an attempt to process an incomplete input list, the value 1 is stored in bit 0 of byte 46 of the parameter block; otherwise, the value 0 is stored in bit 0 of byte 46 of the parameter block, for example, by the processor. An active input list is considered incomplete when the corresponding input list length is greater than zero and less than the number of bytes of the record specified by the input list address. This condition may exist at the beginning of the operation or may be encountered during operation. When the IILF contains the value 1, the input list number of the encountered incomplete input list is placed in the IILN field of the parameter block. In one example, the program initializes the IILF to zero.

[0154] When the operation ends with condition code 2 set and the result value in the IILF field is zero, the operation ended due to an empty input list. When the operation ends with condition code 2 set and the result value in the IILF field is 1, the operation ended due to an incomplete input list.

[0155] When resuming an operation, the IILF may be referenced at the start of execution of an instruction. It is expected that the program does not modify the IILF when re-executing instructions for the purpose of resuming an operation; otherwise, the results are unpredictable.

[0156] Incomplete Input List Number (IILN) 386: When a condition causes a value of 1 to be stored in the IILF field, the processor stores the input list number of the incomplete input list encountered, for example, in byte 47 of the parameter block; otherwise, a value of zero is stored in byte 47 of the parameter block. When multiple input lists are incomplete, which incomplete input list number is stored in the IILN field depends on the model. In one example, the program initializes IILN to zero.

[0157] IILN is ignored at the start of the operation.

[0158] Continuation Record Recall Buffer Origin 388: A 4K-byte buffer in the storage device (called the Continuation Record Recall Buffer) is provided by the program for the CPU to store and reference data between two executions of the same list sort instruction (in case the operation is completed and can be resumed later). The 52 bits of the parameter block, starting from bit 0 of byte 56 to bit 3 of byte 62, contain an unsigned binary integer used in forming the Continuation Record Recall Address, which is aligned on a 4K-byte boundary. The Continuation Record Recall Address is, for example, the logical address of the leftmost byte of the Continuation Record Recall Buffer.

[0159] In the 24-bit addressing mode, bits 40 to 51 of the start of the continue recording recall buffer with 12 zeros appended to the right form the continue recording recall address. In the 31-bit addressing mode, bits 33 to 51 of the start of the continue recording recall buffer with 12 zeros appended to the right form the continue recording recall address. In the 64-bit addressing mode, bits 0 to 51 of the start of the continue recording recall buffer with 12 zeros appended to the right form the continue recording recall address.

[0160] In the access register mode, access register 1 specifies the address space in the storage device that contains the continue recording recall buffer.

[0161] When the merge mode (MM) is zero, the operation ends after storing one or more records and no normal completion occurs, and the key of the last record stored in the first operand is also stored in the continue record recall buffer. When MM is 1, the start of the continue record recall buffer is ignored.

[0162] The resume recording recall buffer start point is not modified during the execution of the instruction.

[0163] It is expected that in the event that instructions are re-executed for the purpose of recovery operations, the program does not modify the resume record recall buffer starting point; otherwise, the results are unpredictable.

[0164] Continuation State Buffer (CSB) 390: When conditions cause a value of 1 to be stored in the CF field, internal state data is stored, for example, by the processor, in bytes 64-575 of the parameter block; otherwise, bytes 64-575 of the parameter block are undefined and modifiable. The stored internal state data is model-dependent and can be subsequently used to resume operation when the instruction is re-executed. In one example, the program initializes the Continuation State Buffer to zero. It is expected that the program does not modify the Continuation State Buffer when re-executing instructions for the purpose of resuming operation; otherwise, the results are unpredictable.

[0165] As an example, the internal state data includes information related to the input list, such as information about previous comparisons of records of the input list to determine the next comparison to be performed. The internal state data is model-dependent in that it can be stored or submitted differently depending on the processor model. Other variations are possible.

[0166] In one embodiment, an instruction may be partially completed by one model in the configuration, and execution may be resumed on a different model in the configuration. While different models may maintain different internal states in one embodiment, in one example, each model must be able to interpret those contents of the CSB that are used to resume the operation (if any). When the operation is resumed, the MVN indicates which contents of the CSB the machine is able to interpret (if any).

[0167] Input List N Address 392, 394, 396: This parameter block defines multiple input lists. The number of input lists defined in the parameter block is N. IS Specified by bits 0-7 of PBVN 362. Input list from zero to (N IS -1). For each input list, the parameter block specifies, for example, an 8-byte input list address. For the Nth input list, the contents of bytes 576+16xN to 583+16xN of the parameter block specify, for example, the logical address of the leftmost byte of the Nth input list in the storage device.

[0168] Each input list address corresponding to an active input list specified by the AILCC field is input to the operation and updated by the operation. Each input list address corresponding to an inactive input list specified by the AILCC field is ignored by the operation.

[0169] In one embodiment, when an input list address is input to an operation, the following applies:

[0170] In 24-bit addressing mode, bits 40-63 of the input list address specify the location of the leftmost byte of the input list in the storage device, and the contents of bits 0-39 of the input list address are considered to be zero.

[0171] In 31-bit addressing mode, bits 33-63 of the input list address specify the location of the leftmost byte of the input list in the storage device, and the contents of bits 0-32 of the input list address are considered to be zero.

[0172] In 64-bit addressing mode, bits 0-63 of the input list address specify the location of the leftmost byte of the input list in storage.

[0173] In access register mode, access register 1 specifies the address space in the memory device that contains the active input list.

[0174] For an input list to be active, the corresponding input list address is specified on a doubleword boundary; otherwise, in one example, a general operand data exception is recognized.

[0175] In one embodiment, when an input list address is updated by an operation, the following applies:

[0176] When one or more records of the input list have been processed as part of an operation, the corresponding input list address is incremented by the number of bytes that the processed record occupies in the storage device.The formation and updating of the input list address depends on the addressing mode.

[0177] In 24-bit addressing mode, bits 40-63 of the updated input list address replace the corresponding bits in the input list address field of the parameter block, the carry out of bit position 40 of the updated input list address is ignored, and the contents of bit positions 0-39 of the input list address field of the parameter block are set to zero.

[0178] In 31-bit addressing mode, bits 33-63 of the updated input list address replace the corresponding bits in the input list address field of the parameter block, the carry from bit position 33 of the updated input list address is ignored, and the contents of bit positions 0-32 of the input list address field of the parameter block are set to zero.

[0179] In 64-bit addressing mode, bits 0-63 of the updated input list address replace the corresponding bits in the input list address field of the parameter block, and carries from bit position 0 of the updated input list address are ignored.

[0180] In 24-bit and 31-bit addressing modes, the input list address corresponding to each 64 bits of the active input list is updated when execution of the instruction ends and the instruction is not suppressed, invalidated, or aborted, even when the address is not incremented.

[0181] Input List N Length 393, 395, 397: For each input list, the parameter block specifies the 8-byte input list length. For the Nth input list, bytes 584+16xN to 591+16xN of the parameter block contain an unsigned integer specifying the number of bytes in the Nth input list.

[0182] The length of each input list corresponding to the active input list specified by the AILCC field is input to the operation and is updated by the operation. The length of each input list corresponding to the inactive input list specified by the AILCC field is ignored by the operation.

[0183] In various addressing modes, the contents of bit positions 0-63 of the Input List Length field specify the length of the corresponding input list.

[0184] When one or more records of an input list have been processed as part of an operation, the corresponding input list length is reduced by the number of bytes occupied in the storage device by the processed records. In various addressing modes, bits 0-63 of the updated input list length replace bits 0-63 of the corresponding input list length field of the parameter block.

[0185] Reserved fields: There are several reserved fields in the parameter block (i.e., fields that do not contain other information). As input to an operation, reserved fields should contain zeros; otherwise, future operations of the program may be incompatible. When the operation ends, the reserved fields can be stored as zeros or left unchanged.

[0186] Figures 5A-5B An example of the original and final values of the input for the SORTL-SFLR function including the fields in the parameter block is summarized.

[0187] In one embodiment, it is not necessary and undesirable for the program to modify the parameter block between ending the operation with condition code 3 set and branching back to the instruction to re-execute the instruction for purposes of resuming the operation.

[0188] In one embodiment, the SORTL-SFLR function includes multiple comparisons between keys of records from different input lists. In one example, when comparing keys, the following applies:

[0189] Treat keys as unsigned binary integers, also known as unstructured data.

[0190] When determining which key contains the lowest or highest value, it is not necessary to access all bytes of each key being compared. The number of bytes per key compared (called the unit of key comparison) is model-dependent. The number of bytes of a key accessed is an integral number of units of key comparison.

[0191] When comparing keys of equal value, in one example, the key from the input list with the highest input list number is selected to precede other keys with the same value in the sort order. In this case, the corresponding record from the input list with the highest input list number is stored to the first operand before other records with the same key value. This applies to both ascending and descending sort orders.

[0192] One implementation can maintain a history of previous comparisons between records from the active input list. When this history is available and applicable, it can be referenced instead of accessing and comparing previously compared records. Reference to this history reduces the execution time required to generate results, thereby improving processing within the computing environment.

[0193] The SORTL-SFLR function involves selecting records from a set of input lists in a specified sort order and placing the selected records at the first operand location. As the operation proceeds, the current values of the first operand address and the address of the active input list are maintained. The function is performed in units of operations. During each unit of operation, for each active input list, the key specified by the corresponding current input list address is checked and a record is placed at the first operand location.

[0194] When the merge mode (MM) is zero, the active input list specifies a list in a random order, for example, from left to right, and each of the lists is considered to contain records. When MM is zero, the records stored in the first operand position constitute one or more output lists, and the starting address and length of each output list are stored in the second operand position. When MM is zero, each operation unit includes the following steps as an example in the specified order:

[0195] 1. Determine whether the next record to be stored to the first operand location can be included in the most recent output list (the output list that includes the record most recently stored to the first operand location) as follows:

[0196] When the continue flag (CF) is zero and the first operation unit is being processed, no record has yet been stored to the first operand location, and the next record to be stored will be the first record of the output list.

[0197] When CF is 1, the previous execution of the instruction ended with condition code 1, and while the first operation unit is being processed for the current execution of the instruction, the next record to be stored will be the first record of the output list.

[0198] When CF is 1, IILF is zero, EILF is zero, the previous execution of the instruction ended with condition code 2, and the first operation unit is being processed for the current execution of the instruction, the next record to be stored will be the first record of the output list.

[0199] When CF is 1, IILF or EILF is 1, the previous execution of the instruction ended with condition code 2, and the first operation unit is being processed for the current execution of the instruction, the next record to be stored may be included in the most recent output list.

[0200] When CF is 1, the previous execution of the instruction ended with condition code 3, and the first operation unit is being processed for the current execution of the instruction, the next record to be stored may be included in the most recent output list.

[0201] When the operation unit being processed is not the first operation unit of the current execution of the instruction, the next record to be stored may be included in the most recent output list.

[0202] 2. When the next record to be stored can be included in the most recent output list, determine the set of records that are eligible to be included in the most recent output list. For each input list that is active, non-empty, and not incomplete, compare the key of the record specified by the current input list address (the current input key) with the key of the record most recently stored to the first operand position (the previously stored key). For this purpose, the reference to the previously stored key is not a reference to the first operand position. Instead, it is a reference to the input list from which the key was selected, or it is a reference to the continue record recall buffer. When the operation is being resumed and the current execution of the instruction has not yet placed any record at the first operand position, it is a reference to the continue record recall buffer.

[0203] When the sort order is ascending and the value of the current input key is greater than or equal to the value of the previously stored key, the current input key is considered to belong to the set of keys that are eligible for inclusion in the most recent output list. When the sort order is descending and the value of the current input key is less than or equal to the value of the previously stored key, the current input key is considered to belong to the set of keys that are eligible for inclusion in the most recent output list. When the number of keys in the set of keys that are eligible for inclusion in the most recent output list is zero, the next record to be stored will be the first record in the output list. When the number of keys in the set of keys that are eligible for inclusion in the most recent output list is non-zero, the next record to be stored will be included in the most recent output list.

[0204] 3. When the next record to be stored is included in the most recently output list, compare the keys in the key set that are eligible for inclusion in the most recently output list. When the sort order is ascending, select the smallest key value and corresponding record. When the sort order is descending, select the largest key value and corresponding record.

[0205] 4. When the next record to be stored will be the first record of the output list, compare the keys of the records specified by the current input list address with those corresponding to the active, non-empty, and non-incomplete input list. When the sort order is ascending, select the smallest key value and corresponding record. When the sort order is descending, select the largest key value and corresponding record.

[0206] 5. Place the selected record at the current first operand position.

[0207] 6. Increment the current first operand address by a number of bytes equal to the selected record length.

[0208] 7. Increment the current input list address corresponding to the input list containing the selected record by a number of bytes equal to the length of the selected record.

[0209] As the part of operation when merging pattern is zero, for each output list that is stored in the first operand position, corresponding output list description (OLD) is stored in the second operand position.Each OLD comprises the OLD address of for example 8 bytes of the position of the first record in the specified corresponding output list, and the OLD length of for example 8 bytes of the length (in byte) of the specified corresponding output list.When operation equals 1 condition code 3, condition code 2 and EILF or finishes with condition code 2 and IILF that equal 1, the nearest output list being processed when operation finishes can be part processing and incomplete processing. That is, the quantity of the record in the output list of part processing is an intermediate value, and can increase when operation is recovered. In this case, the output list description (OLD) corresponding to the output list of part processing will not be placed on the second operand position, until after having recovered operation and having processed output list fully.

[0210] When the merge mode is zero and the operation ends after storing one or more records and normal completion does not occur, the key of the last record stored to the first operand location is also stored to the continuation record recall buffer.

[0211] When the merge mode is zero and the operation ends due to normal completion, one or more output lists have been placed at the first operand location, and an output list description has been placed at the second operand location. The program can use the output list description as the input list address and length value in the parameter block of a subsequent SORTL operation.

[0212] Figures 6A-6D 1 and 2 are shown before and after performing SORTL-SFLR with merge mode equal to zero. Figures 6A-6B , FOSA 600 is the first operand start address: the location specified by R1; FOEA 602 is the first operand end address: the location specified by R1+(R1+1)-1; and OL 604 is the output list (e.g., output list 1...output list N). Further, referring to Figures 6C-6D , SOSA 610 is the second operand starting address: the location specified by R2; SOEA 612 is the second operand ending address: the location specified by R2+(R2+1)−1; and OLD 614 is the output list designation (e.g., output list designation 1 . . . output list designation N).

[0213] When the merge mode (MM) is 1, the active input lists specify that each is treated as a list containing records in the sort order specified by the SO field of the parameter block from left to right. When MM is 1, the records stored in the first operand position constitute a single output list. When MM is 1, each unit operation includes, for example, the following steps in the specified order:

[0214] 1. Compare the keys of the records specified by the current input list address against the active, non-empty, and incomplete input list. When the sort order is ascending, select the smallest key value and corresponding record. When the sort order is descending, select the largest key value and corresponding record.

[0215] 2. Place the selected record at the current first operand position.

[0216] 3. Increment the current first operand address by a number of bytes equal to the selected record length.

[0217] 4. Increment the current input list address corresponding to the input list containing the selected record by a number of bytes equal to the length of the selected record.

[0218] Figures 7A-7B The first operand is illustrated before and after performing SORTL-SFLR with merge mode equal to 1. Figures 7A-7B , FOSA 700 is the first operand starting address: the location specified by R1; FOEA 702 is the first operand ending address: the location specified by R1+(R1+1)−1; and OL 704 is the output list (eg, output list 1).

[0219] As part of the operation when the merge mode is zero or one, the input list address and length of the active input list are updated. For each active input list, the input list address is incremented by the number of bytes from the record selected during the operation and placed at the first operand position, and the input list length is decremented by the same number. The formation and updating of the input list address depends on the addressing mode.

[0220] As an operation proceeds, an incomplete input list may be encountered. An incomplete input list is identified during an operation unit that attempts to reference a record from the incomplete input list. Multiple operation units may complete before an incomplete input list is identified. This applies when the merge mode is 0 or 1.

[0221] As the operation proceeds, access exceptions may be encountered for accesses to the input list, the first operand, or the second operand (as applicable). An access exception is recognized during an operation unit that attempts to access a storage location for which an access exception exists. Multiple operation units may complete before an incomplete input list is recognized. This applies when the merge mode is 0 or 1.

[0222] When an operation ends with partial completion, internal state data, which may contain a history of previous comparisons between records, can be stored in the Continue State Buffer (CSB) field of the parameter block. Later, when the instruction is re-executed, the contents of the CSB can be loaded into the implementation for the purpose of resuming the operation, and the history can be referenced when the operation resumes. This applies when the merge mode is 0 or 1.

[0223] Normal completion occurs when the records from the active input list have been sorted and stored into the first operand.

[0224] In one embodiment, when an operation ends due to normal completion, the following occurs:

[0225] The address and length in general registers R1 and R1+1 are updated respectively.

[0226] When MM is zero, the address and length in general registers R2 and R2+1 are updated respectively.

[0227] Update the input listN address and input listN length fields for the active input list.

[0228] Set the model version number to be set.

[0229] The continue flag is set to zero.

[0230] The empty input list flag is set to zero.

[0231] Empty input list numbers are set to zero.

[0232] The incomplete input list flag is set to zero.

[0233] Incomplete input list numbers are set to zero.

[0234] Condition code 0 is set.

[0235] The address and length are formed and updated depending on the addressing mode.

[0236] When normal completion occurs, the CSB field of the parameter block after the operation is completed is undefined.

[0237] In one embodiment, when a CPU-determined number of bytes have been processed, the operation ends and the following occurs:

[0238] The address and length in general registers R1 and R1+1 are updated respectively.

[0239] When MM is zero, the address and length in general registers R2 and R2+1 are updated respectively.

[0240] Update the input listN address and input listN length fields for the active input list.

[0241] The model version number is set.

[0242] The continue flag is set to 1.

[0243] When MM is zero and one or more records have been placed at the first operand location during execution of the instruction, the key value is stored to the continuation record recall buffer.

[0244] The continue status buffer is updated.

[0245] The empty input list flag is set to zero.

[0246] Empty input list numbers are set to zero.

[0247] The incomplete input list flag is set to zero.

[0248] Incomplete input list numbers are set to zero.

[0249] Condition code 3 is set.

[0250] The address and length are formed and updated depending on the addressing mode.

[0251] The number of bytes determined by the CPU depends on the model and can be a different number each time an instruction is executed. The number of bytes determined by the CPU is usually non-zero. Although this number can be zero and appear as a no-progress case, the CPU protects against repeated recurrence of the no-progress case.

[0252] After an instruction completes with, for example, condition code 3 set, it is expected that the program not modify any input or output specifications of the instruction and branch back to re-execute the instruction to resume operation.

[0253] In one embodiment, when bit 0 of the empty input list control (EILCL) is 1, and the length of input list0 becomes zero during the operation, and normal completion does not apply, the operation ends and the following occurs:

[0254] The address and length in general registers R1 and R1+1 are updated respectively.

[0255] When MM is zero, the address and length in general registers R2 and R2+1 are updated respectively.

[0256] Update the input listN address and input listN length fields for the active input list.

[0257] The model version number is set.

[0258] The continue flag is set to 1.

[0259] When EILCL is binary 10 and MM is zero, the key value may be stored in the continue record recall buffer. When EILCL is binary 11 and MM is zero, the key value may be stored in the continue record recall buffer. In either case, one or more records have been placed at the first operand location during the execution of the instruction.

[0260] The continue status buffer is updated.

[0261] The empty input list flag is set (see Figure 8 , which shows the various parameter block fields when the operation ends).

[0262] Empty input list number is set (refer to Figure 8 ).

[0263] The incomplete input list flag is set to zero.

[0264] Incomplete input list numbers are set to zero.

[0265] Condition code 2 is set.

[0266] The address and length are formed and updated depending on the addressing mode.

[0267] In one embodiment, when bit 1 of the empty input list control (EILCL) is 1, and the length of the active input lists other than input list 0 becomes zero during the operation, and normal completion does not apply, the operation ends and the following occurs:

[0268] The address and length in general registers R1 and R1+1 are updated respectively.

[0269] When MM is zero, the address and length in general registers R2 and R2+1 are updated respectively.

[0270] Update the input listN address and input listN length fields for the active input list.

[0271] The model version number is set.

[0272] The continue flag is set to 1.

[0273] When EILCL is 01 binary and MM is 0, the key value may be stored in the continue record recall buffer. When EILCL is 11 binary and MM is zero, the key value may be stored in the continue record recall buffer. In either case, one or more records have been placed at the first operand location during execution of the instruction.

[0274] The continue status buffer is updated.

[0275] The empty input list flag is set (see Figure 8 ).

[0276] Empty input list number is set (refer to Figure 8 ).

[0277] The incomplete input list flag is set to zero.

[0278] Incomplete input list numbers are set to zero.

[0279] Condition code 2 is set.

[0280] The address and length are formed and updated depending on the addressing mode.

[0281] In one embodiment, when an incomplete input list is encountered in the active state, the operation ends and the following occurs:

[0282] The address and length in general registers R1 and R1+1 are updated respectively.

[0283] When MM is zero, the address and length in general registers R2 and R2+1 are updated respectively.

[0284] Update the input listN address and input listN length fields for the active input list.

[0285] The model version number is set.

[0286] The continue flag is set to 1.

[0287] When MM is zero and one or more records have been placed at the first operand location during execution of the instruction, the key value is stored to the continuation record recall buffer.

[0288] The continue status buffer is updated.

[0289] The empty input list flag is set to zero.

[0290] Empty input list numbers are set to zero.

[0291] The incomplete input list flag (IILF) is set to 1.

[0292] The input list number of the incomplete input list encountered is placed in the Incomplete Input List Number (IILN) field of the parameter block.

[0293] Condition code 2 is set.

[0294] The address and length are formed and updated depending on the addressing mode.

[0295] In one embodiment, when the length of the first operand is insufficient to store another record, the operation ends and the following occurs:

[0296] Update the address and length in general registers R1 and R1+1 respectively.

[0297] When MM is zero, the address and length in general registers R2 and R2+1 are updated respectively.

[0298] Update the input listN address and input listN length fields for the active input list.

[0299] Set the model version number to be set.

[0300] Set the continue flag to 1.

[0301] When MM is zero and one or more records have been placed at the first operand location during execution of the instruction, the key value may be stored to the continuation record recall buffer.

[0302] Update the continue status buffer.

[0303] The empty input list flag is set to zero.

[0304] Empty input list numbers are set to zero.

[0305] The incomplete input list flag is set to zero.

[0306] Incomplete input list numbers are set to zero

[0307] Set condition code 1.

[0308] The address and length are formed and updated depending on the addressing mode.

[0309] In one embodiment, when the merge mode (MM) is zero and the length of the second operand is less than 16, the operation ends and the following occurs:

[0310] Update the address and length in general registers R1 and R1+1 respectively.

[0311] Update the address and length in general registers R2 and R2+1 respectively.

[0312] Update the input listN address and input listN length fields for the active input list.

[0313] Set the model version number.

[0314] Set the continue flag to 1.

[0315] When one or more records have been placed at the first operand location during execution of the instruction, the key value may be stored to the continuation record recall buffer.

[0316] Update the continue status buffer.

[0317] The empty input list flag is set to zero.

[0318] Empty input list numbers are set to zero.

[0319] The incomplete input list flag is set to zero.

[0320] Incomplete input list numbers are set to zero.

[0321] Set condition code 1.

[0322] The address and length are formed and updated depending on the addressing mode.

[0323] When execution of an instruction ends in completion (not in inhibition, invalidation, or termination) and normal completion does not occur, the operation end condition is called partial completion.

[0324] Identify PER (program event recording) storage change events for the first operand location, the second operand location, the continuation recording recall buffer, and portions of the stored parameter block, as applicable. When a PER storage change event is identified, store fewer than 4K of additional bytes to the operand locations that intersect the designated PER storage area before reporting the event.

[0325] PER zero address detection events are recognized for parameter blocks, first operand locations, and second operand locations, as applicable. Zero address detection does not apply to input list addresses specified in parameter blocks and the start of the continue record recall buffer.

[0326] For a description of examples of other conditions that apply to the SORTL-SFLR function, refer to Other Conditions below.

[0327] When the instruction completes with condition code 1, the program may modify the first operand address, first operand length, second operand address, second operand length, any active input list addresses, and any active input list lengths as appropriate and then resume operation.

[0328] When the instruction completes with condition code 2, IILF equal to zero, and EILF equal to zero, the program may modify the first operand address, first operand length, second operand address, second operand length, any active input list addresses, and any active input list lengths appropriately and then resume operation.

[0329] When the instruction ends with condition code 2 and EILF equal to 1, the program can appropriately modify the input list address and length of the input list specified by EILN and then resume operation. In this case, when merge mode (MM) is 1, the program can also modify the first operand address and first operand length.

[0330] When the instruction ends with condition code 2 and IILF equal to 1, the program can appropriately modify the input list address and length of the input list specified by IILN and then resume operation. In this case, when merge mode (MM) is 1, the program can also modify the first operand address and first operand length.

[0331] If, after an instruction completes with condition code 3 and before re-executing the instruction to resume operation, the program modifies any active input list address or length, first operand address or length, or second operand address or length, the results are unpredictable.

[0332] Function Code 2: SORTL-SVLR (Sort Variable-Length Records)

[0333] The operation of the SORTL-SVLR function is the same as that of the SORTL-SFLR function except for the following:

[0334] Records include, for example, Figure 9 Shown are a fixed length key 900, an 8 byte payload length (PL) 902, and a variable length payload 904. Thus, the records are of variable length.

[0335] Bytes 14 to 15 of the parameter block for the SORTL-SVLR function are ignored.

[0336] The least significant, e.g., 2 bytes of the payload length field of each record contain an unsigned binary integer that specifies the length in bytes of the payload in the same record. A payload length of zero is valid. In one example, the payload length will be a multiple of, e.g., 8; otherwise, a general operand data exception is recognized. The most significant, e.g., 6 bytes of the payload length field are reserved bytes and should contain zeros; otherwise, future operation of the program may be incompatible. The sum of the key length 8 and the payload length is not greater than, e.g., 4096; otherwise, in one example, a general operand data exception is recognized. When a general operand data exception is recognized due to an inappropriate payload length, the input list address corresponding to the active input list that encountered the exception specifies the logical address of the leftmost byte of the erroneous record. The reserved bytes of the payload length field are not modified when a variable length record is stored to the first operand location.

[0337] An incomplete input list may not be recognized during an operation unit that attempts to reference only keys from records of an input list whose input list length is greater than the key size and less than the record size. In this case, an incomplete input list will be recognized when an attempt is made to store a record from the incomplete input list into the first operand position.

[0338] The parameter block for the SORTL-SVLR function is identical to the parameter block for the SORTL-SFLR function, except for bytes 14 to 15 as shown above.

[0339] For a description of other conditions that apply to the SORTL-SVLR function, please refer to the Other Conditions below.

[0340] In one embodiment, a specified exception is recognized when an attempt is made to perform a list sort and any of the following applies:

[0341] Bits 57-63 of general register 0 specify unassigned or not installed function codes.

[0342] The R1 field specifies an odd-numbered register or general register 0.

[0343] The R2 field specifies an odd-numbered register or general register 0. This applies when the merge mode (MM) is 0 or 1.

[0344] A parameter block is not specified on a doubleword boundary.

[0345] The SORTL-SFLR function or the SORTL-SVLR function is specified, and the first operand is not specified on a doubleword boundary.

[0346] When MM is zero, a SORTL-SFLR or SORTL-SVLR function is specified, and the second operand is not specified on a doubleword boundary.

[0347] In one embodiment, a specified exception is recognized when an attempt is made to perform a list sort and any of the following applies:

[0348] The SORTL-SFLR or SORT-SVLR functionality is specified and none or more of bits 0-7 of the parameter block version number contain the value 1, in which case the operation is suppressed.

[0349] The SORTL-SFLR or SORTL-SVLR capability is specified and the size or format of the parameter block specified by the parameter block version number is not supported by the model, in which case the operation is suppressed.

[0350] The SORTL-SFLR or SORTL-SVLR capability is specified, and the record key length specifies a key size of 0, a key size that is not a multiple of 8, or a key size greater than 4096, in which case the operation is suppressed.

[0351] The SORTL-SFLR capability is specified and the record payload length specifies a payload size that is not a multiple of 8, or the payload size plus the key size is greater than 4096, in which case the operation is suppressed.

[0352] The SORTL-SVLR capability is specified, and the record payload length specifies a payload size that is not a multiple of 8, or the payload size plus the key size is greater than 4088, in which case the operation is suppressed or aborted depending on the model.

[0353] The SORTL-SFLR or SORTL-SVLR functionality is specified and the value of the Active Input List Count Code (AILCC) plus one is greater than the number of input lists described by the parameter block, in which case the operation is suppressed.

[0354] The SORTL-SFLR or SORTL-SVLR function is specified, and the input list address corresponding to the active input list is not specified on a double-word boundary, in which case the operation is suppressed.

[0355] Other conditions

[0356] In one embodiment, the following conditions apply:

[0357] The execution of the instruction is interruptible. When an interruption occurs, the addresses in general registers R1 and R2, the lengths in general registers R1+1 and R2+1, and specific fields of the parameter block are updated so that the instruction can be resumed at the interruption point when it is re-executed.

[0358] Access exceptions are not recognized for locations greater than 4K bytes to the right of the location specified by the first operand address. Access exceptions are not recognized for locations greater than 4K bytes to the right of the location specified by the input list address.

[0359] If an access exception is recognized for the first operand, the second operand, or any input list, the result is that the exception is recognized or condition code 3 is set. If condition code 3 is set, assuming the exceptional condition still exists, the exception will be recognized when the instruction is executed again to continue processing the same operand.

[0360] Either access anomaly may be identified when the key of a record crosses a page boundary and the access anomaly condition exists for both pages.

[0361] Any of these conditions may be identified when access exception conditions exist for multiple keys being processed during a single unit of operation.

[0362] When a parameter block crosses a page boundary and an access exception condition exists for both pages, an access exception for the leftmost page is identified.

[0363] When the operation ends with partial completion, up to 4K bytes of data may have been stored in the first operand at or to the right of the location specified by the updated first operand address. Such stores result in setting the change bit (when applicable) and identifying a PER store change event (when applicable). Stores to these locations will be repeated when the instruction is executed again to continue processing the same operand.

[0364] As observed by this CPU, other CPUs, and the channel program, references to the parameter block, first operand, output list description buffer, and active input list can be multiple access references, accesses to these storage locations are not necessarily block-parallel, and the sequence of these accesses or references is undefined.

[0365] In one embodiment, when the specified function is SORTL-SFLR or SORTL-SVLR and any of the following apply, the results are unpredictable:

[0366] The parameter block overlaps with any active input list or first operand.

[0367] Any active input lists overlap with the first operand.

[0368] The merge mode is zero and the parameter block overlaps with the second operand or the continuation record recall buffer.

[0369] The merge mode is zero and any active input list overlaps with the second operand or the continuation record recall buffer.

[0370] The merge mode is zero, and the first operand overlaps with the second operand or the continuation record recall buffer.

[0371] The merge mode is zero and the second operand overlaps the continuation record recall buffer.

[0372] Another CPU or channel program stores the key of the record in the input list or continues recording in the recall buffer.

[0373] Example result condition code:

[0374] 0 Completed normally

[0375] 1 The length of the first operand is less than the record size, or the merge mode is zero and the length of the second operand is less than 16 (that is, the first or second operand is not long enough to continue)

[0376] 2 An incomplete input list is encountered (IILF=1), or EILCL is non-zero and the length of the input list becomes equal to zero during the operation (i.e., an incomplete or empty input list is encountered)

[0377] 3. A CPU-determined amount of data is processed (i.e., CPU-determined completion)

[0378] Program exception:

[0379] Access (extract, input list; extract and store, parameter block and continuation record recall buffer; store, operands 1 and 2)

[0380] Data with DXC (Data Exception Code) 0, general operand

[0381] Action (if the enhanced sort facility is not installed)

[0382] Specification

[0383] Transaction constraints

[0384] The following shows the execution priority of the list sort instruction. When there are multiple conditions with priority values beginning with 13, the condition identified is the condition that is encountered first as the operation proceeds. When the operation is being resumed (the continue flag is 1 when the execution of the instruction begins), the history of previous comparisons between keys can be used instead of the initial access to the active and non-empty input list. As a result, access exceptions to accesses to a particular input list may not be encountered at the same processing point compared to when the history of previous comparisons is not used. When variable length records are processed, conditions that are a function of record length can be partially evaluated before the payload length is determined and fully evaluated after the payload length is determined. As a result, the priority observed among such conditions can be different when the condition is determined to exist after only partial evaluation of the requirement rather than after full evaluation of all requirements.

[0385] Execution priority (SORTL)

[0386] 1.-6. Exceptions with the same priority as program interruption conditions used for normal cases.

[0387] 7.A The access to the second instruction halfword is abnormal.

[0388] 7.B operation is abnormal.

[0389] 7.C transaction constraints.

[0390] 8. Specification exception due to invalid function code or invalid register number.

[0391] 8.B The specified exception is due to the first operand not being specified on a doubleword boundary.

[0392] 8.C The specified exception is attributed to the first operand not specified on a doubleword boundary.

[0393] 8.D The specified exception is attributed to a second operand that is not specified on a doubleword boundary and the merging mode is zero.

[0394] 9. Access exception when accessing bytes 0-7 of the parameter block.

[0395] 10. General operand data exception caused by unsupported value of PBVN field in parameter block.

[0396] 11. Access exceptions to bytes other than bytes 0-7 in the parameter block.

[0397] 12. General operand data exception caused by invalid values of fields other than PBVN in the parameter block.

[0398] 13.A Access exception occurred while accessing the active input list.

[0399] 13.B Access to the continuation record and call buffer is abnormal when the merge mode is 0.

[0400] 13.C Access exception for accessing the first operand.

[0401] 13. Access exception when accessing the second operand when D merge mode is 0.

[0402] 13.E Condition code 2 attributed to incomplete input list.

[0403] 13.F Condition code 1 due to insufficient length of first operand

[0404] 13.G Attributed to condition code 1 for insufficient length of second operand when merge mode is 0.

[0405] 13.H General operand data exception due to invalid payload length for variable length record.

[0406] 13.I attributed condition code 2 to an empty input list.

[0407] 14. Condition code 3.

[0408] Programming Notes. In one embodiment:

[0409] 1. The intended use of empty input lists control (EILCL) is as follows:

[0410] EILCL(0:1)

[0411] (Binary) Description

[0412] 00 Stop after the records of the active input lists (e.g., all records of all active input lists) are sorted.

[0413] 10 Stop after input list0 (always active) becomes empty.

[0414] 11 Stop after any active input list becomes empty.

[0415] 2. When the active input list count code (AILCC) is zero, there is, for example, only one active input list, and the result stored at the first operand location is the same as the data obtained from input listO.

[0416] 3. Models that implement separate instruction and data caches can use the instruction cache to perform store operand fetch references to data in the active input list.

[0417] 4. When the program expects to call list sort multiple times with merge mode equal to zero, as part of processing a large data set, in one example, the program utilizes the available input lists and divides the records evenly across the input lists. This reduces the number of times the data is accessed when sorting the entire data set.

[0418] 5. After a list sort operation with merge mode equal to zero completes with condition code 0 set and multiple output list descriptions (OLD) in the second operand, a program intended to generate a single list of records in sorted order calls another list sort operation, specifying the input list to be the result OLD from the previous list sort call. In this case, in one example, the second call to list sort specifies merge mode equal to 1.

[0419] Similarly, in one embodiment, after calling list sort with merge mode equal to zero as many times as needed or desired to generate a complete set of sorted lists from a large number of randomly sorted records, in one example, list sort with merge mode equal to 1 is called as many times as needed or desired to generate a single sorted list.

[0420] 6. In one embodiment, to reduce the number of times each record is accessed when merging multiple sorted lists into a single list sorted in ascending order (for example), the program performs the following processing:

[0421] Determines the maximum number N of input lists that can be used for list sorting.

[0422] Compare the keys of the first records of the sorted lists that have not yet been merged into a single list. Select the N lists with the smallest first key values.

[0423] Perform a list sort with merge mode (MM) equal to 1, where empty input list control (EILCL) is equal to binary 10, input list0 specifies only the first record of the list with the highest first key value of the selected N lists, and the remaining input lists specify the other N-1 selected lists.

[0424] After the list is sorted, ending with condition code 2, IILF equal to zero, and EILF equal to zero, the process repeats.

[0425] 7. After list sorting ends with condition code 1 set, in one example, before calling list sorting again, the program performs the following actions to resume operation:

[0426] If the first operand length is less than the maximum record length of the record being processed, then the first operand length or the first operand address and length should be updated appropriately.

[0427] If the merge mode (MM) is zero and the second operand length is less than 16, the second operand length or the second operand address and length shall be updated as appropriate.

[0428] If the length of any active input list is equal to zero, then the corresponding input list address and length may be updated to specify another list of records to be included in the sort operation.

[0429] 8. After list sorting ends with condition code 2 set, in one example, before calling list sorting again, the program performs the following actions to resume operation:

[0430] If the incomplete input list flag (IILF) is 1, the input list length or input list address and the length of the input list identified by the incomplete input list number (IILN) should be updated appropriately.

[0431] If the empty input list flag (EILF) is 1, the input list length or the input list address and the length of the input list identified by the empty input list number (EILN) should be updated appropriately.

[0432] If IILF is zero, EILF is zero, and input list0 length is zero, then the input list0 length or the input list0 address and length should be updated as appropriate. Additionally, the input list address and length of the active input list may be updated, which may be appropriate if there is only one record originally specified by input list0 and the empty input list control (EILCL) is binary 10.

[0433] If the merge mode (MM) is 1 and the first operand length is less than the maximum record length of the record being processed, then the first operand length or the first operand address and length should be updated appropriately.

[0434] If MM is zero and IILF is 1 or EILF is 1, the first operand address and length and the second operand address and length shall not be updated.

[0435] If MM is zero, IILF is zero, EILF is zero, and the first operand length is less than the maximum record length of the record being processed, then the first operand length or the first operand address and length should be updated appropriately.

[0436] If MM is zero, IILF is zero, EILF is zero, and the second operand length is less than 16, the second operand length or the second operand address and length shall be updated appropriately.

[0437] As described herein, in one aspect, a single instruction (e.g., a machine instruction of a single architecture, list sorting) is provided to perform sorting and / or merging operations on a general-purpose processor. In one example, a program that implements sorting and / or merging operations for a database and is executed on a general-purpose processor can replace an important subset of basic instructions with a single instruction to implement the operation. The instruction is, for example, a hardware instruction defined in an instruction set architecture (ISA). As a result, the complexity of the program associated with the sorting and / or merging operations is reduced. In addition, the performance of the operation is improved, and therefore the performance of the processor is improved.

[0438] Advantageously, the list sorting instructions are executed on a general purpose processor (e.g., a central processing unit, referred to herein as a processor) rather than a specialized processor (such as a graphics processing unit (GPU), database engine (DBE), or other type of specialized processor).

[0439] Although different fields and registers are described, one or more aspects of the present invention may use other, additional, or fewer fields or registers, or fields and registers of other sizes, etc. Many variations are possible. For example, implicit registers may be used in place of explicitly specified instruction registers or fields, and / or explicitly specified registers or fields may be used in place of implicit registers or fields. Other variations are also possible.

[0440] In one example, the list sorting instruction operates on a large amount of data (such as megabytes or terabytes) of a database (e.g., a commercial database).Thus, the instruction is interruptible and processing can be resumed where it was interrupted.

[0441] When an instruction is interrupted, an operation (such as sorting and / or merging) is only partially completed. Execution of the instruction ends with the condition code set to a value that notifies the program (e.g., the program that issued the instruction) of the partial completion of the operation. The program can then re-execute the instruction to resume processing.

[0442] In one embodiment, the instruction takes a certain number (e.g., a significant number) of execution cycles to provide metadata to the processor before generating a result. Each time the instruction is executed or re-executed, the processor is booted with the metadata. Thus, according to one aspect of the present invention, previously generated metadata is stored and used so that the previously generated metadata does not need to be regenerated when the instruction is re-executed.

[0443] In one example, the metadata includes an internal state of the processor, including, for example, information about the input list, such as information about previous comparisons of records of the input list, in order to determine a next comparison to be made.

[0444] The processor extracts the metadata and stores it in a location provided by the program. Then, when instructions are re-executed after an interruption, the metadata is extracted from this location and loaded into the processor instead of using the task to regenerate the metadata. This saves the time that would otherwise be required to generate metadata for the operation.

[0445] In one specific example, a computing environment is a computing complex that includes multiple systems that can be linked together to operate as a single system image. The individual systems (e.g., processors) may not be of the same model type or version. A program can be released for execution on any processor within the computing complex. Furthermore, individual instructions can be executed on one processor, terminated to partial completion, and re-executed on a different processor to resume operation. In one embodiment, the instructions support saving and loading model-related data, which is not required for the recovery operation but can be used to minimize the overhead associated with the recovery operation. Model-related metadata is metadata that is stored / loaded based on the processor's model and accumulated during the execution of instructions (e.g., sequencing instructions). If, for example, the processor re-executing the instruction is capable of interpreting the model-related metadata, the model-related metadata is used during the re-execution of the instruction. A determination is made based on the re-execution of the instruction as to whether the processor is capable of interpreting the model-related metadata. If so, in one example, the model-related metadata is used during the re-execution of the instruction to improve operational processing and performance within the computing environment.

[0446] In one embodiment, an indication of the version of the processor that executed the instruction before the interruption (e.g., a model version number) is saved in a location specified by the instruction (e.g., in a parameter block). If the instruction is re-executed and the model version number of the processor that previously executed the instruction has a predefined relationship (e.g., is equal) to the model version number of the processor selected to re-execute the instruction, the model-related metadata is used when re-executing the instruction.

[0447] Reference Figures 10A-10B Further details of one embodiment of the resume execution operation are described. For example, Figure 10A depicting the processing associated with the partially completed instruction; Figure 10B Depicts processing associated with resuming execution of a partially completed instruction. In this example, the instruction is an instruction that performs sorting and / or merging, such as a sort list instruction; however, in other examples, the instruction may be other interruptible instructions. Figures 10A-10B The processing is performed, for example, by a processor (eg, processor 102 or 204).

[0448] First refer to Figure 10AInstructions executing on the processor and performing an operation such as a sort and / or merge are interrupted before completing the operation, step 1000. Based on the partial completion, a continuation indicator (e.g., the continue flag 368 of the parameter block 360), for example, is set to 1 to indicate the partial completion, step 1002. Additionally, model-related metadata of the processor, such as information about previous comparisons of records of the input list for a sort or merge operation, is stored in the parameter block, for example, in the continue status buffer 390, step 1004.

[0449] Afterwards, refer to Figure 10B , execute the instruction (e.g., a sort / merge instruction) on the selected processor (step 1050). If this is a re-execution of the instruction, the processor is, for example, the same processor that previously executed the instruction or a different processor of the compute complex. A determination is made as to whether the resume indicator is set to indicate that this is a re-execution of the instruction (inquiry 1052). If the resume indicator is set to indicate resumption of operation (step 1053), then, in one embodiment, a further determination is made as to whether the model type or version of the selected processor is the same as or compatible with the model type or version of the processor that executed the instruction when the instruction was interrupted. For example, a determination is made as to whether the model version number of the previous processor is the same as the model version number of the selected processor (inquiry 1054). If the model version numbers are the same (or there is another indication that the processors are compatible), model-dependent data stored, for example, in the resume state buffer 390 is retrieved (step 1056) and loaded into one or more selected locations within the processor (step 1058). The retrieved and loaded model-dependent data is then used when the instruction is re-executed (step 1060). For example, rather than repeating a previously performed comparison, model-related data is used to determine the next comparison to make, thereby reducing execution time and improving performance.

[0450] Returning to query 1054, if the model version numbers are not the same, then in one embodiment, re-execution of the instruction continues without using the model-dependent data, step 1062. Further, in one embodiment, if the continue indicator is not set (query 1052), then the instruction begins operation rather than resuming operation (step 1064). Thus, in one embodiment, operation proceeds without using data (e.g., model-dependent data) from the continue status buffer 390 of the parameter block 360 (step 1066).

[0451] One or more aspects of the present invention are integral to computer technology and facilitate internal computer processing, thereby improving performance. When re-executing instructions after an interruption, the extracted and saved metadata is used instead of regenerating the metadata, saving time and improving performance within the computing environment.

[0452] In one specific example, the re-implemented instruction is a list sort instruction, which is a single architectural machine instruction that replaces multiple software instructions to perform sorting and / or merging of a large number of database records in a database, thereby improving performance within a computing environment. These sorted and / or merged records can be used in many technical fields that manage and / or use large amounts of data, such as computer processing, medical processing, security, etc. By providing optimizations in the sorting / merging, these technical fields can be improved due to reduced execution time when retrieving and using information, as well as reduced storage requirements.

[0453] Reference Figures 11A-11B Further details of one embodiment of facilitating processing within a computing environment are described as it relates to one or more aspects of the present invention.

[0454] Reference Figure 11A In one embodiment, a determination is made that processing of an operation of an instruction executed on a processor has been interrupted before completion (1100). The instruction is re-executed on a selected processor to resume forward processing of the instruction (1102). The re-execution includes determining whether the selected processor is to use model-specific metadata when re-executing the instruction (1104). Based on the determination that the model-specific metadata is to be used, the model-specific metadata is used in re-executing the instruction (1106). Based on the determination that the model-specific metadata is not to be used, the re-execution of the instruction continues without using the model-specific metadata (1108).

[0455] In one embodiment, determining whether to use model-related metadata includes comparing a model version indicator of the interrupted processor with a model version indicator of a selected processor (1110). Based on the model version indicator of the selected processor having a predefined relationship with the model version indicator of the processor, the model-related metadata is to be used in re-executing the instruction (1112). As an example, the predefined relationship is equality (1114).

[0456] In one embodiment, the processor's model version indication is a model version number (1116) stored in a location specified by the instruction. The location is, for example, a parameter block (1118) in memory. Furthermore, the parameter block in memory also includes model-related metadata (1120).

[0457] As an example, see Figure 11B The re-execution instruction further includes checking a continue indicator to determine whether the operation is partially completed (1122). Based on the continue indicator being set to indicate that the operation is partially completed, determining whether to use model-related metadata (1124). The continue indicator is stored, for example, in a parameter block in memory (1126).

[0458] In one embodiment, using the model-related metadata includes extracting the model-related metadata from a location specified by the instruction (1128); and loading the model-related metadata extracted from the location into one or more selected locations of the selected processor (1130). The model-related metadata is provided to the selected processor without repeating one or more tasks of generating the model-related metadata (1132). As an example, the location specified by the instruction contains a continuation state buffer for a parameter block in a memory specified by the instruction (1134).

[0459] Other variations and embodiments are possible.

[0460] Aspects of the present invention may be used by many types of computing environments. Figure 12A Another embodiment of a computing environment for incorporating and using one or more aspects of the present invention is described. In this example, the computing environment 1100 includes, for example, a local central processing unit (CPU) 12, memory 14, and one or more input / output devices and / or interfaces 16 coupled to each other via, for example, one or more buses 18 and / or other connections. As an example, the computing environment 100 may include a processor provided by International Business Machines Corporation of Armonk, New York. processor; an HP Superdome with an Intel Itanium II processor, provided by Hewlett-Packard Company, Palo Alto, California, USA; and / or other machines based on architectures provided by International Business Machines Corporation, Hewlett-Packard, Intel Corporation, Oracle, or others. IBM, z / Architecture, IBM Z, z / OS, PR / SM, and PowerPC are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction. Intel and Itanium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

[0461] The local central processing unit 12 includes one or more local registers 20, such as one or more general purpose registers and / or one or more special purpose registers used during processing within the environment. These registers include information representing the state of the environment at any particular point in time.

[0462] In addition, the local central processing unit 12 executes instructions and codes stored in the memory 14. In a specific example, the central processing unit executes emulator code 22 stored in the memory 14. This code enables a computing environment configured in one architecture to emulate another architecture. For example, the emulator code 22 allows a machine based on an architecture other than the z / Architecture hardware architecture (such as a PowerPC processor, an HP Superdome server, or others) to emulate the z / Architecture hardware architecture and execute software and instructions developed based on the z / Architecture hardware architecture.

[0463] Reference Figure 12B Further details regarding the emulator code 22 are described. The guest instructions 30 stored in the memory 14 include software instructions (e.g., related to machine instructions) developed for execution in an architecture different from the architecture of the local CPU 12. For example, the guest instructions 30 may have been designed to execute on a processor based on the z / Architecture hardware architecture, but are instead emulated on the local CPU 12, which may be, for example, an Intel Itanium II processor. In one example, the emulator code 22 includes an instruction fetch routine 32 to obtain one or more guest instructions 30 from the memory 14 and optionally provide local buffering for the obtained instructions. It also includes an instruction conversion routine 34 to determine the type of guest instruction that has been obtained and convert the guest instruction into one or more corresponding native instructions 36. This conversion includes, for example, identifying the function to be performed by the guest instruction and selecting a native instruction to perform the function.

[0464] Furthermore, the emulator code 22 includes an emulation control routine 40 to cause native instructions to be executed. The emulation control routine 40 may cause the local CPU 12 to execute a routine that emulates one or more previously acquired guest instructions, and at the end of this execution, return control to the instruction fetch routine to emulate the acquisition of the next guest instruction or set of guest instructions. The execution of the native instructions 36 may include loading data from memory 14 into registers, storing data from registers back to memory, or performing some type of arithmetic or logical operation, as determined by the conversion routine.

[0465] Each routine is implemented, for example, in software that is stored in memory and executed by the local central processing unit 12. In other examples, one or more of the routines or operations are implemented in firmware, hardware, software, or some combination thereof. The registers of the emulated processor may be emulated using the registers 20 of the local CPU or by using locations in memory 14. In an embodiment, the guest instructions 30, the native instructions 36, and the emulator code 22 may reside in the same memory or may be distributed among different memory devices.

[0466] The computing environments described above are merely examples of computing environments that may be used. Other environments may be used, including but not limited to other non-partitioned environments, other partitioned environments, and / or other simulation environments; embodiments are not limited to any one environment.

[0467] Each computing environment can be configured to include one or more aspects of the present invention. For example, each computing environment can be configured to provide sorting and / or merging according to one or more aspects of the present invention.

[0468] One or more aspects may relate to cloud computing.

[0469] It should be understood that although the present disclosure includes detailed descriptions about cloud computing, the implementation of the teachings cited herein is not limited to cloud computing environments. Instead, embodiments of the present invention can be implemented in conjunction with any other type of computing environment now known or later developed.

[0470] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be quickly provisioned and released with minimal management effort or interaction with the service provider. The cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0471] Features are as follows:

[0472] On-demand self-service: Cloud consumers can automatically and unilaterally provision computing capabilities, such as server time and network storage, on demand without requiring manual interaction with the service provider.

[0473] Broad Network Access: Functionality is provided over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin-client or thick-client platforms (e.g., mobile phones, laptops, and PDAs).

[0474] Resource pooling: Providers' computing resources are pooled to serve multiple consumers using a multi-tenant model, where different physical and virtual resources are dynamically allocated and reallocated as needed. Location independence is important because consumers typically have no control or knowledge of the exact location of the provided resources, but may be able to specify a location at a higher level of abstraction (e.g., country, state, or data center).

[0475] Rapid elasticity: In some cases, capabilities can be provisioned quickly and elastically to scale up and down quickly and released quickly to scale back in. To the consumer, the capabilities available for provisioning often appear to be unlimited and can be purchased at any time and in any quantity.

[0476] Measured services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the services being used.

[0477] The service model is as follows:

[0478] Software as a Service (SaaS): The ability provided to consumers is to use the provider's applications running on a cloud infrastructure. These applications are accessible from various client devices through a thin client interface such as a web browser (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even individual application functionality, with the possible exception of limited user-specific application configuration settings.

[0479] Platform as a Service (PaaS): The capability provided to consumers is to deploy consumer-created or acquired applications on cloud infrastructure, using programming languages and tools supported by the provider. Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but do have control over the deployed applications and possibly the configuration of the application hosting environment.

[0480] Infrastructure as a Service (IaaS): The capabilities provided to consumers are processing, storage, networking, and other basic computing resources on which they can deploy and run arbitrary software, including operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but rather have control over the operating system, storage, deployed applications, and possibly limited control over selected networking components (e.g., host firewalls).

[0481] The deployment model is as follows:

[0482] Private cloud: Cloud infrastructure is operated solely for an organization. It can be managed by the organization or a third party and can exist on-premises or off-premises.

[0483] Community cloud: The cloud infrastructure is shared by multiple organizations and supports a specific community with common concerns (e.g., mission, security requirements, policy, and compliance considerations). It can be managed by the organization or a third party and can exist on-premises or off-premises.

[0484] Public cloud: Cloud infrastructure is available to the general public or large industry groups and is owned by the organization that sells cloud services.

[0485] Hybrid cloud: A cloud infrastructure composed of two or more clouds (private, community, or public) that remain unique entities but are bound together by standardized or proprietary technologies that enable data and application portability (e.g., cloud bursting for load balancing between clouds).

[0486] The cloud computing environment is service-oriented and focuses on statelessness, low coupling, modularity, and semantic interoperability. The core of cloud computing is the infrastructure consisting of a network of interconnected nodes.

[0487] Now refer to Figure 13 , depicts an illustrative cloud computing environment 50. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 52, with which local computing devices used by cloud consumers (such as personal digital assistants (PDAs) or cell phones 54A, desktop computers 54B, laptop computers 54C, and / or automobile computer systems 54N) can communicate. The nodes 52 can communicate with each other. They can be physically or virtually grouped (not shown) in one or more networks, such as in the private clouds, community clouds, public clouds, or hybrid clouds described above, or a combination thereof. This allows the cloud computing environment 50 to provide infrastructure, platforms, and / or software as a service for which cloud consumers do not need to maintain resources on their local computing devices. It should be understood that Figure 13 The types of computing devices 54A-N shown in are intended to be illustrative only, and computing nodes 52 and cloud computing environment 50 may communicate with any type of computerized device over any type of network and / or network-addressable connection (eg, using a web browser).

[0488] Now refer to Figure 14 , showing the cloud computing environment 50 ( Figure 13 ) provides a set of functional abstraction layers. It should be understood in advance that Figure 14 The components, layers, and functions shown in the figure are intended to be illustrative only, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0489] The hardware and software layer 60 includes hardware and software components. Examples of hardware components include: host 61; server 62 based on RISC (Reduced Instruction Set Computer) architecture; server 63; blade server 64; storage 65; and network and networking components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0490] Virtualization layer 70 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual servers 71 ; virtual storage 72 ; virtual networks 73 , including virtual private networks; virtual applications and operating systems 74 ; and virtual clients 75 .

[0491] In one example, the management layer 80 may provide the functionality described below. Resource provisioning 81 provides dynamic acquisition of computing resources and other resources for performing tasks within the cloud computing environment. Metering and pricing 82 provides cost tracking when resources are utilized within the cloud computing environment and bills or invoices for the consumption of these resources. In one example, these resources may include application software licenses. Security provides authentication for cloud consumers and tasks, as well as protection of data and other resources. User portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides cloud computing resource allocation and management so that required service levels are met. Service level agreement (SLA) planning and fulfillment 85 provides pre-arrangement and procurement of cloud computing resources for future requirements anticipated according to the SLA.

[0492] The workload layer 90 provides examples of functionality that can take advantage of a cloud computing environment. Examples of workloads and functionality that can be provided from this layer include: mapping and navigation 91; software development and lifecycle management 92; virtual classroom education delivery 93; data analytics processing 94; transaction processing 95; and sorting and / or merging processing 96.

[0493] The various aspects of the present invention may be systems, methods, and / or computer program products at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform aspects of the present invention.

[0494] A computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device (such as a punched card or a raised structure in a groove with instructions recorded thereon), and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (e.g., a light pulse by a fiber optic cable), or an electrical signal transmitted by a wire.

[0495] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards these computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0496] The computer-readable program instructions for performing the operation of the present technical solution can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, the configuration data of integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, and procedural programming languages, such as "C" programming language or similar programming languages. The computer-readable program instructions can be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or executed entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network (including local area network (LAN) or wide area network (WAN)), or can be connected to an external computer (for example, by using the Internet of an Internet service provider). In certain embodiments, electronic circuits (including for example programmable logic circuits, field programmable gate arrays (FPGAs) or programmable logic arrays (PLAs)) can execute computer-readable program instructions to personalize the electronic circuits by using the state information of computer-readable program instructions, so as to perform the various aspects of the present technical solution.

[0497] Various aspects of the present technical solution are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the technical solution. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0498] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine that, when executed by the processor of the computer or other programmable data processing apparatus, creates a means for implementing the functions / actions specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, a programmable data processing apparatus, and / or other device to function in a specific manner, such that the computer-readable storage medium having the instructions stored therein comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowcharts and / or block diagrams.

[0499] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other apparatus that causes a series of operating steps to be performed on a computer, other programmable apparatus or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus or other device implement the functions and actions specified in one or more blocks in the flowchart and / or block diagram.

[0500] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions and operations of the systems, methods and computer program products according to the different embodiments of the present technical solution. To this end, each box in the flowchart or block diagram may represent a part of a module, segment or instruction, which includes one or more executable instructions for implementing the specified logical function. In some alternative embodiments, the functions marked in the box may not occur in the order marked in the figure. For example, depending on the functions involved, the two boxes shown in succession can actually be executed substantially simultaneously, or these boxes can sometimes be executed in the opposite order. It will also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart can be implemented by a system based on dedicated hardware, which performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0501] In addition to the above, one or more aspects may be provided, committed, deployed, managed, serviced, etc., by a service provider that provides management of a customer environment. For example, a service provider may create, maintain, and support computer code and / or computer infrastructure that performs one or more aspects for one or more customers. In return, the service provider may receive payment from the customer, for example, under a subscription and / or fee agreement. Additionally or alternatively, the service provider may receive payment from the sale of advertising content to one or more third parties.

[0502] In one aspect, an application program for executing one or more embodiments may be deployed. As an example, deployment of the application program includes providing a computer infrastructure operable to execute one or more embodiments.

[0503] As another aspect, a computing infrastructure may be deployed including integrating computer readable code into a computing system, wherein the code in combination with the computing system is capable of performing one or more embodiments.

[0504] As another aspect, a process for integrating a computing infrastructure may be provided, the process comprising integrating computer-readable code into a computer system. The computer system includes a computer-readable medium, wherein the computer medium includes one or more embodiments. The code, in combination with the computer system, is capable of executing one or more embodiments.

[0505] Although various embodiments are described above, these are merely examples. For example, computing environments of other architectures may be used to include and use one or more embodiments. Further, different instructions or operations may be used. In addition, different registers may be used and / or other types of indications (other than register numbers) may be specified. Many variations are possible.

[0506] Further, other types of computing environments can benefit and can be used. As an example, a data processing system suitable for storing and / or executing program code is available, which includes at least two processors that are directly or indirectly coupled to a memory element through a system bus. The memory element includes, for example, a local memory, a mass storage device, and a temporary storage of at least some program codes that is used during the actual execution of the program code to reduce the number of times that code must be retrieved from the mass storage device during execution.

[0507] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, DASDs, tapes, CDs, DVDs, thumb drives, and other storage media) can be coupled to the system directly or through intervening I / O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the available types of network adapters.

[0508] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0509] All means or steps in the following claims plus the corresponding structures, materials, acts, and equivalents of functional elements (if any) are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of one or more embodiments has been given for purposes of illustration and description, but is not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments are chosen and described in order to best explain the various aspects and practical applications, and to enable those of ordinary skill in the art to understand different embodiments with different modifications suitable for the specific use contemplated.

Claims

1. A computer program product for facilitating processing within a computing environment, the computer program product comprising: A computer-readable storage medium readable by a processing circuit and storing instructions for performing a method comprising: determining that processing of an operation of an instruction executing on a processor has been interrupted before completion; and re-executing the instruction on the selected processor to resume forward processing of the instruction, the re-executing comprising: determining whether model-dependent metadata is to be used by the selected processor when re-executing the instruction, wherein the determining comprises determining whether the selected processor is capable of interpreting the model-dependent metadata, the model-dependent metadata being metadata stored / loaded according to a model of the processor and accumulated during execution of the instruction; Based on determining that the selected processor is capable of interpreting the model-related metadata or determining that the model-related metadata will be used, using the model-related metadata when re-executing the instructions; and Based on determining that the model-related metadata will not be used, re-executing the instructions continues without using the model-related metadata.

2. The computer program product of claim 1, wherein: The determining whether to use the model-related metadata comprises comparing a model version indication of the interrupted processor with a model version indication of a selected processor, wherein the model-related metadata is to be used when re-executing the instruction based on the model version indication of the processor having a predefined relationship with the model version indication of the selected processor.

3. The computer program product of claim 2, wherein: The predefined relationship is equality.

4. The computer program product of claim 2, wherein: The processor model version indication is a model version number stored in the location specified by the instruction.

5. The computer program product of claim 4, wherein: The location comprises a parameter block in memory.

6. The computer program product of claim 5, wherein: The parameter block in memory further includes the model related metadata.

7. The computer program product of claim 6, wherein: The re-execution further includes checking a continuation indicator to determine whether the operation is partially completed, wherein the determining whether to use the model-related metadata is performed based on the continuation indicator being set to indicate that the operation is partially completed, the continuation indicator being stored in the parameter block in the memory.

8. The computer program product of claim 1, wherein: The re-executing further includes checking a continuation indicator to determine whether the operation is partially completed, wherein the determining whether to use the model-related metadata is performed based on the continuation indicator being set to indicate that the operation is partially completed.

9. The computer program product of claim 1, wherein: The use of the model-related metadata includes: Extracting the model-related metadata from the location specified by the instruction; and The model-related metadata extracted from the location is loaded into one or more selected locations of the selected processor, wherein the model-related metadata is provided to the selected processor without repeating one or more tasks to generate the model-related metadata.

10. The computer program product of claim 1, wherein: The location specified by the instruction includes a continuation status buffer for the parameter block in the memory specified by the instruction.

11. A computer system for facilitating processing within a computing environment, the computer system comprising: Memory; and one or more processors in communication with the memory, wherein the computer system is configured to perform a method comprising: determining that processing of an operation of an instruction executing on a processor has been interrupted before completion; and re-executing the instruction on the selected processor to resume forward processing of the instruction, the re-executing comprising: determining whether model-dependent metadata is to be used by the selected processor when re-executing the instruction, wherein the determining comprises determining whether the selected processor is capable of interpreting the model-dependent metadata, the model-dependent metadata being metadata stored / loaded according to a model of the processor and accumulated during execution of the instruction; Based on determining that the selected processor is capable of interpreting the model-related metadata or determining that the model-related metadata will be used, using the model-related metadata when re-executing the instructions; and Based on determining that the model-related metadata will not be used, re-executing the instructions continues without using the model-related metadata.

12. The computer system of claim 11, wherein: The determining whether to use the model-related metadata comprises comparing a model version indication of the interrupted processor with a model version indication of a selected processor, wherein the model-related metadata is to be used when re-executing the instruction based on the model version indication of the processor having a predefined relationship with the model version indication of the selected processor.

13. The computer system of claim 12, wherein: The model version indication of the processor is a model version number stored in a location specified by the instruction, the location including a parameter block in a memory, the parameter block in the memory further including the model-related metadata.

14. The computer system of claim 11, wherein: The re-executing further includes checking a continuation indicator to determine whether the operation is partially completed, wherein the determining whether to use the model-related metadata is performed based on the continuation indicator being set to indicate that the operation is partially completed.

15. The computer system of claim 11, wherein: The use of the model-related metadata includes: Extracting the model-related metadata from the location specified by the instruction; and The model-related metadata extracted from the location is loaded into one or more selected locations of the selected processor, wherein the model-related metadata is provided to the selected processor without repeating one or more tasks to generate the model-related metadata.

16. A computer-implemented method of facilitating processing within a computing environment, the computer-implemented method comprising: determining that processing of an operation of an instruction executing on a processor has been interrupted before completion; and re-executing the instruction on the selected processor to resume forward processing of the instruction, the re-executing comprising: determining whether model-dependent metadata is to be used by the selected processor when re-executing the instruction, wherein the determining comprises determining whether the selected processor is capable of interpreting the model-dependent metadata, the model-dependent metadata being metadata stored / loaded according to a model of the processor and accumulated during execution of the instruction; Based on determining that the selected processor is capable of interpreting the model-related metadata or determining that the model-related metadata will be used, using the model-related metadata when re-executing the instructions; and Based on determining that the model-related metadata will not be used, re-executing the instructions continues without using the model-related metadata.

17. The computer-implemented method of claim 16, wherein: The determining whether to use the model-related metadata comprises comparing a model version indication of the interrupted processor with a model version indication of a selected processor, wherein the model-related metadata is to be used when re-executing the instruction based on the model version indication of the processor having a predefined relationship with the model version indication of the selected processor.

18. The computer-implemented method of claim 17, wherein: The model version indication of the processor is a model version number stored in a location specified by the instruction, the location including a parameter block in a memory, the parameter block in the memory further including the model-related metadata.

19. The computer-implemented method of claim 16, wherein: The re-executing further includes checking a continuation indicator to determine whether the operation is partially completed, wherein the determining whether to use the model-related metadata is performed based on the continuation indicator being set to indicate that the operation is partially completed.

20. The computer-implemented method of claim 16, wherein: The use of the model-related metadata includes: Extracting the model-related metadata from the location specified by the instruction; and The model-related metadata extracted from the location is loaded into one or more selected locations of the selected processor, wherein the model-related metadata is provided to the selected processor without repeating one or more tasks to generate the model-related metadata.

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