Display device, data driving circuit and data driving method

Abstract

A display device includes: a plurality of sub-pixels are arranged at positions where a plurality of data lines and a plurality of gate lines intersect each other in a display panel; a gate driving circuit that drives the plurality of sub-pixels via the plurality of gate lines; a data driving circuit that provides data output signals to the plurality of sub-pixels via the plurality of data lines, the data output signals including a data voltage and an offset data voltage generated by adding an offset to the data voltage; and a timing controller that controls the gate driving circuit and the data driving circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0167406, filed on December 16, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a display device, a data driving circuit, and a data driving method, and more particularly, to a display device, a data driving circuit, and a data driving method that can reduce a setup time and power consumption of a data voltage by applying an offset value to the data voltage.

[0004] Related technical discussions

[0005] Examples of flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode display (OLED).

[0006] In such a flat panel display device, a plurality of gate lines and a plurality of data lines are arranged perpendicular to each other, and each region defined by the intersection of one gate line and one data line is defined as a sub-pixel. Such sub-pixels are formed in a matrix in a display panel.

[0007] In order to drive the sub-pixels in the display panel, scan signals are sequentially supplied to a plurality of gate lines, and image data voltages to be displayed are supplied to the sub-pixels turned on in response to the scan signals via the data lines.

[0008] The data driving circuit that provides such data voltage to the display panel is controlled by a timing controller that provides a digital data signal, a clock signal for sampling the digital data signal, a control signal for controlling the operation of the data driving circuit, etc. via an interface such as a low voltage differential signaling interface (LVDS).

[0009] The data driving circuit converts digital data signals serially input from the timing controller into parallel signals, converts the digital data signals into analog data voltages using a gamma compensation voltage, and supplies the resulting analog data voltages via data lines.

[0010] The end portion of the data driving circuit includes a driving amplifier that supplies a data voltage to the data line, and power consumption in the driving amplifier is caused due to a variation in the data voltage supplied to the sub-pixel.

[0011] Recently, in response to requests from users, a display device with a large screen that can be driven at high speed is required. According to the reduction of the time interval of the horizontal period due to high-speed driving, the bias setting value is adjusted to reduce the setup time of the data voltage and increase the slew rate. Summary of the invention

[0012] However, when the bias setting value is adjusted to reduce the setup time of the data voltage supplied to the display panel and increase the slew rate, there is a problem in that a constant current flowing in a driving amplifier of the data driving circuit increases and thus power consumption in the display device increases overall.

[0013] Therefore, the present disclosure provides a display device that can reduce the setup time of a data voltage and power consumption without increasing a constant current of a data driving circuit.

[0014] The present disclosure also provides a display device, a data driving circuit, and a data driving method that can reduce a setup time of a data voltage and power consumption by applying an offset value to the data voltage.

[0015] Objectives achieved by the embodiments of the present disclosure are not limited to the above-mentioned problems, and other objectives not mentioned above will be clearly understood by those skilled in the art from the following description.

[0016] According to an embodiment of the present disclosure, a display device is provided including: a display panel in which a plurality of sub-pixels are arranged at positions where a plurality of data lines and a plurality of gate lines intersect each other; a gate driving circuit, which drives the plurality of sub-pixels via the plurality of gate lines; a data driving circuit, which provides a data output signal to the plurality of sub-pixels via the plurality of data lines, the data output signal including a data voltage and an offset data voltage generated by adding an offset to the data voltage; and a timing controller, which controls the gate driving circuit and the data driving circuit.

[0017] In a display device according to an embodiment of the present disclosure, a data driving circuit may include: a data controller, which generates offset image data by adding an offset to digital image data received from a timing controller; a first latch circuit, which stores the digital image data received from the data controller; a first offset latch circuit, which stores the offset image data received from the data controller; a second latch circuit, which stores the digital image data and the offset image data transmitted from the first latch circuit and the first offset latch circuit, respectively; a digital-to-analog converter, which converts the digital image data and the offset image data transmitted from the second latch circuit into a data voltage and an offset data voltage; and an output buffer, which provides the data voltage and the offset data voltage to the display panel under the control of the data controller.

[0018] In the display device according to the embodiment of the present disclosure, the data controller may include a lookup table in which the digital image data and the offset image data are stored.

[0019] In the display device according to an embodiment of the present disclosure, the output buffer may include a driving amplifier which provides a data voltage or offsets the data voltage to the display panel according to a bias voltage.

[0020] In the display device according to the embodiment of the present disclosure, the offset may be varied according to the grayscale of the digital image data.

[0021] In the display device according to the embodiment of the present disclosure, the offset may be determined by applying an interpolation method to an intermediate level of grayscale.

[0022] In the display device according to an embodiment of the present disclosure, the data controller may control an offset time at which the offset data voltage is provided to the display panel in the data enable section.

[0023] In the display device according to an embodiment of the present disclosure, the offset time may have an interval equal to or greater than a time from a start time point of the data enable portion to a time point at which the offset data voltage reaches a stable level of the data voltage.

[0024] In a display device according to an embodiment of the present disclosure, the second latch circuit may include: a second normal latch circuit, which stores digital image data transmitted from the first latch circuit; and a second offset latch circuit, which stores offset image data transmitted from the first offset latch circuit.

[0025] According to another embodiment of the present disclosure, a data driving circuit is provided, including: a data controller, which generates offset image data by adding an offset to digital image data received from a timing controller; a first latch circuit, which stores the digital image data received from the data controller; a first offset latch circuit, which stores the offset image data received from the data controller; a second latch circuit, which stores the digital image data and the offset image data transmitted from the first latch circuit and the first offset latch circuit, respectively; a digital-to-analog converter, which converts the digital image data and the offset image data transmitted from the second latch circuit into a data voltage and an offset data voltage, and an output buffer, which provides the data voltage and the offset data voltage to a display panel under the control of the data controller.

[0026] According to another embodiment of the present disclosure, a data driving method is provided, including: generating offset image data by adding an offset to digital image data received from a timing controller; storing the digital image data and the offset image data; converting the digital image data and the offset image data into analog type data voltages and offset data; and providing the data voltages and the offset data voltages to a display panel at different times.

[0027] According to an embodiment of the present disclosure, a display device can be provided which can reduce the setup time of a data voltage and power consumption without increasing a constant current of a data driving circuit.

[0028] According to an embodiment of the present disclosure, a display device, a data driving circuit, and a data driving method may be provided, which may reduce a setup time of a data voltage and power consumption by applying an offset value to the data voltage.

[0029] Advantages of the embodiments of the present disclosure are not limited to the above advantages. The embodiments of the present disclosure can achieve advantages that are not mentioned above and will be clearly understood by those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a diagram schematically showing a configuration of a flexible display device according to an embodiment of the present disclosure;

[0031] Figure 2 is a diagram showing a circuit structure of each sub-pixel arranged in a display device according to an embodiment of the present disclosure;

[0032] Figure 3 is a diagram showing a waveform of a data voltage applied to a display panel via a data driving circuit in a display device;

[0033] Figure 4 is a block diagram showing a data driving circuit in a display device according to an embodiment of the present disclosure;

[0034] Figure 5 is a diagram illustrating an example of a lookup table in which digital image data and offset image data are stored in a display device according to an embodiment of the present disclosure.

[0035] Figure 6 is a diagram showing a data driving circuit and a portion of a sub-pixel in a display device according to an embodiment of the present disclosure;

[0036] Figure 7 is a diagram showing an example of an experimental graph for an offset setting value and an offset time in a display device according to an embodiment of the present disclosure;

[0037] Figure 8 is a diagram showing the timing of signals applied to a display panel via a data driving circuit in a display device according to an embodiment of the present disclosure;

[0038] Fig. 9 is a diagram illustrating an advantage in which a setup time is reduced by offsetting a data voltage in a display device according to an embodiment of the present disclosure;

[0039] Fig.10 is a diagram showing a waveform of a data output signal using an offset data voltage applied to a display panel in a display device according to an embodiment of the present disclosure;

[0040] Fig.11 is a block diagram illustrating a data driving circuit in a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] The advantages and features of the present disclosure and the methods for achieving the advantages or features will become apparent from the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments, but can be modified in various forms. The embodiments are provided only to complete the disclosure of the present invention and to fully inform the scope of the present invention to those skilled in the art. The scope of the present invention is limited only by the appended claims.

[0042] The shapes, sizes, ratios, angles, number of pieces, etc. shown in the drawings provided for the purpose of illustrating embodiments of the present invention are exemplary, and therefore the present invention is not limited to the details shown. In the following description, similar elements are represented by similar reference numerals. When it is determined that the detailed description of the relevant known functions or configurations involved in the present invention obscures the subject matter of the present invention, its detailed description will not be made. When "including", "having", "constituting", etc. are mentioned in the specification, another element may be added unless "only" is used. Unless otherwise specified, the singular expression of an element includes two or more elements.

[0043] Even if not explicitly stated, the constituent elements in the embodiments of the present invention include a margin of error.

[0044] For example, when “on,” “above,” “below,” “beside,” etc. are used to describe the positional relationship between two components, one or more other components may be disposed between the two components unless “only” or “directly” is used.

[0045] When describing a time relationship, for example, when "after", "subsequently", "next", and "before" are used to describe a time sequence, discontinuous cases may be included unless "only" or "directly" is used.

[0046] When describing a signal transmission relationship, for example, when “a signal is transmitted from node A to node B”, unless “only” or “directly” is used, a case where the signal is transmitted from node A to node B via another node may be included.

[0047] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0048] The features (elements) of the embodiments of the present invention may be coupled or combined with each other, or may be partially or entirely separated from each other, and may be technically interconnected and driven in various forms. The embodiments may be put into practice independently or in combination.

[0049] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0050] Figure 1 is a diagram schematically showing a configuration of a display device according to an embodiment of the present disclosure.

[0051] Reference Figure 1 , a display device 100 according to an embodiment of the present disclosure includes a display panel 110 , a gate driving circuit 120 , a data driving circuit 130 , and a timing controller (T-CON) 140 .

[0052] The display panel 110 displays an image based on a scan signal SCAN transmitted from the gate driving circuit 120 via a plurality of gate lines GL and a data voltage Vdata transmitted from the data driving circuit 130 via a plurality of data lines DL.

[0053] The display panel 110 includes a liquid crystal layer formed between two substrates and may operate in any known mode such as a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in-plane switching (IPS) mode, a fringe field switching (FFS) mode.

[0054] A plurality of sub-pixels SP constituting the display panel 110 are defined by a plurality of data lines DL and a plurality of gate lines GL. Each sub-pixel SP includes a thin film transistor TFT formed in a region where one of the data lines DL and one of the gate lines GL intersect each other, a light emitting element such as an organic light emitting diode (OLED) charged with a data voltage Vdata, and a storage capacitor Cst electrically connected to the light emitting element and storing a voltage.

[0055] For example, the display device 100 having a resolution of 2160×3840 includes 2160 gate lines GL and 3840 data lines DL, and the sub-pixels SP are arranged at positions where the gate lines GL and the data lines DL intersect each other.

[0056] The timing controller 140 controls the gate driving circuit 120 and the data driving circuit 130. The timing controller 140 is supplied with timing signals from a host system (not shown in the drawing), such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a main clock MCLK, and digital image data DATA.

[0057] The timing controller 140 controls the gate driving circuit 120 based on the scanning timing control signals such as the gate start pulse GSP, the gate clock signal GCLK and the gate output enable signal GOE. The timing controller 140 controls the data driving circuit 130 based on the data timing control signals such as the source sampling clock signal SCLK, the polarity control signal POL and the source output enable signal SOE.

[0058] The gate driving circuit 120 sequentially drives the plurality of gate lines GL by sequentially providing a scan signal SCAN through the plurality of gate lines GL to the display panel 110. Here, the gate driving circuit 120 is also referred to as a scan driving circuit or a gate driver IC (GDIC).

[0059] The gate driving circuit 120 includes one or more gate driver ICs (GDICs), and the gate driving circuit 120 may be provided on only one side or on both sides of the display panel 110 according to the driving mode. Alternatively, the gate driving circuit 120 may be included in a frame region of the display panel 110 and implemented in the form of a gate-in-panel (GIP).

[0060] The gate driving circuit 120 sequentially supplies a scan signal SCAN of a turn-on voltage or a turn-off voltage to the plurality of gate lines GL under the control of the timing controller 140. For this purpose, the gate driving circuit 120 includes a shift register or a level shifter.

[0061] The data driving circuit 130 is provided with digital image data DATA from the timing controller 140, and drives a plurality of data lines DL by converting the digital image data DATA into an analog type data voltage Vdata and providing the data voltage Vdata to the plurality of data lines DL. Here, the data driving circuit 130 is also referred to as a source driving circuit or a source driver IC (SDIC).

[0062] The data drive circuit 130 includes one or more source driver ICs (SDICs). The source driver IC may be connected to a bonding pad of the display panel 110 in a tape automated bonding (TAB) manner or a chip on glass (COG) manner, or may be directly disposed on the display panel 110. In some cases, each source driver IC (SDIC) may be integrated and arranged on the display panel 110. Each source driver IC (SDIC) is implemented in a chip on film (COF) manner. In this case, each source driver IC is mounted on a circuit film and electrically connected to a data line DL of the display panel 110 via the circuit film.

[0063] When a specific gate line GL is turned on by the gate driving circuit 120 , the data driving circuit 130 converts the digital image data DATA received from the timing controller 140 into an analog type data voltage Vdata and supplies the data voltage Vdata to the plurality of data lines DL.

[0064] The data driving circuit 130 may be disposed in only one of the upper and lower portions of the display panel 110 , or may be disposed in both the upper and lower portions of the display panel 110 , according to a driving mode or a design mode.

[0065] The data driving circuit 130 includes a shift register, a latch circuit, a digital-to-analog converter DAC, and an output buffer. Here, the digital-to-analog converter DAC is an element that converts digital image data DATA received from the timing controller 140 into an analog type data voltage Vdata to provide the data voltage Vdata to the data line DL.

[0066] On the other hand, the display device 100 further includes a memory. The memory temporarily stores the digital image data DATA output from the timing controller 140, and outputs the digital image data DATA to the data driving circuit 130 at a predetermined time. The memory may be provided inside or outside the data driving circuit 130. When the memory is provided outside the data driving circuit 130, the memory may be provided between the timing controller 140 and the data driving circuit 130. The memory further includes a buffer memory that stores the digital image data DATA received from the outside and provides the stored digital image data DATA to the timing controller 140.

[0067] In addition, the display device 100 includes an interface for inputting a signal to another external electronic device or an external electronic component, outputting a signal from another external electronic device or an external electronic component, or communicating with another external electronic device or an external electronic component. The interface includes, for example, one or more of a low voltage differential signaling interface (LVDS), a mobile industry processor interface (MIPI), and a serial interface.

[0068] Examples of the display device 100 include a liquid crystal display device, an organic light emitting display device, and a plasma display device.

[0069] Figure 2 is a diagram showing a circuit structure of a sub-pixel provided in a display device according to an embodiment of the present disclosure.

[0070] Reference Figure 2 , each sub-pixel SP provided in the display device 100 according to an embodiment of the present disclosure includes one or more transistors and a capacitor, and includes an organic light emitting diode OLED as a light emitting element.

[0071] For example, the sub-pixel SP includes a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor Cst, and an organic light emitting diode OLED.

[0072] The driving transistor DRT includes a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT is a gate node, and a data voltage Vdata is applied to the first node N1 via a corresponding data line DL when the switching transistor SWT is turned on. The second node N2 of the driving transistor DRT is electrically connected to the anode electrode of the organic light emitting diode OLED, and the second node N2 is a source node or a drain node. The third node N3 of the driving transistor DRT is electrically connected to a driving voltage line DVL to which a driving voltage EVDD is applied, and the third node N3 is a drain node or a source node.

[0073] In the image driving period, the driving voltage EVDD required for image driving is provided via the driving voltage line DVL. For example, the driving voltage EVDD required for image driving may be 27V.

[0074] The switching transistor SWT is electrically connected between the first node N1 of the driving transistor DRT and the corresponding data line DL, and includes a gate node connected to the corresponding gate line GL and operates in response to a scan signal SCAN provided via the gate line GL. When the switching transistor SWT is turned on, the switching transistor SWT transmits a data voltage Vdata provided via the data line DL to the gate node of the driving transistor DRT to control the operation of the driving transistor DRT.

[0075] The sensing transistor SENT is electrically connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL, the sensing transistor SENT includes a gate node connected to the corresponding gate line GL and operates in response to a scan signal SCAN provided via the gate line GL. When the sensing transistor SENT is turned on, the sensing transistor SENT transmits a sensing reference voltage Vref provided via the reference voltage line RVL to the second node N2 of the driving transistor DRT.

[0076] That is, the voltage of the first node N1 and the second node N2 of the driving transistor may be controlled by controlling the switching transistor SWT and the sensing transistor SENT, and thus a current for driving the organic light emitting diode OLED may be provided.

[0077] The switching transistor SWT and the sensing transistor SENT may be connected to the same gate line GL, or may be connected to different signal lines. In this example, the switching transistor SWT and the sensing transistor SENT are connected to the same gate line GL. In this case, the switching transistor SWT and the sensing transistor SENT may be simultaneously controlled using a scan signal SCAN transmitted via a single gate line GL, and the aperture ratio of the sub-pixel SP may be increased.

[0078] On the other hand, the transistor provided in each sub-pixel SP may be formed as an n-type transistor or a p-type transistor, and it is assumed that the transistor provided in each sub-pixel SP is formed as an n-type transistor.

[0079] The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, and maintains the data voltage Vdata within one frame.

[0080] Depending on the type of the driving transistor DRT, the storage capacitor Cst may be connected between the first node N1 and the third node N3 of the driving transistor DRT. The anode electrode of the organic light emitting diode OLED is electrically connected to the second node N2 of the driving transistor DRT, and a basic voltage EVSS is applied to the cathode electrode of the organic light emitting diode OLED. Here, the basic voltage EVSS may be a ground voltage, or may be higher or lower than the ground voltage. The basic voltage EVSS may vary depending on the driving state. For example, the basic voltage EVSS at the image driving time point and the basic voltage EVSS at the sensing driving time point may be set to be different from each other.

[0081] Figure 3 is a diagram showing a waveform of a data voltage applied to a display panel via a data driving circuit in a display device according to the related art.

[0082] Reference Figure 3, at the timing when the data driving circuit 130 of the display device operates on a specific horizontal line selected by the horizontal synchronization signal Hsync in the display panel 110, in response to the gate clock signal GCLK (operated in response to the low-level gate clock signal GCLK), a data voltage Vdata is provided to the sub-pixel specified by applying a data enable signal to the data driving circuit 130.

[0083] The horizontal synchronization signal Hsync and the gate clock signal GCLK are digital signals, and the data voltage Vdata output from the data driving circuit 130 is an analog signal.

[0084] As described above, since each sub-pixel SP constituting the display panel 110 includes a storage capacitor Cst, the storage capacitor Cst requires a certain settling time TsetH or TsetL in the process of increasing the data voltage Vdata to the high-level data voltage VH or decreasing the data voltage Vdata to the low-level data voltage VL. Here, the high-level data voltage VH or the low-level data voltage VL is a voltage level at which the data voltage Vdata is at a stable level.

[0085] Therefore, in order to make the data voltage Vdata output to the display panel 110 a high level data voltage VH or a low level data voltage VL corresponding to a saturation state, the storage capacitor Cst of the subpixel SP needs to be fully charged or discharged before the gate clock signal GCLK transitions to a low level.

[0086] That is, after the setup time TsetH or TsetL has passed, the gate clock signal GCLK must be enabled.

[0087] However, since the time interval of the horizontal period is reduced to form a display panel 110 with a high resolution and to drive the display panel 110 at a high speed, the bias setting value of the data driving circuit 130 may be adjusted to reduce the setup time TsetH or TsetL and increase the slew rate, and thus there is a problem in that a constant current flowing in a driving amplifier of the data driving circuit 130 increases and power consumption increases rapidly.

[0088] Particularly, a driving amplifier converting digital image data DATA into an analog type data voltage Vdata in the data driving circuit 130 accounts for 60% or more of total power consumption, and thus serves as a main factor increasing the total power consumption of the display device 100 .

[0089] The inventors of the present disclosure have discovered that the setup time of the data voltage Vdata and the power consumption can be reduced by applying an offset Offset to the data voltage Vdata applied to the display panel 110 by the data driving circuit 130 .

[0090] Figure 4 is a block diagram illustrating a data driving circuit in a display device according to an embodiment of the present disclosure.

[0091] Reference Figure 4 According to an embodiment of the present disclosure, the data driving circuit 130 in the display device 100 includes a data controller 131, a bias voltage generating circuit 132, a gamma reference voltage generating circuit 133, a shift register 134, a plurality of first latch circuits 135A and 135B, a second latch circuit 136, a digital-to-analog converter 137, and an output buffer 138.

[0092] The data controller 131 receives the data control signal DCS from the timing controller 140 , and controls the level of the data output signal Sout applied to the display panel 110 based on the data control signal DCS.

[0093] The data controller 131 generates a bias control signal BCS for adjusting the level of a bias voltage Vbias applied to a driving amplifier of the output buffer 138 .

[0094] The data controller 131 generates a gamma enable signal GEN. The gamma enable signal GEN controls the gamma reference voltage generating circuit 133 so as to generate a gamma reference voltage Vgm. The gamma reference voltage Vgm is used to convert the digital image data DATA provided from the timing controller 140 into an analog type data voltage Vdata of gray scale.

[0095] The data driving circuit 130 according to an embodiment of the present disclosure can reduce the setup time TsetH or TsetL and power consumption of the data voltage Vdata by: generating offset image data DATA(Offset), wherein the offset image data DATA(Offset) is obtained by adding an offset to the digital image data DATA provided from the timing controller 140; and providing an offset data voltage Vdata(Offset) corresponding to the offset image data DATA(Offset) to the horizontal line of the display panel 110 within the offset time portion before the gate clock signal GCLK is enabled.

[0096] The data controller 131 generates offset image data DATA (Offset) in which an offset is applied to the digital image data DATA based on the digital image data DATA and the grayscale provided from the timing controller 140, and includes a lookup table storing the generated offset image data DATA (Offset) together.

[0097] Figure 5is a diagram illustrating an example of a lookup table in which digital image data and offset image data are stored in a display device according to an embodiment of the present disclosure.

[0098] Reference Figure 5 , the digital image data DATA provided from the timing controller 140 and the offset image data DATA(Offset) to which the offset is applied are stored together in the lookup table in the display device 100 according to the embodiment of the present disclosure.

[0099] The lookup table may be provided inside the data controller 131 , or may be provided outside the data controller 131 .

[0100] The offset applied to the digital image data DATA may vary according to the gray level of the digital image data DATA. For example, when the gray level is applied from 0 to 256, an offset value A corresponding to a gray level of 255 is applied to the digital image data DATA.

[0101] An offset value of +A is applied in a portion where the digital image data DATA increases to a gray level of 255, and an offset value of −A is applied in a portion where the digital image data DATA decreases to a gray level of 255.

[0102] The offset value varies according to the gray level. For example, an offset value B corresponding to a gray level of 191 is applied to the digital image data DATA, and an offset value I corresponding to a gray level of 0 is applied to the digital image data DATA.

[0103] At this time, the offset value applied to the digital image data DATA can be independently determined for each gray level, or after determining the offset value A applied to the digital image data DATA corresponding to the gray level of 255 and the offset value I applied to the digital image data DATA corresponding to the gray level of 0, for the gray level corresponding to the intermediate level, the offset value can be determined by applying interpolation to the offset value A and the offset value I to satisfy the predetermined function.

[0104] When an interpolation method is used for grayscales at intermediate levels, the grayscale range to which the interpolation method is applied may be variously changed.

[0105] The data controller 131 stores the digital image data DATA received from the timing controller 140 together with the offset image data DATA (Offset) having the offset value applied to the digital image data DATA in the lookup table.

[0106] The data controller 131 transmits the digital image data DATA stored in the lookup table to the first latch circuit 135A, and transmits the offset image data DATA (Offset) having an offset value to the first offset latch circuit 135B.

[0107] The bias voltage generating circuit 132 generates a bias voltage Vbias having various voltage levels in response to the bias control signal BCS.

[0108] The gamma reference voltage generating circuit 133 receives the gamma enable signal GEN and generates gamma reference voltages Vgm having various voltage levels.

[0109] The shift register 134 generates a first latch enable signal 1st LEN for operating the first latch circuit 135A and a first offset latch enable signal 1st LEN (Offset) for operating the first offset latch circuit 135B based on the source sampling clock signal SCLK.

[0110] The first latch enable signal 1st LEN may control a timing of outputting the digital image data DATA stored in the second latch circuit 136 via the first latch circuit 135A to the display panel 110 .

[0111] The first offset latch enable signal 1st LEN(Offset) may control a timing of outputting the offset image data DATA(Offset) stored in the second latch circuit 136 via the first offset latch circuit 135B to the display panel 110 .

[0112] The first latch circuit 135A temporarily stores the digital image data DATA received from the data controller 131. The digital image data DATA may be sequentially stored in the first latch circuit 135A to correspond to a position where the digital image data DATA is output to the display panel 110.

[0113] The first offset latch circuit 135B temporarily stores the offset image data DATA(Offset) received from the data controller 131. The offset image data DATA(Offset) may be sequentially stored in the first offset latch circuit 135B to correspond to the position where the offset image data DATA(Offset) is output to the display panel 110.

[0114] The first latch circuit 135A may transfer the latched digital image data DATA to the second latch circuit 136 at a desired timing under the control of the first latch enable signal 1st LEN received from the shift register 134. The first offset latch circuit 135B may transfer the latched offset image data DATA (Offset) to the second latch circuit 136 at a desired timing under the control of the first offset latch enable signal 1st LEN (Offset) received from the shift register 134.

[0115] The second latch circuit 136 receives the digital image data DATA stored in the first latch circuit 135A and the offset image data DATA (Offset) stored in the first offset latch circuit 135B.

[0116] The second latch circuit 136 receives the second latch enable signal 2nd LEN from the data controller 131 and transmits the digital image data DATA or the offset image data DATA (Offset) to the digital-to-analog converter 137 .

[0117] Here, the second latch enable signal 2nd LEN controls an offset data voltage Vdata(Offset) corresponding to the offset image data DATA(Offset) which is output during a predetermined offset time at a time point when the analog type data voltage Vdata is applied to the horizontal line of the display panel 110. The second latch enable signal 2nd LEN may control a data voltage Vdata corresponding to the digital image data DATA which is output when the offset time for outputting the offset data voltage Vdata(Offset) has passed.

[0118] The digital-to-analog converter 137 converts the digital image data DATA or the offset image data DATA (Offset) transmitted to the digital-to-analog converter 137 into a gray voltage Vgs using the gamma reference voltage Vgm received from the gamma reference voltage generating circuit 133 .

[0119] The output buffer 138 includes a plurality of driving amplifiers, and each driving amplifier outputs a data output signal Sout to the display panel 110 based on the grayscale voltage Vgs received from the digital-to-analog converter 137. The data output signal Sout includes a data voltage Vdata corresponding to the digital image data DATA or an offset data voltage Vdata(Offset) corresponding to the offset image data DATA(Offset).

[0120] Therefore, the data output signal Sout applied to the display panel 110 via the output buffer 138 is the offset data voltage Vdata(Offset) applied with an offset during the first offset time in the data enable portion, and is the data voltage Vdata not applied with an offset after the offset time has passed.

[0121] Figure 6 is a diagram illustrating a data driving circuit and a portion of a sub-pixel in a display device according to an embodiment of the present disclosure.

[0122] Reference Figure 6 The output buffer 138 constituting the data driving circuit 130 in the display device 100 according to the embodiment of the present disclosure includes a driving amplifier Amp. Herein, one digital-to-analog converter 137 required to drive one sub-pixel SP and one driving amplifier Amp included in the output buffer 138 are shown.

[0123] The driving amplifier Amp receives the gray voltage Vgs from the digital-to-analog converter 137 and amplifies the gray voltage Vgs according to the level of the bias voltage Vbias.

[0124] The data output signal Sout amplified by the driving amplifier Amp includes a data voltage Vdata corresponding to the digital image data DATA or an offset data voltage Vdata(Offset) corresponding to the offset image data DATA(Offset).

[0125] Here, the data output signal Sout output to the sub-pixel SP provided in the display panel 110 is applied with the offset data voltage Vdata(Offset) during the first offset time, and is not applied with the offset data voltage Vdata after the offset time has passed.

[0126] Therefore, the offset data voltage Vdata(Offset) may be used to reduce the setup time TsetH or TsetL of the data output signal Sout provided to the display panel 110 and reduce power consumption.

[0127] Figure 7 is a diagram showing an example of an experimental graph of an offset setting value and an offset time in a display device according to an embodiment of the present disclosure.

[0128] Reference Figure 7, the data output signal Sout applied to the display panel 110 in the display device 100 according to the embodiment of the present disclosure should be output at a timing before the gate clock signal GCLK changes from a high level to a low level in the data enable portion. Here, it takes time T1 from the data enable start time point to the time point when the gate clock signal GCLK is changed to a low level.

[0129] For example, when the data output signal Sout applied to the display panel 110 changes from VH to VL1 , the data output signal Sout should be stabilized from VH to VL1 within time T1 , and thus the setup time TsetL should be set to be less than T1 .

[0130] Here, the high level data voltage VH and the low level data voltage VL in the digital image data DATA are stored in the lookup table.

[0131] When the data voltage of the low level VL2 is changed to the offset data voltage Vdata(Offset) by applying a predetermined offset to the digital image data DATA, time T2 is required until the data output signal Sout reaches the level VL1. That is, when the predetermined offset is applied, time T1-T2 is shortened until the data output signal reaches the data voltage of the low level VL1.

[0132] In this way, when the data output signal Sout is generated using the offset image data DATA (Offset) until the data output signal Sout reaches the low level data voltage VL and then the data output signal Sout is generated using the digital image data DATA to which no offset is applied, the setup time TsetL required until the data output signal Sout is stabilized at the low level data voltage VL can be reduced.

[0133] In this case, the offset time Tos in which the data output signal Sout is generated using the offset image data DATA(Offset) is set to T2 corresponding to the time until the data output signal Sout reaches the low level data voltage of VL1 or a slightly longer time.

[0134] In the present embodiment, the data output signal Sout decreases from a high level to a low level, but the same is true about the case where the data output signal Sout increases from a low level to a high level.

[0135] Figure 8 is a diagram showing an example of the timing of a signal applied to a display panel via a data driving circuit in a display device according to an embodiment of the present disclosure.

[0136] Reference Figure 8According to an embodiment of the present disclosure, the data driving circuit 130 of the display device 100 provides a data output signal Sout to a sub-pixel specified in a data enable portion, in which a high-level data enable signal DE is applied to a specific horizontal line selected by a horizontal synchronization signal Hsync in the display panel 110.

[0137] Therefore, in the data enable portion, the data controller 131 transfers the digital image data DATA stored in the lookup table to the first latch circuit 1st Latch and transfers the offset image data DATA (Offset) having the offset value applied thereto to the first offset latch circuit 1st Offset Latch.

[0138] Therefore, the first latch circuit 1st Latch temporarily stores the digital image data DATA received from the data controller 131 , and the first offset latch circuit 1st Offset Latch temporarily stores the offset image data DATA (Offset) received from the data controller 131 .

[0139] The digital image data DATA and the offset image data DATA (Offset) are transferred to the second latch circuit 2nd Latch according to the first latch enable signal 1st LEN and the first offset latch enable signal 1st LEN (Offset) generated by the shift register 134 .

[0140] The second latch circuit 2nd Latch receives the second latch enable signal 2nd LEN from the data controller 131 and transmits the digital image data DATA or the offset image data DATA (Offset) to the digital-to-analog converter 137 .

[0141] Here, the second latch enable signal 2nd LEN is a signal to be output for controlling the digital image data DATA stored in the second latch circuit 2ndLatch, and the second latch enable signal 2nd LEN includes a second offset latch enable signal 2nd LEN (Offset) to be output for controlling the offset image data DATA (Offset).

[0142] Therefore, the offset image data DATA(Offset) is output from the second latch circuit 2nd Latch during the offset time Tos in which the second offset latch enable signal 2nd LEN(Offset) is provided from the data controller 131. Therefore, the data output signal Sout applied to the display panel 110 via the driving amplifier Amp of the output buffer 138 during the offset time Tos is the offset data voltage Vdata(Offset) corresponding to the offset image data DATA(Offset).

[0143] After the offset time Tos, the digital image data DATA is output from the second latch circuit 2nd Latch. Therefore, the data output signal Sout applied to the display panel 110 via the driving amplifier Amp of the output buffer 138 in the time portion after the offset time Tos is the data voltage Vdata corresponding to the digital image data DATA.

[0144] Therefore, by using the offset data voltage Vdata(Offset) output to the display panel 110 within the offset time Tos, the setup time TsetH or TsetL of the data output signal Sout provided to the display panel 110 may be reduced and power consumption may be reduced.

[0145] Fig. 9 is a diagram illustrating an advantage of reducing a setup time using an offset data voltage in a display device according to an embodiment of the present disclosure. Fig.10 is a diagram showing a waveform of a data output signal using an offset data voltage applied to a display panel in a display device according to an embodiment of the present disclosure.

[0146] Reference Fig. 9 and Fig.10 , the data output signal Sout applied to the display panel 110 by the data driving circuit 130 is a digital voltage Vdata corresponding to the digital image data DATA provided from the timing controller 140 to the data driving circuit 130. The display device 100 according to the embodiment of the present disclosure can reduce the setup time TsetH or TsetL by outputting an offset data voltage Vdata(Offset) corresponding to the offset image data DATA(Offset) having an offset applied to the digital image data DATA within an offset time Tos at a predetermined interval from the time point when the data voltage Vdata is applied.

[0147] That is, within the offset time Tos, the data driving circuit 130 can reduce the time until the data output signal Sout reaches the high level data voltage VH or the low level data voltage VL by outputting the offset data voltage Vdata(Offset) corresponding to the offset image data DATA(Offset), and after the offset time Tos, the data driving circuit 130 can enable the data signal Sout to be stably maintained at the high level data voltage VH or the low level data voltage VL by outputting the data voltage Vdata corresponding to the digital image data DATA.

[0148] Therefore, it can be understood that the setup time TsetH(Vdata(Offset)) obtained by outputting the offset data voltage Vdata(Offset) within the offset time Tos is reduced more than the setup time TsetH(Vdata) obtained by only outputting the data voltage Vdata without considering the offset time Tos of the output offset data voltage Vdata(Offset).

[0149] Therefore, using the display device 100 according to an embodiment of the present disclosure, even if the time interval of the horizontal period is reduced due to the rapid driving of the data driving circuit 130, the setup time TsetH or TsetL of the data output signal Sout can be reduced without increasing the bias setting value applied to the data driving circuit 130, and thus the total power consumption can be reduced by reducing the constant current provided to the driving amplifier Amp.

[0150] On the other hand, it has been described above that the digital image data DATA of the first latch circuit 135A and the offset image data DATA (Offset) of the first offset latch circuit 135B are provided to a second latch circuit 136, and the timing of providing the digital image data DATA and the offset image data DATA (Offset) is controlled by a second latch circuit 136, but the second latch circuit 136 that respectively controls the timing of providing the digital image data DATA and the timing of providing the offset image data DATA (Offset) may be separate.

[0151] Fig.11 is a block diagram illustrating a data driving circuit in a display device according to another embodiment of the present disclosure.

[0152] Reference Fig.11 The data driving circuit 130 in the display device 100 according to another embodiment of the present disclosure includes a data controller 131, a bias voltage generating circuit 132, a gamma reference voltage generating circuit 133, a shift register 134, a plurality of first latch circuits 135A and 135B, a plurality of second latch circuits 136A and 136B, a digital-to-analog converter 137 and an output buffer 138.

[0153] The data controller 131 receives the data control signal DCS from the timing controller 140 , and controls the level of the data output signal Sout provided to the display panel 110 based on the data control signal DCS.

[0154] The data driving circuit 130 generates offset image data DATA(Offset) having an offset applied to the digital image data DATA transmitted from the timing controller 140, and within the offset time Tos before the gate clock signal GCLK is enabled, the data driving circuit 130 provides an offset data voltage Vdata(Offset) corresponding to the offset image data DATA(Offset) in the horizontal line of the display panel 110, thereby reducing the setup time TsetH or TsetL of the data voltage Vdata and power consumption.

[0155] The data controller 131 stores the digital image data DATA received from the timing controller 140 together with the offset image data DATA (Offset) having the offset value applied to the digital image data DATA in the lookup table.

[0156] The data controller 131 transmits the digital image data DATA stored in the lookup table to the first latch circuit 135A, and transmits the offset image data DATA (Offset) having the offset value applied thereto to the first offset latch circuit 135B.

[0157] The shift register 134 generates a first latch enable signal 1st LEN for operating the first latch circuit 135A and a first offset latch enable signal 1st LEN (Offset) for operating the first offset latch circuit 135B based on the source sampling clock signal SCLK.

[0158] The first latch enable signal 1st LEN may control a timing at which the digital image data DATA transmitted from the first latch circuit 135A to the second latch circuit 136A is output to the display panel 110 .

[0159] The first offset latch enable signal 1st LEN(Offset) may control a timing at which the offset image data DATA(Offset) transmitted from the first offset latch circuit 135B to the second offset latch circuit 136B is output to the display panel 110 .

[0160] The first latch circuit 135A transfers the latched digital image data DATA to the second latch circuit 136A at a desired timing under the control of the first latch enable signal 1st LEN received from the shift register 134 .

[0161] The first offset latch circuit 135B transfers the latched offset image data DATA (Offset) to the second offset latch circuit 136B at a desired timing under the control of the first offset latch enable signal 1stLEN (Offset) received from the shift register 134 .

[0162] The second latch circuit 136A receives the digital image data DATA stored in the first latch circuit 135A, and receives the offset image data DATA(Offset) stored in the first offset latch circuit 135B. In this case, the second latch circuit 135A is also referred to as a second normal latch circuit.

[0163] The second latch circuit 136A receives the second latch enable signal 2nd LEN from the data controller 131 and transmits the digital image data DATA to the digital-to-analog converter 137 .

[0164] The second offset latch circuit 136B receives the second offset latch enable signal 2nd LEN (Offset) from the data controller 131 and transmits the offset image data DATA (Offset) to the digital-to-analog converter 137 .

[0165] The second offset latch enable signal 2nd LEN(Offset) may control an offset data voltage Vdata(Offset) to be output to a horizontal line of the display panel 110 within a predetermined offset time Tos. The second latch enable signal 2nd LEN may control a data voltage Vdata corresponding to the digital image data DATA to be output when the offset time Tos for outputting the offset data voltage Vdata(Offset) has passed.

[0166] The digital-to-analog converter 137 converts the digital image data DATA or the offset image data DATA (Offset) transmitted to the digital-to-analog converter 137 into a gray voltage Vgs using the gamma reference voltage Vgm received from the gamma reference voltage generating circuit 133 .

[0167] The output buffer 138 includes a plurality of driving amplifiers, and each driving amplifier outputs a data output signal Sout to the display panel 110 based on the grayscale voltage Vgs received from the digital-to-analog converter 137. The data output signal Sout includes a data voltage Vdata corresponding to the digital image data DATA or an offset data voltage Vdata(Offset) corresponding to the offset image data DATA(Offset).

[0168] Therefore, the data output signal Sout applied to the display panel 110 via the output buffer 138 is the offset data voltage Vdata(Offset) applied thereto during the first offset time in the data enable portion, and is the data voltage Vdata not applied thereto after the offset time.

[0169] Therefore, even if the time interval of the horizontal period is reduced due to the rapid driving of the data driving circuit 130, the setup time TsetH or TsetL of the data output signal Sout can be reduced without increasing the bias setting value applied to the data driving circuit 130, and thus the total power consumption can be reduced by reducing the constant current supplied to the driving amplifier Amp.

[0170] The above description only illustrates the technical concept of the present disclosure, and those skilled in the art may make various modifications and changes, such as combination, separation, replacement and change of configurations, without departing from the essential features of the present invention. Therefore, the embodiments of the present disclosure are not limited to the technical concept of the present disclosure, but illustrate the technical concept of the present disclosure. The technical concept of the present disclosure is not limited to the embodiments. The scope of the present disclosure is defined by the appended claims, and all technical concepts within the scope equivalent thereto should be interpreted as belonging to the scope of the present disclosure.

[0171] Reference numerals list

[0172] 100: Display device

[0173] 110: Display panel

[0174] 120: Gate drive circuit

[0175] 130: Data drive circuit

[0176] 131: Data Controller

[0177] 132: Bias voltage generation circuit

[0178] 133: Gamma reference voltage generation circuit

[0179] 134: Shift register

[0180] 135A: First latch circuit

[0181] 135B: First offset latch circuit

[0182] 136, 136A: Second latch circuit

[0183] 136B: Second offset latch circuit

[0184] 137: Digital to Analog Converter

[0185] 138: Output buffer

[0186] 140: Timing controller

Claims

1. A display device, comprising: a display panel in which a plurality of sub-pixels are arranged at positions where a plurality of data lines and a plurality of gate lines intersect each other; a gate driving circuit, the gate driving circuit driving the plurality of sub-pixels via the plurality of gate lines; a data driving circuit that provides data output signals to the plurality of sub-pixels via the plurality of data lines, the data output signals including a data voltage and an offset data voltage generated by adding an offset to the data voltage; as well as a timing controller, the timing controller controlling the gate driving circuit and the data driving circuit, Wherein, the data driving circuit comprises: a data controller that generates offset image data by adding an offset to digital image data received from the timing controller using a lookup table that stores the digital image data and the offset image data; a first latch circuit storing the digital image data received from the data controller; a first offset latch circuit storing the offset image data received from the data controller; a second latch circuit that stores the digital image data and the offset image data transmitted from the first latch circuit and the first offset latch circuit, respectively, and selectively transmits the stored digital image data and the offset image data based on a second latch enable signal received from the data controller; a digital-to-analog converter that converts the digital image data and the offset image data transmitted from the second latch circuit into the data voltage and the offset data voltage; and An output buffer provides a selected one of the data voltage and the offset data voltage to the display panel under the control of the data controller.

2. The display device according to claim 1, wherein: The output buffer includes a driving amplifier that provides the data voltage or the offset data voltage to the display panel according to a bias voltage.

3. The display device according to claim 1, wherein: The offset varies according to a grayscale level of the digital image data.

4. The display device according to claim 1, wherein: The offset is determined independently for each gray level in a plurality of gray levels.

5. The display device according to claim 1, wherein: The offset is determined by applying an interpolation method to intermediate levels of grayscale.

6. The display device according to claim 1, wherein: The data controller controls an offset time of the offset data voltage in a data enable section to be provided to the display panel.

7. The display device according to claim 6, wherein: The offset time has an interval that is equal to or greater than a time from a start time point of the data enable portion to a time point at which the offset data voltage reaches a stable level of the data voltage.

8. The display device according to claim 6, wherein: The data controller controls the data voltage to be provided to the display panel after the offset time has elapsed.

9. The display device according to claim 1, wherein: The second latch circuit comprises: a second normal latch circuit storing the digital image data transmitted from the first latch circuit; and A second shift latch circuit stores the shift image data transferred from the first shift latch circuit.

10. A data driving circuit, comprising: a data controller that generates offset image data by adding an offset to digital image data received from a timing controller using a lookup table that stores the digital image data and the offset image data; a first latch circuit storing the digital image data received from the data controller; a first offset latch circuit storing the offset image data received from the data controller; a second latch circuit that stores the digital image data and the offset image data transmitted from the first latch circuit and the first offset latch circuit, respectively, and selectively transmits the stored digital image data and the offset image data based on a second latch enable signal received from the data controller; a digital-to-analog converter that converts the digital image data and the offset image data transmitted from the second latch circuit into a data voltage and an offset data voltage, and An output buffer provides a selected one of the data voltage and the offset data voltage to a display panel under control of the data controller.

11. The data driving circuit according to claim 10, wherein: The output buffer includes a driving amplifier that provides the data voltage or the offset data voltage to the display panel according to a bias voltage.

12. The data driving circuit according to claim 10, wherein: The offset varies according to a grayscale level of the digital image data.

13. The data driving circuit according to claim 10, wherein: The offset is determined by applying an interpolation method to intermediate levels of grayscale.

14. The data driving circuit according to claim 10, wherein: The data controller controls an offset time of the offset data voltage in a data enable section to be provided to the display panel.

15. The data driving circuit according to claim 14, wherein: The offset time has an interval that is equal to or greater than a time from a start time point of the data enable portion to a time point at which the offset data voltage reaches a stable level of the data voltage.

16. The data driving circuit according to claim 10, wherein: The second latch circuit comprises: a second normal latch circuit storing the digital image data transmitted from the first latch circuit; and The second shift latch circuit stores the shift image data transmitted from the first shift latch circuit.

17. A data-driven method comprising: generating, by a data controller, offset image data by adding an offset to digital image data received from a timing controller using a lookup table, the lookup table storing the digital image data and the offset image data; storing, by a first latch circuit, the digital image data received from the data controller; storing, by a first offset latch circuit, the offset image data received from the data controller; storing the digital image data and the offset image data by a second latch circuit; selectively transmitting, by the second latch circuit, the stored digital image data and the offset image data based on a second latch enable signal received from the data controller; Converting the digital image data and the offset image data into an analog data voltage and an offset data voltage by a digital-to-analog converter; as well as A selected one of the data voltage and the offset data voltage is provided to a display panel by an output buffer at different times.

18. The data driven method according to claim 17, wherein: The offset data voltage is provided to the display panel during an offset time in a data enable portion.

19. The data driven method according to claim 18, wherein: The offset time has an interval that is equal to or greater than a time from a start time point of the data enable portion to a time point at which the offset data voltage reaches a stable level of the data voltage.

20. The data driven method according to claim 17, wherein: The offset varies according to a grayscale level of the digital image data.

21. The data driven method according to claim 17, wherein: The offset is determined by applying an interpolation method to intermediate levels of grayscale.

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