Transmission driver and display device including the same

Abstract

A emission driver and a display device including the emission driver are provided herein. The display device includes a plurality of pixels. Each pixel of the plurality of pixels includes: a driving transistor including a first electrode, a second electrode, and a first gate electrode; a first emission transistor including a third electrode, a fourth electrode, and a second gate electrode, the third electrode being coupled to the first electrode of the driving transistor; and a second emission transistor including a fifth electrode, a sixth electrode, and a third gate electrode, the fifth electrode being coupled to the second electrode of the driving transistor. Both the second gate electrode and the third gate electrode are connected to an emission line. Based on an emission signal supplied from the emission line, the first emission transistor is turned on while the second emission transistor is turned off.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2019-0168093, filed on Dec. 16, 2019, the entire disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure generally relates to a display device, and more particularly, to a transmit driver for displaying an image at multiple frequencies and a display device including the transmit driver. Background Art

[0003] According to the material of the emission layer, light-emitting display devices are generally classified into inorganic light-emitting display devices and organic light-emitting display devices. An active matrix organic light-emitting display device includes an organic light-emitting diode that emits light by itself (hereinafter referred to as an "OLED") and may have a relatively fast response time, a relatively high emission efficiency, a relatively high brightness, and a relatively large viewing angle. Summary of the Invention

[0004] Exemplary embodiments of the present disclosure relate to a display device in which the visibility of an afterimage is minimized when the display device is driven at multiple frequencies.

[0005] In addition, exemplary embodiments of the present disclosure relate to a display device including a transmit driver that uses a power supply voltage to enable a driving transistor to be in an on-biased state.

[0006] The present disclosure is not limited to the exemplary embodiments described herein, and other technical variations not mentioned can be easily understood by those of ordinary skill in the art based on the following description.

[0007] Exemplary embodiments of the present disclosure include a display device including a plurality of pixels, wherein each pixel of the plurality of pixels includes: a driving transistor including a first electrode, a second electrode, and a first gate electrode; a first emission transistor including a third electrode, a fourth electrode, and a second gate electrode, the third electrode being coupled to the first electrode of the driving transistor; and a second emission transistor including a fifth electrode, a sixth electrode, and a third gate electrode, the fifth electrode being coupled to the second electrode of the driving transistor; wherein both the second gate electrode and the third gate electrode are connected to an emission line, and wherein, based on an emission signal supplied from the emission line, the first emission transistor is turned on while the second emission transistor is turned off.

[0008] The display device may further include: a transmit driver configured to supply an emission signal to both the second gate electrode and the third gate electrode through the emission line.

[0009] The emission driver may supply an emission signal having a first level, a second level, or a third level to the pixel through an emission line, and the third level is between the first level and the second level.

[0010] When the emission signal of the third level is supplied to the pixel, the first emission transistor may be turned on, while the second emission transistor may be turned off.

[0011] When the emission signal of the first level is supplied to the pixel, the first emission transistor and the second emission transistor may be turned off, and when the emission signal of the second level is supplied to the pixel, the first emission transistor and the second emission transistor may be turned on.

[0012] The driving transistor, the first emission transistor, and the second emission transistor may be P-type metal oxide semiconductor (PMOS) transistors.

[0013] When the emission signal of the third level is supplied to the pixel, the driving transistor may be set to an on-bias state.

[0014] The threshold voltage of the second emission transistor is larger than the threshold voltage of the first emission transistor.

[0015] The voltage range of the third level may vary from about 7.5V to about 8.5V.

[0016] Each pixel of the plurality of pixels may further include a light-emitting diode, and the sixth electrode may be coupled to the anode of the light-emitting diode.

[0017] The fourth electrode may be coupled to the first power supply line, a first power supply voltage signal is supplied through the first power supply line, and the cathode of the light-emitting diode may be coupled to the second power supply line, and a second power supply voltage signal having a level lower than the first power supply voltage signal is supplied through the second power supply line.

[0018] Exemplary embodiments of the present disclosure include an emission driver, the emission driver including a plurality of stage circuits, each stage circuit of the plurality of stage circuits including: a carry controller configured to generate a first output signal having a first level or a second level based on a first control signal and a second control signal; and an output buffer coupled to a first control line and a second control line, and configured to generate a second output signal having one of a first level, a second level, and a third level based on the first control signal supplied from the first control line and the second control signal supplied from the second control line, the third level being between the first level and the second level.

[0019] The output buffer may be coupled to an intermediate voltage signal line, and one of a voltage signal of the first level and a voltage signal of the third level is supplied through the intermediate voltage signal line.

[0020] During a first period of a frame period, the output buffer may generate a second output signal having a first level based on a first control signal, and during a second period of the frame period, the output buffer may generate a second output signal having a third level based on the first control signal.

[0021] The stage circuit may include a first stage circuit and a second stage circuit. The second stage circuit may be connected to the first stage circuit, and a first output signal of the first stage circuit may be supplied to a carry controller of the second stage circuit.

[0022] Exemplary embodiments of the present disclosure include a display device, the display device including: a display including a plurality of pixel rows, each pixel row of the plurality of pixel rows being defined by a plurality of pixels coupled to the same emission line; a scan driver configured to supply a scan signal to each of the plurality of pixels; a data driver configured to supply a data signal to each of the plurality of pixels; and an emission driver configured to supply an emission signal to each of the plurality of pixel rows through the emission line, wherein the emission signal has a first level, a second level, or a third level, and the third level is between the first level and the second level.

[0023] The emission driver may include a pair of emission drivers respectively disposed on opposite sides of the display.

[0024] The display may include a plurality of pixel rows, the plurality of pixel rows may include a first pixel row to a k-th pixel row and a (k + 1)-th pixel row to an n-th pixel row, and during a period in which an emission signal of the first level is supplied to at least some of the pixel rows from the (k + 1)-th pixel row to the n-th pixel row, an emission signal of the third level may be supplied to at least some of the pixel rows from the first pixel row to the k-th pixel row.

[0025] The first level may be higher than the second level.

[0026] The first pixel row to the k-th pixel row may be coupled to a first intermediate voltage signal line, and a voltage of the third level may be supplied through the first intermediate voltage signal line, and the (k + 1)-th pixel row to the n-th pixel row may be coupled to a second intermediate voltage signal line, and a voltage of the third level may be supplied through the second intermediate voltage signal line, wherein k and n are natural numbers, and k is greater than 1 and less than n.

[0027] The first intermediate voltage signal line and the second intermediate voltage signal line may be insulated from each other and may cross each other.

[0028] k may be substantially half of n.

[0029] The frame period may include: a data programming period during which data signals are written and each of the plurality of pixels emits light; and a holding period during which an emission signal of a third level is supplied to each of the plurality of pixels and each of the plurality of pixels emits light.

[0030] Each of the plurality of pixels may be driven at a first frequency and a second frequency, the second frequency being lower than the first frequency.

[0031] When driven at the second frequency, the frame period may further include an edge period during which, for each frame, the respective pixels arranged in parallel in the horizontal direction are synchronized.

[0032] Other details of the exemplary embodiments are included in the detailed description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure;

[0034] Figure 2 is a block diagram schematically showing a display device according to an embodiment of the present disclosure;

[0035] Figure 3 is Figure 2 an equivalent circuit diagram of a pixel in the display device of

[0036] Figure 4 is a graph showing the drain-source current of a driving transistor according to a voltage signal difference between the gate and the source of the driving transistor in a gate-on bias state and a gate-off bias state in a display device according to an embodiment of the present disclosure;

[0037] Figure 5 is a block diagram showing the relationship between a light emission driver and a display according to an embodiment of the present disclosure;

[0038] Figure 6 is a block diagram more specifically showing a light emission driver according to an embodiment of the present disclosure;

[0039] Figure 7 is Figure 6 an equivalent circuit diagram of a stage circuit of

[0040] Figure 8 and Figure 9 is a timing diagram showing a method of driving a display device according to an embodiment of the present disclosure;

[0041] Figure 10 is a block diagram showing the relationship between a light emission driver and a display in a display device according to another embodiment of the present disclosure;

[0042] Figure 11 is a block diagram showing the relationship between a transmit driver and a display in a display device according to another embodiment of the present disclosure;

[0043] Figure 12 is a block diagram showing the relationship between a transmit driver and a display in a display device according to another embodiment of the present disclosure;

[0044] Figure 13 is an equivalent circuit diagram of a stage circuit in a transmit driver according to another embodiment of the present disclosure; and

[0045] Figure 14 is a block diagram schematically showing a display device according to another embodiment of the present disclosure. Detailed Description of the Embodiments

[0046] According to the following exemplary embodiments to be described in more detail with reference to the accompanying drawings, the understanding of the present disclosure of a method including exemplary devices and operations will be clear. However, the present disclosure is not limited to the following exemplary embodiments and can be implemented in various forms. Therefore, the exemplary embodiments are provided only to describe the present disclosure and to make those skilled in the art aware of the category of the present disclosure, while the present invention will be defined based on the claims.

[0047] When it is stated that a first element or layer is formed on a second element or layer, the first element or layer can not only be directly on the second element or layer, but also a third element or layer can be interposed therebetween. Throughout the specification, the same reference numerals or the same reference signs denote the same elements.

[0048] Terms such as "first" and "second" can be used to describe various components, but they should not limit the various components. Those terms are only for the purpose of distinguishing a component from other components. For example, without departing from the spirit and scope of the present disclosure, the first component can be referred to as the second component, and the second component can be referred to as the first component, etc. In addition, as long as it is not explicitly mentioned in the sentence, the singular form can include the plural form.

[0049] The driving circuit of a flat panel display device includes a data driving circuit configured to supply data signals to data lines, a scan driving circuit configured to supply scan signals to scan lines or gate lines, and a transmit driving circuit configured to supply transmit signals, transmit control signals, etc. The transmit driving circuit can be directly formed on the same substrate on which circuit elements forming an effective area of the screen are formed. The circuit elements in the effective area construct pixel circuits, and each of the pixel circuits is formed in each of the pixels defined in a matrix by the data lines of the pixel array and the transmit driving circuit. Each of the circuit elements in the effective area and the transmit driving circuit includes a plurality of transistors.

[0050] A method of driving a display device at multiple frequencies can be employed, which can reduce the power consumed by the display device. When the display device is driven at some frequencies, afterimages can be visible. In a preferred embodiment, the display device may include a driving transistor within a pixel circuit configured to be in a conductive bias state before emitting light, which can reduce the visibility of such afterimages.

[0051] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals may be used to denote the same or like elements.

[0052] Figure 1 A display device according to an embodiment of the present disclosure is shown. Figure 1 The display device 1 can be used not only in large electronic devices (such as televisions, monitors, etc.) but also in small or medium-sized electronic devices (such as mobile phones, tablet PCs, vehicle navigation systems, gaming devices, smart watches, etc.).

[0053] Referring to Figure 1 , the display device 1 according to an embodiment of the present disclosure includes a display surface IS configured to display an image IM. The display surface IS on which the image IM is displayed is parallel to the surface defined by a first direction DR1 and a second direction DR2. The direction perpendicular to the display surface IS (i.e., the thickness direction of the display device 1) is indicated by a third direction DR3. Thus, the directions DR1, DR2, and DR3 can be orthogonal to each other.

[0054] In the present embodiment, for ease of description, the length direction of the display device 1 is defined as the first direction DR1, and the direction intersecting the first direction DR1 is defined as the second direction DR2. That is, the second direction DR2 can indicate the width direction of the display device 1. The thickness direction of the display device 1 intersecting each of the first direction DR1 and the second direction DR2 is defined as the third direction DR3. However, the embodiment is not limited to the above directions, and it should be understood that the first direction DR1, the second direction DR2, and the third direction DR3 are relative directions intersecting each other.

[0055] In an embodiment, the display surface IS of the display device 1 may include a plurality of regions. The display surface IS of the display device 1 may include a display region DA where the image IM is displayed and a non-display region NDA adjacent to the display region DA.

[0056] The display area DA is defined as the area where the image IM is displayed. In addition, the display area DA can be used as a detection member for detecting the external environment. That is to say, the display area DA can be used as, for example, an area for displaying the image IM and recognizing the fingerprint or touch of the user. In an embodiment, the display area DA may have a flat shape, but is not limited thereto, so at least a part of the display area DA may have curvature.

[0057] The non-display area NDA may be an area where the image IM is not displayed. The non-display area NDA may have a shape surrounding the display area DA. However, it is not limited thereto, and the shape of the display area DA and the shape of the non-display area NDA may change relative to each other.

[0058] In operation, Figure 1 A video player application running on the display device 1 is shown as an example of the image IM. In an embodiment, the display device 1 may be driven at multiple frequencies. For example, when the user scrolls the content on the display area DA of the display device 1 or when a moving image is displayed, the display device 1 may be driven at a first frequency, which is a relatively high frequency. When a still image is displayed in the display area DA of the display device 1, the display device 1 may be driven at a second frequency, which is a relatively low frequency. Compared with when the display device 1 is driven only at the first frequency, the power consumption can be reduced when the display device 1 is driven at a variable frequency (such as by switching to the first frequency or the second frequency).

[0059] In an embodiment, the display device 1 may be driven in such a way that different frequencies are used for each area in the display area DA. For example, a part of the display area DA where a moving image is displayed may be driven at a first frequency, which is a relatively high frequency, and another part of the display area DA where a still image is displayed may be driven at a second frequency, which is a relatively low frequency. Compared with when the entire display area DA is driven only at the first frequency, the power consumption can be reduced when the display device 1 is configured such that its display area DA is divided into multiple areas to be driven at different frequencies.

[0060] Figure 2 A display device according to an embodiment of the present disclosure is shown. Figure 3 Shown is Figure 2 the pixels in the display device of

[0061] Referring to Figure 2, the display device 1 includes a timing controller 10, a data driver 20, a scan driver 30, a transmit driver 40, a display 50, and a power supply 60. The timing controller 10 can generate signals required for the display device 1 by receiving an external input signal for an image frame from an external processor. For example, the timing controller 10 can supply a gray value and a control signal to the data driver 20. In addition, the timing controller 10 can supply a clock signal, a scan start signal, etc. to the scan driver 30. In addition, the timing controller 10 can supply a clock signal, a transmit stop signal, etc. to the transmit driver 40.

[0062] The data driver 20 can generate data voltages to be supplied to data lines DL1, DL2, ……, DLm using the gray value and the control signal received from the timing controller 10. For example, the data driver 20 can sample the gray value using a clock signal and apply data voltages corresponding to the gray value to the data lines DL1, DL2, ……, DLm in units of pixel rows (e.g., pixels coupled to the same scan line). Here, m can be a natural number greater than 0.

[0063] The scan driver 30 can generate scan signals to be supplied to scan lines GIL1, GWL1, GBL1, ……, GILn, GWLn, and GBLn by receiving a clock signal, a scan start signal, etc. from the timing controller 10. Here, n can be a natural number greater than 0.

[0064] Although not shown, the scan driver 30 can include a plurality of sub-scan drivers. For example, the first sub-scan driver can supply scan signals (e.g., Figure 3 GI) for the first scan lines GIL1, ……, GILn, the second sub-scan driver can supply scan signals (e.g., Figure 3 GW) for the second scan lines GWL1, ……, GWLn, and the third sub-scan driver can supply scan signals (e.g., Figure 3 GB) for the third scan lines GBL1, ……, GBLn. Each of the sub-scan drivers can include a plurality of scan stage circuits coupled in the form of a shift register. For example, the scan signal can be generated in such a way that a scan start signal having a conductive level pulse is supplied to a scan start line and the pulse is sequentially transmitted to a subsequent scan stage circuit.

[0065] The transmit driver 40 can generate transmit signals (e.g., Figure 3 EM) to be supplied to transmit lines EL1, EL2, ……, ELn by receiving a clock signal, a transmit stop signal, etc. from the timing controller 10. For example, the transmit driver 40 can transmit a transmit signal having a cut-off level pulse (such as Figure 7The VGH) is sequentially supplied to the emission lines EL1, EL2, …, ELn. For example, the emission driver 40 may be configured in the form of a shift register and may generate an emission signal by sequentially transmitting an emission stop signal having a cut-off level to a subsequent emission stage circuit (hereinafter referred to as a stage circuit) under the control of a clock signal.

[0066] The display 50 includes pixels PXij. For example, the pixel PXij may be coupled to its corresponding data line DLi, a plurality of scan lines GILj, GWLj, and GBLj, and an emission line ELj. However, the number of the data line DLi, scan lines GILj, GWLj, and GBLj, and the emission line ELj corresponding to the pixel PXij is not limited to the number shown in the example.

[0067] A plurality of pixels PXij may define an emission region that emits light of multiple colors. For example, a plurality of pixels PXij may define an emission region that emits red light, green light, and blue light. For example, the pixel PXij includes a plurality of transistors and at least one capacitor.

[0068] The display 50 may define a display region ( Figure 1 in DA) that includes the emission region, and the emission region emits light of multiple colors defined by the pixels PXij.

[0069] In an embodiment, the pixels PXij may be arranged in a matrix. For example, the pixels PXij arranged in the row direction among the pixels PXij may be respectively coupled to the same first scan lines GIL1, …, GILn, the same second scan lines GWL1, …, GWLn, the same third scan lines GBL1, …, GBLn, and the same emission lines EL1, EL2, …, ELn. The row direction may be the second direction DR2 described above. The pixels PXij arranged in the row direction and respectively coupled to the same first scan lines GIL1, …, GILn, the same second scan lines GWL1, …, GWLn, the same third scan lines GBL1, …, GBLn, and the same emission lines EL1, EL2, …, ELn may define a pixel row.

[0070] The power supply 60 may receive an external input voltage signal and convert it to supply a power supply voltage signal to an output terminal. For example, the power supply 60 generates a high power supply voltage signal ELVDD and a low power supply voltage signal ELVSS based on the external input voltage signal. In the present embodiment, the high power supply voltage signal ELVDD and the low power supply voltage signal ELVSS may be powers having relative voltage levels. The power supply 60 may supply a first initialization voltage signal VINT1 and a second initialization voltage signal VINT2 to each pixel PXij, and the first initialization voltage signal VINT1 is configured to turn on a driving transistor (Figure 3 The gate electrode of T1) therein is initialized, and the second initialization voltage signal VINT2 is configured to initialize the anode of the light-emitting diode ( Figure 3 LD) therein.

[0071] The power supply 60 can receive an external input voltage signal from a battery or the like, and can generate a power supply voltage signal higher than the external input voltage signal by boosting the external input voltage signal. For example, the power supply 60 can be configured as a power management integrated circuit (PMIC). For example, the power supply 60 can be configured as an external DC / DC PMIC.

[0072] The power supply 60 can include an initialization voltage signal generator 61. The initialization voltage signal generator 61 can control the supply periods of the initialization voltage signals VINT1 and VINT2, which are supplied to each pixel PXij. That is, the initialization voltage signal generator 61 can respectively control the supply periods of the initialization voltage signals VINT1 and VINT2, which are supplied to each pixel PXij.

[0073] Referring to Figure 3 , the pixel PXij according to an embodiment of the present disclosure includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a light-emitting diode LD.

[0074] The first transistor T1 can be configured such that: its first electrode is coupled to the first electrode of the second transistor T2 and the second electrode of the fifth transistor T5, its second electrode is coupled to the first electrode of the third transistor T3 and the first electrode of the sixth transistor T6, and its gate electrode is coupled to the second electrode of the third transistor T3. The first transistor T1 can be referred to as a driving transistor. In this embodiment, either the first electrode or the second electrode of each transistor is a source electrode, and the other is a drain electrode.

[0075] The second transistor T2 can be configured such that: its first electrode is coupled to the first electrode of the first transistor T1, its second electrode is coupled to the data line DLi, and its gate electrode is coupled to the second scan line GWLj. The second transistor T2 can be referred to as a scan transistor.

[0076] The third transistor T3 can be in a form in which a plurality of transistors are serially coupled. The third transistor T3 can be configured such that: the first electrode of the transistor on one side is coupled to the second electrode of the first transistor T1, the second electrode of the transistor on the other side is coupled to the gate electrode of the first transistor T1, and the gate electrode of the third transistor T3 is coupled to the second scan line GWLj. The third transistor T3 can be referred to as a diode-connected transistor.

[0077] The fourth transistor T4 may be in a form in which a plurality of transistors are connected in series. The fourth transistor T4 may be configured such that: the first electrode of the transistor on one side is connected to the second electrode of the storage capacitor Cst, the second electrode of the transistor on the other side is connected to the first initialization line (a first initialization voltage signal VINT1 is supplied through the first initialization line), and the gate electrode of the fourth transistor T4 is connected to the first scan line GILj. The fourth transistor T4 may be referred to as a gate initialization transistor. The third transistor T3 and the fourth transistor T4 are configured such that a plurality of transistors are connected in series, whereby current leakage can be minimized.

[0078] The fifth transistor T5 may be configured such that: its first electrode is connected to the high power supply line ELVDDL, its second electrode is connected to the first electrode of the first transistor T1, and its gate electrode is connected to the emission line ELj. The fifth transistor T5 may be referred to as a first emission transistor.

[0079] The sixth transistor T6 may be configured such that: its first electrode is connected to the second electrode of the first transistor T1, its second electrode is connected to the anode of the light-emitting diode LD, and its gate electrode is connected to the emission line ELj. The sixth transistor T6 may be referred to as a second emission transistor.

[0080] In an embodiment, the threshold voltage of the fifth transistor T5 and the threshold voltage of the sixth transistor T6 may be slightly different. For example, if both are P-type (PMOS) transistors, as Figure 3 depicted, then the threshold voltage of the sixth transistor T6 may be a negative voltage slightly lower than the threshold voltage of the fifth transistor T5. That is, when the gate voltage signal of each of the fifth transistor T5 and the sixth transistor T6 has a specific voltage level, the fifth transistor T5 may be placed in an on state, while the sixth transistor T6 may be placed in an off state. The specific voltage level at the gate may be in the range of about 7.5V to 8.5V, where the gate-source voltage signal Vgs for overcoming each corresponding threshold voltage Vth is the specific voltage level at the gate minus the voltage level at the source (e.g., ELVDD), but is not limited to this voltage level range.

[0081] In an embodiment, the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 may be connected to the same emission line ELj. That is, the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 may be electrically connected to each other.

[0082] The seventh transistor T7 can be configured such that: its first electrode is coupled to the anode of the light-emitting diode LD, its second electrode is coupled to the second initialization line (to which a second initialization voltage signal VINT2 is supplied through the second initialization line), and its gate electrode is coupled to the third scan line GBLj. The seventh transistor T7 can be referred to as an anode initialization transistor.

[0083] Since the gate electrode of the first transistor T1 is electrically coupled to the first initialization line to which a first initialization voltage signal VINT1 is applied and the anode of the light-emitting diode LD is electrically coupled to the second initialization line to which a second initialization voltage signal VINT2 is applied, the initialization voltage signal of the gate electrode of the first transistor T1 can be set to a different voltage level independent of the initialization voltage signal of the anode of the light-emitting diode LD. Therefore, the electrical stress or degradation (such as but not limited to electrical overstress (EOS, also referred to as electrical overload)) of the initialization voltage signal caused by applying the same initialization voltage signal to both the gate electrode of the first transistor T1 and the anode of the light-emitting diode LD can be reduced or avoided.

[0084] The storage capacitor Cst can be configured such that: its first electrode is coupled to the high power supply line ELVDDL, and its second electrode is coupled to the gate electrode of the first transistor T1.

[0085] The light-emitting diode LD can be configured such that: its anode is coupled to the second electrode of the sixth transistor T6, and its cathode is coupled to the low power supply line ELVSSL. The low power supply voltage signal ELVSS applied to the low power supply line ELVSSL can be set to be lower than the high power supply voltage signal ELVDD applied to the high power supply line ELVDDL. The light-emitting diode LD can be an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot light-emitting diode, etc.

[0086] The light-emitting diode LD can have its own capacitance Cel. For example, the cathode of the light-emitting diode LD can form the capacitance Cel through its relationship with its anode, the second electrode of the sixth transistor T6, and the first electrode of the seventh transistor T7.

[0087] The light emission amount of the light-emitting diode LD can be determined according to the current level of the drive current Ids supplied from the high power supply line ELVDDL. The drive current Ids can be the drain-source current Ids of the first transistor T1. The current level of the drive current Ids can be directly affected by the transistors coupled between the high power supply line ELVDDL and the low power supply line ELVSSL. For example, in this embodiment, the transistors coupled between the high power supply line ELVDDL and the low power supply line ELVSSL are the first transistor T1, the fifth transistor T5, and the sixth transistor T6. In this embodiment, the drive current Ids is substantially the same as the drain-source current Ids of the first transistor T1, and thus the same reference numeral is used for it.

[0088] In an embodiment, the transistors T1 to T7 can be P-type (PMOS) transistors. The channels of the transistors T1 to T7 can be formed of polysilicon. The polysilicon transistors can be low-temperature polysilicon (LTPS) transistors. The polysilicon transistors can have a high electron mobility and thus have fast drive characteristics.

[0089] In another embodiment, the transistors T1 to T7 can be N-type (NMOS) transistors. Here, the channels of the transistors T1 to T7 can be formed of an oxide semiconductor. A low-temperature process can be performed on the oxide semiconductor transistors, and the oxide semiconductor transistors can have a lower charge mobility than the polysilicon transistors. Therefore, the amount of leakage current generated in the oxide semiconductor transistors in the off state can be smaller than the amount of leakage current generated in the polysilicon transistors in the off state.

[0090] In still another embodiment, some of the transistors (e.g., T1, T2, T5, T6, and T7) can be P-type transistors. Here, the other transistors (e.g., T3 and T4) can be N-type transistors.

[0091] When a data signal (e.g., Figure 3 DATA) is being supplied because the second transistor T2 is turned on, the third transistor T3 is also turned on, whereby the gate electrode of the first transistor T1 and its second electrode are electrically coupled to each other. Therefore, the gate electrode and the second electrode can have the same electric potential. When the gate and the source of the first transistor T1 (e.g., for Figure 3When the voltage signal difference (e.g., Vgs) between the gate electrode and the first electrode of the P-type transistor is higher than the threshold voltage, the first transistor T1 forms a current path until the voltage difference between its gate electrode and the first electrode decreases to or below the threshold voltage of the first transistor T1, whereby the voltage potential of the gate electrode and the second electrode is charged. That is, when a data signal is supplied to the first electrode of the first transistor T1, the voltages of the gate electrode and the second electrode of the first transistor T1 rise to the voltage difference between the data signal and the threshold voltage. Therefore, the first transistor T1 can be diode-connected, and the threshold voltage can be compensated.

[0092] Figure 4 Shows the drain-source current of the driving transistor in a display device according to an embodiment of the present disclosure. As shown, the achieved drain-source current Ids or driving current Ids depends on the voltage difference between the gate and the source of the driving transistor T1. At least for intermediate gray levels, the achieved drain-source current Ids or driving current Ids can be different based on whether the driving transistor T1 starts in the gate-on bias state according to a curve with a downward-pointing arrow to the right or in the gate-off bias state according to a curve with an upward-pointing arrow to the left.

[0093] The gate-on bias state (hereinafter referred to as the on-bias state) represents the state in which the peak white gray level voltage signal dW is applied to the gate electrode of the first transistor T1, whereby the drain-source current Ids of the first transistor T1 corresponds to the full white gray level. For example, the drain-source current Ids corresponding to the full white gray level can be a current with the highest level.

[0094] The gate-off bias state (hereinafter referred to as the off-bias state) represents the state in which the peak black gray level voltage signal dB is applied to the gate electrode of the driving transistor T1, whereby the drain-source current Ids of the first transistor T1 corresponds to the full black gray level. For example, the drain-source current Ids corresponding to the full black gray level can be a current with the lowest level.

[0095] The peak white gray level voltage signal dW represents the voltage applied to the gate electrode of the first transistor T1 in order to enable the light-emitting diode LD to emit light with the peak white gray level, and the peak black gray level voltage signal dB represents the voltage applied to the gate electrode of the first transistor T1 in order to enable the light-emitting diode LD to emit light with the peak black gray level. For example, when the gray level is represented as an 8-bit (bit, or also called a byte) value, the peak black gray level can correspond to the minimum value "0", and the peak white gray level can correspond to the maximum value "255".

[0096] However, referring to Figure 4, in the P-type first transistor T1, there is a difference between the scan curve in the on-bias state and the scan curve in the off-bias state. This causes the drain-source current Ids of the first transistor T1 for the same gray level to be different depending on whether the starting state is the on-bias state or the off-bias state.

[0097] That is to say, specifically, when presenting an intermediate gray value, based on the gate-source voltage difference of the driving transistor T1, the difference between the scan line in the on-bias state and the scan curve in the off-bias state of the drain-source current characteristics of the driving transistor T1 is called the hysteresis phenomenon (or called the hysteresis phenomenon), and this will cause afterimage.

[0098] In addition, when, for example, a P-type transistor is used as the driving transistor of an organic light-emitting display device, the difference in the drain-source current Ids may cause the driving characteristics of the light-emitting diode LD (the light-emitting diode LD is driven based on the driving current Ids) not to be completely stable, thereby causing a brightness difference.

[0099] Specifically, when the display device 1 driven at a first frequency, which is a relatively high frequency, changes its driving frequency to a second frequency, which is a relatively low frequency, and is thus driven at the second frequency, the afterimage caused by the hysteresis phenomenon will be visible. Therefore, in order to minimize the visibility of the afterimage caused by the hysteresis phenomenon when the display device 1 is driven at the second frequency, the driving transistor T1 can be set to the on-bias state before the start of the light-emitting period.

[0100] In this embodiment, the driving transistor T1 can be set to the on-bias state using a high power supply voltage signal ELVDD. That is to say, by turning on the fifth transistor T5, the high power supply voltage signal ELVDD is applied to the first electrode of the first transistor T1, whereby the first transistor T1 can be set to the on-bias state. At this time, the sixth transistor T6 remains in the off state. Here, it can be achieved by controlling the emission driver 40 to turn on the fifth transistor T5 while maintaining the off state of the sixth transistor T6. Hereinafter, the emission driver 40 will be described in more detail.

[0101] Figure 5 Shows the relationship between the emission driver and the display according to an embodiment of the present disclosure. Refer to Figure 5 , the emission driver 40 may include a plurality of stage circuits ST1 to STk and STk + 1 to STn. Here, k may be a natural number greater than 1 and less than n. The plurality of stage circuits ST1 to STn may correspond to the pixel rows PXL1 to PXLn of the display 50.

[0102] Each of the stage circuits ST1 to STk and STk+1 to STn may be coupled to one end of the corresponding one of the emission lines EL1 to ELk and ELk+1 to ELn, and may supply an emission signal to all pixels in each of the pixel rows PXL1 to PXLn corresponding to the respective emission lines EL1 to ELk and ELk+1 to ELn.

[0103] The stage circuits ST1 to STk and STk+1 to STn may output a first output signal corresponding to a first voltage signal ( Figure 7 VGH in) or a second voltage signal ( Figure 7 VGL in) in response to the clock signals CLK1 and CLK2 supplied from the timing controller 10.

[0104] The stage circuits ST1 to STk and STk+1 to STn may output a first output signal and a second output signal in response to a first control signal and a second control signal in each of the stage circuits ST1 to STk and STk+1 to STn, and the second output signal corresponds to a first intermediate voltage signal VGM1 or a second intermediate voltage signal VGM2.

[0105] The first intermediate voltage signal VGM1 may be supplied to the first stage circuits ST1 to the k-th stage circuits STk corresponding to the first pixel row PXL1 to the k-th pixel row PXLk among the stage circuits ST1 to STk and STk+1 to STn. The second intermediate voltage signal VGM2 may be supplied to the (k + 1)-th stage circuits STk+1 to the n-th stage circuits STn corresponding to the (k + 1)-th pixel row PXLk+1 to the n-th pixel row PXLn among the stage circuits ST1 to STk and STk+1 to STn.

[0106] In the display 50, a first pixel group 50a including the first pixel row PXL1 to the k-th pixel row PXLk and a second pixel group 50b including the (k + 1)-th pixel row PXLk+1 to the n-th pixel row PXLn may be defined. That is, the first pixel group 50a and the second pixel group 50b may be distinguished from each other in such a way that the first pixel group 50a is supplied with the second output signal corresponding to the first intermediate voltage signal VGM1 from the emission driver 40 through the first emission lines EL1 to the k-th emission line ELk, and the second pixel group 50b is supplied with the second output signal corresponding to the second intermediate voltage signal VGM2 from the emission driver 40 through the (k + 1)-th emission line ELk+1 to the n-th emission line ELn.

[0107] In an embodiment, a first intermediate voltage signal line that supplies a first intermediate voltage signal VGM1 and a second intermediate voltage signal line that supplies a second intermediate voltage signal VGM2 may be insulated from each other and cross each other in a region adjacent to the (k + 1)-th stage circuit STk+1 to the n-th stage circuit STn. In a region adjacent to the first stage circuit ST1 to the k-th stage circuit STk, the first intermediate voltage signal line and the second intermediate voltage signal line do not need to cross each other, but they are not limited thereto.

[0108] In an embodiment, k and n may have a relationship of k = [n / 2]. Here, '[x]' is the Gaussian symbol, which indicates the largest integer not greater than x. However, in some embodiments, when n is odd, the relationship may be k = [n / 2] + 1.

[0109] Figure 6 A transmission driver according to an embodiment of the present disclosure is shown. Figure 7 Further shown is Figure 6 the stage circuit.

[0110] In Figure 7 , the first stage circuit ST1 and the second stage circuit ST2 are shown. Since Figure 6 the other stage circuits in Figure 7 may be constructed as shown, repeated descriptions will be omitted.

[0111] Referring to Figure 6 and Figure 7 , each of the stage circuits ST1 to STk and STk+1 to STn includes a carry controller 111 and an output buffer 121 or 122.

[0112] The carry controller 111 of each of the stage circuits ST1 to STk and STk+1 to STn may start operating by receiving a start signal FLM or a first output signal OS1 of the previous stage circuit. The carry controller 111 of each of the stage circuits ST1 to STk and STk+1 to STn may output a first output signal OS1.

[0113] For example, the carry controller 111 included in the first stage circuit ST1 may be supplied with the start signal FLM, and the carry controllers 111 included in the other stage circuits ST2 to STn may be supplied with the first output signal OS1 output from the carry controller 111 included in the previous stage circuit.

[0114] The first voltage signal VGH and the second voltage signal VGL can be supplied to the carry controller 111 in each of the stage circuits ST1 to STk and STk+1 to STn. The carry controller 111 in each of the stage circuits ST1 to STk and STk+1 to STn can select the first voltage signal VGH or the second voltage signal VGL as the first output signal OS1 based on the first control signal applied to the first control line CL1 and the second control signal applied to the second control line CL2. The first voltage signal VGH can have a first level V1, and the second voltage signal VGL can have a second level V2 lower than the first level V1. According to the above operations, the carry controllers 111 of sequential rows can sequentially output the first output signal OS1.

[0115] Each output buffer 121 or 122 can be coupled to the first intermediate voltage signal line or the second intermediate voltage signal line respectively. The first intermediate voltage signal VGM1 is supplied through the first intermediate voltage signal line, and the second intermediate voltage signal VGM2 is supplied through the second intermediate voltage signal line. The first intermediate voltage signal VGM1 and the second intermediate voltage signal VGM2 can have the first level V1 and a third level V3 between the first level V1 and the second level V2. Each output buffer 121 or 122 can select the second voltage signal VGL or the intermediate voltage signal VGM1 or VGM2, generate the second output signal OS2 as the emission signal, and output the generated emission signal to the corresponding one of the emission lines EL1 to ELn. When each output buffer 121 or 122 selects the second voltage signal VGL, the voltage level of the generated second output signal OS2 as the emission signal can be the second level V2; when each output buffer 121 or 122 selects the intermediate voltage signal VGM1 or VGM2, the voltage level of the generated second output signal OS2 as the emission signal can be the first level V1 or the third level V3. Therefore, each output buffer 121 or 122 can output the second output signal OS2 having the first level V1, the second level V2, or the third level V3.

[0116] Based on the first control signal and the second control signal, each output buffer 121 or 122 can respectively select the second voltage signal VGL or the intermediate voltage signal VGM1 or VGM2 as the second output signal OS2. This selection can be controlled by the carry controller 111. The output buffer 121 or 122 can be classified as the output buffer 121 coupled to the first intermediate voltage signal line or the output buffer 122 coupled to the second intermediate voltage signal line.

[0117] The output buffer 121 or 122 is coupled to the carry controller 111 and the control lines CL1 and CL2, and the on / off of the transistors M13 and M14 in the output buffer 121 or 122 can be controlled by the carry controller 111.

[0118] Each of the stage circuits ST1 to STk and STk+1 to STn may include a plurality of transistors M1 to M14. Hereinafter, a description will be made on the assumption that the transistors M1 to M14 in each stage circuit are P-type (e.g., PMOS) transistors, but those skilled in the art can construct the stage circuits by replacing some or all of the transistors M1 to M14 with N-type (e.g., NMOS) transistors and the like.

[0119] Hereinafter, a description will be made based on the first stage circuit ST1. The carry controller 111 may include a first transistor M1 to a twelfth transistor M12 and a first capacitor C1 to a third capacitor C3. The output buffer 121 may include a thirteenth transistor M13 and a fourteenth transistor M14.

[0120] A first electrode of the first transistor M1 may be supplied with a start signal FLM, a gate electrode thereof may be supplied with a first clock signal CLK1, and a second electrode thereof may be coupled to a first electrode of the third transistor M3, a first electrode of the twelfth transistor M12, a gate electrode of the fourth transistor M4, and a gate electrode of the eighth transistor M8.

[0121] A first electrode of the second transistor M2 may be coupled to a second electrode of the third transistor M3, a second electrode thereof may be coupled to a second electrode of the eighth transistor M8 and be supplied with a first voltage signal VGH, and a gate electrode thereof may be coupled to a second electrode of the fourth transistor M4 and a first electrode of the eleventh transistor M11.

[0122] A gate electrode of the third transistor M3 may be supplied with a second clock signal CLK2, a first electrode thereof may be coupled to a second electrode of the first transistor M1, and a second electrode thereof may be coupled to a first electrode of the second transistor M2.

[0123] The fourth transistor M4 may be in a form in which a plurality of transistors are connected in series. A first electrode of the transistors located on one side among the fourth transistors M4 may be supplied with the first clock signal CLK1, a second electrode of the transistors located on the other side among the fourth transistors M4 may be coupled to a gate electrode of the second transistor M2, and a gate electrode of the fourth transistor M4 may be coupled to a second electrode of the first transistor M1.

[0124] The first electrode of the fifth transistor M5 may be supplied with a second voltage signal VGL, its second electrode may be coupled to the gate electrode of the second transistor M2 and the first electrode of the eleventh transistor M11, and its gate electrode may be supplied with a first clock signal CLK1.

[0125] The first electrode of the sixth transistor M6 may be coupled to the second electrode of the seventh transistor M7, its second electrode may be coupled to the gate electrode of the ninth transistor M9 and the gate electrode of the thirteenth transistor M13, and its gate electrode may be supplied with a second clock signal CLK2.

[0126] The first electrode of the seventh transistor M7 may be supplied with a second clock signal CLK2, its second electrode may be coupled to the first electrode of the sixth transistor M6, and its gate electrode may be coupled to the second electrode of the eleventh transistor M11.

[0127] The first electrode of the eighth transistor M8 may be coupled to the second electrode of the sixth transistor M6, its second electrode may be supplied with a first voltage signal VGH, and its gate electrode may be coupled to the second electrode of the first transistor M1 and the first electrode of the twelfth transistor M12.

[0128] The first electrode of the ninth transistor M9 may be coupled to a carry output terminal configured to supply a first output signal OS1, its second electrode may be supplied with a first voltage signal VGH, and its gate electrode may be coupled to the second electrode of the sixth transistor M6.

[0129] The first electrode of the tenth transistor M10 may be supplied with a second voltage signal VGL, its second electrode may be coupled to the carry output terminal configured to supply a first output signal OS1, and its gate electrode may be coupled to the second electrode of the twelfth transistor M12.

[0130] The carry output terminal mentioned in the descriptions of the ninth transistor M9 and the tenth transistor M10 may be coupled to the first electrode of the first transistor M1 in a subsequent stage circuit (e.g., the second stage circuit ST2). When the ninth transistor M9 is turned on by a first control signal and the tenth transistor M10 is turned off by a second control signal, the carry controller 111 may generate and output a first output signal OS1 at a first level V1 based on the first voltage signal VGH. In addition, when the ninth transistor M9 is turned off by the first control signal and the tenth transistor M10 is turned on by the second control signal, the carry controller 111 may generate and output a first output signal OS1 at a second level V2 based on the second voltage signal VGL.

[0131] The first electrode of the eleventh transistor M11 may be coupled to the second electrode of the fourth transistor M4 and the second electrode of the fifth transistor M5, its second electrode may be coupled to the gate electrode of the seventh transistor M7, and its gate electrode may be supplied with a second voltage signal VGL.

[0132] The first electrode of the twelfth transistor M12 may be coupled to the second electrode of the first transistor M1, its second electrode may be coupled to the gate electrode of the tenth transistor M10 and the gate electrode of the fourteenth transistor M14, and its gate electrode may be supplied with a second voltage signal VGL.

[0133] The first capacitor C1 may electrically couple a node supplied with a first voltage signal VGH to the second electrode of the sixth transistor M6, the gate electrode of the ninth transistor M9, and the gate electrode of the thirteenth transistor M13.

[0134] The second capacitor C2 may electrically couple the gate electrode of the seventh transistor M7 and the second electrode of the eleventh transistor M11 to the first electrode of the sixth transistor M6 and the second electrode of the seventh transistor M7.

[0135] The third capacitor C3 may electrically couple a node supplied with a second clock signal CLK2 to the second electrode of the twelfth transistor M12, the gate electrode of the tenth transistor M10, and the gate electrode of the fourteenth transistor M14.

[0136] The first electrode of the thirteenth transistor M13 may be coupled to the emission line EL1, its second electrode may be supplied with a first intermediate voltage signal VGM1, and its gate electrode may be coupled to the second electrode of the sixth transistor M6. The gate electrode of the thirteenth transistor M13 may be coupled to a first control line CL1 extending from the carry controller 111. The first control line CL1 may be electrically coupled to the same node to which the second electrode of the sixth transistor M6 is coupled.

[0137] The first electrode of the fourteenth transistor M14 may be supplied with a second voltage signal VGL, its second electrode may be coupled to the emission line EL1, and its gate electrode may be coupled to the second electrode of the twelfth transistor M12. The gate electrode of the fourteenth transistor M14 may be coupled to a second control line CL2 extending from the carry controller 111. The second control line CL2 may be electrically coupled to the same node to which the second electrode of the twelfth transistor M12 is coupled.

[0138] When the thirteenth transistor M13 is turned off by the first control signal and the fourteenth transistor M14 is turned on by the second control signal, the output buffer 121 can generate and output a second output signal OS2 of the second level V2 as a transmission signal based on the second voltage signal VGL. In addition, when the thirteenth transistor M13 is turned on by the first control signal and the fourteenth transistor M14 is turned off by the second control signal, the output buffer 121 can generate and output a second output signal OS2 of the first level V1 or the third level V3 as a transmission signal based on the first intermediate voltage signal VGM1.

[0139] The second electrode of the thirteenth transistor M13 in each of the (k + 1)-th stage circuit STk+1 to the n-th stage circuit STn can be supplied with the second intermediate voltage signal VGM2 instead of the first intermediate voltage signal VGM1, but is otherwise similar to the above.

[0140] The second stage circuit ST2 can also be configured such that a terminal corresponding to the terminal supplied with the first clock signal CLK1 in the first stage circuit ST1 is supplied with the second clock signal CLK2, and a terminal corresponding to the terminal supplied with the second clock signal CLK2 in the first stage circuit ST1 is supplied with the first clock signal CLK1.

[0141] That is, terminals in the even-stage circuits ST2, ST4,... corresponding to the terminals controlled by the first clock signal CLK1 in the odd-stage circuits ST1, ST3,... can be controlled by the second clock signal CLK2, and terminals in the even-stage circuits ST2, ST4,... corresponding to the terminals controlled by the second clock signal CLK2 in the odd-stage circuits ST1, ST3,... can be controlled by the first clock signal CLK1.

[0142] The first clock signal CLK1 and the second clock signal CLK2 can have the same frequency. That is, the first clock signal CLK1 and the second clock signal CLK2 have the same period. The second clock signal CLK2 is a signal obtained by shifting the first clock signal CLK1 by half of the period of the first clock signal CLK1 or 180 degrees in phase.

[0143] The start signal FLM can be supplied only to the first stage circuit ST1. When the first clock signal CLK1 changes from a high level to a low level, the start signal FLM can change from a low level to a high level. During some time period after the start signal FLM changes from a low level to a high level, the start signal FLM remains at a high level. That is, the start signal FLM is activated when the first clock signal CLK1 changes from a high level to a low level and remains in an activated state during some time period.

[0144] Hereinafter, the high level of each signal is defined as a first level V1, and the low level lower than the high level is defined as a second level V2. In addition, the second voltage signal VGL may have the second level V2, and the first voltage signal VGH may have the first level V1. Here, the first intermediate voltage signal VGM1 and the second intermediate voltage signal VGM2 may each have a voltage level between the voltage level of the second voltage signal VGL and the voltage level of the first voltage signal VGH. In an embodiment, the first intermediate voltage signal VGM1 and the second intermediate voltage signal VGM2 may each have the first level V1 or a third level V3 between the first level V1 and the second level V2. For example, the first intermediate voltage signal VGM1 and the second intermediate voltage signal VGM2 may each have the first level V1 in a first period (e.g., a data programming period) of a frame period, and may each have the third level V3 in a second period (e.g., a holding period) of a frame period. Here, when each output buffer 121 or 122 generates a second output signal OS2 corresponding to the voltage level of the intermediate voltage signal VGM1 or VGM2, each output buffer 121 or 122 may output the second output signal OS2 of the first level V1 as a transmission signal to a corresponding one of the transmission lines EL1 to ELn in a first period of a frame period, and may output the second output signal OS2 of the third level V3 as a transmission signal to a corresponding one of the transmission lines EL1 to ELn in a second period of a frame period.

[0145] In an embodiment, the first level V1 may be in the range of about 14.5V to about 15.5V, the second level V2 may be in the range of about 1.5V to about 2.5V, and the third level V3 may be in the range of about 7.5V to about 8.5V. However, the embodiments are not limited to the above voltage level ranges.

[0146] In an embodiment, the voltage level of the first intermediate voltage signal VGM1 may be the same as the voltage level of the second intermediate voltage signal VGM2, but the voltage levels are not limited thereto.

[0147] The carry controller 111 of each of the stage circuits ST1 to STk and STk+1 to STn can control the transistors M13 and M14 of the output buffer 121 or 122, so as to selectively output the second voltage signal VGL or the intermediate voltage signal VGM1 or VGM2 as the second output signal OS2. The output buffer 121 or 122 can be supplied with a first control signal from the carry controller 111 through the first control line CL1, and supplied with a second control signal through the second control line CL2. For example, each of the stage circuits ST1 to STk and STk+1 to STn turns off the thirteenth transistor M13 and turns on the fourteenth transistor M14, so as to output a signal corresponding to the voltage level of the second voltage signal VGL to the corresponding one of the emission lines EL1 to ELn as the second output signal OS2. In addition, each of the stage circuits ST1 to STk and STk+1 to STn turns on the thirteenth transistor M13 and turns off the fourteenth transistor M14, so as to output a signal corresponding to the voltage level of the first intermediate voltage signal VGM1 or the second intermediate voltage signal VGM2 to the corresponding one of the emission lines EL1 to ELn as the second output signal OS2.

[0148] Figure 8 and Figure 9 is a timing diagram showing a method of driving a display device according to an embodiment of the present disclosure. Figure 8 shows the case of driving the display device 1 at a relatively high frequency, i.e., the first frequency, Figure 9 shows the case of driving the display device 1 at a relatively low frequency, i.e., the second frequency.

[0149] For example, the first frequency can be the highest frequency within the range of frequencies capable of driving the display device 1.

[0150] Referring to Figure 8 , when the emission signals EM[1] to EM[n] have a high level (e.g., 14.5V to 15.5V) in the pixel rows PXL1 to PXLn, the fifth transistor T5 and the sixth transistor T6 of each pixel PXij can remain in the off state; when the emission signals EM[1] to EM[n] have a low level (e.g., 1.5V to 2.5V), the fifth transistor T5 and the sixth transistor T6 can remain in the on state. Therefore, when the emission signals EM[1] to EM[n] have a high level in the pixel rows PXL1 to PXLn, this period can be defined as a non-emission period; when the emission signals EM[1] to EM[n] have a low level, this period can be defined as an emission period.

[0151] In an embodiment, when driving the display device 1 at a first frequency, a frame period may include only a data programming period. The data programming period may be configured such that a threshold voltage signal of the driving transistor T1 is compensated, an anode (i.e., an anode of the light-emitting diode LD) is initialized, and a data signal is written during a non-emission period, and such that the light-emitting diode LD can emit light during an emission period. For example, during the non-emission period, scan signals GW[1] to GW[n] having a low level capable of turning on the second transistor T2 may be supplied to the pixel PXij.

[0152] In the operation of the embodiment as Figure 8 shown, when driving the display device 1 at a first frequency, the emission driver 40 may be controlled to output emission signals EM[1] to EM[n] having only a first level V1 and a second level V2. For example, the emission driver 40 may output emission signals EM[1] to EM[n] having the first level V1 and the second level V2 during one frame period. Here, a holding period is not required.

[0153] In the operation of the embodiment as Figure 9 shown, when driving the display device 1 at a second frequency, a frame period may include a data programming period and a holding period. In addition, at least a part of the frame period may include a porch period. For example, for each of the pixel rows PXL1 to PXLn, the porch period may be included in the holding period. A period from a moment when a non-emission period in the data programming period of the nth pixel row PXLn ends to a moment when a non-emission period of the first pixel row PXL1 starts may be defined as the porch period. The porch period is a period in which pixels arranged in parallel in the horizontal direction are synchronized because the vertical synchronization signal Vsync is turned on when driving at the second frequency.

[0154] In an embodiment, a data programming period of each of the pixel rows PXL1 to PXLn may include a period for compensating a threshold voltage signal of the driving transistor T1, a period for initializing an anode, and a period for writing a data signal during a non-emission period, and may include a period in which the light-emitting diode LD emits light during an emission period.

[0155] In an embodiment, the holding period of each of pixel rows PXL1 to PXLn may include a period in which the driving transistor T1 is set to an on-bias state. During the period in which the driving transistor T1 is set to the on-bias state, the first-stage circuit ST1 to the k-th stage circuit STk may output emission signals EM[1] to EM[k] of a third level V3 to emission lines EL1 to ELk. Similarly, the (k + 1)-th stage circuit STk+1 to the n-th stage circuit STn may output emission signals EM[k + 1] to EM[n] of the third level V3 to emission lines ELk+1 to ELn.

[0156] When the emission signals of the third level V3 are supplied to the gate electrodes of the fifth transistor T5 and the sixth transistor T6 of each pixel PXij, the sixth transistor T6 may remain in the off state, and the fifth transistor T5 may remain in the on state.

[0157] While the sixth transistor T6 remains in the off state and the fifth transistor T5 remains in the on state, a high power supply voltage signal ELVDD may be supplied to the first electrode of the first transistor T1. Accordingly, the first transistor T1 may be set to the on-bias state.

[0158] In an embodiment, the holding period may include an emission period after the period in which the driving transistor T1 is set to the on-bias state. Each of the stage circuits ST1 to STk and STk+1 to STn may output an emission signal of a second level V2 to the emission line after the period in which the driving transistor T1 is set to the on-bias state. When the emission signal of the second level V2 is supplied to the gate electrodes of the fifth transistor T5 and the sixth transistor T6 of each pixel PXij, the fifth transistor T5 and the sixth transistor T6 may remain in the on state, and the light-emitting diode LD may emit light.

[0159] As described above, in this embodiment, by supplying the emission signal of the third level V3 to a single emission line, the first emission transistor T5 in the pixel PXij may be turned on and the second emission transistor T6 may be turned off, enabling the driving transistor T1 to be set to the on-bias state.

[0160] Next, a display device according to another embodiment will be described. Hereinafter, the description of the same components in Figures 1 to 9 will be omitted, and the same or similar reference numerals will be used for them.

[0161] Figure 10 shows the relationship between the emission driver and the display in a display device according to still another embodiment of the present disclosure. Referring to Figure 10 , this embodiment is different from the embodiment of Figure 5 in that there are a plurality of emission drivers 40 and 41.

[0162] In an embodiment, the first emission driver 40 may be disposed on one side of the display 50, and the second emission driver 41 may be disposed on the other side of the display 50. Each of the first emission driver 40 and the second emission driver 41 may include a first-stage circuit to an n-stage circuit ST1 to STk and STk+1 to STn. Each of the stage circuits ST1 to STk and STk+1 to STn in the first emission driver 40 and its corresponding stage circuit in the second emission driver 41 may supply the same emission signal to the same pixel row among the pixel rows PXL1 to PXLn. That is, each of the emission lines EL1 to ELn coupled to the corresponding stage circuits among the stage circuits ST1 to STk and STk+1 to STn incorporated in the first emission driver 40 and the second emission driver 41 may be coupled to the same pixel row among the pixel rows PXL1 to PXLn, and the emission lines coupled to the same pixel row may be electrically coupled to each other.

[0163] Each of the first emission driver 40 and the second emission driver 41 performs the same function as the Figure 5 emission driver 40, and thus a repeated description will be omitted. The first emission driver 40 and the second emission driver 41 are respectively disposed on one side and the other side of the display 50, whereby the emission signal can be simultaneously supplied to the pixels in each of the pixel rows PXL1 to PXLn.

[0164] Figure 11 The relationship between the emission driver and the display in a display device according to still another embodiment of the present disclosure is shown. Referring to Figure 11 this, the difference between this embodiment and the Figure 5 embodiment is that the stage circuits ST1 to STk and STk+1 to STn in the emission driver 40_1 are coupled in a staggered manner. In this embodiment, the description will be made on the assumption that n is even, but the embodiment is not limited thereto.

[0165] In the embodiment, the first output signal of the first-stage circuit ST1 may be supplied to the third-stage circuit ST3. In addition, although not clearly shown, the first output signal of the third-stage circuit ST3 may be supplied to the fifth-stage circuit ST5. In this way, the first output signal is transmitted to the odd-stage circuits, whereby the first output signal can finally reach the (n-1)th-stage circuit STn-1, which is the last odd-stage circuit.

[0166] Then, the first output signal of the (n-1)-th stage circuit STn-1 can be supplied to the second stage circuit ST2. The first output signal of the second stage circuit ST2 can be supplied to the fourth stage circuit ST4. In this way, the first output signal is transmitted to the even-stage circuits, and the first output signal can finally reach the n-th stage circuit STn which is the last even-stage circuit.

[0167] Since the emission driver 40_1 operates in an interleaved manner, the capacitive coupling between adjacent pixel rows PXL1 to PXLn can be reduced, thereby reducing the power consumed by the display device.

[0168] Figure 12 The relationship between the emission driver and the display in a display device according to another embodiment of the present disclosure is shown. Referring to Figure 12 , this embodiment is different from the embodiment of Figure 5 in that the first intermediate voltage signal line and the second intermediate voltage signal line coupled to the emission driver 40_2 do not cross each other.

[0169] In the embodiment, the first intermediate voltage signal line through which the first intermediate voltage signal VGM1_1 is supplied extends from one side of the display device, so as to be coupled to the first stage circuit ST1 to the k-th stage circuit STk. The second intermediate voltage signal line through which the second intermediate voltage signal VGM2_1 is supplied extends from the other side of the display device, so as to be coupled to the (k + 1)-th stage circuit STk+1 to the n-th stage circuit STn. That is, the direction in which the first intermediate voltage signal line extends and the direction in which the second intermediate voltage signal line extends can be opposite to each other.

[0170] Figure 13 The stage circuits in an emission driver according to another embodiment of the present disclosure are shown. Referring to Figure 13 , the first stage circuit ST1_1 according to this embodiment is different from the embodiment of Figure 7 in that the equivalent circuit of the carry controller 111_1 is different.

[0171] The first electrode of the first transistor M1 can be supplied with the start signal FLM, its gate electrode can be supplied with the second clock signal CLK2, and its second electrode can be coupled to the first electrode of the twelfth transistor M12, the gate electrodes of the fourth transistor M4, the eighth transistor M8, and the tenth transistor M10.

[0172] The first electrode of the second transistor M2 can be coupled to the second electrode of the third transistor M3, its second electrode can be coupled to the second electrode of the eighth transistor M8 and be supplied with the first voltage signal VGH, and its gate electrode can be coupled to the second electrode of the fourth transistor M4 and the first electrode of the eleventh transistor M11.

[0173] The gate electrode of the third transistor M3 may be coupled to the second electrode of the twelfth transistor M12, whose first electrode may be supplied with the first clock signal CLK1, and whose second electrode may be coupled to the first electrode of the second transistor M2.

[0174] The fourth transistor M4 may be in the form in which a plurality of transistors are coupled in series. The first electrode of the transistors located on one side among the fourth transistors M4 may be supplied with the second clock signal CLK2, the second electrode of the transistors located on the other side among the fourth transistors M4 may be coupled to the gate electrode of the second transistor M2, and the gate electrode of the fourth transistor M4 may be coupled to the second electrode of the first transistor M1.

[0175] The first electrode of the fifth transistor M5 may be supplied with the second voltage signal VGL, its second electrode may be coupled to the gate electrode of the second transistor M2 and the first electrode of the eleventh transistor M11, and its gate electrode may be supplied with the second clock signal CLK2.

[0176] The first electrode of the sixth transistor M6 may be coupled to the second electrode of the seventh transistor M7, its second electrode may be coupled to the gate electrode of the ninth transistor M9 and the gate electrode of the thirteenth transistor M13 and the first electrode of the eighth transistor M8, and its gate electrode may be supplied with the first clock signal CLK1.

[0177] The first electrode of the seventh transistor M7 may be supplied with the first clock signal CLK1, its second electrode may be coupled to the first electrode of the sixth transistor M6, and its gate electrode may be coupled to the second electrode of the eleventh transistor M11.

[0178] The first electrode of the eighth transistor M8 may be coupled to the second electrode of the sixth transistor M6 and the gate electrode of the ninth transistor M9 and the gate electrode of the thirteenth transistor M13, its second electrode may be supplied with the first voltage signal VGH, and its gate electrode may be coupled to the second electrode of the first transistor M1 and the first electrode of the twelfth transistor M12.

[0179] The first electrode of the ninth transistor M9 may be coupled to the carry output terminal configured to supply the first output signal OS1, its second electrode may be supplied with the first voltage signal VGH, and its gate electrode may be coupled to the second electrode of the sixth transistor M6 and the first electrode of the eighth transistor M8.

[0180] The first electrode of the tenth transistor M10 may be supplied with the second voltage signal VGL, its second electrode may be coupled to the carry output terminal configured to supply the first output signal OS1, and its gate electrode may be coupled to the second electrode of the twelfth transistor M12.

[0181] The carry output terminal mentioned in the description of the ninth transistor M9 and the tenth transistor M10 may be coupled to the first electrode of the first transistor M1 in a subsequent stage circuit (e.g., the second stage circuit ST2).

[0182] The first electrode of the eleventh transistor M11 may be coupled to the second electrodes of the fourth transistor M4 and the fifth transistor M5, its second electrode may be coupled to the gate electrode of the seventh transistor M7, and its gate electrode may be supplied with the second voltage signal VGL.

[0183] The first electrode of the twelfth transistor M12 may be coupled to the second electrode of the first transistor M1, its second electrode may be coupled to the gate electrodes of the tenth transistor M10 and the fourteenth transistor M14, and its gate electrode may be supplied with the second voltage signal VGL.

[0184] The first capacitor C1 may electrically couple the node supplied with the first voltage signal VGH to the second electrode of the sixth transistor M6, the gate electrode of the ninth transistor M9, and the gate electrode of the thirteenth transistor M13.

[0185] The second capacitor C2 may electrically couple the gate electrode of the seventh transistor M7 and the second electrode of the eleventh transistor M11 to the first electrode of the sixth transistor M6 and the second electrode of the seventh transistor M7.

[0186] The third capacitor C3 may electrically couple the second electrode of the third transistor M3 and the first electrode of the second transistor M2 to the gate electrodes of the tenth transistor M10 and the fourteenth transistor M14.

[0187] However, the circuit of the carry controller 111_1 is not limited to this example, and various known circuits may be applied.

[0188] Figure 14 A display device according to another embodiment of the present disclosure is shown. Referring to Figure 14 , the data driver 21 according to the present embodiment is different from the embodiment of Figure 2 in that the timing controller is included in the data driver 21.

[0189] In the display device 2, the data driver 20 and the timing controller 10 described in the embodiment of Figure 2 may be integrated. In an embodiment, the data driver 21 may include a timing controller. For example, the data driver 21 may be provided in the form of a timing controller embedded driver integrated circuit (TED).

[0190] The TED may be in a form in which the timing controller 10, the data driver 20, the scan driver 30, and the emission driver 40 integrated therein are integrated. Figure 2 of

[0191] According to an embodiment of the present disclosure, although pixels in a display device are coupled to a single emission line, a driving transistor can be set to an on-bias state using a power supply voltage.

[0192] In addition, although the display device is driven at multiple frequencies, the visibility of afterimages can be minimized.

[0193] The effects that can be obtained from the embodiments are not limited to the above effects, and various effects are included in this description.

[0194] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, those of ordinary skill in the relevant art will understand that the present disclosure can be implemented in other specific forms without changing the technical scope or spirit of the present disclosure. Therefore, it should be noted that the foregoing embodiments are illustrative in all respects and should not be construed as limiting the present disclosure.

Claims

1. A display device, the display device comprising: a plurality of pixels, including a first pixel row to a k-th pixel row and a (k + 1)-th pixel row to an n-th pixel row, wherein each pixel of the plurality of pixels includes: a driving transistor including a first electrode, a second electrode, and a first gate electrode; a first emission transistor including a third electrode, a fourth electrode, and a second gate electrode, the third electrode being coupled to the first electrode of the driving transistor; and a second emission transistor including a fifth electrode, a sixth electrode, and a third gate electrode, the fifth electrode being coupled to the second electrode of the driving transistor, wherein both the second gate electrode and the third gate electrode are coupled to an emission line, wherein, based on an emission signal having a first level, a second level, or a third level between the first level and the second level supplied from the emission line, the first emission transistor is turned on while the second emission transistor is turned off, wherein when the emission signal of the first level is supplied to the pixel, the first emission transistor and the second emission transistor are turned off; when the emission signal of the second level is supplied to the pixel, the first emission transistor and the second emission transistor are turned on; and when the emission signal of the third level is supplied to the pixel, the first emission transistor is turned on while the second emission transistor is turned off, and wherein during a period in which the emission signal of the first level is supplied to at least some of the (k + 1)-th pixel row to the n-th pixel row, the emission signal of the third level is supplied to at least some of the first pixel row to the k-th pixel row, k and n are natural numbers, and k is greater than 1 and less than n.

2. The display device according to claim 1, the display device further comprising: an emission driver that supplies the emission signal to both the second gate electrode and the third gate electrode through the emission line, and wherein the emission driver supplies the emission signal to the pixel through the emission line.

3. The display device according to claim 2, wherein, When the emission signal of the third level is supplied to the pixel, the driving transistor is set to an on-bias state.

4. The display device according to claim 1, wherein, Each pixel of the plurality of pixels further includes a light-emitting diode, and wherein: the sixth electrode is coupled to the anode of the light-emitting diode, the fourth electrode is coupled to a first power supply line, and a first power supply voltage signal is supplied through the first power supply line, and the cathode of the light-emitting diode is coupled to a second power supply line, and a second power supply voltage signal having a level lower than the first power supply voltage signal is supplied through the second power supply line.

5. An emission driver, the emission driver comprising: a plurality of stage circuits, each stage circuit of the plurality of stage circuits including: a carry controller that generates a first output signal having a first level or a second level based on a first control signal and a second control signal; and An output buffer is coupled to a first control line and a second control line, and generates a second output signal having one of a first level, a second level, and a third level based on a first control signal supplied from the first control line and a second control signal supplied from the second control line, the third level being between the first level and the second level. Wherein, when the second output signal of the first level is supplied to the pixel, the first emission transistor and the second emission transistor are turned off; when the second output signal of the second level is supplied to the pixel, the first emission transistor and the second emission transistor are turned on; and when the second output signal of the third level is supplied to the pixel, the first emission transistor is turned on and the second emission transistor is turned off, and wherein a plurality of pixel rows include a first pixel row to a k-th pixel row and a (k + 1)-th pixel row to an n-th pixel row, and during a period in which the second output signal of the first level is supplied to at least some of the pixel rows from the (k + 1)-th pixel row to the n-th pixel row, the second output signal of the third level is supplied to at least some of the pixel rows from the first pixel row to the k-th pixel row, k and n are natural numbers, and k is greater than 1 and less than n.

6. The emission driver according to claim 5, wherein, The output buffer is coupled to an intermediate voltage signal line, and supplies one of a voltage signal of the first level and a voltage signal of the third level through the intermediate voltage signal line.

7. The emission driver according to claim 6, wherein: In a first period of a frame period, the output buffer generates a second output signal having the first level based on the first control signal, and In a second period of the frame period, the output buffer generates a second output signal having the third level based on the first control signal.

8. A display device, the display device comprising: A display including a plurality of pixel rows, each pixel row of the plurality of pixel rows being defined by a plurality of pixels coupled to the same emission line; A scan driver configured to supply a scan signal to each of the plurality of pixels; A data driver configured to supply a data signal to each of the plurality of pixels; And An emission driver configured to supply an emission signal to each of the plurality of pixel rows through the emission line, wherein the emission signal has a first level, a second level, or a third level, the third level being between the first level and the second level, wherein the first level is higher than the second level, wherein, when the emission signal of the first level is supplied to the pixel, the first emission transistor and the second emission transistor are turned off; when the emission signal of the second level is supplied to the pixel, the first emission transistor and the second emission transistor are turned on; and when the emission signal of the third level is supplied to the pixel, the first emission transistor is turned on and the second emission transistor is turned off, wherein the plurality of pixel rows include a first pixel row to a k-th pixel row and a (k + 1)-th pixel row to an n-th pixel row, and During a period in which the emission signal of the first level is supplied to at least some of the pixel rows from the (k + 1)-th pixel row to the n-th pixel row, the emission signal of the third level is supplied to at least some of the pixel rows from the first pixel row to the k-th pixel row, where k and n are natural numbers, and k is greater than 1 and less than n.

9. The display device according to claim 8, wherein, The emission driver includes a pair of emission drivers respectively disposed on opposite sides of the display.

10. The display device according to claim 8, wherein: The first pixel row to the k-th pixel row are coupled to a first intermediate voltage signal line, and the voltage of the third level is supplied through the first intermediate voltage signal line, and The (k + 1)-th pixel row to the n-th pixel row are coupled to a second intermediate voltage signal line, and the voltage of the third level is supplied through the second intermediate voltage signal line.

11. The display device according to claim 10, wherein, The first intermediate voltage signal line and the second intermediate voltage signal line are insulated from each other and cross each other.

12. The display device according to claim 8, wherein, The frame period includes: A data programming period in which the data signal is written and each of the plurality of pixels emits light; and A holding period in which the emission signal of the third level is supplied to each of the plurality of pixels, and each of the plurality of pixels emits light.

13. The display device according to claim 12, wherein, Each of the plurality of pixels is driven at a first frequency and a second frequency, and the second frequency is lower than the first frequency, and During the period in which the second frequency is used for driving, the frame period further includes an edge period in which the respective pixels arranged in parallel in the horizontal direction are synchronized.

Images