A frequency synthesizer, a frequency synthesis method, an electronic device, and a storage medium

Abstract

Embodiments of the present application relate to the field of communication, and disclose a frequency synthesizer, a frequency synthesis method, an electronic device and a storage medium. In the present application, the frequency synthesizer comprises a reference crystal oscillator, an integer frequency synthesizer circuit and a fractional frequency synthesizer circuit; the reference crystal oscillator is configured to provide a reference clock signal for the integer frequency synthesizer circuit; the integer frequency synthesizer circuit is configured to provide the reference clock signal for the fractional frequency synthesizer circuit, so that the fractional frequency synthesizer circuit obtains a phase discrimination frequency according to the reference clock signal; and the fractional frequency synthesizer circuit is configured to generate a frequency signal with a fractional spur value greater than a preset threshold according to the phase discrimination frequency. By taking the output of the integer frequency synthesizer as the reference clock of the fractional frequency synthesizer, the circuit structure is simplified, the control difficulty is reduced, and the phase discrimination frequency of the fractional frequency synthesizer circuit can be flexibly changed, so that good fractional spur avoidance can be achieved when different frequency signals are output, and the spectral quality of the output signal is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of communication, in particular to a frequency synthesizer, a frequency synthesis method, an electronic device and a storage medium. BACKGROUND

[0002] With the development of communication technology, in the process of electronic communication, the signal is synthesized and output by the phase-locked loop frequency synthesizer, and the frequency band width of the output signal becomes larger and larger. Due to the characteristics of high frequency resolution and wide output frequency range of the fractional frequency synthesizer, it is widely used in electronic communication test systems. When the fractional frequency synthesizer needs to output a wide-band full-coverage radio frequency signal, the fractional spur will inevitably fall within the phase-locked loop bandwidth in the traditional scheme. How to suppress the fractional spur problem has always been a technical problem. The existing fractional spur suppression method mainly realizes the adjustment of the phase detection frequency input to the final fractional frequency synthesizer by using two or more fractional frequency synthesizer circuits, that is, connecting one or more fractional frequency synthesizers after the reference clock signal to realize the adjustment of the phase detection frequency input to the final fractional frequency synthesizer, so as to suppress the fractional spur of the final fractional frequency synthesizer. Or multiple reference oscillators are used as reference for the fractional frequency synthesizer, and different reference sources are switched by a switch to realize the switching of the reference frequency input to the final fractional frequency synthesizer, so as to realize the adjustment of the phase detection frequency of the final fractional frequency synthesizer to suppress the fractional spur.

[0003] When synthesizing the signal, the adjustment of the phase detection frequency needs a relatively complex circuit structure, and the control is complex when switching the phase detection frequency, which may introduce new fractional spur. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a frequency synthesizer, a frequency synthesis method, an electronic device and a storage medium, so that the phase detection frequency can be flexibly switched according to the frequency of the output signal, the fractional spur can be well avoided, the circuit complexity and control difficulty can be reduced, and the frequency spectrum quality of the output signal can be improved.

[0005] To solve the above technical problems, the embodiments of the present application provide a frequency synthesizer, comprising: a reference oscillator, an integer frequency synthesizer circuit and a fractional frequency synthesizer circuit; wherein the reference oscillator is connected with a reference clock input end of the integer frequency synthesizer circuit, and is used to provide a reference clock signal for the integer frequency synthesizer circuit; an output end of the integer frequency synthesizer circuit is connected with a reference clock input end of the fractional frequency synthesizer circuit, and is used to provide a reference clock signal for the fractional frequency synthesizer circuit, so that the fractional frequency synthesizer circuit obtains a phase detection frequency according to the reference clock signal; and the fractional frequency synthesizer circuit is used to generate a frequency signal with a fractional spur value greater than a preset threshold according to the phase detection frequency.

[0006] The embodiment of the present application further provides a frequency synthesis method, which is applied to a frequency synthesizer, the frequency synthesizer comprising a reference crystal oscillator, an integer frequency synthesizer circuit and a fractional frequency synthesizer circuit, the reference crystal oscillator being connected with a reference clock input end of the integer frequency synthesizer circuit, and an output end of the integer frequency synthesizer circuit being connected with a reference clock input end of the fractional frequency synthesizer circuit; the frequency synthesis method comprising: obtaining an output signal of the integer frequency synthesizer circuit, taking the output signal as a reference clock signal of the fractional frequency synthesizer circuit, and inputting the reference clock signal into the fractional frequency synthesizer circuit; detecting whether a fractional spur value of a frequency signal generated by the fractional frequency synthesizer circuit is greater than a preset threshold value; if the fractional spur value is not greater than the preset threshold value, adjusting the output signal of the integer frequency synthesizer circuit, and re-detecting whether the fractional spur value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold value until the fractional spur value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold value.

[0007] The embodiment of the present application further provides an electronic device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the frequency synthesis method.

[0008] The embodiment of the present application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the frequency synthesis method.

[0009] Compared with the prior art, the embodiment of the present application adjusts the reference clock signal of the fractional frequency synthesizer circuit by adjusting the output of the integer frequency synthesizer circuit, and then ensures that the phase discrimination frequency of the fractional frequency synthesizer circuit can be flexibly adjusted according to the frequency of the output signal, so that good fractional spur avoidance can be achieved when signals of various frequencies are output; by taking the output of the integer frequency synthesizer circuit as the reference clock of the fractional frequency synthesizer circuit, the problems of complex circuit structure and control mode caused by multiple fractional frequency synthesizer circuits are avoided, and new fractional spur is avoided, and the frequency spectrum quality of the output signal is improved.

[0010] In addition, the integer frequency synthesizer circuit comprises: a first phase detector, a first loop filter, a first voltage-controlled oscillator, a first frequency divider and a second frequency divider; wherein a first input end of the first phase detector is connected to a reference crystal oscillator, a second input end of the first phase detector is connected to an output end of the first frequency divider, an output end of the first phase detector is connected to an input end of the first loop filter, for phase detecting a first phase frequency determined according to a reference clock signal provided by the reference crystal oscillator and a feedback signal of the first voltage-controlled oscillator after frequency division, and transmitting a phase detection result to the first loop filter; an output end of the first loop filter is connected to an input end of the first voltage-controlled oscillator, for generating a first control signal according to the phase detection result and transmitting the first control signal to the first voltage-controlled oscillator; a feedback output end of the first voltage-controlled oscillator is connected to an input end of the first frequency divider, and a signal output end of the first voltage-controlled oscillator is connected to an input end of the second frequency divider, for adjusting a frequency of an output signal, outputting a frequency signal and transmitting a feedback signal to the first frequency divider; the first frequency divider is used for frequency dividing the feedback signal of the first voltage-controlled oscillator; an output end of the second frequency divider is connected to a reference clock input end of the fractional frequency synthesizer circuit, for frequency dividing the output signal of the first voltage-controlled oscillator, so that the output signal can be adjusted in frequency according to a reference clock signal required by the fractional frequency synthesizer, thereby ensuring that the fractional frequency synthesizer circuit can well avoid fractional spurs of the output signal according to a corresponding phase detection frequency of the reference clock signal.

[0011] In addition, the integer frequency synthesizer circuit comprises: a first phase detector, a first loop filter, a first voltage-controlled oscillator, a first frequency divider, a second frequency divider and a third frequency divider; wherein the input end of the third frequency divider is connected with a reference crystal oscillator, the output end of the third frequency divider is connected with the first input end of the first phase detector, and the third frequency divider is used for frequency dividing a reference clock signal provided by the reference crystal oscillator; the second input end of the first phase detector is connected with the output end of the first frequency divider, the output end of the first phase detector is connected with the input end of the first loop filter, and the first phase detector is used for phase detecting a first phase frequency determined according to the frequency-divided reference clock signal and a feedback signal of the frequency-divided first voltage-controlled oscillator, and transmitting the phase detection result to the first loop filter; the output end of the first loop filter is connected with the input end of the first voltage-controlled oscillator, and the first loop filter is used for generating a first control signal according to the phase detection result and transmitting the first control signal to the first voltage-controlled oscillator; the feedback output end of the first voltage-controlled oscillator is connected with the input end of the first frequency divider, and the signal output end of the first voltage-controlled oscillator is connected with the input end of the second frequency divider, and the first voltage-controlled oscillator is used for adjusting the frequency of a to-be-output signal, outputting a frequency signal and transmitting a feedback signal to the first frequency divider; the first frequency divider is used for frequency dividing the feedback signal of the first voltage-controlled oscillator; and the output end of the second frequency divider is connected with the reference clock input end of the fractional frequency synthesizer circuit, and the second frequency divider is used for frequency dividing the output signal of the first voltage-controlled oscillator, so that the output signal of the integer frequency synthesizer circuit can be more consistent with the reference clock signal required by the fractional frequency synthesizer circuit, the fractional frequency synthesizer can obtain a required reference clock, and the spectral quality of the finally output signal is ensured.

[0012] In addition, the fractional frequency synthesizer circuit comprises: a second phase detector, a second loop filter, a second voltage-controlled oscillator and a fourth frequency divider; wherein the first input end of the second phase detector is connected with the circuit output end of the integer frequency synthesizer circuit, the second input end of the second phase detector is connected with the output end of the fourth frequency divider, the output end of the second phase detector is connected with the input end of the second loop filter, and the second phase detector is used for phase detecting a phase frequency determined according to the reference clock signal provided by the integer frequency synthesizer circuit and a feedback signal of the frequency-divided second voltage-controlled oscillator, and transmitting the phase detection result to the second loop filter; the output end of the second loop filter is connected with the input end of the second voltage-controlled oscillator, and the second loop filter is used for generating a second control signal according to the phase detection result and transmitting the second control signal to the second voltage-controlled oscillator; the feedback output end of the second voltage-controlled oscillator is connected with the input end of the fourth frequency divider, and the second voltage-controlled oscillator is used for adjusting the frequency of a to-be-output signal, outputting a frequency signal and transmitting a feedback signal to the fourth frequency divider; and the fourth frequency divider is used for frequency dividing the feedback signal of the second voltage-controlled oscillator, and the fourth frequency divider is used for feedback control adjustment according to the phase detection result of the phase detector, so that the fractional spur of the output signal can be effectively avoided.

[0013] In addition, the fractional frequency synthesizer circuit comprises a second phase detector, a second loop filter, a second voltage-controlled oscillator, a fourth frequency divider, a fifth frequency divider and a sixth frequency divider; the input end of the fifth frequency divider is connected to the circuit output end of the integer frequency synthesizer circuit, the output end of the fifth frequency divider is connected to the first input end of the second phase detector, and the fifth frequency divider is used for frequency dividing the reference clock signal provided by the integer frequency synthesizer circuit; the first input end of the second phase detector is connected to the output end of the fifth frequency divider, the second input end of the second phase detector is connected to the output end of the fourth frequency divider, the output end of the second phase detector is connected to the input end of the second loop filter, and the second phase detector is used for phase detecting the phase frequency determined according to the frequency-divided reference clock signal provided by the integer frequency synthesizer circuit and the feedback signal of the frequency-divided second voltage-controlled oscillator, and transmitting the phase detection result to the second loop filter; the output end of the second loop filter is connected to the input end of the second voltage-controlled oscillator, and the second loop filter is used for generating a second control signal according to the phase detection result and transmitting the second control signal to the second voltage-controlled oscillator; the feedback output end of the second voltage-controlled oscillator is connected to the input end of the sixth frequency divider, and the second voltage-controlled oscillator is used for adjusting the frequency of the to-be-output signal, outputting a frequency signal and transmitting the feedback signal to the sixth frequency divider; the output end of the sixth frequency divider is connected to the input end of the fourth frequency divider, and the sixth frequency divider is used for pre-dividing the feedback signal of the second voltage-controlled oscillator and outputting the pre-divided feedback signal of the second voltage-controlled oscillator to the fourth frequency divider, so that the fourth frequency divider re-divides the pre-divided feedback signal of the second voltage-controlled oscillator; by pre-dividing the feedback signal, the frequency division ratio and difficulty of the fourth frequency divider are reduced, the problem of signal quality reduction caused by excessively high frequency division ratio is avoided, and the signal quality of the output signal is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0014] One or more embodiments are illustrated by way of example with reference to the drawings, which are not limiting to the embodiments.

[0015] Figure 1 is a structural schematic diagram of a frequency synthesizer according to the prior art;

[0016] Figure 2 is a structural schematic diagram of another frequency synthesizer according to the prior art;

[0017] Figure 3 is a structural schematic diagram of a frequency synthesizer according to the first embodiment of the present application;

[0018] Figure 4 is a structural schematic diagram of a frequency synthesizer according to the second embodiment of the present application;

[0019] Figure 5 is a flowchart of a frequency synthesis method according to the third embodiment of the present application;

[0020] Figure 6 is a schematic diagram of an electronic device structure according to a fourth embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the various embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the various embodiments of the present application, many technical details are presented in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments. The division of the following various embodiments is for the convenience of description, and should not constitute any limitation on the specific embodiments of the present application, and the various embodiments can be combined and referenced with each other under the premise of no contradiction.

[0022] When performing fractional spurs avoidance, usually the difference Δf between the harmonic of the phase detection frequency closest to the output signal frequency and the output signal frequency is taken as the quantization target of the fractional spurs, and generally the fractional spurs can be suppressed at a position of 20 to 30 times the fractional frequency synthesizer loop filter bandwidth BW, so that most of the fractional spurs can be suppressed. The structure schematic diagram of the signal synthesis with fractional spurs avoidance function in the prior art is shown in Figure 1 and Figure 2 The structure shown in Figure 1 , by providing a same reference crystal oscillator for the first fractional frequency synthesizer and the second fractional frequency synthesizer, obtaining two outputs ref1 and ref2 through the two fractional frequency synthesizers, and then connecting the outputs of the two fractional frequency synthesizers to a radio frequency switch, selecting the reference clock signal input to the third fractional frequency synthesizer according to the radio frequency switch, and then adjusting the reference clock of the third fractional frequency synthesizer, so as to adjust the phase detection frequency determined according to the reference clock, so that the phase detection frequency of the third fractional frequency synthesizer is adjustable.

[0023] The structure shown in Figure 2 , the reference crystal oscillator 1 and the reference crystal oscillator 2 are supplied by different power supplies, different reference crystal oscillators are generated by means of frequency generators, and then the reference crystal oscillators are input to a radio frequency switch, the reference crystal oscillator to be input to the frequency detector is selected by means of a crystal oscillator switching circuit, and then the phase detection frequency is determined according to the reference crystal oscillator by means of a phase-locked loop circuit, and different frequency signals are output according to the phase detection frequency after synthesis, and by selecting one of the multiple reference crystal oscillators as the reference crystal oscillator of the phase-locked loop circuit, the switching of the phase detection frequency of the phase-locked loop circuit is realized.

[0024] When the phase detection frequency of the third fractional frequency synthesizer is adjusted by the plurality of fractional frequency synthesizers in combination with the radio frequency switch, there are problems of requiring more fractional frequency synthesizers, the circuit structure and control being relatively complex, and new fractional spur being possibly introduced; when one of the plurality of reference crystal oscillators is selected by the radio frequency switch to provide a reference clock signal for the phase-locked loop circuit, and the phase detection frequency is adjusted by the selected reference clock signal, there is a problem of requiring a plurality of reference crystal oscillators, occupying a large circuit area.

[0025] The first embodiment of the present application relates to a frequency synthesizer, and a structural schematic diagram of the frequency synthesizer in the embodiment is shown in Figure 3 The output of the integer frequency synthesizer circuit is taken as the input of the reference clock of the fractional frequency synthesizer circuit, the output of the integer frequency synthesizer circuit is adjusted according to the frequency of the output signal of the fractional frequency synthesizer circuit, so that the phase detection frequency of the fractional frequency synthesizer circuit is flexibly adjusted.

[0026] The implementation details of the frequency synthesizer in the embodiment are specifically described below, and the following content is only provided for the implementation details for the convenience of understanding, and is not necessary for implementing the present solution.

[0027] In the frequency synthesizer in the embodiment, the reference crystal oscillator is connected to the reference clock input end of the integer frequency synthesizer circuit, the reference crystal oscillator is taken as the input of the integer frequency synthesizer circuit, the reference clock signal is provided for the integer frequency synthesizer circuit, so that the integer frequency synthesizer can generate the output signal according to the reference crystal oscillator; the output end of the integer frequency synthesizer circuit is connected to the reference clock input end of the fractional frequency synthesizer circuit, the output of the integer frequency synthesizer circuit is taken as the reference clock signal of the fractional frequency synthesizer circuit, so that the reference clock input of the fractional frequency synthesizer circuit can be flexibly changed according to the output of the integer frequency synthesizer circuit, the fractional frequency synthesizer circuit determines the phase detection frequency according to the reference clock signal provided by the integer frequency synthesizer circuit, and then generates a frequency signal with a fractional spur value greater than a preset threshold according to the phase detection frequency. By taking the output of the integer frequency synthesizer circuit as the reference clock input of the fractional frequency synthesizer circuit, the reference clock of the fractional frequency synthesizer circuit can be changed according to the output of the integer frequency synthesizer circuit, and then the phase detection frequency of the fractional frequency synthesizer circuit is flexibly switched, so that the fractional frequency synthesizer circuit can generate signals with different frequencies, and good fractional spur avoidance can be performed.

[0028] Further, the integer frequency synthesizer circuit comprises: a first phase detector, a first loop filter, a first voltage-controlled oscillator, a first frequency divider and a second frequency divider; wherein a first input end of the first phase detector is connected with the reference crystal oscillator, a second input end of the first phase detector is connected with an output end of the first frequency divider, an output end of the first phase detector is connected with an input end of the first loop filter, for performing phase detection on a first phase frequency determined according to the reference crystal oscillator and a feedback signal of the first voltage-controlled oscillator after frequency division, and transmitting the phase detection result to the first loop filter; an output end of the first loop filter is connected with an input end of the first voltage-controlled oscillator, for generating a first control signal according to the phase detection result and transmitting the first control signal to the first voltage-controlled oscillator; a feedback output end of the first voltage-controlled oscillator is connected with an input end of the first frequency divider, and a signal output end of the first voltage-controlled oscillator is connected with an input end of the second frequency divider, for adjusting the frequency of the output signal and transmitting the feedback signal to the first frequency divider; the first frequency divider is used for frequency dividing the feedback signal of the first voltage-controlled oscillator; and an output end of the second frequency divider is connected with a reference clock input end of the fractional frequency synthesizer circuit, for frequency dividing the output signal of the first voltage-controlled oscillator. The signal output by the integer frequency synthesizer circuit is frequency divided by adjusting the frequency division coefficient of the programmable second frequency divider to obtain Fout1, and the frequency-divided output signal Fout1 is transmitted to the reference clock signal input end of the fractional frequency synthesizer circuit, so that when the fractional frequency synthesizer circuit synthesizes and outputs the signal according to the phase frequency corresponding to the obtained reference clock signal, it can have good fractional spurious emission avoidance effect on various frequency output signals.

[0029] Further, the integer frequency synthesizer circuit further comprises: a third frequency divider; an input end of the third frequency divider is connected with the reference crystal oscillator, and an output end of the third frequency divider is connected with the second input end of the first phase detector, for frequency dividing the reference crystal oscillator obtained by the integer frequency synthesizer circuit; by frequency dividing the reference crystal oscillator, the frequency of the output signal of the integer frequency synthesizer circuit is more consistent with the demand of the fractional frequency synthesizer circuit for the frequency of the reference clock signal, so that the fractional frequency synthesizer obtains the required reference clock, thereby ensuring the quality of the finally output signal.

[0030] Further, the fractional frequency synthesizer circuit comprises a second phase detector, a second loop filter, a second voltage-controlled oscillator and a fourth frequency divider; the first input end of the second phase detector is connected to the circuit output end of the integer frequency synthesizer circuit, the second input end of the second phase detector is connected to the output end of the fourth frequency divider, the output end of the second phase detector is connected to the input end of the second loop filter, and the second phase detector is used for phase detection on a phase detection frequency determined according to a reference clock signal provided by the integer frequency synthesizer circuit and a feedback signal of the second voltage-controlled oscillator after frequency division, and transmitting a phase detection result to the second loop filter; the output end of the second loop filter is connected to the input end of the second voltage-controlled oscillator, and the second loop filter is used for generating a second control signal according to the phase detection result and transmitting the second control signal to the second voltage-controlled oscillator; the feedback output end of the second voltage-controlled oscillator is connected to the input end of the fourth frequency divider, and the second voltage-controlled oscillator is used for adjusting the frequency of the to-be-output signal, outputting a frequency signal and transmitting a feedback signal to the fourth frequency divider; the fourth frequency divider is used for frequency division on the feedback signal of the second voltage-controlled oscillator, and the output signal of the fourth frequency divider enters the second phase detector for phase comparison with the reference signal; the second loop filter generates a control signal according to the phase detection result of the feedback signal and the phase detection frequency determined by the second phase detector, to adjust the frequency of the output signal of the second voltage-controlled oscillator, so that the fractional spur of the output signal can be effectively avoided when the signals of various frequencies are output; and the fractional frequency synthesizer circuit is realized based on Σ-Δ modulation technology.

[0031] Further, the fractional frequency synthesizer circuit further comprises a fifth frequency divider; the input end of the fifth frequency divider is connected to the circuit output end of the integer frequency synthesizer circuit, and the output end of the fifth frequency divider is connected to the first input end of the second phase detector, and the fifth frequency divider is used for frequency division on a reference clock signal provided by the integer frequency synthesizer circuit; the first input end of the second phase detector is connected to the circuit output end of the integer frequency synthesizer circuit through the fifth frequency divider, the reference clock signal obtained is frequency-divided through the fifth frequency divider, so that the determined phase detection frequency meets the demand of the fractional frequency synthesizer circuit, and good avoidance of the fractional spur is realized.

[0032] In one example, when the frequency synthesizer synthesizes and outputs a signal, the configuration data of the first voltage-controlled oscillator of the integer frequency synthesizer circuit and the frequency division factor of the second frequency divider are first adjusted by software to obtain different frequencies Fout1 that the integer frequency synthesizer circuit can output, the alternative library of the reference clock signal of the fractional frequency synthesizer circuit is formed according to these possible outputs of the integer frequency synthesizer circuit, then the requirement of avoiding fractional spurs is determined according to the loop bandwidth of the fractional frequency synthesizer circuit, when synthesizing and outputting a signal, the phase detection frequency that can meet the requirement of avoiding fractional spurs is calculated by the configuration algorithm when the fractional frequency synthesizer circuit outputs a frequency signal, then the required reference clock signal of the fractional frequency synthesizer circuit is determined according to the determined phase detection frequency, the configuration data of the integer frequency synthesizer circuit is adjusted according to the determined reference clock signal, so that the integer frequency synthesizer circuit outputs a frequency signal that meets the requirement. Here, in order to achieve better fractional spur elimination effect, the avoidance principle can be set as when Δf < n·BW, avoidance is performed, so that the fractional spur falls outside n times of the loop bandwidth, and is filtered out by the loop filter. Considering design and circuit cost and other problems, the value range of n can be set to 30 to 120.

[0033] For example, the frequency range of the output signal of the fractional frequency synthesizer circuit is between 3-9GHz, the loop bandwidth of the output signal is 50kHz, the base phase detection frequency is 50MHz, according to the avoidance principle of fractional spurs, n is selected as 100, that is, the fractional spur falls at 100 times the loop bandwidth, at this time, the harmonic of the phase detection frequency and the output frequency difference Δf<5MHz need to be avoided, that is, when the fractional spur Δf<5MHz, the phase detection frequency needs to be reselected, all possible outputs of the integer frequency synthesizer circuit are obtained through software calculation, a reference clock signal candidate library is obtained, and the 50MHz output signal is selected as the base output signal according to the base phase detection frequency of the fractional frequency synthesizer circuit. When the fractional frequency synthesizer circuit synthesizes and outputs a signal, the configuration data of the second frequency divider of the integer frequency synthesizer and the first voltage controlled oscillator are set according to the base output signal, and a 50MHz output signal is output. At a certain moment, the fractional frequency synthesizer circuit outputs a 4500.03MHz signal, and the phase detection frequency obtained according to the reference clock signal is the base phase detection frequency 50MHz, through software calculation, the 90th harmonic of the phase detection frequency is closest to the output frequency, and at this time, Δf=30kHz, which is less than 50kHz, that is, the fractional spur at this time will appear within the loop bandwidth of 50kHz, and it is judged that the avoidance requirement of the fractional spur cannot be met, at this time, the data in the reference clock signal candidate library is queried, the candidate signal with a frequency greater than the current signal frequency and closest to the current signal frequency is selected as the to-be-output signal, through the data in the reference clock candidate library, it is obtained that 51.28205MHz is closest to 50MHz, and the signal with a frequency of 51.28205MHz is selected as the to-be-output signal, the configuration data of the second frequency divider and the first voltage controlled oscillator are adjusted according to the frequency of the to-be-output signal, so that the output signal of the integer frequency synthesizer circuit is 51.28205MHz, at this time, the phase detection frequency of the fractional frequency synthesizer circuit is changed to 51.28205MHz, at this time, the 88th harmonic of the phase detection frequency is closest to the frequency of the output signal, and Δf=12.7904MHz is calculated, which is much greater than 50kHz, and good fractional spur avoidance can be achieved, therefore, the configuration data of the second frequency divider and the first voltage controlled oscillator is maintained unchanged, and the fractional frequency synthesizer circuit synthesizes and outputs a frequency signal.

[0034] Thus, the embodiment provides a frequency synthesizer, by means of the integer frequency synthesizer circuit, the fractional frequency synthesizer circuit is provided with a proper reference clock signal, so that the fractional frequency synthesizer circuit can change the corresponding phase detection frequency according to the output of the integer frequency synthesizer circuit, and ensures that when the fractional frequency synthesizer outputs signals of different frequencies, good fractional spur avoidance can be realized; the integer frequency synthesizer circuit provides the reference clock of the fractional frequency synthesizer circuit, avoids the need to set multiple reference clock signal generating circuits, simplifies the structure of the circuit, reduces the complexity and control difficulty of the circuit, saves the circuit area and cost, and avoids the problem that new fractional spur may be introduced when multiple fractional frequency synthesizer circuits are combined, ensures the fractional spur avoidance effect, and improves the quality of the output signal.

[0035] The second embodiment of the present application relates to a frequency synthesizer, and the second embodiment is substantially the same as the first embodiment, in the embodiment, a sixth frequency divider for pre-dividing the feedback signal of the fractional frequency synthesizer is added in the fractional frequency synthesizer circuit, by pre-dividing the feedback signal, the frequency division requirement and difficulty of the fourth frequency divider are reduced, the problem that the signal quality is reduced due to the too high frequency division ratio and affects the phase detection result is avoided, and the quality of the output signal is further ensured.

[0036] The structural schematic diagram of the embodiment is shown in Figure 4 In the embodiment, the modules except the sixth frequency divider are similar to the modules in the first embodiment, in order to avoid repetition, the modules will not be described one by one, and only the sixth frequency divider will be described.

[0037] In the embodiment, the fractional frequency synthesizer circuit further comprises: a sixth frequency divider; the input end of the sixth frequency divider is connected with the feedback output end of the second voltage-controlled oscillator, the output end of the sixth frequency divider is connected with the input end of the fourth frequency divider, and the sixth frequency divider is used for pre-dividing the feedback signal of the second voltage-controlled oscillator; by pre-dividing the feedback signal, the frequency division ratio of the fourth frequency divider is reduced, the problem that the signal quality is reduced due to the too high frequency division ratio is avoided, and the signal quality of the output signal is ensured.

[0038] In one example, a sixth frequency divider is added in the fractional frequency synthesizer circuit, since the phase comparator compares the difference between the certain harmonic of the phase detection frequency and the frequency of the signal received by the fourth frequency divider, at this time, the fractional spur is Δf / p, wherein p is the frequency division coefficient of the sixth frequency divider, for example, the fractional frequency synthesizer needs to output a signal of 3-9GHz, the base phase detection frequency of the fractional frequency synthesizer is 50MHz, the loop bandwidth is 50kHz, the frequency division coefficient of the sixth phase detector is 2, at a certain moment, the frequency of the output signal is 4500.03MHz, the 90th harmonic of the phase detection frequency is closest to the frequency of the signal fed back to the fourth frequency divider, at this time, the feedback signal that needs to be output to the phase detector should be the signal after the output frequency is divided by the sixth frequency divider and the fourth frequency divider, since the frequency division coefficient of the sixth frequency divider is 2, the feedback signal has been divided, therefore, at this time, only the frequency division coefficient of the fourth frequency divider needs to be set to 45.0003, at this time, the difference Δf between the 90th harmonic of the phase detection frequency and the output frequency of the sixth frequency divider is 30kHz, the corresponding fractional spur is Δf / p, that is, 15kHz, then the fractional spur avoidance effect is detected according to the fractional spur avoidance requirement, and the parameters of the integer frequency synthesizer circuit are adjusted according to the detection result, so that the integer frequency synthesizer circuit outputs a suitable frequency, the phase detection frequency of the fractional frequency synthesizer circuit is modified, and the fractional spur avoidance effect is satisfied until the fractional spur avoidance effect meets the requirement.

[0039] Therefore, the embodiment provides a frequency synthesizer, by adding a sixth frequency divider in front of the fourth frequency divider in the feedback signal transmission channel of the fractional frequency synthesizer circuit, the frequency division process of the feedback signal is changed to twice frequency division, the frequency division ratio of the fourth frequency divider is reduced, the signal quality is prevented from being reduced due to the too large frequency division ratio, the quality of the signal received by the phase detector is ensured, and then the accuracy of the phase detection result is ensured, so that the fractional spur avoidance effect is prevented from being affected by the inaccurate phase detection result, and the quality of the output signal is ensured.

[0040] The third embodiment of the present application relates to a frequency synthesis method, and specifically, the flow is as shown in Figure 5 The frequency synthesis method comprises the following steps:

[0041] In step 101, the output signal of the integer frequency synthesizer circuit is obtained.

[0042] Specifically, before the synthesis and output of the frequency signal, the output signal of the integer frequency synthesizer circuit is obtained, and the obtained output signal of the integer frequency synthesizer circuit is taken as a reference clock signal of the fractional frequency synthesizer circuit and input to the fractional frequency synthesizer circuit.

[0043] Step 102, detecting whether the fractional spurious value is greater than the preset threshold value, if greater than the preset threshold value, entering step 104, if not greater than the preset threshold value, entering step 103.

[0044] Specifically, after the output signal of the integer frequency synthesizer circuit obtained is taken as the reference clock signal of the fractional frequency synthesizer circuit, the phase detection frequency of the fractional frequency synthesizer circuit is determined according to the reference clock signal of the fractional frequency synthesizer circuit, the difference between the harmonic closest to the output frequency in the phase detection frequency harmonics and the output frequency is calculated according to the determined phase detection frequency and the frequency of the frequency signal to be output, the fractional spurious value of the frequency signal generated by the fractional frequency synthesizer circuit is determined, whether the fractional spurious value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold value is detected, if greater than the preset threshold value, entering step 104, if not greater than the preset threshold value, entering step 103.

[0045] In actual application, the preset threshold value of the fractional spurious value can be set according to the actual situation of the fractional spurious avoidance demand, and the specific value of the preset threshold value is not limited in the embodiment.

[0046] Step 103, adjusting the output of the integer frequency synthesizer circuit.

[0047] Specifically, when it is detected that the signal synthesis and output according to the phase detection frequency corresponding to the current reference clock signal is performed, and the fractional spurious value is not greater than the preset threshold value, it is determined that the phase detection frequency corresponding to the current reference clock signal cannot realize good fractional spurious avoidance in the process of signal synthesis and output of the current frequency, and the reference clock signal needs to be adjusted, that is, the output signal of the integer frequency synthesizer circuit is adjusted, and then it is returned to step 102 again to detect whether the fractional spurious value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold value, until the fractional spurious value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold value.

[0048] In one example, when synthesizing and outputting the frequency signal, a reference clock signal candidate library 1 is generated according to all candidate frequencies of the output signal of the integer frequency synthesizer circuit, then a basic output signal of the integer frequency synthesizer circuit is selected from the reference clock signal candidate library 1 according to the basic phase detection frequency of the fractional frequency synthesizer circuit, then the phase detection frequency required when the output signal of the fractional frequency synthesizer circuit is at different frequencies is calculated through software according to the frequency range of the output signal of the fractional frequency synthesizer circuit, the output signal frequency range applicable to the current phase detection frequency is detected based on the current phase detection frequency, when the current phase detection frequency does not meet the requirement of fractional spur avoidance, the target frequency closest to the current output signal frequency is selected from the reference clock signal candidate library 1, the configuration data of the integer frequency synthesizer circuit is adjusted according to the target frequency, and the output signal of the target frequency is output by the integer frequency synthesizer circuit, then the output signal range applicable to the phase detection frequency corresponding to the new reference clock signal is detected, until the traversal of all output signals of the fractional frequency synthesizer circuit is completed. The reference clock signal candidate library 2 is generated according to the reference clock signal selected in the traversal calculation process, when the output of the integer frequency synthesizer circuit is adjusted, the target frequency closest to the current phase detection frequency is directly selected from the reference clock signal candidate library 2, and the configuration data of the integer frequency synthesizer circuit is adjusted according to the selected target frequency, and the output signal of the target frequency is output by the integer frequency synthesizer circuit.

[0049] In actual application, the target frequency can be the frequency value closest to the current signal frequency in the frequency greater than the current signal frequency or the frequency less than the current signal frequency, and the specific selection rule is not limited in the embodiment.

[0050] For example, the fractional frequency synthesizer needs to output a 3-9GHz signal, the base phase detection frequency of the fractional frequency synthesizer is 50MHz, and the loop bandwidth is 50kHz. The frequencies of the output signals of the integer frequency synthesizer circuit include: 50MHz, 55.55555MHz, 54.05405MHz, 52.63157MHz, 51.28205MHz, 48.78048MHz, 47.61904MHz, 46.51162MHz, 45.45454MHz, 55.88235MHz, 54.28571MHz, 52.77777MHz, 51.35135MHz, 48.71794MHz, 47.5MHz, 46.34146MHz, 45.23809MHz, etc. According to the multiple possible output signals of the integer frequency synthesizer circuit, the reference clock candidate library 1 is generated, and then the software traversal calculation is performed to determine that the phase detection frequencies required for the 3-9GHz signal output include: 50MHz, 51.28205MHz, 51.35135MHz, 52.63157MHz and 52.77777MHz. According to the reference clock signals corresponding to the five phase detection frequencies, the reference clock candidate library 2 is generated. At a certain moment, the fractional frequency synthesizer circuit outputs a 4500.03MHz signal, and the phase detection frequency used at this moment is 50MHz. The 90th harmonic of the phase detection frequency is closest to the frequency of the output signal, and the difference Δf between the two is 30kHz, that is, the fractional spur value at this moment is 30kHz, which does not meet the fractional spur avoidance requirement. At this moment, the 51.28205MHz reference clock closest to the current phase detection frequency is selected from the signals with a frequency greater than the current phase detection frequency in the reference clock candidate library 2 as the signal to be output, and the configuration data of the integer frequency synthesizer circuit is adjusted according to the selected signal so that the integer frequency synthesizer circuit outputs a signal with a frequency of 51.28205MHz. Then, return to step 102 to re-detect whether the fractional spur value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold.

[0051] Step 104, output the frequency signal.

[0052] Specifically, when it is detected that the fractional spur value of the frequency signal output by the fractional frequency synthesizer circuit is greater than the preset threshold, it can be directly determined that the phase detection frequency corresponding to the current reference clock can achieve good fractional spur avoidance in the process of synthesizing and outputting the current frequency signal. Therefore, the output of the frequency signal is directly performed according to the current reference clock signal.

[0053] Thus, the embodiment provides a frequency synthesis method, by taking the output of the integer frequency synthesizer circuit as the input of the reference clock signal of the fractional frequency synthesizer circuit, so that the reference clock of the fractional frequency synthesizer can be flexibly changed according to the output of the integer frequency synthesizer, and the phase detection frequency is flexibly changed; the selection of the reference clock signal and the adjustment of the integer frequency synthesizer circuit are performed through the pre-established reference clock alternative library, the efficiency of the phase detection frequency adjustment is improved; the output signal of the integer frequency synthesizer circuit is adjusted through the relationship between the calculation result of the fractional spur value and the preset threshold, so that the phase detection frequency of the fractional frequency synthesizer circuit can be changed according to different frequency output signals, good fractional spur avoidance can be realized when different frequency signals are output, and the quality of the output signal is ensured.

[0054] The step division of the above various methods is only for clear description, and can be combined into one step or split into multiple steps in implementation, as long as the same logical relationship is included, and all are within the protection scope of the patent; adding insignificant modifications or introducing insignificant designs in the algorithm or flow, but not changing the core design of the algorithm and flow are within the protection scope of the patent.

[0055] The fourth embodiment of the present application relates to an electronic device, such as Figure 6 As shown, comprising at least one processor;And the memory connected with at least one processor;Wherein, the memory has instructions that can be executed by at least one processor, the instructions are executed by at least one processor, so that at least one processor can execute the frequency synthesis method described above.

[0056] Wherein, the memory and the processor are connected in a bus mode, the bus can include any number of interconnected buses and bridges, and the bus connects one or more processors and various circuits of the memory together. The bus can also connect various other circuits such as peripheral devices, voltage regulators and power management circuits together, which are well known in the art, and therefore, they will not be further described herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be one element or multiple elements, such as multiple receivers and transmitters, which provide units for communicating with various other devices on the transmission medium. The data processed by the processor is transmitted on the wireless medium through the antenna, and further, the antenna also receives data and transmits the data to the processor.

[0057] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interface, voltage regulation, power management and other control functions. And the memory can be used to store the data used by the processor in the execution operation.

[0058] The fifth embodiment of the present application relates to a computer readable storage medium storing a computer program. The computer program, when executed by a processor, implements the method embodiments described above.

[0059] That is, those skilled in the art can understand that all or part of the steps of the methods in the above embodiments can be completed by a program instructing related hardware, the program is stored in a storage medium, and includes a plurality of instructions for causing an apparatus (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0060] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. A frequency synthesizer, characterized by, The method comprises the following steps: A reference crystal oscillator, an integer frequency synthesizer circuit and a fractional frequency synthesizer circuit are provided; The reference crystal oscillator is connected to a reference clock input terminal of the integer frequency synthesizer circuit, and is used to provide a reference clock signal for the integer frequency synthesizer circuit; An output terminal of the integer frequency synthesizer circuit is connected to a reference clock input terminal of the fractional frequency synthesizer circuit, and is used to provide a reference clock signal bank for the fractional frequency synthesizer circuit, and the fractional frequency synthesizer circuit obtains a phase detection frequency according to a reference clock signal in the reference clock signal bank, wherein the avoidance requirement of fractional spurs is determined according to the loop bandwidth of the fractional frequency synthesizer circuit, and when the signal is synthesized and output, the phase detection frequency that can meet the avoidance requirement of fractional spurs is calculated by configuring an algorithm when the fractional frequency synthesizer circuit outputs each frequency signal; The fractional frequency synthesizer circuit is used to generate a frequency signal with a fractional spur value greater than a preset threshold according to the phase detection frequency, wherein the fractional spur value is the difference between the harmonic of the phase detection frequency and the output frequency of the fractional frequency synthesizer circuit.

2. The frequency synthesizer of claim 1, wherein, The integer frequency synthesizer circuit comprises a first phase detector, a first loop filter, a first voltage-controlled oscillator, a first frequency divider and a second frequency divider; The first input terminal of the first phase detector is connected to the reference crystal oscillator, the second input terminal of the first phase detector is connected to the output terminal of the first frequency divider, the output terminal of the first phase detector is connected to the input terminal of the first loop filter, and the first phase detector is used to perform phase detection on a first phase detection frequency determined according to a reference clock signal provided by the reference crystal oscillator and a feedback signal of the first voltage-controlled oscillator after frequency division, and transmit the phase detection result to the first loop filter; The output terminal of the first loop filter is connected to the input terminal of the first voltage-controlled oscillator, and the first loop filter is used to generate a first control signal according to the phase detection result and transmit the first control signal to the first voltage-controlled oscillator; The feedback output terminal of the first voltage-controlled oscillator is connected to the input terminal of the first frequency divider, and the signal output terminal of the first voltage-controlled oscillator is connected to the input terminal of the second frequency divider, which is used to adjust the frequency of the to-be-output signal, output a frequency signal and transmit a feedback signal to the first frequency divider; The first frequency divider is used to divide the feedback signal of the first voltage-controlled oscillator; The output terminal of the second frequency divider is connected to the reference clock input terminal of the fractional frequency synthesizer circuit, and the second frequency divider is used to divide the output signal of the first voltage-controlled oscillator.

3. The frequency synthesizer of claim 1, wherein, The integer frequency synthesizer circuit comprises a first phase detector, a first loop filter, a first voltage-controlled oscillator, a first frequency divider, a second frequency divider and a third frequency divider; The input terminal of the third frequency divider is connected to the reference crystal oscillator, and the output terminal of the third frequency divider is connected to the first input terminal of the first phase detector, which is used to divide the reference clock signal provided by the reference crystal oscillator; The second input end of the first phase detector is connected with the output end of the first frequency divider, and the output end of the first phase detector is connected with the input end of the first loop filter, for phase detection of a first phase frequency determined according to the divided reference clock signal and the feedback signal of the divided first voltage-controlled oscillator, and transmitting the phase detection result to the first loop filter; The output end of the first loop filter is connected with the input end of the first voltage-controlled oscillator, for generating a first control signal according to the phase detection result, and transmitting the first control signal to the first voltage-controlled oscillator; The feedback output end of the first voltage-controlled oscillator is connected with the input end of the first frequency divider, and the signal output end of the first voltage-controlled oscillator is connected with the input end of the second frequency divider, for adjusting the frequency of the to-be-output signal, outputting a frequency signal and transmitting a feedback signal to the first frequency divider; The first frequency divider is used for dividing the feedback signal of the first voltage-controlled oscillator; The output end of the second frequency divider is connected with the reference clock input end of the fractional frequency synthesizer circuit, for dividing the output signal of the first voltage-controlled oscillator.

4. The frequency synthesizer of claim 1, wherein, The fractional frequency synthesizer circuit comprises a second phase detector, a second loop filter, a second voltage-controlled oscillator and a fourth frequency divider; The first input end of the second phase detector is connected with the circuit output end of the integer frequency synthesizer circuit, the second input end of the second phase detector is connected with the output end of the fourth frequency divider, the output end of the second phase detector is connected with the input end of the second loop filter, for phase detection of a phase frequency determined according to the reference clock signal provided by the integer frequency synthesizer circuit and the feedback signal of the divided second voltage-controlled oscillator, and transmitting the phase detection result to the second loop filter; The output end of the second loop filter is connected with the input end of the second voltage-controlled oscillator, for generating a second control signal according to the phase detection result, and transmitting the second control signal to the second voltage-controlled oscillator; The feedback output end of the second voltage-controlled oscillator is connected with the input end of the fourth frequency divider, for adjusting the frequency of the to-be-output signal, outputting a frequency signal and transmitting a feedback signal to the fourth frequency divider; The fourth frequency divider is used for dividing the feedback signal of the second voltage-controlled oscillator.

5. The frequency synthesizer of claim 1, wherein, The fractional frequency synthesizer circuit comprises a second phase detector, a second loop filter, a second voltage-controlled oscillator, a fourth frequency divider and a fifth frequency divider; The input end of the fifth frequency divider is connected with the circuit output end of the integer frequency synthesizer circuit, and the output end of the fifth frequency divider is connected with the first input end of the second phase detector, for dividing the reference clock signal provided by the integer frequency synthesizer circuit; The second input end of the second phase detector is connected with the output end of the fourth frequency divider, the output end of the second phase detector is connected with the input end of the second loop filter, and the second phase detector is used for phase detection on the phase detection frequency determined according to the reference clock signal provided by the integer frequency synthesizer circuit after frequency division and the feedback signal of the second voltage controlled oscillator after frequency division, and the phase detection result is transmitted to the second loop filter; The output end of the second loop filter is connected with the input end of the second voltage controlled oscillator, and the second loop filter is used for generating a second control signal according to the phase detection result and transmitting the second control signal to the second voltage controlled oscillator; The feedback output end of the second voltage controlled oscillator is connected with the input end of the fourth frequency divider, and the second voltage controlled oscillator is used for adjusting the frequency of the to-be-output signal, outputting a frequency signal and transmitting a feedback signal to the fourth frequency divider; The fourth frequency divider is used for frequency division on the feedback signal of the second voltage controlled oscillator.

6. The frequency synthesizer of claim 1, wherein, The fractional frequency synthesizer circuit comprises a second phase detector, a second loop filter, a second voltage controlled oscillator, a fourth frequency divider, a fifth frequency divider and a sixth frequency divider; The input end of the fifth frequency divider is connected with the circuit output end of the integer frequency synthesizer circuit, and the output end of the fifth frequency divider is connected with the first input end of the second phase detector, and the fifth frequency divider is used for frequency division on the reference clock signal provided by the integer frequency synthesizer circuit; The first input end of the second phase detector is connected with the output end of the fifth frequency divider, the second input end of the second phase detector is connected with the output end of the fourth frequency divider, and the output end of the second phase detector is connected with the input end of the second loop filter, and the second phase detector is used for phase detection on the phase detection frequency determined according to the reference clock signal provided by the integer frequency synthesizer circuit after frequency division and the feedback signal of the second voltage controlled oscillator after frequency division, and the phase detection result is transmitted to the second loop filter; The output end of the second loop filter is connected with the input end of the second voltage controlled oscillator, and the second loop filter is used for generating a second control signal according to the phase detection result and transmitting the second control signal to the second voltage controlled oscillator; The feedback output end of the second voltage controlled oscillator is connected with the input end of the sixth frequency divider, and the second voltage controlled oscillator is used for adjusting the frequency of the to-be-output signal, outputting a frequency signal and transmitting a feedback signal to the sixth frequency divider; The output end of the sixth frequency divider is connected with the input end of the fourth frequency divider, and the sixth frequency divider is used for pre-frequency division on the feedback signal of the second voltage controlled oscillator and outputs the feedback signal of the second voltage controlled oscillator after pre-frequency division to the fourth frequency divider, so that the fourth frequency divider performs re-frequency division on the feedback signal of the second voltage controlled oscillator after pre-frequency division.

7. A frequency synthesis method characterized by, The frequency synthesizer comprises a reference crystal oscillator, an integer frequency synthesizer circuit and a fractional frequency synthesizer circuit, the reference crystal oscillator is connected with the reference clock input end of the integer frequency synthesizer circuit, the output end of the integer frequency synthesizer circuit is connected with the reference clock input end of the fractional frequency synthesizer circuit; and the frequency synthesis method comprises: acquiring an output signal of the integer frequency synthesizer circuit, inputting the output signal as a reference clock signal of the fractional frequency synthesizer circuit to the fractional frequency synthesizer circuit; detecting whether a fractional spur value of a frequency signal generated by the fractional frequency synthesizer circuit is greater than a preset threshold value; if the fractional spur value is not greater than the preset threshold value, adjusting the output signal of the integer frequency synthesizer circuit, and re-detecting whether the fractional spur value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold value, until the fractional spur value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold value; the adjusting the output signal of the integer frequency synthesizer circuit comprises: acquiring all alternative frequencies of the output signal of the integer frequency synthesizer circuit; determining a target frequency closest to a current output signal frequency according to the alternative frequencies; adjusting configuration data of the integer frequency synthesizer circuit according to the target frequency, so that the integer frequency synthesizer circuit outputs an output signal of the target frequency.

8. An electronic device, comprising: comprise: at least one processor; and a memory connected in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the frequency synthesis method of claim 7.

9. A computer readable storage medium storing a computer program, characterized in that, The computer program is executed by the processor to implement the frequency synthesis method of claim 7. The computer program is executed by the processor to implement the frequency synthesis method of claim 7.

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