Display driving device and display device including the same

Abstract

The present invention discloses a display driver device that allows high-speed data communication to be supported by controlling the length of a data packet and a display device including the display driver device. The display device may include: a timing controller configured to send a communication signal; and a source driver connected to the timing controller through a communication link and configured to receive the communication signal. The source driver may receive the communication signal in the format of leading data, start data, configuration data, end data, and configuration completion data from the timing controller in a configuration mode, and the configuration data may include a header that defines the length of the data packet.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 2019-0174232, filed on December 24, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a display device, and more particularly, to a display driving device allowing support of high-speed data communication and a display device including the display driving device. Background Art

[0004] Typically, a display device includes a display panel, a source driver, a timing controller, and the like.

[0005] The source driver converts the digital image data provided from the timing controller into a data voltage and provides the data voltage to the display panel. The source driver may be integrated into an integrated circuit chip (IC chip) and may be configured as a plurality of IC chips in consideration of the size and resolution of the display panel.

[0006] At the same time, the display device sets the internal option of the source driver at a low speed to allow for high-speed communication.

[0007] However, the number of configuration options required for high-speed communication may vary depending on the application and the source driver vendor. Therefore, there is a problem that as the time required for the configuration process at a low speed increases, the response speed of the display device is affected. Summary of the invention

[0008] The present disclosure is directed to providing a display driving device that allows supporting high-speed data communication by controlling the length of a data packet and a display device including the display driving device.

[0009] According to one aspect of the present disclosure, a display device is provided, comprising: a timing controller configured to send a communication signal; and a source driver connected to the timing controller via a communication link and configured to receive the communication signal. The source driver can receive the communication signal in the format of leading data, start data, configuration data, end data, and configuration completion data from the timing controller in a configuration mode, and the configuration data can include a header defining the length of a data packet.

[0010] According to another aspect of the present disclosure, a display driving device is provided, comprising at least one source driver, wherein the source driver is configured to receive a communication signal from a timing controller in a configuration mode, wherein the communication signal has a format of leading data, start data, configuration data, end data, and configuration completion data. The configuration data may include a header defining a length of a data packet. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0012] Figure 1 is a block diagram of a display device according to an embodiment;

[0013] Figure 2 is a diagram for describing a recovery protocol of a display device according to one embodiment;

[0014] Figure 3 is a diagram for describing a recovery protocol of a display device according to another embodiment; and

[0015] Figure 4 is a diagram for describing a configuration protocol of a display device according to an embodiment. DETAILED DESCRIPTION

[0016] The embodiment discloses a display driving device and a display device including the same, which supports high-speed data communication by defining a variable data packet length in a packet header, thereby allowing a reduction in time for a configuration mode to operate at a low frequency.

[0017] The embodiment discloses a display driving device and a display device including the same, and when a communication abnormality occurs due to an unexpected variable during communication between a timing controller and a source driver, the communication abnormal state can be restored to a normal state.

[0018] In an embodiment, the recovery protocol or the recovery mode may be defined as a protocol or a mode that makes the communication status between the timing controller and the source driver in the same state.

[0019] In an embodiment, a configuration protocol, a configuration mode, or a configuration cycle may be defined as a protocol, mode, or cycle for setting options for an Internet Protocol (IP) for a communication link for high-speed operation in display mode, options for a clock data recovery circuit of a source driver, options for pre-clock training, and equalizer options.

[0020] In an embodiment, a display mode or a display cycle may be defined as a mode or a cycle for processing configuration data and image data of a source driver.

[0021] In an embodiment, the pre-clock training or bandwidth setting period may be defined as a mode or period for searching and setting an optimal frequency bandwidth for a communication link operating at high speed in a display mode.

[0022] In an embodiment, equalizer training or an equalizer cycle may be defined as a pattern or cycle for setting an equalizer gain level to improve the characteristics of a communication link operating at high speed in a display mode.

[0023] In an embodiment, the terms "first", "second", etc. may be used for the purpose of distinguishing a plurality of elements from one another. Here, the terms "first", "second", etc. are not intended to limit the elements.

[0024] Figure 1 is a block diagram of a display device according to an embodiment.

[0025] Reference Figure 1 , the display device may include a timing controller TCON, first to fifth plurality of source drivers SDIC1 to SDIC5 , and a display panel.

[0026] The timing controller TCON may be connected to the first to fifth plurality of source drivers SDIC1 to SDIC5 in a point-to-point manner through first to fifth communication links CL1 to CL5 .

[0027] As an example, the timing controller TCON may be connected to the first source driver SDIC1 through the first communication link CL1, and the timing controller TCON may be connected to the second source driver SDIC2 through the second communication link CL2. The timing controller TCON may be connected to the third source driver SDIC3 through the third communication link CL3, and the timing controller TCON may be connected to the fourth source driver SDIC4 through the fourth communication link CL4. The timing controller TCON may be connected to the fifth source driver SDIC5 through the fifth communication link CL5. In addition, each of the first to fifth communication links CL1 to CL5 may be configured as a pair of differential signal channels.

[0028] The timing controller TCON may provide communication signals CEDS GEN2+ / − to the source drivers SDIC1 to SDIC5 through the first to fifth communication links CL1 to CL5 , respectively.

[0029] In addition, the first to fifth source drivers SDIC1 to SDIC5 may be connected to each other in a cascade manner through the first to fifth locking links LL1 to LL5 .

[0030] As an example, the power supply voltage terminal VCC may be connected to the first source driver SDIC1 through the first locking link LL1. The first source driver SDIC1 may be connected to the second source driver SDIC2 through the second locking link LL2, and the second source driver SDIC2 may be connected to the third source driver SDIC3 through the third locking link LL3. The third source driver SDIC3 may be connected to the fourth source driver SDIC4 through the fourth locking link LL4, and the fourth source driver SDIC4 may be connected to the fifth source driver SDIC5 through the fifth locking link LL5. In addition, the fifth source driver SDIC5, which is the last one, may be connected to the timing controller TCON through the feedback link FL.

[0031] The first source driver SDIC1 may send a first locking signal LOCK1 to the second source driver SDIC2 through the second locking link LL2, and the second source driver SDIC2 may send a second locking signal LOCK2 to the third source driver SDIC3 through the third locking link LL3. The third source driver SDIC3 may send a third locking signal LOCK3 to the fourth source driver SDIC4 through the fourth locking link LL4, and the fourth source driver SDIC4 may send a fourth locking signal LOCK4 to the fifth source driver SDIC5 through the fifth locking link LL5. In addition, the fifth source driver SDIC5 may send a fifth locking signal RX_LOCK to the timing controller TCON through the feedback link FL. Here, the fifth locking signal RX_LOCK may indicate a communication state of at least one of the first to fifth source drivers SDIC1 to SDIC5. When a locking failure occurs in at least one of the first to fifth source drivers SDIC1 to SDIC5, the fifth locking signal RX_LOCK may be switched to have a value indicating a communication abnormal state.

[0032] Figure 2 is a diagram for describing a recovery protocol of a display device according to one embodiment.

[0033] Reference Figure 2 , when a communication abnormal state occurs due to external noise such as electrostatic discharge (ESD) while executing a display mode, the display device may switch from the display mode to the configuration mode.

[0034] As an example, when a lock failure occurs in at least one of the first to fifth source drivers SDIC1 to SDIC5 , the fifth source driver SDIC5 may switch the level of the fifth lock signal RX_LOCK from a high level to a low level and provide the fifth lock signal RX_LOCK to the timing controller TCON.

[0035] When a lock failure occurs, the timing controller TCON may include a recovery command SYNC_RST for recovering the communication state in the communication signal CEDS GEN2+ / − and transmit the communication signal CEDS GEN2+ / − to the first to fifth source drivers SDIC1 to SDIC5 through the first to fifth communication links CL1 to CL5 .

[0036] As an example, the timing controller TCON may transmit the resume command SYNC_RST having a predetermined level within a predetermined time period. In addition, the timing controller TCON may transmit the configuration data packet RX CFG to the first to fifth source drivers SDIC1 to SDIC5 after transmitting the resume command SYNC_RST having a predetermined level within a predetermined time period.

[0037] The first to fifth source drivers SDIC1 to SDIC5 may receive the resume command SYNC_RST and the configuration packet RXCFG and may execute a configuration mode according to the configuration packet RXCFG. Here, the configuration mode may be defined as a mode for setting IP options of the first to fifth communication links CL1 to CL5 operating at high speed in the display mode.

[0038] Additionally, the configuration mode may be set to operate in a lower frequency band compared to the display mode.

[0039] In addition, the timing controller TCON may transmit configuration completion data CFG DONE to the first to fifth source drivers SDIC1 to SDIC5 after transmitting the entire configuration data packet RX CFG.

[0040] As an example, the timing controller TCON may transmit the configuration completion data CFG DONE having a value that continuously switches between 0 and 1 within a predetermined time period to the first to fifth source drivers SDIC1 to SDIC5 .

[0041] In addition, when the first to fifth source drivers SDIC1 to SDIC5 receive the configuration completion data CFG DONE from the timing controller TCON, the first to fifth source drivers SDIC1 to SDIC5 may switch from the configuration mode to the display mode.

[0042] The first to fifth source drivers SDIC1 to SDIC5 may recover a phase locked loop (PLL) clock of an internal clock data recovery circuit (not shown) by performing clock training in a display period.

[0043] Next, after the clock training in the display period, the first to fifth source drivers SDIC1 to SDIC5 may lock the symbol boundary detection and the symbol clock by performing link training.

[0044] Next, after the link training in the display period, the first to fifth source drivers SDIC1 to SDIC5 may receive the frame data transmitted from the timing controller TCON, convert the row data included in the frame data into data voltages, and provide the data voltages to the display panel.

[0045] Figure 3 is a diagram for describing a recovery protocol of a display device according to another embodiment. Figure 3 When, with reference Figure 2 The description of the embodiment described is repeated by Figure 2 Description instead.

[0046] Reference Figure 3 , when a communication abnormal state occurs due to external noise, the timing controller TCON may transmit a restoration command SYNC_RST having a predetermined level to the first to fifth source drivers SDIC1 to SDIC5 within a predetermined time period.

[0047] Next, after sending the resume command SYNC_RST within a predetermined time period, the timing controller TCON may send the configuration data packet RX CFG to the first to fifth source drivers SDIC1 to SDIC5 .

[0048] As an example, when transmitting the configuration data packet RX CFG to the first to fifth source drivers SDIC1 to SDIC5 , the timing controller TCON may cause the pre-clock training option and the equalizer training option to be included in the configuration data packet RX CFG.

[0049] Next, after completing the configuration mode, the first to fifth source drivers SDIC1 to SDIC5 may perform pre-clock training to set optimal frequency bandwidths of the first to fifth communication links CL1 to CL5 operating at a high speed in the display mode.

[0050] Next, after the pre-clock training is completed, the first to fifth source drivers SDIC1 to SDIC5 may perform equalizer training, thereby setting an equalizer gain level that may improve the characteristics of a communication link operating at a high speed in a display mode.

[0051] As an example, the timing controller TCON may repeat the pattern of sending the equalizer clock training and the equalizer link training during the equalizer cycle for the number of times set in the previous configuration mode.

[0052] The first to fifth source drivers SDIC1 to SDIC5 may change the level of the equalizer gain level by the value set in the previous configuration mode.

[0053] In addition, each of the first to fifth source drivers SDIC1 to SDIC5 may check the lock, symbol lock, and the number of errors of the clock data recovery circuit according to its equalizer gain level.

[0054] In addition, the first to fifth source drivers SDIC1 to SDIC5 can compare the lock, symbol lock and error numbers of the clock data recovery circuits according to the equalizer gain level to select the most effective equalizer gain level and set the first to fifth communication links CL1 to CL5 accordingly.

[0055] Here, the pre-clock training and the equalizer training may be set to operate at a high frequency band compared to the configuration mode.

[0056] In addition, after the equalizer training is completed, the first to fifth source drivers SDIC1 to SDIC5 may be switched to the display mode.

[0057] The first to fifth source drivers SDIC1 to SDIC5 may recover the PLL clock by performing clock training in the display mode, and may lock the symbol boundary detection and the symbol clock by performing link training.

[0058] In addition, the first to fifth source drivers SDIC1 to SDIC5 may convert row data transmitted from the timing controller TCON into data voltages and provide the data voltages to the display panel.

[0059] As described above, according to the embodiment, when a communication abnormality occurs between a timing controller and a source driver due to an unexpected variable, the communication abnormal state can be restored to a normal state at a desired time, thereby preventing a communication failure.

[0060] Figure 4 1 is a diagram for describing a configuration protocol of a display device according to an embodiment. In the following, for the convenience of description, a case where communication is performed between a timing controller and a source driver will be taken as an example for description.

[0061] Reference Figure 4 , the source driver can receive a communication signal having a format of leading data PREAMBLE, start data START, configuration data CFG_DATA, end data END and configuration completion data CFG_DONE from the timing controller TCON in the configuration mode. The configuration data CFG_DATA may include a limited data packet DATA 1 To DATA N The length of the packet header CFG[7:0].

[0062] The configuration data CFG_DATA may have the following format: header CFG[7:0], data packet DATA 1To DATA N And checksum CHECK_SUM[7:0].

[0063] The packet header CFG[7:0] can limit the data packet DATA currently being exchanged 1 To DATA N In addition, the header CFG[7:0] may define the total number of the configuration data CFG_DATA sequence CFG_DATA[1] to CFG_DATA[N]. In addition, the header CFG[7:0] may define whether the checksum CHECK_SUM[7:0] is activated.

[0064] As an example, the packet header CFG[7:0] may include 8 bits, and the [0] bit of the packet header CFG[7:0] may be used for synchronization, and the [3:1] bits of the packet header CFG[7:0] may be used to define the data packet DATA currently being exchanged. 1 To DATA N The [6:4] bits of the header CFG[7:0] can be used to define the total number of the configuration data CFG_DATA sequence CFG_DATA[1] to CFG_DATA[N]. In addition, the [7] bit of the header CFG[7:0] can define whether the checksum CHECK_SUM[7:0] is activated.

[0065] First, in the configuration mode, the source driver may receive preamble data PREAMBLE that continuously switches between a 0 level and a 1 level.

[0066] Next, when the source driver continuously receives the leading data PREAMBLE within a predetermined time period, the source driver may send a lock signal RX_LOCK indicating that the source driver is ready to receive the configuration data CFG_DATA to the timing controller TCON. As an example, the source driver may provide the lock signal RX_LOCK by switching from a low level to a high level.

[0067] Next, the timing controller TCON may transmit start data START, configuration data CFG_DATA, end data END, and configuration completion data CFG_DONE to the source driver in response to the lock signal RX_LOCK. Here, the start data START may be set to a level "0011", and the end data END may be set to a level "1100".

[0068] Next, after receiving the end data END '1100', the source driver may receive the configuration completion data CFG_DONE which continuously switches between a 0 level and a 1 level.

[0069] Next, when the source driver receives the configuration completion data CFG_DONE within a predetermined time period, the source driver may perform a pre-clock training, an equalizer training, or a display mode according to the configuration data CFG_DATA.

[0070] As described above, according to the embodiment, by defining a variable data packet length in a packet header, the time for a configuration mode operating at a low frequency can be reduced, thereby supporting high-speed data communication and improving system efficiency.

Claims

1. A display device, comprising: a timing controller configured to send a communication signal; as well as a source driver connected to the timing controller via a communication link and configured to receive the communication signal, wherein the source driver receives the communication signal having the format of leading data, start data, configuration data, end data and configuration completion data from the timing controller in the configuration mode, The configuration data includes a header that defines the length of the data packet. When a communication abnormality state occurs due to external noise while executing the display mode, the display device switches from the display mode to the configuration mode.

2. The display device according to claim 1, wherein: The configuration data has a format including: the packet header, the data packet, and a checksum, and The packet header defines the number of bytes of the data packet currently being exchanged.

3. The display device according to claim 2, wherein: The header further defines a total number of sequences of the configuration data.

4. The display device according to claim 3, wherein: The packet header further defines whether the checksum is activated.

5. The display device according to claim 1, wherein: The source driver receives the leading data which continuously switches between a 0 level and a 1 level.

6. The display device according to claim 5, wherein: When the leading data is received within a predetermined time period, the source driver sends a lock signal to the timing controller indicating that the source driver is ready to receive the configuration data.

7. The display device according to claim 6, wherein: The timing controller transmits the start data, the configuration data, the end data, and the configuration completion data to the source driver in response to the lock signal.

8. The display device according to claim 1, wherein: The configuration data includes: The packet header defines at least one or more of the following: the number of bytes of the currently exchanged data packet, the total number of sequences of the configuration data, and whether the checksum is activated; said data packet comprising configuration options; and The checksum is used to check the data packet for errors.

9. The display device according to claim 1, wherein: The start data is set to have a level of "0011", and the end data is set to have a level of "1100".

10. The display device according to claim 9, wherein: After receiving the end data, the source driver receives the configuration completion data that continuously switches between a 0 level and a 1 level.

11. The display device according to claim 10, wherein: When the source driver receives the configuration completion data within a predetermined time period, the source driver performs pre-clock training, equalizer training, or the display mode according to the configuration data.

12. A display driving device, comprising at least one source driver, wherein the source driver is configured to receive a communication signal from a timing controller in a configuration mode, wherein the communication signal has a format of leading data, start data, configuration data, end data, and configuration completion data, in, The configuration data includes a header defining the length of the data packet, When a communication abnormality state occurs due to external noise while the display mode is being executed, the display driving device switches from the display mode to the configuration mode.

13. The display driving device according to claim 12, wherein: The configuration data includes: The packet header defines at least one or more of the following: the number of bytes of the currently exchanged data packet, the total number of sequences of the configuration data, and whether the checksum is activated; said data packet comprising configuration options; and The checksum is used to check the data packet for errors.

14. The display driving device according to claim 12, wherein: The source driver receives the leading data which continuously switches between a 0 level and a 1 level.

15. The display driving device according to claim 14, wherein: When the leading data is received within a predetermined time period, the source driver sends a lock signal to the timing controller indicating that the source driver is ready to receive the configuration data.

16. The display driving device according to claim 12, wherein: The start data is set to have a level of "0011", and the end data is set to have a level of "1100".

17. The display driving device according to claim 16, wherein: After receiving the end data, the source driver receives the configuration completion data that continuously switches between a 0 level and a 1 level.

18. The display driving device according to claim 17, wherein: When the source driver receives the configuration completion data within a predetermined time period, the source driver performs a pre-clock training, an equalizer training, or a display mode according to the configuration data.

Images