Display driving device and display device including the same

Abstract

The present invention discloses a display driving device capable of avoiding the influence of high voltage noise in display panel driving and a display device including the display driving device. The display device includes a timing controller configured to send a communication signal including a blank pattern and line data at a horizontal line interval; and a source driver configured to recover the blank pattern and line data in the communication signal and drive the display panel using the blank pattern and line data. The timing controller may include a configuration packet in the blank pattern, and may place the configuration packet in the end period of the blank pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 2019-0174234, filed on December 24, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a display device, and more particularly, to a display driving device capable of avoiding the influence of high voltage noise in display panel driving and a display device including the display driving device. Background Art

[0004] Typically, a display device includes a display panel, a source driver, a timing controller, and the like.

[0005] The source driver converts the digital image data provided from the timing controller into a data voltage and provides the data voltage to the display panel. The source driver may be integrated into an integrated circuit chip (IC chip) and may be configured as a plurality of IC chips in consideration of the size and resolution of the display panel.

[0006] Meanwhile, the source driver drives the horizontal lines of the display panel at each frame time to display an image. When the source driver drives the display panel at horizontal line intervals, high voltage noise may be periodically generated.

[0007] The high voltage noise may affect the low voltage range circuit to cause abnormal operation, and may affect the low voltage input data input during the horizontal blank period, thereby possibly affecting the display panel driving.

[0008] As an example, a problem with the prior art is that when a data packet such as a scrambled reset signal is affected by high voltage noise, an important control data packet may not be received normally, and thus the display panel may not be driven normally. Summary of the invention

[0009] The present disclosure aims to provide a display driving device capable of avoiding the influence of high voltage noise in display panel driving and a display device including the display driving device.

[0010] According to one aspect of the present disclosure, a display device is provided, including a timing controller configured to send a communication signal including a blank pattern and line data at a horizontal line interval; and a source driver configured to recover the blank pattern and line data in the communication signal and drive a display panel using the blank pattern and line data. The timing controller may include a configuration packet in the blank pattern, and may place the configuration packet in an end period of the blank pattern.

[0011] According to another aspect of the present disclosure, a display driving device is provided, comprising at least one source driver configured to recover a blank pattern and line data in a communication signal sent at horizontal line intervals, and drive a display panel using the blank pattern and the line data. A configuration packet may be included in the blank pattern, and the configuration packet may be arranged to be located in an end period of the blank pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0013] Figure 1 is a block diagram of a display device according to an embodiment;

[0014] Figure 2 is a diagram for describing a recovery protocol of a display device according to one embodiment;

[0015] Figure 3 is a diagram for describing a recovery protocol of a display device according to another embodiment;

[0016] Figure 4 is a diagram for describing a configuration protocol of a display device according to an embodiment;

[0017] Figure 5 is a diagram for describing a scrambling protocol of a display device according to one embodiment; and

[0018] Figure 6 is a diagram for describing a protocol for defining a location of a configuration package of a display device according to one embodiment. DETAILED DESCRIPTION

[0019] The embodiment discloses a display driving device capable of avoiding the influence of high voltage noise in display panel driving and a display device including the display driving device.

[0020] The embodiment discloses a display driving device and a display device including the display driving device, which can improve the effect of reducing electromagnetic interference (EMI) by converting transmission data into a completely random code sequence.

[0021] The embodiment discloses a display driving device and a display device including the same, which supports high-speed data communication by defining a variable data packet length in a packet header, thereby allowing a reduction in time for a configuration mode to operate at a low frequency.

[0022] The embodiment discloses a display driving device and a display device including the same, and when a communication abnormality occurs due to an unexpected variable during communication between a timing controller and a source driver, the communication abnormal state can be restored to a normal state.

[0023] In an embodiment, the recovery protocol or the recovery mode may be defined as a protocol or a mode that makes the communication status between the timing controller and the source driver in the same state.

[0024] In an embodiment, a configuration protocol, a configuration mode, or a configuration cycle may be defined as a protocol, mode, or cycle for setting options for an Internet Protocol (IP) for a communication link for high-speed operation in display mode, options for a clock data recovery circuit of a source driver, options for pre-clock training, and equalizer options.

[0025] In an embodiment, a display mode or a display cycle may be defined as a mode or a cycle for processing configuration data and image data of a source driver.

[0026] In an embodiment, the pre-clock training or bandwidth setting period may be defined as a mode or period for searching and setting an optimal frequency bandwidth for a communication link operating at high speed in a display mode.

[0027] In an embodiment, equalizer training or an equalizer cycle may be defined as a pattern or cycle for setting an equalizer gain level to improve the characteristics of a communication link operating at high speed in a display mode.

[0028] In an embodiment, the scrambling protocol can be defined as a commitment protocol between the timing controller and the source driver, wherein the timing controller scrambles the transmission data into a random code sequence and sends the random code sequence to the source driver, and the source driver recovers the transmission data by descrambling the random code sequence.

[0029] In an embodiment, the configuration of the horizontal blanking period may include a scramble reset.

[0030] In an embodiment, the terms "first", "second", etc. may be used for the purpose of distinguishing a plurality of elements from one another. Here, the terms "first", "second", etc. are not intended to limit the elements.

[0031] Figure 1 is a block diagram of a display device according to an embodiment.

[0032] Reference Figure 1 , the display device may include a timing controller TCON, first to fifth plurality of source drivers SDIC1 to SDIC5 , and a display panel.

[0033] The timing controller TCON may be connected to the first to fifth plurality of source drivers SDIC1 to SDIC5 in a point-to-point manner through first to fifth communication links CL1 to CL5 .

[0034] As an example, the timing controller TCON may be connected to the first source driver SDIC1 through the first communication link CL1, and the timing controller TCON may be connected to the second source driver SDIC2 through the second communication link CL2. The timing controller TCON may be connected to the third source driver SDIC3 through the third communication link CL3, and the timing controller TCON may be connected to the fourth source driver SDIC4 through the fourth communication link CL4. The timing controller TCON may be connected to the fifth source driver SDIC5 through the fifth communication link CL5. In addition, each of the first to fifth communication links CL1 to CL5 may be configured as a pair of differential signal channels.

[0035] The timing controller TCON may provide communication signals CEDS GEN2+ / − to the source drivers SDIC1 to SDIC5 through the first to fifth communication links CL1 to CL5 , respectively.

[0036] In addition, the first to fifth source drivers SDIC1 to SDIC5 may be connected to each other in a cascade manner through the first to fifth locking links LL1 to LL5 .

[0037] As an example, the power supply voltage terminal VCC may be connected to the first source driver SDIC1 through the first locking link LL1. The first source driver SDIC1 may be connected to the second source driver SDIC2 through the second locking link LL2, and the second source driver SDIC2 may be connected to the third source driver SDIC3 through the third locking link LL3. The third source driver SDIC3 may be connected to the fourth source driver SDIC4 through the fourth locking link LL4, and the fourth source driver SDIC4 may be connected to the fifth source driver SDIC5 through the fifth locking link LL5. In addition, the fifth source driver SDIC5, which is the last one, may be connected to the timing controller TCON through the feedback link FL.

[0038] The first source driver SDIC1 may send a first locking signal LOCK1 to the second source driver SDIC2 through the second locking link LL2, and the second source driver SDIC2 may send a second locking signal LOCK2 to the third source driver SDIC3 through the third locking link LL3. The third source driver SDIC3 may send a third locking signal LOCK3 to the fourth source driver SDIC4 through the fourth locking link LL4, and the fourth source driver SDIC4 may send a fourth locking signal LOCK4 to the fifth source driver SDIC5 through the fifth locking link LL5. In addition, the fifth source driver SDIC5 may send a fifth locking signal RX_LOCK to the timing controller TCON through the feedback link FL. Here, the fifth locking signal RX_LOCK may indicate a communication state of at least one of the first to fifth source drivers SDIC1 to SDIC5. When a locking failure occurs in at least one of the first to fifth source drivers SDIC1 to SDIC5, the fifth locking signal RX_LOCK may be switched to have a value indicating a communication abnormal state.

[0039] Figure 2 is a diagram for describing a recovery protocol of a display device according to one embodiment.

[0040] Reference Figure 2 , when a communication abnormal state occurs due to external noise such as electrostatic discharge (ESD) while executing a display mode, the display device may switch from the display mode to the configuration mode.

[0041] As an example, when a lock failure occurs in at least one of the first to fifth source drivers SDIC1 to SDIC5 , the fifth source driver SDIC5 may switch the level of the fifth lock signal RX_LOCK from a high level to a low level and provide the fifth lock signal RX_LOCK to the timing controller TCON.

[0042] When a lock failure occurs, the timing controller TCON may include a recovery command SYNC_RST for recovering the communication state in the communication signal CEDS GEN2+ / − and transmit the communication signal CEDS GEN2+ / − to the first to fifth source drivers SDIC1 to SDIC5 through the first to fifth communication links CL1 to CL5 .

[0043] As an example, the timing controller TCON may transmit the resume command SYNC_RST having a predetermined level within a predetermined time period. In addition, the timing controller TCON may transmit the configuration data packet RX CFG to the first to fifth source drivers SDIC1 to SDIC5 after transmitting the resume command SYNC_RST having a predetermined level within a predetermined time period.

[0044] The first to fifth source drivers SDIC1 to SDIC5 may receive the resume command SYNC_RST and the configuration packet RXCFG and may execute a configuration mode according to the configuration packet RXCFG. Here, the configuration mode may be defined as a mode for setting IP options of the first to fifth communication links CL1 to CL5 operating at high speed in the display mode.

[0045] Additionally, the configuration mode may be set to operate in a lower frequency band compared to the display mode.

[0046] In addition, the timing controller TCON may transmit configuration completion data CFG DONE to the first to fifth source drivers SDIC1 to SDIC5 after transmitting the entire configuration data packet RX CFG.

[0047] As an example, the timing controller TCON may transmit the configuration completion data CFG DONE having a value that continuously switches between 0 and 1 within a predetermined time period to the first to fifth source drivers SDIC1 to SDIC5 .

[0048] In addition, when the first to fifth source drivers SDIC1 to SDIC5 receive the configuration completion data CFG DONE from the timing controller TCON, the first to fifth source drivers SDIC1 to SDIC5 may switch from the configuration mode to the display mode.

[0049] The first to fifth source drivers SDIC1 to SDIC5 may recover a phase locked loop (PLL) clock of an internal clock data recovery circuit (not shown) by performing clock training in a display period.

[0050] Next, after the clock training in the display period, the first to fifth source drivers SDIC1 to SDIC5 may lock the symbol boundary detection and the symbol clock by performing link training.

[0051] Next, after the link training in the display period, the first to fifth source drivers SDIC1 to SDIC5 may receive the frame data transmitted from the timing controller TCON, convert the row data included in the frame data into data voltages, and provide the data voltages to the display panel.

[0052] Figure 3 is a diagram for describing a recovery protocol of a display device according to another embodiment. Figure 3 When, with reference Figure 2 The description of the embodiment described is repeated by Figure 2 Description instead.

[0053] Reference Figure 3, when a communication abnormal state occurs due to external noise, the timing controller TCON may transmit a restoration command SYNC_RST having a predetermined level to the first to fifth source drivers SDIC1 to SDIC5 within a predetermined time period.

[0054] Next, after sending the resume command SYNC_RST within a predetermined time period, the timing controller TCON may send the configuration data packet RX CFG to the first to fifth source drivers SDIC1 to SDIC5 .

[0055] As an example, when transmitting the configuration data packet RX CFG to the first to fifth source drivers SDIC1 to SDIC5 , the timing controller TCON may cause the pre-clock training option and the equalizer training option to be included in the configuration data packet RX CFG.

[0056] Next, after completing the configuration mode, the first to fifth source drivers SDIC1 to SDIC5 may perform pre-clock training to set optimal frequency bandwidths of the first to fifth communication links CL1 to CL5 operating at a high speed in the display mode.

[0057] Next, after the pre-clock training is completed, the first to fifth source drivers SDIC1 to SDIC5 may perform equalizer training, thereby setting an equalizer gain level that may improve the characteristics of a communication link operating at a high speed in a display mode.

[0058] As an example, the timing controller TCON may repeat the pattern of sending the equalizer clock training and the equalizer link training the number of times set in the previous configuration mode during the equalizer cycle.

[0059] The first to fifth source drivers SDIC1 to SDIC5 may change the level of the equalizer gain level by the value set in the previous configuration mode.

[0060] In addition, each of the first to fifth source drivers SDIC1 to SDIC5 may check the lock, symbol lock, and the number of errors of the clock data recovery circuit according to its equalizer gain level.

[0061] In addition, the first to fifth source drivers SDIC1 to SDIC5 can compare the lock, symbol lock and error numbers of the clock data recovery circuits according to the equalizer gain level to select the most effective equalizer gain level and set the first to fifth communication links CL1 to CL5 accordingly.

[0062] Here, the pre-clock training and the equalizer training may be set to operate at a high frequency band compared to the configuration mode.

[0063] In addition, after the equalizer training is completed, the first to fifth source drivers SDIC1 to SDIC5 may be switched to the display mode.

[0064] The first to fifth source drivers SDIC1 to SDIC5 may recover the PLL clock by performing clock training in the display mode, and may lock the symbol boundary detection and the symbol clock by performing link training.

[0065] In addition, the first to fifth source drivers SDIC1 to SDIC5 may convert row data transmitted from the timing controller TCON into data voltages and provide the data voltages to the display panel.

[0066] As described above, according to the embodiment, when a communication abnormality occurs between a timing controller and a source driver due to an unexpected variable, the communication abnormal state can be restored to a normal state at a desired time, thereby preventing a communication failure.

[0067] Figure 4 1 is a diagram for describing a configuration protocol of a display device according to an embodiment. In the following, for the convenience of description, a case where communication is performed between a timing controller and a source driver will be taken as an example for description.

[0068] Reference Figure 4 , the source driver can receive a communication signal having a format of leading data PREAMBLE, start data START, configuration data CFG_DATA, end data END and configuration completion data CFG_DONE from the timing controller TCON in the configuration mode. The configuration data CFG_DATA may include a limited data packet DATA 1 To DATA N The length of the packet header CFG[7:0].

[0069] The configuration data CFG_DATA may have the following format: header CFG[7:0], data packet DATA 1 To DATA N And checksum CHECK_SUM[7:0].

[0070] The packet header CFG[7:0] can limit the data packet DATA currently being exchanged 1 To DATA N In addition, the header CFG[7:0] may define the total number of the configuration data CFG_DATA sequence CFG_DATA[1] to CFG_DATA[N]. In addition, the header CFG[7:0] may define whether the checksum CHECK_SUM[7:0] is activated.

[0071] As an example, the packet header CFG[7:0] may include 8 bits, and the [0] bit of the packet header CFG[7:0] may be used for synchronization, and the [3:1] bits of the packet header CFG[7:0] may be used to define the data packet DATA currently being exchanged. 1 To DATA N The [6:4] bits of the header CFG[7:0] can be used to define the total number of the configuration data CFG_DATA sequence CFG_DATA[1] to CFG_DATA[N]. In addition, the [7] bit of the header CFG[7:0] can define whether the checksum CHECK_SUM[7:0] is activated.

[0072] First, in the configuration mode, the source driver may receive preamble data PREAMBLE that continuously switches between a 0 level and a 1 level.

[0073] Next, when the source driver continuously receives the leading data PREAMBLE within a predetermined time period, the source driver may send a lock signal RX_LOCK indicating that the source driver is ready to receive the configuration data CFG_DATA to the timing controller TCON. As an example, the source driver may provide the lock signal RX_LOCK by switching from a low level to a high level.

[0074] Next, the timing controller TCON may transmit start data START, configuration data CFG_DATA, end data END, and configuration completion data CFG_DONE to the source driver in response to the lock signal RX_LOCK. Here, the start data START may be set to a level "0011", and the end data END may be set to a level "1100".

[0075] Next, after receiving the end data END '1100', the source driver may receive the configuration completion data CFG_DONE which continuously switches between a 0 level and a 1 level.

[0076] Next, when the source driver receives the configuration completion data CFG_DONE within a predetermined time period, the source driver may perform a pre-clock training, an equalizer training, or a display mode according to the configuration data CFG_DATA.

[0077] Figure 5 is a diagram for describing a scrambling protocol of a display device according to one embodiment.

[0078] The timing controller TCON may scramble the transmission data into a pseudo-random binary sequence (PRBS) using a linear feedback shift register (LFSR), and the timing controller TCON may include the PRBS in a communication signal and transmit the communication signal to the source driver SDIC. The transmission data may include at least one of a control data packet, image data, and a data checksum.

[0079] As an example, the timing controller TCON may include a scrambler (not shown) for scrambling the transmission data. Scrambling is a process of mixing each bit of the transmission data to be sent, and can prevent the same bit (e.g., 1 or 0) from being placed more than K times in a row in the data transmission stream (where K is a natural number greater than or equal to 2). Scrambling can be performed according to a previously agreed protocol.

[0080] An LFSR is a type of shift register and may have a structure in which the value input to the register is calculated as a linear function of the previous state value. As an example, an LFSR may use an exclusive-OR (XOR) operation as a linear function. Here, the initial bit value of the LFSR may be referred to as a seed, and since the operation of the LFSR is deterministic, the sequence of values ​​generated by the LFSR may be determined by the previous values. In addition, since the number of values ​​that a register can have is limited, the sequence may be repeated at a specific period.

[0081] The timing controller TCON may periodically change the seed value of the LFSR. As an example, the timing controller TCON may change the seed value at a frame interval or a line interval. In addition, the timing controller TCON may use a control data packet to change the seed value. As another example, the timing controller TCON may use at least one of the image data and the data checksum to change the seed value.

[0082] The timing controller TCON may calculate the value of the transmission data input to the LFSR and the state value of the previous transmission data through a linear function to scramble the transmission data.

[0083] In addition, the timing controller TCON may cause the PRBS obtained by scrambling the transmission data to be included in the communication signal, and may transmit the communication signal to the source driver through the communication link.

[0084] The source driver SDIC may receive a communication signal from the timing controller TCON through a communication link, and may descramble the PRBS included in the communication signal into transmission data. In addition, the source driver SDIC may drive the display panel using the transmission data.

[0085] As an example, the source driver SDIC may include a descrambler (not shown) configured to descramble the PRBS into transmission data. The descrambler may perform a function of restoring a data stream in which each bit is mixed with each other to the original data.

[0086] The source driver SDIC may receive the scrambled reset signal in the blank link training period.

[0087] As an example, when the scrambling reset signal ISCR is activated, the source driver SDIC may descramble the PRBS using at least one of a control data packet, image data, and a data checksum that are sent as transmission data of a previous horizontal line.

[0088] As described above, the timing controller TCON may perform the scramble reset at regular intervals, and may change the seed value using at least one of the control data packet, the image data, and the data checksum transmitted as the transmission data each time the scramble reset is performed.

[0089] Then, the source driver SDIC may descramble the PRBS using at least one of the control data packet, the image data, and the data checksum transmitted as the previously transmitted data.

[0090] The timing controller TCON and the source driver SDIC may perform both high-speed data communication and low-speed data communication, and may perform transmission and reception of the above-described control data packet, image data, and data checksum through the high-speed data communication.

[0091] The clock and link are trained during the display period for high-speed data communication, and control data packets, image data, and data checksums may be sent and received according to the trained clock and link.

[0092] In the display mode of the display period, after clock training and link training have been performed, transmission data including control data packets, image data, and data checksum in frame units and line units may be repeatedly transmitted and received.

[0093] Since the transmission data is sent and received by high-speed data communication in the display mode, the receiving rate of the data can be changed according to the setting value for communication. In order to increase the receiving rate and allow high-speed data communication to proceed smoothly, the timing controller TCON and the source driver SDIC can send and receive information for supporting high-speed data communication by low-speed data communication. The description related to this is given by Figure 2 Description instead.

[0094] According to the above-described embodiments, by converting transmission data into a completely random code sequence, the effect of reducing electromagnetic interference (EMI) can be improved.

[0095] In addition, according to the embodiment, a low-order polynomial may be used by controlling a seed value in a method of generating a PRBS using an LFSR, so that the size of a source driver chip may be reduced.

[0096] Figure 6 is a diagram for describing a protocol for defining a location of a configuration package of a display device according to one embodiment.

[0097] The timing controller TCON may transmit a communication signal including a blank pattern H-BLANK and line data LINE DATA to at least one source driver SDIC at a horizontal line interval 1-H.

[0098] The timing controller TCON may cause the configuration packet CFG to be included in the blank pattern H-BLANK, and may place the configuration packet CFG in an end period of the blank pattern H-BLANK.

[0099] As an example, the timing controller TCON may place the configuration packet CFG in the end cycle of the blank pattern H-BLANK that is farthest from the line data LINE DATA of the previous horizontal line. The timing controller TCON may include at least one of clock training, link training, and the configuration packet CFG in the blank pattern H-BLANK. In addition, the timing controller TCON may include at least one of a control data packet, image data, and a data checksum in the line data LINE DATA.

[0100] As another example, when the link lock signal LINK_LOCK fails, the timing controller TCON may include the configuration packet CFG in the end period of the blank pattern H-BLANK after recovering the link lock signal LINK_LOCK by enabling the source output enable signal SOE.

[0101] The source driver SDIC may restore the blank pattern H-BLANK and the line data in the communication signal, and may drive the display panel using the blank pattern H-BLANK and the line data LINE DATA.

[0102] The source driver SDIC may receive the source output enable signal SOE enabled at the horizontal line interval 1-H, and may provide a link lock signal LINK_LOCK indicating a lock failure to the timing controller TCON when a lock failure occurs after the source output enable signal is enabled.

[0103] The source driver SDIC can recover the link with the timing controller TCON using at least one of clock training and link training included in the blank pattern H-BLANK. As an example, the source driver SDIC can recover the PLL clock by performing clock training, and can lock the symbol boundary detection and symbol clock by performing link training.

[0104] The source driver SDIC may provide a link lock signal LINK_LOCK indicating link recovery to the timing controller TCON, and after the link recovery, may receive a configuration packet CFG located at an end period of the blank pattern H-BLANK from the timing controller TCON.

[0105] For example, when the source driver SDIC receives the source output enable signal SOE, the source driver SDIC may perform the following operations: outputting a data voltage corresponding to the image data to the display panel (①).

[0106] Here, the source driver SDIC can simultaneously drive multiple output circuits, each of which corresponds to each channel configured to output a data voltage to a plurality of data lines of the display panel. The output circuit operates in a high voltage region, and due to the operation of the output circuit operating in the high voltage region, high voltage noise can be generated instantaneously (②). The high voltage noise can cause a link failure between the timing controller TCON and the source driver SDIC (③).

[0107] The source driver SDIC can recover the link between the timing controller TCON and the source driver SDIC by performing clock training to recover the PLL clock and performing link training to lock the symbol boundary detection and symbol clock (④).

[0108] After the link is restored, the timing controller TCON may include the configuration packet CFG in the blank pattern H-BLANK end period. A scrambled reset signal may be included in the configuration packet CFG.

[0109] The source driver SDIC may restore at least one of the control data packet, the image data, and the data checksum of the line data LINE DATA in response to the scramble reset signal in the configuration packet CFG.

[0110] When a key data packet such as a scrambled reset signal is affected by high voltage noise, the source driver SDIC may not be able to correctly recover the control data packet, and thus normal driving may not be achieved. However, according to an embodiment, by changing the protocol to properly recover the row data including the control data packet, image data, and data checksum, the configuration packet CFG including the scrambled reset signal can be received after the high voltage noise is stabilized, thereby avoiding the high voltage influence when driving the display panel.

[0111] The operation of the display device as described above will be described in detail below.

[0112] When the display device is powered on, the timing controller TCON can send a clock mode for clock training to the source driver SDIC. The clock mode can be sent by including it in the communication signal. The source driver SDIC receives the clock mode and can train its clock according to the clock mode. In addition, the source driver SDIC can switch the level of the locking signal from a low level to a high level after completing the clock training, and send the locking signal to the timing controller TCON through the feedback link FL.

[0113] The timing controller TCON and the source driver SDIC can perform communication using the PLL mode, and in this way, the source driver SDIC can generate an internal clock according to the frequency and phase of the clock mode, and can use the internal clock to recover the control data packet, image data and data checksum.

[0114] In addition, when the link between the timing controller TCON and the source driver SDIC fails, the display device can perform clock training again. After the clock training is completed, the timing controller TCON can send link data through the communication signal.

[0115] The source driver SDIC can receive link data according to its clock, and can train the link according to the link data. Link training can be performed in the initial stage of data transmission. In addition, when the link between the timing controller TCON and the source driver SDIC fails, link training can be performed again. After the link training is completed, the timing controller TCON can send image data through the communication signal.

[0116] Image data may be sent for each frame. In addition, there may be a vertical blank period between the image data sent for each frame.

[0117] One frame period may include a plurality of horizontal line periods 1-H respectively corresponding to a plurality of horizontal lines of the display panel.

[0118] In addition, the timing controller TCON may send image data corresponding to each horizontal line for each horizontal line period 1-H. As an example, with respect to the timing controller TCON, each horizontal line period 1-H may include a blank pattern transmission period and a row data transmission period. The timing controller TCON may include and send a configuration packet including a scrambled reset signal in a blank pattern during the blank pattern transmission period, and may place the configuration packet at the end period of the blank pattern (i.e., the end period of the blank pattern transmission period), and send the configuration packet to the source driver SDIC.

[0119] In addition, the timing controller TCON may transmit the row data including the control data packet, the image data, and the data checksum to the source driver SDIC during the row data transmission period of the horizontal row period 1-H.

[0120] In addition, in the case of the source driver SDIC, the horizontal line period 1-H may include a blank pattern receiving period and a line data receiving period.

[0121] The source driver SDIC may receive a configuration packet including a scramble reset signal during a blank pattern reception period, and restore row data including a control data packet, image data, and data checksum by using the scramble reset signal during a row data reception period. Here, the source driver SDIC may align the image data according to the data link.

[0122] In addition, the source driver SDIC may convert the image data into corresponding data voltages in response to the control data packet and provide the data voltages to corresponding pixels to drive the display panel.

[0123] As described above, according to the embodiment, the display panel can be stably driven by avoiding the influence of high voltage noise in the display panel driving by using the protocol between the timing controller and the source driver.

[0124] In addition, according to the embodiment, by stably restoring a control data packet lost due to high voltage noise, the display panel can be stably driven.

Claims

1. Display equipment, including: a timing controller configured to transmit a communication signal including a blank pattern and line data at horizontal line intervals; as well as a source driver configured to restore the blank pattern and the row data in the communication signal and drive a display panel using the blank pattern and the row data, The timing controller includes the configuration package in the blank pattern and places the configuration package in the end period of the blank pattern. The source driver receives a source output enable signal enabled at the horizontal line intervals, and when a lock failure occurs after the source output enable signal is enabled, provides a link lock signal indicating the lock failure to the timing controller.

2. The display device according to claim 1, wherein: The timing controller places the configuration packet in the end period of the blank pattern which is farthest from the row data of the previous horizontal row.

3. The display device according to claim 1, wherein: When a failure occurs in a link lock signal, the timing controller includes the configuration packet in the blank pattern after the link lock signal is restored.

4. The display device according to claim 1, wherein: The source driver recovers the communication link through at least one of clock training and communication link training.

5. The display device according to claim 4, wherein: The timing controller includes the configuration packet in the blank pattern after the communication link is restored.

6. The display device according to claim 1, wherein: The source driver recovers at least one of a control data packet, image data, and a data checksum of the row data in response to a scramble reset signal of the configuration packet.

7. A display driving device, comprising at least one source driver, the source driver being configured to restore a blank pattern and line data in a communication signal transmitted at horizontal line intervals, and drive a display panel using the blank pattern and the line data, in, The configuration package is included in the blank pattern, and the configuration package is set to be located in the end period of the blank pattern, The source driver receives a source output enable signal enabled at the horizontal line intervals, and when a lock failure occurs after the source output enable signal is enabled, provides a link lock signal indicating the lock failure to the timing controller.

8. The display driving device according to claim 7, wherein: The configuration packet is set to be located in the end period of the blank pattern which is farthest from the row data of the previous horizontal row.

9. The display driving device according to claim 7, wherein: When a failure occurs in a link lock signal, the configuration packet is arranged to be included in the blank pattern after the link lock signal is restored.

10. The display driving device according to claim 7, wherein: The source driver recovers the communication link through at least one of clock training and communication link training.

11. The display driving device according to claim 10, wherein: The source driver provides the link lock signal indicating recovery of the communication link to the timing controller, and receives the configuration packet in an end period of the blank pattern.

12. The display driving device according to claim 7, wherein: The source driver restores at least one of a control data packet, image data, and a data checksum of the row data in response to a scramble reset signal of the configuration packet.

Images