Lock-free access to ftl table of storage device

Abstract

The application provides a lock-free access method of an FTL table of a storage device, and relates to storage technology. The lock-free access method comprises the following steps: a first task obtains an old value of an address in a first entry of the FTL table and saves the old value, and moves data corresponding to the old value of the address to a first new address; a second task writes data into a second new address and writes the second new address into a second entry of the FTL table; the first task compares the address in the first entry of the FTL table with the saved old value of the address, and determines whether to update the first entry of the FTL table with the first new address according to a comparison result. The lock-free access method provided by the application can reduce resource access conflict problems caused by multi-task concurrent processing, and improve parallelism of task processing of the storage device.

Description

TECHNICAL FIELD

[0001] The present application relates to storage technology, and in particular, to concurrent access to an FTL (Flash Translation Table) table of a storage device in a lock-free manner. BACKGROUND

[0002] Taking a storage device as an example, Figure 1 A block diagram of a storage device is shown. The storage device 102 is coupled to a host to provide storage capability for the host. The host and the solid state storage device 102 can be coupled in various ways, including but not limited to connecting the host and the storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fibre Channel, wireless communication network, etc. The host can be an information processing device capable of communicating with the storage device in the above manners, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103, a control component 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 can be adapted to exchange data with the host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is configured to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110, and is also configured to perform storage management, host logical address to flash physical address mapping, wear leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access data of the DRAM 110. The DRAM can store the FTL table and / or buffered IO command data.

[0006] The control component 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that complies with an interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive results of command execution output from the NVM chip 105. Known NVM chip interface protocols include “Toggle”, “ONFI”, etc.

[0007] A memory target is one or more logical units (LUNs) of a shared CE (Chip Enable) signal within a NAND flash package. A NAND flash package can include one or more dies. Typically, a logical unit corresponds to a single die. A logical unit can include multiple planes. Multiple planes within a logical unit can be accessed in parallel, while multiple logical units within a NAND flash chip can execute commands and report status independently of one another.

[0008] Data is typically stored and read from a storage medium in pages. Data is erased in blocks. A block (also referred to as a physical block) contains multiple pages. A block contains multiple pages. A page (referred to as a physical page) on a storage medium has a fixed size, such as 17664 bytes. Physical pages can also have other sizes.

[0009] In a storage device, a FTL (Flash Translation Layer) is used to maintain mapping information from logical addresses (also referred to as logical page addresses) to physical addresses. The logical addresses constitute the storage space of the solid state storage device as perceived by upper layer software such as an operating system. The physical addresses are addresses used to access physical storage units of the solid state storage device. In the related art, address mapping can also be implemented using an intermediate address form. For example, a logical address is mapped to an intermediate address, and the intermediate address is further mapped to a physical address. A table structure that stores the mapping information from logical addresses to physical addresses is referred to as an FTL table.

[0010] The FTL table is important metadata in a storage device. Typically, the data items of the FTL table record address mapping relationships in the solid state storage device in units of data pages.

[0011] The FTL of some storage devices is provided by a host coupled to the storage device, the FTL table is stored in the memory of the host, and the CPU of the host executes software to provide the FTL. There are also storage management devices provided between the host and the storage device to provide the FTL.

[0012] A cache is provided for the storage device to improve the performance of the storage device. For example, the caches for storage devices are provided in Chinese patent applications 201710219077.1, 201710219096.4, 201710219112.X, and 201811154294.8. The cache can also be provided by the host or the storage management device.

[0013] When a logical page is repeatedly written with data, the FTL table entry records the correspondence between the logical page address and the latest physical page address, and the data recorded in the physical page address that has been written with data but is no longer referenced (for example, not recorded in the FTL table) becomes “garbage” (data). The data that has been written with data and is referenced (for example, recorded in the FTL table) is referred to as valid data, and the “garbage” is referred to as dirty data. A physical block containing dirty data is referred to as a “dirty physical block”, and a physical block that has not been written with data is referred to as a “free physical block”.

[0014] In the garbage collection process, valid data is moved from the dirty physical block to the free physical block. In this process, the physical address of the valid data is obtained from the FTL table, the valid data is read out according to the physical address, a new physical address is allocated in the free physical block, the read valid data is written to the new physical address, and the new physical address is recorded in the FTL table.

[0015] The storage device performs a garbage collection (GC) process to recover invalid data. The method of garbage collection and the storage device are provided in Chinese patent applications 2018115664573 and 2019104502264. Summary of the Invention

[0016] In response to write commands from the host, storage devices update the FTL (Functional Time Limit) entry corresponding to the logical address accessed by the write command, recording the physical address carrying the written data in the FTL entry. Similarly, in response to garbage collection operations, newly allocated physical addresses are written to the FTL entries. Storage devices commonly employ parallel computing techniques to enhance performance, using multiple CPUs, threads, and / or hardware components to handle various tasks, including I / O commands. Consequently, concurrent access to the FTL table for processing write commands and garbage collection operations is frequent.

[0017] When two or more tasks access the same resource (called a critical resource) (e.g., an entry in the FTL table), a conflict occurs, which in turn leaves an incorrect entry in the FTL table or causes an incorrect entry in the FTL table to be used in task processing.

[0018] Typically, critical resources are locked to ensure that access to them is executed serially to avoid conflicts. For example, when a task processing write commands accesses the FTL table, the critical FTL table is locked to prevent other tasks (such as garbage collection tasks) from accessing it at the same time. However, serial access to critical resources also severely impacts the concurrency of task processing and affects the performance of storage devices.

[0019] This problem can be mitigated to some extent by adjusting the granularity of the locked resources. For example, the locking granularity can be set to the entries in the FTL table. This allows host write command processing tasks accessing entry A and garbage collection tasks accessing entry B (different from entry A) to be processed concurrently. However, multiple tasks accessing entries in the same FTL table still need to be processed serially.

[0020] According to a first aspect of this application, a lock-free access method for an FTL table of a first storage device is provided, comprising: a first task obtaining and saving an old value of an address from a first entry in the FTL table, and moving the data corresponding to the old value of the address to a first new address; a second task writing the data to a second new address, and writing the second new address to a second entry in the FTL table; and a first task comparing the address in the first entry of the FTL table with the stored old value of the address, and determining whether to update the first entry of the FTL table with the first new address based on the comparison result.

[0021] According to the lock-free access method of the FTL table of the first storage device of the first aspect of this application, a lock-free access method of the FTL table of the second storage device of the first aspect of this application is provided, wherein the first task is a garbage collection task and the second task is a write command processing task.

[0022] According to the lock-free access method of the FTL table of the first or second storage device of the first aspect of this application, a lock-free access method of the FTL table of the third storage device of the first aspect of this application is provided, wherein, in response to the address in the first entry of the FTL table being different from the old value of the stored address, a first task abandons the current update to the first entry of the FTL table.

[0023] According to one of the lock-free access methods for the FTL table of the first to third storage devices of the first aspect of this application, a lock-free access method for the FTL table of the fourth storage device of the first aspect of this application is provided, wherein, in response to the address in the first entry of the FTL table being the same as the old value of the stored address, a first task writes a first new address into the first entry of the FTL table.

[0024] According to the lock-free access method of the FTL table of the first storage device of the first aspect of this application, a lock-free access method of the FTL table of the fifth storage device of the first aspect of this application is provided, wherein a first task performs the step of comparing the address in the first entry of the FTL table with the old value of the stored address by executing a comparison exchange instruction, and determining whether to update the first entry of the FTL table with a first new address based on the comparison result.

[0025] According to the lock-free access method of the FTL table of the fifth storage device of the first aspect of this application, a lock-free access method of the FTL table of the sixth storage device of the first aspect of this application is provided, wherein the comparison exchange instruction includes a parameter old value, a new value and a destination address; the old address of the address is used as the parameter old value, the first new address is used as the parameter new value, and the address in the first entry of the FTL table is used as the destination address.

[0026] According to the lock-free access method of the FTL table of the fifth or sixth storage device of the first aspect of this application, a lock-free access method of the FTL table of the seventh storage device of the first aspect of this application is provided, wherein if a new value is written to the destination address through the execution of a comparison exchange instruction, a first new address is indicated to be written to the first entry of the FTL table; if a new value is not written to the destination address through the execution of a comparison exchange instruction, a first new address is indicated not to be written to the first entry of the FTL table, and the first entry of the FTL table retains the value written to it by other tasks.

[0027] According to the lock-free access method of the FTL table of the first storage device of the first aspect of this application, a lock-free access method of the FTL table of the eighth storage device of the first aspect of this application is provided, wherein a first task uses the LDREX instruction to obtain the old value of the address from the first entry of the FTL table, moves the data corresponding to the old value of the address to the first new address, and sets a mark for the first entry of the FTL table.

[0028] According to the lock-free access method of the FTL table of the eighth storage device of the first aspect of this application, a lock-free access method of the FTL table of the ninth storage device of the first aspect of this application is provided, wherein the second task uses the STORE instruction to write the second new address into the second entry of the FTL table.

[0029] According to the lock-free access method for the FTL table of the eighth or ninth storage device of the first aspect of this application, a lock-free access method for the FTL table of the tenth storage device of the first aspect of this application is provided, wherein the flag is cleared when the first entry of the FTL table is successfully updated.

[0030] According to one of the lock-free access methods for the FTL table of the eighth to tenth storage devices of the first aspect of this application, a lock-free access method for the FTL table of the eleventh storage device of the first aspect of this application is provided, wherein a first task uses the STREX instruction to write a first new address into the first entry of the FTL table, instead of the step of the first task comparing the address in the first entry of the FTL table with the old value of the stored address, and determining whether to update the first entry of the FTL table with the first new address based on the comparison result.

[0031] According to the lock-free access method of the FTL table of the eleventh storage device of the first aspect of this application, a lock-free access method of the FTL table of the twelfth storage device of the first aspect of this application is provided, wherein if there is a flag set by the LDREX instruction on the first entry of the FTL table, the STREX instruction will successfully update the first entry of the FTL table.

[0032] According to the lock-free access method for the FTL table of the eleventh or twelfth storage device of the first aspect of this application, a lock-free access method for the FTL table of the thirteenth storage device of the first aspect of this application is provided, wherein if there is no flag set by the LDREX instruction on the first entry of the FTL table, the STREX instruction will fail to update the FTL table entry.

[0033] According to the lock-free access method of the FTL table of the first storage device of the first aspect of this application, a lock-free access method of the FTL table of the fourteenth storage device of the first aspect of this application is provided, wherein the method further includes, in response to the second task writing data to the second new address, obtaining the old value of the address from the second entry of the FTL table, recording the old value of the address in a cache container, and locking the second entry of the FTL table.

[0034] According to the lock-free access method of the FTL table of the fourteenth storage device of the first aspect of this application, a lock-free access method of the FTL table of the fifteenth storage device of the first aspect of this application is provided, wherein, before the first task obtains the old value of the address from the first entry of the FTL table, if it is detected that the first entry of the FTL table is locked, the step of obtaining and saving the old value of the address from the first entry of the FTL table and moving the data corresponding to the old value of the address to the first new address is not performed.

[0035] According to the lock-free access method of the FTL table of the fourteenth or fifteenth storage device of the first aspect of this application, a lock-free access method of the FTL table of the sixteenth storage device of the first aspect of this application is provided, wherein, before the first task obtains the old value of the address from the first entry of the FTL table, if it is detected that the first entry of the FTL table is not locked, the step of obtaining the old value of the address from the first entry of the FTL table and saving it, and moving the data corresponding to the old value of the address to the first new address is performed.

[0036] According to one of the lock-free access methods for the FTL table of the fourteenth to sixteenth storage devices of the first aspect of this application, a lock-free access method for the FTL table of the seventeenth storage device of the first aspect of this application is provided, wherein, after writing data to a second new address in a second task and writing the second new address to a second entry of the FTL table, the lock on the second entry of the FTL table is released.

[0037] According to a second aspect of this application, a lock-free access method for an FTL table of a first storage device according to the second aspect of this application is provided, comprising: in response to receiving a write command, if the logical address accessed by the write command overlaps with the logical address range of a logical address barrier record, temporarily storing the write command without initiating processing of the write command; a first task obtaining the old value of an address from a first entry of the FTL table, and writing the data corresponding to the old value of the address into a first new address; and a first task comparing the address in the first entry of the FTL table with the stored old value of the address, and determining whether to update the first entry of the FTL table with the first new address based on the comparison result.

[0038] According to the lock-free access method of the FTL table of the first storage device of the second aspect of this application, a lock-free access method of the FTL table of the second storage device of the second aspect of this application is provided, wherein, in response to a new write command, if the logical address accessed by the write command does not overlap with the logical address range of the logical address barrier record, then processing of the write command begins.

[0039] According to the lock-free access method for the FTL table of a first or second storage device of the second aspect of this application, a lock-free access method for the FTL table of a third storage device of the second aspect of this application is provided, wherein, in response to the address in the first entry of the FTL table being different from the old value of the stored address, a first task abandons the current update to the first entry of the FTL table.

[0040] According to one of the lock-free access methods for the FTL table of the first to third storage devices of the second aspect of this application, a lock-free access method for the FTL table of the fourth storage device of the second aspect of this application is provided, wherein, in response to the address in the first entry of the FTL table being the same as the old value of the stored address, a first task writes a first new address into the first entry of the FTL table.

[0041] According to one of the lock-free access methods for the FTL table of the first to fourth storage devices of the second aspect of this application, a lock-free access method for the FTL table of the fifth storage device of the second aspect of this application is provided, wherein a first task performs the step of comparing the address in the first entry of the FTL table with the old value of the stored address by executing a comparison exchange instruction, and determining whether to update the first entry of the FTL table with a first new address based on the comparison result.

[0042] According to the lock-free access method for the FTL table of the fifth storage device of the second aspect of this application, a lock-free access method for the FTL table of the sixth storage device of the second aspect of this application is provided, wherein the comparison exchange instruction includes a parameter old value, a new value, and a destination address; the old value of the address is used as the parameter old value, the first new address is used as the parameter new value, and the address of the first entry in the FTL table is used as the destination address.

[0043] According to one of the lock-free access methods for the FTL table of the first to sixth storage devices of the second aspect of this application, a lock-free access method for the FTL table of the seventh storage device of the second aspect of this application is provided, wherein, in response to the received first write command being a lowercase command to write data to an incomplete logical page, the first write command is sent to a write command processing task utilizing a cache to begin processing the write command.

[0044] According to the lock-free access method of the FTL table of the seventh storage device of the second aspect of this application, a lock-free access method of the FTL table of the eighth storage device of the second aspect of this application is provided, which further includes: in response to receiving a first write command, using a cached write command processing task to lock the second entry of the FTL table to be accessed by the first write command, and in response to successful locking, obtaining the old value of the address from the second entry of the FTL table.

[0045] According to the lock-free access method of the FTL table of the seventh or eighth storage device of the second aspect of this application, a lock-free access method of the FTL table of the ninth storage device of the second aspect of this application is provided, wherein a lock is acquired for the second entry of the FTL table to be accessed by the first write command, and in response to the failure of locking, the old value of the address is obtained from the second entry of the FTL table using cached write command processing.

[0046] According to the lock-free access method of the FTL table of the eighth storage device of the second aspect of this application, a lock-free access method of the FTL table of the tenth storage device of the second aspect of this application is provided, wherein a cache container and a cache unit are allocated for a first write command using a cache write command processing task, the data to be written by the first write command is moved to the allocated cache unit, the index of the allocated cache container is written to the second entry of the FTL table, and the second entry of the FTL table is unlocked.

[0047] According to one of the lock-free access methods for the FTL table of the eighth to tenth storage devices of the second aspect of this application, a lock-free access method for the FTL table of the eleventh storage device of the second aspect of this application is provided, wherein a cached write command processing task is used to fill data into the address range not covered by the first write command, so as to fill the logical page accessed by the first write command, and the first write command is transformed into a normal write command.

[0048] According to the lock-free access method for the FTL table of the eleventh storage device of the second aspect of this application, a lock-free access method for the FTL table of the twelfth storage device of the second aspect of this application is provided, wherein a read command is generated by using a cached write command processing task to read data from an address range not covered by the first write command, and the read data is used to fill the cache unit allocated for the first write command.

[0049] According to the lock-free access method for the FTL table of the eleventh or twelfth storage device of the second aspect of this application, a lock-free access method for the FTL table of the thirteenth storage device of the second aspect of this application is provided, wherein a write command processing task utilizing a cache sends a first write command that has been converted into a normal write command to a write command processing task for data assembly.

[0050] According to the lock-free access method for the FTL table of the thirteenth storage device of the second aspect of this application, a lock-free access method for the FTL table of the fourteenth storage device of the second aspect of this application is provided, wherein a write command processing task utilizing a cache responds to sending a first write command that has completed filling a cache cell to a write command processing task for data assembly, indicating that the first write command processing is complete.

[0051] According to one of the lock-free access methods for the FTL table of the seventh to fourteenth storage devices of the second aspect of this application, a lock-free access method for the FTL table of the fifteenth storage device of the second aspect of this application is provided, wherein, in response to unlocking the second entry of the FTL table by a write command processing task utilizing the cache, the logical address range accessed by the first write command is removed from the address barrier.

[0052] According to one of the lock-free access methods for the FTL table of the first to fifteenth storage devices of the second aspect of this application, a lock-free access method for the FTL table of the sixteenth storage device of the second aspect of this application is provided, wherein, in response to a received second write command being a normal write command for writing data to a complete logical page, the second write command is sent to a write command processing task for data assembly to begin processing the write command, and the write command processing task for data assembly assembles the data to be written by multiple normal write commands into a size acceptable to the programming commands operating the NVM chip.

[0053] According to the lock-free access method for the FTL table of the sixteenth storage device of the second aspect of this application, a lock-free access method for the FTL table of the seventeenth storage device of the second aspect of this application is provided, wherein, in response to the write command processing task for data assembly, the second write command is processed and completed, and the logical address range accessed by the second write command is removed from the address barrier.

[0054] According to the lock-free access method of the FTL table of the sixteenth or seventeenth storage device of the second aspect of this application, a lock-free access method of the FTL table of the eighteenth storage device of the second aspect of this application is provided, wherein the write command processing task for data assembly allocates a physical address for the second write command, and the data carried by the second write command will be written to the allocated physical address location of the NVM chip.

[0055] According to one of the lock-free access methods for the FTL table of the sixteenth to eighteenth storage devices of the second aspect of this application, a lock-free access method for the FTL table of the nineteenth storage device of the second aspect of this application is provided, wherein the write command processing task for data assembly also updates the third entry of the FTL table corresponding to the logical address of the second write command with the allocated physical address, regardless of whether the second entry of the FTL table is locked or whether other tasks are using the third entry.

[0056] According to one of the lock-free access methods for the FTL table of the first to nineteenth storage devices of the second aspect of this application, a lock-free access method for the FTL table of the twentieth storage device of the second aspect of this application is provided, wherein, in response to receiving a first write command, a write command processing task for data assembly allocates a first physical address for the first write command, and the data carried by the first write command is written to the allocated first physical address location of the NVM chip;

[0057] According to one of the lock-free access methods for the FTL table of the sixteenth to nineteenth storage devices of the second aspect of this application, a lock-free access method for the FTL table of the twentieth storage device of the second aspect of this application is provided, wherein, in response to receiving a first write command, a write command processing task for data assembly allocates a first physical address for the first write command, and the data carried by the first write command is written to the allocated first physical address location of the NVM chip; the write command processing task for data assembly further compares the address in the first entry of the FTL table with the old value of the second entry of the FTL table recorded in the cache container, and determines whether to update the second entry of the FTL table with the first physical address based on the comparison result.

[0058] According to the lock-free access method for the FTL table of the twentieth storage device of the second aspect of this application, a lock-free access method for the FTL table of the twenty-first storage device of the second aspect of this application is provided, wherein, in response to the address in the first entry of the FTL table being different from the old value of the second entry of the FTL table recorded in the cache container, the write command processing task for data assembly abandons the current update of the second entry of the FTL table using the first physical address.

[0059] According to the lock-free access method for the FTL table of the twentieth or twentieth eleventh storage device of the second aspect of this application, a lock-free access method for the FTL table of the twentieth twentieth storage device of the second aspect of this application is provided, wherein, in response to the address in the first entry of the FTL table being the same as the old value of the second entry of the FTL table recorded in the cache container, a write command processing task for data assembly writes the first physical address into the second entry of the FTL table.

[0060] According to one of the lock-free access methods for the FTL table of the nineteenth to twenty-second storage devices of the second aspect of this application, a lock-free access method for the FTL table of the twenty-third storage device of the second aspect of this application is provided, wherein a write command processing task for data assembly performs the step of comparing the address in the second entry of the FTL table with the old value of the second entry of the FTL table recorded in the cache container by executing a comparison exchange instruction.

[0061] According to one of the lock-free access methods for the FTL table of the storage device in the second aspect of this application, a lock-free access method for the FTL table of the storage device in the second aspect of this application is provided, wherein the comparison and exchange instruction includes parameters old value, new value and destination address; the old value of the second entry of the FTL table recorded in the cache container is used as the parameter old value, the first physical address is used as the parameter new value, and the address of the second entry of the FTL table is used as the destination address.

[0062] According to one of the lock-free access methods for the FTL table of the sixteenth to twenty-fourth storage devices of the second aspect of this application, a lock-free access method for the FTL table of the twenty-fifth storage device of the second aspect of this application is provided, wherein a write command processing task for data assembly maintains one or more programming units, each programming unit records multiple cache unit indices, each programming unit corresponds to the data size required by the programming command to access the NVM chip, and the cache unit corresponding to the cache unit index recorded by the programming unit provides the programming unit with a command to write to the NVM chip through a programming command.

[0063] According to one of the lock-free access methods for the FTL table of the storage device of the second aspect of this application, a lock-free access method for the FTL table of the storage device of the second aspect of this application is provided, wherein, in response to the programming unit being filled, a write command processing task for data assembly instructs the media interface controller to write the data corresponding to the programming unit to the NVM chip through a programming command.

[0064] According to one of the lock-free access methods for the FTL table of the sixteenth to twenty-sixth storage devices of the second aspect of this application, a lock-free access method for the FTL table of the twenty-seventh storage device of the second aspect of this application is provided, wherein the programming unit includes multiple cache units; in response to receiving a normal write command, a write command processing task for data assembly is allocated to a cache unit, the data to be written by the normal write command is moved to the cache unit, and the cache unit is recorded in the programming unit.

[0065] According to a third aspect of this application, a first storage device according to the third aspect of this application is provided, wherein a controller and a non-volatile memory chip are included, the controller performing the method of the first or second aspect. Attached Figure Description

[0066] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0067] Figure 1 This is a block diagram of a storage device in the prior art;

[0068] Figure 2A This diagram illustrates an access conflict between a write command processing task and a garbage collection (GC) task.

[0069] Figure 2B The flowchart illustrates the concurrent processing of write command processing tasks and garbage collection (GC) tasks;

[0070] Figure 3 A flowchart illustrating the concurrent processing of write command processing tasks and garbage collection (GC) tasks according to embodiments of this application is provided.

[0071] Figure 4 This is a schematic diagram of FTL-managed storage space according to yet another embodiment of this application;

[0072] Figure 5A The top-to-bottom direction in the diagram represents the increasing direction of the logical address space.

[0073] Figure 5B The FTL table of an embodiment of this application is shown;

[0074] Figure 6 A schematic diagram illustrating the unified caching of an embodiment of this application is shown;

[0075] Figure 7A A flowchart illustrating the writing of data to a storage device according to an embodiment of this application is shown;

[0076] Figure 7B A flowchart illustrating the writing of data to a storage device according to yet another embodiment of this application is shown;

[0077] Figures 8A-8D A flowchart illustrating the concurrent processing of write command processing tasks and garbage collection (GC) tasks according to another embodiment of this application is shown;

[0078] Figure 9 A flowchart illustrating the concurrent processing of write command processing tasks and garbage collection (GC) tasks according to yet another embodiment of this application is shown;

[0079] Figure 10A A block diagram of the control components of a storage device according to yet another embodiment of this application is shown;

[0080] Figure 10B A schematic diagram illustrating the unified caching capability of this application in another embodiment is shown;

[0081] Figure 11 This illustration shows an access conflict between a write command processing task and a garbage collection (GC) task according to yet another embodiment of the present application;

[0082] Figures 12A-12C A flowchart illustrating the concurrent processing of write command processing tasks and garbage collection (GC) tasks according to yet another embodiment of this application is shown. Detailed Implementation

[0083] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0084] Figure 2A This diagram illustrates an access conflict between a write command processing task and a garbage collection (GC) task. The storage device's File System Timetable (FTL) consists of multiple entries, each recording a physical address (denoted as PBA). The index (or position) of an entry in the FTL indicates its corresponding logical address. Write command processing and garbage collection (GC) tasks are handled by their respective CPUs. A resource access conflict occurs when both tasks attempt to access the same FTL entry (indicated by PBA 210) simultaneously.

[0085] See Figure 2A The write command processing task needs to access the FTL table once to write the physical address of the NVM chip carrying the written data to the FTL table entry. The GC task also needs to access the FTL table, including reading the physical address from the FTL table entry to read valid data from the NVM chip, and writing a new physical address carrying the valid data to the FTL table entry. If, after the GC task reads the physical address from the FTL table entry but before writing the new physical address, a write command processing task writes a different physical address to that entry, and then the GC task updates that entry in the FTL table again, an error occurs. The physical address written by the write command processing task to the FTL table entry is overwritten, so when accessing that entry again to read data, an incorrect physical address will be read, resulting in incorrect data.

[0086] Figure 2B The flowchart illustrates the concurrent processing of write command processing tasks and garbage collection (GC) tasks.

[0087] As an example Figure 2B In this process, GC tasks and write command processing tasks are processed concurrently, and both need to access entries in the FTL table (for example, see...). Figure 2A (FTL table entry indicated by 210). Figure 2B In the diagram, the downward direction represents the passage of time. Time intervals T1, T2, and T3 occur sequentially.

[0088] At time T1, the GC task retrieves the physical address from FTL table entry 210, and then moves the valid data according to the retrieved physical address, writing the valid data to physical address PBA 220. Before time T2, the write command processing task writes the data indicated by the write command to physical address PBA 240. At time T2, the write command processing task writes physical address PBA 240 to FTL table entry 210. At time T3, the GC processing task writes physical address PBA 220 to FTL table entry 210. At this time, FTL table entry 210 records PBA 220, which overwrites physical address PBA 240, causing the data written by the write command processing task to no longer be readable.

[0089] Using locking can solve the above problems to some extent. At time T1, the GC task locks FTL table entry 210. At time T3, the GC task updates FTL table entry 210 (writes PBA 220 to it) and then releases the lock. Due to the lock, the write command processing task's update of FTL table entry 210 at time T2 will fail until time T3, when the lock is released and the write command processing task can complete the update of FTL table entry 210 (writes PBA 240 to it). Thus, FTL table entry 210 records the physical address PBA 240. Later, when processing read commands, the data written by the write command can be retrieved from PBA 240, while the data written to PBA 220 by the GC task becomes garbage data. This approach can solve the problem of data errors caused by conflicts between the GC task and the write command processing task accessing FTL table entries. However, the cost is that between time T1 and T3, PBA 220 cannot be accessed by other tasks besides the GC task, reducing the parallelism of storage device task processing.

[0090] Figure 3 A flowchart illustrating the concurrent processing of write command processing tasks and garbage collection (GC) tasks according to embodiments of this application is shown.

[0091] As an example Figure 3 In this process, GC tasks and write command processing tasks are processed concurrently, and both need to access entries in the FTL table (denoted as entry C). Figure 3 In the diagram, the downward direction represents the passage of time. Time intervals T1, T2, and T3 occur sequentially.

[0092] At time T1, the GC task retrieves the old value (denoted as old_PBA) of the physical address from FTL table entry C and temporarily saves this value (old_PBA) (step 310). Then, based on the retrieved physical address (old_PBA), it moves the valid data and writes the valid data to the new physical address (denoted as new_PBA_1) (step 320). Before time T2, the write command processing task writes the data indicated by the write command to the new physical address (new_PBA_2) (step 315). At time T2, the write command processing task writes the physical address (new_PBA_2) to FTL table entry C (step 325). It should be noted that, according to the embodiments of this application, when updating the FTL table, the write command processing task does not care whether the accessed FTL table entry C is used by other tasks, such as the GC task; that is, regardless of whether FTL table entry C is used by other tasks, it directly updates the entry C. Therefore, the write command processing task's operation of updating the FTL table will not be blocked by other tasks, but can be processed in parallel with other tasks accessing the FTL table, thereby reducing the possibility and time of write command processing tasks being blocked and improving the performance of the storage device.

[0093] Next, at time T3, the GC task wants to write the physical address (new_PBA_1) into FTL table entry C. According to an embodiment of this application, in step 340, the GC task reads the physical address (currently PBA_new_2) from FTL table entry C and compares it with the old physical address value (old_PBA) saved previously (in step 310). In response to the fact that the old physical address value (old_PBA) is different from the physical address (PBA_new_2) read from entry C, the GC task abandons the current update to FTL table entry C, and step 340 is completed. Optionally, in step 340, if the old physical address value (old_PBA) is the same as the physical address read from entry C, the GC task writes the physical address to be accessed (PBA_new_1) into FTL table entry C, and step 340 is completed. In step 340, the physical address (old_PBA) is read from entry C, the read physical address (old_PBA) is compared with the previously recorded old physical address value (old_PBA), and entry C is updated with the physical address (new_PBA_1) or not updated according to the comparison result. These operations are performed continuously without any other operations accessing entry C being inserted during this period.

[0094] Furthermore, by executing a CAS (Compare And Swap) instruction to complete step 340, it is ensured that the multiple operations in step 340 are executed consecutively without being interrupted by other operations accessing entry C. The CAS instruction includes the old value (old_val), the new value (new_val), and the destination address (addr). The old physical address value (old_PBA) previously saved (in step 310) is used as the old value (old_val), the physical address (new_PBA_1) is used as the new value (new_val), and the address of FTL table entry C is used as the destination address (addr). Optionally, the CAS instruction provides an execution result indicating whether the new value (new_val) has been written to the destination address (addr). According to the embodiments of this application, if the execution of the CAS instruction writes the new value (new_val) to the destination address (addr), it means that between T1 and T3, no other task updates entry C to a different value. Therefore, the GC task's update of entry C in step 340 takes effect, and the physical address to be accessed (new_PBA_1) is written to entry C. If the execution of the CAS instruction does not write the new value (new_val) to the destination address (addr), it means that between T1 and T3, other tasks update entry C to a different value. Therefore, the GC task's update of entry C in step 340 does not take effect, and entry C retains the value written to it by other tasks. Thus, regardless of the execution result of the CAS instruction, the processing in step 340 is completed without further processing based on the execution result of the CAS instruction. This further accelerates the processing of the GC task and improves the performance of the storage device.

[0095] According to another embodiment of this application, instead of using the CAS instruction, the LDREX and STREX instructions of the ARM architecture are used. In step 310, the old value of the physical address (denoted as old_PBA) is obtained from FTL table entry C using LDREX. The valid data is moved based on the obtained physical address (old_PBA) and written to the new physical address (denoted as new_PBA_1) (step 320). Specifically, it is not necessary to separately save the old value of the physical address (old_PBA) obtained from entry C. The ARM processor sets a flag for entry C in response to the execution of the LDREX instruction and uses this flag to handle access conflicts to entry C.

[0096] In step 325, the write command processing task uses, for example, a standard STORE (write memory) instruction (for ARM architecture) to write the physical address (PBA_new_2) to entry C in the FTL table, regardless of whether entry C has been marked by an LDREX instruction. Optionally, the write command processing task updates entry C in step 325 using other instructions and ensures that the update takes effect. If entry C has been marked by an LDREX instruction, that mark will be cleared by any successful update to entry C.

[0097] In step 340, the GC task uses the STREX instruction to attempt to write the physical address (PBA_new_1) into entry C. If entry C has a flag set by the LDREX instruction (meaning that entry C has not been updated since the LDREX instruction read it), the STREX instruction's update of entry C will succeed, and the physical address (PBA_new_1) will be written into entry C. If entry C does not have a flag set by the LDREX instruction (meaning that entry C has been updated since the LDREX instruction read it), the STREX instruction's update of entry C will fail, and the physical address (PBA_new_1) will not be written into entry C.

[0098] By combining the LDREX and STREX instructions, operations on memory addresses (entry C) accessed by other tasks during the execution of these instructions are not blocked, and there is no need to occupy additional memory to store the old value read by the LDREX instruction. Furthermore, regardless of the result of the STREX instruction, step 340 is completed without further processing based on the STREX instruction's result. This further accelerates GC task processing and improves storage device performance.

[0099] Figure 4 This is a schematic diagram of FTL-managed storage space according to yet another embodiment of this application.

[0100] according to Figure 4 In one embodiment, the control unit 410 of storage device 102 provides an FTL (Framework Transfer Layer). The storage device provides a logical address (called LBA) space to the host. The host uses logical addresses to access the storage device. The FTL maps the logical addresses provided by the host to physical addresses.

[0101] According to embodiments of this application, the physical address obtained through FTL mapping is partly the physical address for accessing the NVM chip 105 and partly the physical address for accessing the DRAM 110. Therefore, see... Figure 4 The NVM chip 105 and DRAM 110 provide a storage space 400 managed by the FTL.

[0102] Alternatively, in addition to DRAM 110, other types of memory such as SRAM are also used to provide storage space managed by FTL.

[0103] Understandably, the FTL according to another embodiment of this application is provided by a host coupled to a storage device, or by a storage management device disposed between the host and the storage device.

[0104] FTL is implemented by, for example, software, firmware, and / or hardware as part of an ASIC running in the CPU of the control unit 410.

[0105] Figure 5A This is a schematic diagram of the logical address (LBA) space according to an embodiment of this application. As an example, the logical address space is a contiguous address space. The FTL maintains the logical address space.

[0106] Figure 5A The top-to-bottom direction in the logical address space represents the increasing direction. The logical address space comprises multiple regions of equal size, each called a block. Each entry in the FTL table (also called an FTL entry) records the mapping from blocks in the logical address space to physical addresses. Figure 5A The diagram shows multiple entries in the FTL table, including FTL entry 0, FTL entry 1, ..., FTL entry 5. For example, the size of the logical address space corresponding to each FTL entry could be, for example, 512 bytes, 1KB, or 4KB. The FTL entry is indexed based on its logical address space address. For example, the quotient obtained by dividing the logical address space address by the size of the logical address space corresponding to the FTL entry is the index of the FTL entry.

[0107] Figure 5B An FTL table from an embodiment of this application is shown.

[0108] The FTL table contains multiple FTL entries, each corresponding to one of the small blocks. The value of each FTL entry records either the address of an NVM data frame that provides storage space for the small block or a cache container index. Optionally, the value of an FTL entry can be used to identify whether it indicates an NVM data frame address or a cache container index. For example, FTL entry values ​​greater than a threshold are mapped to NVM data frame addresses, while FTL entry values ​​not greater than the threshold are mapped to cache container indices. As another example, a flag bit can be recorded in the FTL entry to indicate whether the value of the FTL entry indicates an NVM data frame address or a cache container index.

[0109] The FTL table is stored, for example, in DRAM 110 (see also...). Figure 4The FTL calculates the index of the corresponding FTL entry based on the accessed logical address, and obtains the NVM data frame or cache container that provides storage space for the small block from the FTL entry.

[0110] An NVM data frame address is, for example, the physical address of a physical page accessing an NVM chip, the physical address of multiple combined physical pages of an NVM chip (combined physical pages are, for example, physical pages with the same physical page number located on multiple planes of the same logical unit (LUN), or the physical address of a portion of a data unit within a physical page of an NVM chip. A cache container index is, for example, the address of a cache cell in DRAM or the address of a cache cell descriptor. A cache cell is, for example, a segment of storage space in DRAM. A cache cell descriptor is used to describe a cache cell. A cache container is used to record cache cell descriptors.

[0111] Figure 6 A schematic diagram illustrating the unified caching of an embodiment of this application is shown.

[0112] FTL uses a unified cache 620. For example, a unified cache is provided using DRAM, or a cache unit that provides cached data for the unified cache. For example, FTL maps the logical address space to one or more NVM chips 610 and the unified cache 620.

[0113] The storage space of the NVM chip 610 comprises multiple physical blocks. The storage space of the NVM chip 610 is organized into NVM data frames (see block 612). The large block 612 comprises multiple NVM data frames. The size of the NVM data frame is the same as the size of the small block, so that the data stored in the logical address space corresponding to a small block can be recorded in one NVM data frame.

[0114] The storage space of the Unified Cache 620 is organized into cache cells. A cache cell is, for example, a segment of storage space in DRAM. The size of a cache cell is the same as the size of a block, so that the data stored in the logical address space corresponding to a block can be recorded in one cache cell.

[0115] See also Figure 5B The value of the FTL entry records the index of the cache container, which indicates the cache container. The cache unit associated with the cache container can be accessed based on the cache container.

[0116] Return to view Figure 6A cache container describes one or more cache units associated with it. Cache units can be assigned to a cache container, or cache units can have a specified association with a cache container. For example, a cache container records cache unit descriptors for one or more cache units associated with the cache container, and the cache unit descriptors record the address and working status of the cache units.

[0117] Continue reading Figure 6 The values ​​of FTL entries 0, 2, 3, and 4 indicate the NVM data frame address located in the NVM chip 610, while the values ​​of FTL entries 1 and 5 indicate the index of the cache container located in the unified cache 620. Thus, the FTL obtains the FTL entry based on the logical address, and based on the value of the FTL entry, provides the physical address for providing storage space for small blocks in the logical address space.

[0118] Figure 7A A flowchart illustrating the writing of data to a storage device according to an embodiment of this application is shown.

[0119] The storage device receives a write command from the host, which specifies a logical address (710). The storage device's control unit queries the FTL table (712) based on the logical address to obtain the physical address corresponding to the logical address.

[0120] Optionally, the write command indicates multiple blocks in the logical address space, and correspondingly, the FTL table is queried based on the logical address of each block to obtain the corresponding physical address. For clarity, in one or more examples below, embodiments according to this application are described using a write command accessing a single block as an example.

[0121] Identify whether the physical address corresponding to the obtained logical address indicates a cache container index (714). If the physical address of the logical address accessed by the write command provided by the FTL is a cache container index, then use the cache container index to access the cache unit of the corresponding cache container to carry the data to be written by the write command (716). Also, record the physical address obtained from the FTL table in step 712 in the cache container.

[0122] If the physical address corresponding to the logical address accessed by the write command provided by the FTL is not a cache container index (714) (for example, it is an NVM data frame address, or other content), then a new cache container is allocated for the logical address (718), and the data to be written by the write command is written to the cache unit (720) of the newly allocated cache container. The index of the newly allocated cache container is also recorded in the FTL entry corresponding to the logical address (722).

[0123] According to embodiments of this application, optionally, data stored in the cache units of cache containers indicated by one or more FTL entries is written to the NVM chip when needed or periodically. In response to the data stored in the cache unit being written to the NVM chip, the cache container index in the FTL entry is replaced with the NVM data frame address of the NVM chip. Thus, until the cache container index recorded in the FTL table entry is modified to indicate the physical address of the data unit of the NVM chip, the FTL table entry always records the cache container index. This means that during this period, if a read or write command is received to access these FTL table entries, the unified cache will be hit, and the cache unit recorded by the cache container index will be used to respond to the read or write command. If the process of writing the data stored in the cache unit to the NVM chip fails, or a power outage occurs, in response to the data in the cache unit not being written to the NVM chip, the physical address recorded in the cache container is written back to the FTL table entry from which the physical address is read, replacing the cache container index in the FTL entry.

[0124] Figure 7B A flowchart illustrating the writing of data to a storage device according to yet another embodiment of this application is shown.

[0125] The storage device receives a write command from the host, which specifies a logical address (730). The storage device's control unit queries the FTL table (732) based on the logical address to obtain the physical address corresponding to the logical address.

[0126] The system identifies whether the physical address corresponding to the obtained logical address indicates a cache container index (734). If the physical address of the logical address accessed by the write command provided by the FTL is a cache container index, it further identifies whether the cache unit of the cache container corresponding to the cache container index is being used (736). The cache unit is being used, for example, data is being written to the cache unit according to other write commands, data is being read from the cache unit, or the control unit is writing data from the cache unit to the NVM chip. If the cache unit is not currently being used, the cache unit is used to carry the data to be written by the write command (738). If the cache unit is currently being used, a new cache unit is allocated to the cache container (740), and the new cache unit is used to carry the data to be written by the write command (742). The physical address obtained from the FTL table in step 732 is also recorded in the cache container.

[0127] If the physical address of the logical address accessed by the write command provided by the FTL is not the cache container index (734) (for example, it is an NVM data frame address, or other content), then a new cache container is allocated for the logical address (744), and the data to be written by the write command is written to the cache unit (746) of the newly allocated cache container. The index of the newly allocated cache container is also recorded in the FTL entry corresponding to the logical address (748).

[0128] The data stored in the cache cells of the cache containers indicated by one or more FTL entries is written to the NVM chip. In response to the data being written to the NVM chip, the cache container index in the FTL entry is replaced with the NVM data frame address of the NVM chip. If the process of writing the data stored in the cache cell to the NVM chip fails, or if a power outage occurs, in response to the data not being written to the NVM chip, the physical address recorded in the cache container is written back to the FTL table entry from which that physical address was read, replacing the cache container index in the FTL entry.

[0129] According to another embodiment of this application, the write command processing task is implemented. Figure 7A or Figure 7B The process is illustrated. Therefore, writing commands to process tasks requires reading the physical address from the FTL table entry and updating the FTL table entry with either the newly allocated physical address or the old physical address.

[0130] Figures 8A-8D A flowchart illustrating the concurrent processing of write command processing tasks and garbage collection (GC) tasks according to another embodiment of this application is shown.

[0131] according to Figures 8A-8D In one embodiment, the write command processing task is based on Figure 7A or Figure 7B The process demonstrated involves handling write commands. GC tasks and write command processing tasks are processed concurrently, and both need to access an entry in the FTL table (denoted as entry C). Figures 8A-8D In the diagram, the downward direction represents the passage of time. Time intervals T0, T1, T2, T3, and T4 appear sequentially.

[0132] See Figure 8A At time T0, the write command processing task retrieves the old value (denoted as old_PBA) of the physical address from FTL table entry C to process the write command (820) (entry C is associated with the logical address accessed by the write command). The old value of the physical address (old_PBA) is recorded in the cache container. Subsequently, before time T2, the write command processing task writes the data indicated by the write command to the new physical address (new_PBA_2) (step 822).

[0133] At time T1, the GC task retrieves the old value (old_PBA) of the physical address from the FTL table entry C and temporarily saves the value (old_PBA) (step 810). Then, based on the retrieved physical address (old_PBA), it moves the valid data and writes the valid data to the new physical address (denoted as new_PBA_1) (step 812).

[0134] At time T2, the write command processing task writes the physical address (new_PBA_2) to FTL table entry C (step 825). It should be noted that, according to one embodiment of this application, as long as the write command processing task confirms that data has been written or will be written to the allocated physical address (new_PBA_2), it does not care whether the accessed FTL table entry C is used by other tasks, such as the GC task, when updating the FTL table. That is, regardless of whether FTL table entry C is used by other tasks, it directly updates entry C. Therefore, the write command processing task's operation of updating the FTL table will not be blocked by other tasks, but can be processed in parallel with other tasks accessing the FTL table, thereby reducing the possibility and time of write command processing task blocking and improving the performance of the storage device.

[0135] Next, at time T3, the GC task wants to write the physical address (new_PBA_1) into FTL table entry C. According to an embodiment of this application, in step 814, the GC task reads the physical address (currently PBA_new_2) from FTL table entry C and compares it with the old physical address value (old_PBA) saved previously (in step 810). In response to the difference between the old physical address value (old_PBA) and the read physical address (PBA_new_2), the GC task abandons the current update to FTL table entry C, thus completing step 814. Optionally, in step 814, if the previously saved old physical address value (old_PBA) is the same as the physical address read from entry C, the GC task writes the physical address to be accessed (new_PBA_1) into FTL table entry C, thus completing step 814. In step 814, the old physical address value (old_PBA) is read from entry C, the old physical address value (old_PBA) is compared with the physical address to be accessed (PBA_new_2), and entry C is updated with the physical address to be accessed (new_PBA_1) or not updated according to the comparison result. These operations are performed continuously without any other operations to access entry C being inserted during the process.

[0136] Furthermore, by executing a CAS (Compare And Swap) instruction to complete step 814, it is ensured that the multiple operations in step 814 are executed consecutively without being interrupted by other operations accessing entry C. The CAS instruction includes the old value (old_val), the new value (new_val), and the destination address (addr). The old physical address value (old_PBA) previously saved (in step 810) is used as the old value (old_val), the physical address (new_PBA_1) is used as the new value (new_val), and the address of FTL table entry C is used as the destination address (addr). Optionally, the CAS instruction provides an execution result indicating whether the new value (new_val) has been written to the destination address (addr). According to the embodiments of this application, if the execution of the CAS instruction writes the new value (new_val) to the destination address (addr), it means that between T1 and T3, no other task updates entry C to a different value. Therefore, the GC task's update of entry C in step 814 takes effect, and the physical address to be accessed (new_PBA_1) is written to entry C. If the execution of the CAS instruction does not write the new value (new_val) to the destination address (addr), it means that between T1 and T3, other tasks update entry C to a different value. This causes the GC task's update of entry C in step 814 to not take effect, and entry C retains the value written to it by other tasks. Therefore, regardless of the execution result of the CAS instruction, the processing in step 814 is completed without further processing based on the execution result of the CAS instruction. This further accelerates the processing of the GC task and improves the performance of the storage device.

[0137] According to another embodiment of this application, instead of using the CAS instruction, the LDREX and STREX instructions of the ARM architecture are used. In step 810, the old value of the physical address (denoted as old_PBA) is obtained from FTL table entry C using LDREX. The valid data is moved based on the obtained physical address (old_PBA) and written to the new physical address (denoted as new_PBA_1) (step 812). Specifically, it is not necessary to separately save the old value of the physical address (old_PBA) obtained from entry C. The ARM processor sets a flag for entry C in response to the execution of the LDREX instruction and uses this flag to handle access conflicts to entry C.

[0138] In step 825, the write command processing task uses, for example, a standard STORE (write memory) instruction for ARM architecture to write the physical address (PBA_new_2) to entry C in the FTL table, regardless of whether entry C is marked by an LDREX instruction. Optionally, the write command processing task updates entry C in step 825 using other instructions and ensures that the update takes effect (e.g., using a STREX instruction). If entry C is marked by an LDREX instruction, that mark will be cleared by any successful update to entry C.

[0139] In step 814, the GC task uses the STREX instruction to attempt to write the physical address (PBA_new_1) into entry C. If entry C has a flag set by the LDREX instruction (meaning that entry C has not been updated since the LDREX instruction read it), the STREX instruction's update of entry C will succeed, and the physical address (PBA_new_1) will be written into entry C. If entry C does not have a flag set by the LDREX instruction (meaning that entry C has been updated since the LDREX instruction read it), the STREX instruction's update of entry C will fail, and the physical address (PBA_new_1) will not be written into entry C.

[0140] Optionally, in step 820, using the LDREX instruction to obtain entry C can also correctly handle concurrent access to entry C.

[0141] By combining the LDREX and STREX instructions, operations on memory addresses (entry C) accessed by other tasks during the execution of these instructions are not blocked, and there is no need to occupy additional memory to store the old value read by the LDREX instruction. Furthermore, regardless of the result of the STREX instruction, step 814 is completed without further processing based on the STREX instruction's result. This further accelerates GC task processing and improves storage device performance.

[0142] See Figure 8B At time T0, the write command processing task retrieves the old value of the physical address (denoted as old_PBA) from FTL table entry C to process the write command (840). Subsequently, before time T3, the write command processing task writes the data indicated by the write command to the new physical address (new_PBA_2) (step 842).

[0143] At time T1, the GC task retrieves the old value (old_PBA) of the physical address from the FTL table entry C and temporarily saves the value (old_PBA) (step 830). Then, based on the retrieved physical address (old_PBA), it moves the valid data and writes the valid data to the new physical address (denoted as new_PBA_1) (step 832).

[0144] Next, at time T3, the GC task wants to write the physical address (new_PBA_1) into FTL table entry C. According to an embodiment of this application, in step 834, the GC task reads the physical address (currently old_PBA) from FTL table entry C, compares it with the old physical address value (old_PBA) saved previously (in step 830). In response to the fact that the previously saved old physical address value (old_PBA) is the same as the physical address (old_PBA) read from entry C, the GC task writes the physical address (currently new_PBA_1) into entry C. The update to FTL table entry C is successful, and step 834 is complete. Optionally, in step 834, if the previously saved old physical address value (old_PBA) is different from the physical address read from entry C (e.g., new_PBA_2), the GC task abandons the current update to FTL table entry C, and step 834 is complete. Multiple operations in step 834 are executed consecutively without any other operations accessing entry C being inserted during this period.

[0145] Furthermore, by executing the CAS (Compare And Swap) instruction to complete step 834, it is ensured that the multiple operations of step 834 are executed consecutively without being interrupted by other access entries C.

[0146] At time T4, the write command processing task writes the physical address (new_PBA_2) to FTL table entry C (step 845). It should be noted that, according to one embodiment of this application, as long as the write command processing task confirms that data has been written or will be written to the allocated physical address (new_PBA_2), it does not care whether the accessed FTL table entry C is used by other tasks, such as the GC task, when updating the FTL table. That is, regardless of whether FTL table entry C is used by other tasks, it directly updates entry C. Therefore, the write command processing task's operation of updating the FTL table will not be blocked by other tasks, but can be processed in parallel with other tasks accessing the FTL table, thereby reducing the possibility and time of write command processing task blocking and improving the performance of the storage device.

[0147] Optionally, a CAS instruction can also be used to complete step 845, wherein the old value (old_val) required by the CAS instruction parameter is the physical address (old_PBA) obtained from FTL table entry C in step 840, and the new value (new_val) of the parameter is the physical address (new_PBA_1).

[0148] According to another embodiment of this application, instead of using the CAS instruction, the LDREX and STREX instructions of the ARM architecture are used. In step 830, the old value of the physical address (denoted as old_PBA) is obtained from FTL table entry C using LDREX. There is no need to separately save the old value of the physical address (old_PBA) obtained from entry C.

[0149] In step 845, the write command processing task uses, for example, a standard STORE (write memory) instruction for ARM architecture to write the physical address (PBA_new_2) to entry C in the FTL table, regardless of whether entry C is marked by an LDREX instruction. Optionally, the write command processing task updates entry C in step 845 using other instructions and ensures that the update takes effect (e.g., using a STREX instruction). If entry C is marked by an LDREX instruction, that mark will be cleared by any successful update to entry C.

[0150] In step 834, the GC task uses the STREX instruction to attempt to write the physical address (PBA_new_1) into entry C. If entry C has a flag set by the LDREX instruction (meaning that entry C has not been updated since the LDREX instruction read it), the STREX instruction's update of entry C will succeed, and the physical address (PBA_new_1) will be written into entry C. If entry C does not have a flag set by the LDREX instruction (meaning that entry C has been updated since the LDREX instruction read it), the STREX instruction's update of entry C will fail, and the physical address (PBA_new_1) will not be written into entry C.

[0151] Optionally, in step 840, using the LDREX instruction to obtain entry C can also correctly handle concurrent access to entry C.

[0152] pass Figure 8A and Figure 8BAs seen in the example, regardless of whether the write command processing task reads FTL table entries (820 and 840) or updates the FTL table (825 and 845), the GC task and the write command processing task access the FTL table entries in the same way, regardless of whether the GC task accesses the same entries first or later. This simplifies the complexity of the write command processing task and the GC task and ensures the parallelism of task processing on the storage device.

[0153] See Figure 8C At time T0, the write command processing task retrieves the old value (denoted as old_PBA) of the physical address from FTL table entry C to process the write command (860), and temporarily saves the value (old_PBA). Subsequently, the write command processing task learns that it should abandon the write command (no longer write its data to the NVM chip) (e.g., because writing data to the new physical address (new_PBA_2) failed) (step 862).

[0154] At time T1, the GC task retrieves the old value (old_PBA) of the physical address from the FTL table entry C and temporarily saves the value (old_PBA) (step 850). Then, based on the retrieved physical address (old_PBA), it moves the valid data and writes the valid data to the new physical address (denoted as new_PBA_1) (step 852).

[0155] Next, at time T3, the GC task wants to write the physical address (new_PBA_1) into FTL table entry C. According to an embodiment of this application, in step 854, the GC task reads the physical address (currently old_PBA) from FTL table entry C and compares it with the old physical address value (old_PBA) saved previously (in step 850). If the physical address read from entry C is the same as the old physical address value (old_PBA) recorded in step 850, the physical address (new_PBA_1) is written into entry C. The GC task's update of FTL table entry C is successful, and step 854 is complete. Optionally, in step 854, if the old physical address value (old_PBA) saved previously (in step 850) is different from the physical address read from FTL table entry C, the GC task abandons the current update of FTL table entry C, and step 854 is complete. Multiple operations in step 854 are executed consecutively without any other operations accessing entry C being inserted during this period.

[0156] Furthermore, by executing the CAS (Compare And Swap) instruction to complete step 854, it is ensured that the multiple operations of step 854 are executed consecutively without being interrupted by other access entries C.

[0157] At time T4, the write command processing task attempts to write the old physical address value (old_PBA) saved in step 860 back to entry C (865) of the FTL table. The write command processing task completes step 865 by executing a CAS (Compare And Swap) instruction. The old value (old_val) required by the CAS instruction parameter is the physical address (old_PBA) obtained from entry C of the FTL table in step 860, the new value required by the CAS instruction parameter is also a physical address (old_PBA), and the destination address (addr) required by the CAS instruction parameter is the address of entry C.

[0158] exist Figure 8C In the example, because entry C was written to the physical address (new_PBA_1) at time T3 (step 864), the CAS operation to update entry C at time T4 (step 865) failed. The processing in step 865 ends here. According to the embodiments of this application, in step 865, the execution result of the CAS instruction is irrelevant; regardless of whether the CAS instruction successfully updates entry C or fails, the processing in step 865 ends here.

[0159] According to another embodiment of this application, instead of using the CAS instruction, the LDREX and STREX instructions of the ARM architecture are used. In steps 850 and 860, the old value of the physical address (denoted as old_PBA) is obtained from FTL table entry C using LDREX. There is no need to separately save the old value of the physical address (old_PBA) obtained from entry C.

[0160] In step 854, the GC task uses the STREX instruction to attempt to write the physical address (PBA_new_1) to entry C. In step 865, the write command processing task uses the STREX instruction to attempt to write the saved physical address (old_PBA) to entry C of the FTL table.

[0161] See Figure 8D At time T0, the write command processing task retrieves the old value (denoted as old_PBA) of the physical address from FTL table entry C to process the write command (880), and temporarily stores this value (old_PBA). Subsequently, before time T3, the write command processing task learns that it is to abandon the write command (no longer write its data to the NVM chip) (e.g., because writing data to the new physical address (new_PBA_2) failed) (step 882).

[0162] At time T1, the GC task retrieves the old value (old_PBA) of the physical address from the FTL table entry C and temporarily saves the value (old_PBA) (step 870). Then, based on the retrieved physical address (old_PBA), it moves the valid data and writes the valid data to the new physical address (denoted as new_PBA_1) (step 872).

[0163] At time T2, the write command processing task attempts to write the old physical address value (old_PBA) saved in step 880 back to entry C (885) of the FTL table. The write command processing task completes step 885 by executing a CAS (Compare And Swap) instruction. The old value (old_val) required by the CAS instruction parameter is the physical address (old_PBA) obtained from entry C of the FTL table in step 880; the new value required by the CAS instruction parameter is also a physical address (old_PBA); and the destination address (addr) required by the CAS instruction parameter is the address of entry C. Figure 8D In step 885, the CAS instruction is executed successfully, and entry C is written to the old value (old_val) of the physical address.

[0164] Next, at time T3, the GC task wants to write the physical address (new_PBA_1) into FTL table entry C. According to an embodiment of this application, in step 874, the GC task reads the physical address (currently old_PBA) from FTL table entry C and compares it with the old physical address value (old_PBA) saved previously (in step 870). If the physical address read from entry C is the same as the old physical address value (old_PBA) recorded in step 870, the physical address (new_PBA_1) is written into entry C. The GC task's update of FTL table entry C is successful, and step 874 is complete. Optionally, in step 874, if the old physical address value (old_PBA) saved previously (in step 870) is different from the physical address read from FTL table entry C, the GC task abandons the current update of FTL table entry C, and step 874 is complete. Multiple operations in step 874 are executed consecutively without any other operations accessing entry C being inserted during this period.

[0165] Furthermore, by executing the CAS (Compare And Swap) instruction to complete step 874, it is ensured that the multiple operations of step 874 are executed consecutively without being interrupted by other access entries C.

[0166] exist Figure 8DIn the example, since entry C was written to the physical address (old_PBA) at time T2 (step 864), the CAS operation at time T3 (step 875) successfully updated entry C. The process in step 885 ends here. According to the embodiments of this application, in step 885, the execution result of the CAS instruction is irrelevant; regardless of whether the CAS instruction successfully updated entry C or not, the process in step 885 ends here.

[0167] pass Figure 8C and Figure 8D As seen in the example, regardless of whether the write command processing task reads FTL table entries (860 and 880) or updates the FTL table (865 and 885), the GC task and the write command processing task access the FTL table entries in the same way, regardless of whether the GC task accesses the same entries first or later. This simplifies the complexity of the write command processing task and the GC task and ensures the parallelism of task processing on the storage device.

[0168] Furthermore, in Figures 8A-8D In the context of GC tasks and write command processing tasks, if both use CAS instructions when updating entry C, then in... Figure 8A and Figure 8B In the scenario where the write command processing task needs to write the newly allocated physical address to entry C, both the GC task and the write command processing task access the FTL table entries in the same way, and in... Figure 8C and Figure 8D In the case where the write command processing task needs to write back the old physical address read from the entry to entry C, both the GC task and the write command processing task access the entries of the FTL table in the same way, which simplifies the complexity of the write command processing task and the GC task and ensures the parallelism of task processing on the storage device.

[0169] Figure 9 A flowchart illustrating the concurrent processing of write command processing tasks and garbage collection (GC) tasks according to yet another embodiment of this application is shown.

[0170] See Figure 9 At time T0, the write command processing task utilizes the cache container to process write commands (920) (according to...). Figure 7A and Figure 7B (The process is shown). The write command processing task retrieves the old value of the physical address (denoted as old_PBA) from FTL table entry C to process the write command, and also locks entry C so that other tasks can no longer access entry C.

[0171] Subsequently, if the GC task at time T1 wants to retrieve the old value (old_PBA) of the physical address from entry C in the FTL table, it needs to first check whether entry C is locked. Figure 9 In the example, since entry C is locked, steps 910, 912 and 914 will not occur.

[0172] Before time T2, the write command processing task writes the data indicated by the write command to the new physical address (new_PBA_2) (step 922). At time T2, the write command processing task writes the physical address (new_PBA_2) to FTL table entry C (step 925) and releases the lock on the entry. If the GC task then wants to retrieve the old value (old_PBA) of the physical address from FTL table entry C, since entry C is not locked, steps 910, 912, and 914 will occur. In step 910, the GC task retrieves the old value (old_PBA) of the physical address from entry C and temporarily saves it. Then, based on the retrieved physical address (old_PBA), it performs the transfer of valid data, writing the valid data to the new physical address (denoted as new_PBA_1) (step 912). Next, at time T3, the GC task attempts to write the physical address (new_PBA_1) to FTL table entry C (step 914). According to an embodiment of this application, in step 914, the GC task reads the physical address from FTL table entry C and compares it with the old physical address value (old_PBA) previously saved (in step 910). If the previously saved old physical address value (old_PBA) is the same as the physical address read from entry C, the GC task writes the physical address (currently new_PBA_1) into entry C. The update to FTL table entry C is successful, and step 914 is complete. Optionally, in step 914, if the previously saved old physical address value (old_PBA) is different from the physical address read from entry C (e.g., new_PBA_2), the GC task abandons the current update to FTL table entry C, and step 914 is complete. Multiple operations in step 914 are executed consecutively without any other operations accessing entry C being inserted during this period.

[0173] Furthermore, by executing the CAS (Compare And Swap) instruction to complete step 914, it is ensured that the multiple operations of step 914 are executed consecutively without being interrupted by other access entries C.

[0174] Continue reading Figure 9 If write command processing tasks do not utilize a cache container to process write commands (930) (according to) Figure 3(The process is shown). The write command processing task writes the data to be written to the allocated physical address (denoted as new_PBA_2) (930), and then the write command processing task writes the physical address (new_PBA_2) to FTL table entry C (step 935). It should be noted that in step 935, when the write command processing task updates the FTL table, it does not care whether the accessed FTL table entry C is used by other tasks, such as the GC task; that is, regardless of whether FTL table entry C is used by other tasks, it directly updates the entry C.

[0175] Figure 10A A block diagram of the control components of a storage device according to yet another embodiment of this application is shown.

[0176] See also Figure 1 The control unit 104 includes a host interface 103 coupled to the host and a media interface controller 106 coupled to the NVM chip. The control unit also includes one or more CPUs, on which programs provide multiple tasks (or task processing units) for processing I / O commands of the storage device. Figure 10A The diagram illustrates two command parsing tasks (1010 and 1012), two cached write command processing tasks (1020 and 1022), and two write command processing tasks for data assembly (1030 and 1032). In addition to being implemented as programs running on the CPU, one or more tasks are also implemented as hardware circuitry. Understandably, the control unit of the storage device can provide one or more parsing tasks, one or more cached write command processing tasks, and one or more write command processing tasks for data assembly. For simplicity, "command parsing tasks (1010 and 1012)" will be understood as either of the two command parsing tasks, "cached write command processing tasks (1020 and 1022)" will be understood as either of the two cached write command processing tasks, and "write command processing tasks for data assembly (1030 and 1032)" will be understood as either of the two write command processing tasks for data assembly.

[0177] The command parsing task is used to obtain commands provided by the host to the storage device from host interface 103. A write command indicates that data should be written to one or more logical pages. When a write command indicates that data should be written to multiple logical pages, the command parsing task further breaks the write command into multiple subcommands, each writing data to one logical page. For simplicity, unless otherwise specified, a write command will be referred to below as a command to write data to a single logical page.

[0178] Logical pages are, for example, 4KB in size. Some write commands instruct data to be written to a portion (e.g., 2KB) of the 4KB logical address space. Write commands that write data to an incomplete logical page are called lowercase commands, while write commands that write data to a complete logical page are called normal write commands. Command parsing tasks (1010 and 1012) send lowercase commands to cached write command processing tasks (1020 and 1022), while sending normal write commands randomly or in turn to write command processing tasks used for data assembly (1030 and 1032).

[0179] because Figure 10A In this embodiment, there are two write command processing tasks (1020 and 1022) utilizing a cache, and two write command processing tasks (1030 and 1032) for data assembly. These tasks may conflict when processing two or more write commands accessing the same logical address. To avoid conflicts, command parsing tasks (1010 and 1012) also provide a logical address barrier to record the logical address ranges accessed by each write command sent to the write command processing tasks utilizing a cache and the write command processing tasks for data assembly. When a command parsing task receives a new write command, and the logical address accessed by this write command overlaps with the logical address range recorded by the logical address barrier, processing of the new write command is paused until either the write command processing task utilizing a cache or the write command processing task for data assembly reports that the write command processing is complete. The logical address range accessed by the completed write command is then removed from the address barrier, and the new write command is sent to either the write command processing task utilizing a cache or the write command processing task for data assembly, with its accessed logical address range recorded in the logical address barrier. Chinese patent application No. 2017105235581 provides a logical address barrier. The entire contents of the patent application are incorporated herein by reference. Due to the presence of the logical address barrier, multiple write command processing tasks utilizing cache and multiple write command processing tasks for data assembly, processed simultaneously, will not access overlapping logical addresses.

[0180] The cached write command processing tasks (1020 and 1022) respond to a received lowercase command by allocating a cache container and cache unit for the lowercase command and moving the data to be written by the lowercase command to the cache unit. The cached write command processing tasks (1020 and 1022) also identify the address range within the logical page accessed by the lowercase command that is not covered by the lowercase command. For example, if the lowercase command writes data to the logical address range 1KB-2KB, which is provided by a logical page covering the range 0KB-3KB, then the address range not covered by the lowercase command is 0KB-1KB and 2KB-3KB. The cached write command processing tasks (1020 and 1022) also fill the address range not covered by the lowercase command with data to fill the logical page accessed by the lowercase command. The cached write command processing tasks (1020 and 1022) generate a read command to read data from the address range not covered by the lowercase command and fill the cache unit allocated for the lowercase command with the read data. After the data in the address range not covered by the lowercase command has been read and filled into the cache unit, the lowercase command has effectively become a normal write command. The write command processing tasks (1020 and 1022) that utilize the cache send the lowercase command, which has been converted into a normal write command, to the write command processing tasks (1030 and 1032) used for data assembly.

[0181] The write command processing tasks (1030 and 1032) for data assembly assemble the data to be written by multiple ordinary write commands into a size acceptable to the programming commands operating the NVM chip (called a programming unit). For example, if a programming command writes data to 64 NVM data frames at a time, the write command processing tasks (1030 and 1032) for data assembly assemble the data to be written by an ordinary write command accessing 64 logical pages into a programming unit, and send the programming unit to the NVM chip via a programming command by instructing the media interface controller 106.

[0182] When processing lowercase commands using cached write command processing tasks (1020 and 1022), they also access the FTL table based on the logical address of the lowercase command, retrieve the corresponding physical address (PBA) from the FTL table entry, record it in the allocated cache container, and populate the FTL table entry with the index of the allocated cache container to replace the retrieved physical address (PBA). After the cached write command processing tasks (1020 and 1022) send the lowercase command (converted to a normal write command) that has completed cache filling to the write command processing task (1030 and 1032) for data assembly, they also indicate to the command parsing task (1010 or 1012) that the lowercase command processing is complete. Thus, the command parsing task (1010 or 1012) can indicate to the host that the lowercase command processing is complete.

[0183] After the write command processing task (1030 and 1032) for data assembly completes the processing of the ordinary write command, it also indicates to the command parsing task (1010 or 1012) that the ordinary write command was sent that the processing of the ordinary write command is complete, so that the command parsing task (1010 or 1012) can indicate to the host that the processing of the ordinary write command is complete.

[0184] The write command processing tasks (1030 and 1032) for data assembly also allocate a physical address (PBA) for each ordinary write command. The data carried by the ordinary write command will be written to the assigned physical address (PBA) location on the NVM chip. The write command processing tasks (1030 and 1032) for data assembly also update the FTL table entry corresponding to the logical address of the ordinary write command using the allocated physical address (PBA). Therefore, both cached write command processing tasks (1020 and 1022) and both write command processing tasks (1030 and 1032) for data assembly update the FTL table, which can cause access conflicts to FTL table entries.

[0185] Figure 10B A schematic diagram illustrating the unified caching implementation of this application in another embodiment is shown.

[0186] FTL uses a unified cache 1020. For example, a unified cache can be provided using DRAM, or a cache unit can be used to provide cached data for the unified cache. For example, FTL maps the logical address space to one or more NVM chips 1010 and the unified cache 61020.

[0187] The storage space of the NVM chip 1010 comprises multiple physical blocks. The storage space of the NVM chip 1010 is organized into NVM data frames (see block 1012).

[0188] The storage space of the unified cache 1020 is organized into cache units.

[0189] The value of the FTL entry records the index of the cache container, which indicates the cache container. The cache unit associated with the cache container can be accessed based on the cache container.

[0190] Continue reading Figure 6 The values ​​of FTL entries 0, 2, 3, and 4 indicate the NVM data frame address located in NVM chip 1010, while the values ​​of FTL entries 1 and 5 indicate the index of the cache container located in unified cache 1020. Thus, the FTL obtains the FTL entry based on the logical address, and provides the physical address for allocating storage space for small blocks in the logical address space based on the value of the FTL entry.

[0191] Figure 10BIt also demonstrates a write command processing task for data assembly. This write command processing task for data assembly maintains one or more programming units. Figure 10B Two programming units are shown. As an example, each programming unit records multiple cache unit indices. Each programming unit corresponds to the data size required by the programming command to access the NVM chip. The cache unit corresponding to the recorded cache unit index provides the programming unit with the command to be written to the NVM chip via a programming command. In response to receiving a normal write command, the write command processing task for data assembly records the index of the cache unit containing the data to be written by the normal write command in the programming unit. In response to the programming unit being full, the write command processing task for data assembly instructs the media interface controller to write the data corresponding to the programming unit to the NVM chip via a programming command.

[0192] In an alternative implementation, the programming unit includes multiple cache units instead of... Figure 10B The displayed cache unit index. In response to receiving a normal write command, the write command processing task for data assembly allocates a cache unit, moves the data to be written by the normal write command to the cache unit, and records the cache unit in the programming unit.

[0193] Figure 11 A schematic diagram illustrating an access conflict between a write command processing task and a garbage collection (GC) task according to yet another embodiment of this application is shown.

[0194] Write command processing tasks are, for example, write command processing tasks that utilize caching (1020 and 1022, see also...). Figure 10A ) or write command processing tasks used for data assembly (1030 and 1032, see also) Figure 10A ).

[0195] Figure 11 It demonstrates two write command processing tasks that utilize caching, one write command processing task for data assembly, and one garbage collection (GC) task.

[0196] Write command processing tasks and garbage collection (GC) tasks are handled by their respective CPUs. A resource access conflict occurs when two or more tasks attempt to access the same FTL table entry simultaneously (as indicated by PBA 1110).

[0197] See Figure 11The write command processing task utilizing the cache requires two accesses to the FTL table to handle lowercase commands: reading the physical address (PBA) from the FTL table entry and writing the allocated cache container index to the FTL table entry. The write command processing task for data assembly requires one access to the FTL table to handle ordinary write commands, writing the physical address of the NVM chip carrying the written data to the FTL table entry. The GC task, however, requires accessing the FTL table, including reading the physical address from the FTL table entry to read valid data from the NVM chip, and writing the new physical address carrying the valid data to the FTL table entry.

[0198] If a write command processing task writes a new physical address to an entry in the FTL table after the GC task reads the physical address but before writing it to a new physical address, and then the GC task updates that entry in the FTL table again, an error will occur. The physical address of the FTL table entry written by the write command processing task will be overwritten, and when the entry is accessed again to read data, the wrong physical address will be read, resulting in incorrect data.

[0199] Multiple write command processing tasks concurrently updating the same entry in the FTL table can also lead to errors. To avoid such errors, command parsing tasks (1010 and 1012, see also...) Figure 10A Logical address barriers are used to prevent multiple write commands accessing the same logical address from being processed concurrently by multiple write command processing tasks. However, this blocking of write commands weakens the concurrency of the control unit in processing write commands, which is detrimental to the performance of the storage device. Therefore, according to the embodiments of this application, in order to avoid errors, the write command processing task notifies the command task to release the logical address corresponding to the write command as early as possible, so as to improve the concurrency of the control unit in processing write commands.

[0200] Figures 12A-12C A flowchart illustrating the concurrent processing of write command processing tasks and garbage collection (GC) tasks according to yet another embodiment of this application is shown. Figures 12A-12C In the diagram, the downward direction represents the way time flows. The times T0, T1, T2, T3, T4, T5, and T6 appear in chronological order.

[0201] The command parsing task sends the received lowercase commands to the write command processing task that utilizes the cache, while sending the regular write commands to the write command processing task used for data assembly. Figures 12A-12CIn the example, lowercase command 1202 and normal write command 1204 access the same logical address (denoted as L1). The command parsing task receives lowercase command 1202 first, and then receives normal write command 1204. In response to receiving lowercase command 1202, the command parsing task sends lowercase command 1202 to the write command processing task utilizing the cache, and records the logical address L1 in the logical address barrier. Because logical address L1 exists in the logical address barrier, the command parsing task suspends processing of normal write command 1204. Understandably, if a write command accesses another logical address that does not conflict with the logical address, the command parsing task can send it to the write command processing task utilizing the cache or the write command processing task used for data assembly. The entry C in the FTL table is associated with logical address L1.

[0202] The garbage collection (GC) task retrieves the old value (old_PBA) of the physical address from FTL table entry C and temporarily stores this value (old_PBA). Then, based on the retrieved physical address (old_PBA), it moves the valid data to a new physical address (denoted as new_PBA_1). Next, the GC task attempts to write this new physical address (new_PBA_1) to FTL table entry C.

[0203] See Figure 12A In step 1210, the garbage collection (GC) task needs to first check whether the entry C to be accessed is locked. Figure 12A In the example, since entry C is locked, subsequent operations in step 1210, as well as steps 1212 and 1214, will not occur. Optionally or further, the garbage collection (GC) task also checks whether the cache container index has been written to the entry C to be accessed. If the cache container index has been written to entry C, subsequent operations in step 1210, as well as steps 1212 and 1214, will also not occur. However, if entry C records a physical address and is not locked, subsequent operations in step 1210, as well as steps 1212 and 1214, will occur.

[0204] If step 1214 occurs, in step 1214, the GC task attempts to write the physical address (new_PBA_1) into FTL table entry C. According to an embodiment of this application, in step 1214, the GC task reads the physical address from FTL table entry C and compares it with the old physical address value (old_PBA) previously saved (in step 1210). In response to the previous saved old physical address value (old_PBA) being the same as the physical address read from entry C, the GC task writes the physical address (currently new_PBA_1) into entry C, and the current update to FTL table entry C is successful, thus completing step 1214. Optionally, in step 1214, if the previous saved old physical address value (old_PBA) is different from the physical address read from entry C (e.g., new_PBA_2), the GC task abandons the current update to FTL table entry C, thus completing step 1214. Multiple operations in step 1214 are executed consecutively without any other operations accessing entry C being inserted during this period.

[0205] Optionally, step 1214 can be completed by executing a CAS (Compare And Swap) instruction.

[0206] In step 1220, in response to receiving a lowercase command (at time T0), the cached write command processing task locks the FTL entry C to process the lowercase command. In response to successful locking, the old value of the physical address (denoted as old_PBA) is retrieved from the FTL table entry C (at time T1), and this value (old_PBA) is recorded in the cache container. The cached write command processing task allocates a cache container and cache unit for the lowercase command, and fills the allocated cache unit with the data to be written by the lowercase command. At time T2, the cached write command processing task also writes the index of the allocated cache container into the FTL table entry C to replace the old value of the physical address (old_PBA), and notifies the command parsing task that the lowercase command has been submitted (or processed). In response, the command parsing task deletes the logical address L1 recorded for the lowercase command in the address barrier, and the command parsing task can continue processing the ordinary write command 1204 and send it to the write command processing task for data assembly.

[0207] According to an embodiment of this application, in step 1220, in response to the completion of the operation of updating FTL table entry C with the index of the allocated cache container, entry C is unlocked (at time T2). The locking and unlocking operations of entry C using the cache write command processing task occur between time T1 and time T2. The required operations include obtaining the old value (old_PBA) of the physical address from entry C and writing the cache container to entry C. This interval is very short, thereby minimizing the locking time of entry C and reducing the impact on the concurrency performance of the storage device.

[0208] In step 1220, if locking entry C fails, the cached write command processing task attempts to lock entry C again until the locking succeeds.

[0209] Next, the write command processing task using the cache also fills the portion of the cache cell not covered by the data to be written by the lowercase command (1222). The write command processing task using the cache generates a read command based on the logical address accessed by the lowercase command to read data from the address range not covered by the lowercase command (corresponding to the portion of the cache cell not covered by the data to be written), and fills the cache cell allocated for the lowercase command with the read data.

[0210] Once the data in the address range not covered by the lowercase command has been read and filled into the cache, the lowercase command has effectively become a normal write command. The write command processing task utilizing the cache then sends this normal write command to the write command processing task used for data assembly.

[0211] At time T3, the command parsing task sends the ordinary write command 1204 to the write command processing task for data assembly, and records the logical address L1 for the ordinary write command in the logical address barrier. In response to receiving the ordinary write command (at time T3), the write command processing task for data assembly allocates a new physical address (denoted as new_PBA_2) for the ordinary write command to carry the data to be written by the ordinary write command, and also assembles the data to be written by the ordinary write command (1230). At time T4, the write command processing task for data assembly also notifies the command parsing task that the ordinary write command 1204 has been submitted (or processed successfully). In response, the command parsing task deletes the logical address L1 recorded for the ordinary write command in the address barrier; at time T5, the write command processing task for data assembly also writes the new physical address (new_PBA_2) into the FTL table entry C (1232).

[0212] Understandably, the write command processing task for data assembly notifies the command parsing task that the ordinary write command 1204 has been submitted, which may occur simultaneously with or in a different order than updating FTL entry C. The write command processing task for data assembly updates entry C with a new physical address (new_PBA_2), regardless of whether entry C is locked or whether other tasks are using entry C.

[0213] The write command processing task for data assembly responds to assembling the data to be written by multiple ordinary write commands into a programming unit, and provides the assembled programming unit and its physical address to the media interface controller to write the programming unit (1238) to the NVM chip.

[0214] The write command processing task used for data assembly also receives a normal write command (1234) provided by the write command processing task using the cache. In response, it also allocates a new physical address (denoted as new_PBA_3) for the normal write command and assembles the data to be written by the normal write command.

[0215] In response to the normal write command being received from a write command processing task utilizing a cache, the write command processing task for data assembly also retrieves the old physical address (old_PBA) from the cache container associated with the normal write command, and writes the allocated new physical address (new_PBA_3) to entry C while the value of entry C is still the old physical address (old_PBA). However, in Figure 12A In the example, because the write command processing task for data assembly updates entry C to the physical address (new_PBA_2) at time T5, the value of entry C at time T6 is different from the old physical address (old_PBA), thus the update to entry C is abandoned in step 1236. Figure 12A In this case, indicated by the "X" next to T6, the assembly of the data to be written for the normal write command in step 1234 is also cancelled. Optionally, the assembly of the data to be written for the normal write command occurs after determining whether the value of entry C is equal to the old physical address (old_PBA) at time T6, so that no assembly operation is performed based on the fact that the value of entry C is different from the old physical address (old_PBA).

[0216] Further, in step 1236, a CAS (Compare And Swap) instruction is executed to ensure that while the value of entry C is still the old physical address (old_PBA), the allocated new physical address (new_PBA_3) is written to entry C. The CAS instruction includes the parameter old value (old_val), the new value (new_val), and the destination address (addr). The old physical address value (old_PBA) saved from the cache container is used as the parameter old value (old_val), the physical address (new_PBA_3) is used as the parameter new value (new_val), and the address of FTL table entry C is used as the destination address (addr).

[0217] Optionally, the CAS instruction provides an execution result indicating whether the new value (new_val) has been written to the destination address (addr). According to an embodiment of this application, if the execution of the CAS instruction writes the new value (new_val) to the destination address (addr), it means that between T1 and T6, no other task updates entry C to a different value, thus the update of entry C in step 1236 takes effect, the physical address to be accessed (new_PBA_3) is written to entry C, and the assembly of data for the ordinary write command also takes effect. If the execution of the CAS instruction does not write the new value (new_val) to the destination address (addr), it means that between T1 and T6, other tasks update entry C to a different value, and in response, the assembly of data for the ordinary write command also does not take effect.

[0218] See Figure 12B In step 1240, at time T0, the garbage collection (GC) task needs to first check whether the entry C to be accessed is locked. Figure 12B In the example, since entry C is not locked, the garbage collection (GC) task retrieves the old value (old_PBA) of the physical address from entry C in the FTL table and temporarily stores this value (old_PBA) (1240). Then, based on the retrieved physical address (old_PBA), it moves the valid data and writes the valid data to the new physical address (denoted as new_PBA_1) (step 1242). Next, at time T7, the GC task attempts to write the new physical address (new_PBA_1) to entry C in the FTL table (step 1244).

[0219] exist Figure 12B In the example, at time T3, between time T0 and time T7, the write command processing task uses the cache to write the cache container index to entry C. Therefore, at time T7, the GC task recognizes that the value of entry C is different from the old value recorded in step 1240, and thus, the GC task abandons the update of entry C (1244). Optionally, if the GC task recognizes at time T7 that the value of entry C is the same as the old value recorded in step 1240, then the GC task completes the update of entry C (1244).

[0220] Optionally, step 1244 is completed by executing a CAS (Compare And Swap) instruction to ensure that the allocated new physical address (new_PBA_1) is written to entry C while the value of entry C is still the old physical address (old_PBA). The saved old physical address value (old_PBA) obtained from entry C is used as the old value of the parameter (old_val), the new physical address (new_PBA_1) is used as the new value of the parameter (new_val), and the address of FTL table entry C is used as the destination address (addr).

[0221] Optionally, the CAS instruction provides an execution result indicating whether the new value (new_val) has been written to the destination address (addr). Figure 12B In the example, the execution of the CAS instruction did not write the new value (new_val) to the destination address (addr) because the old value (old_PBA) of the previously recorded entry C was different from the current value of the entry (cache container index). This means that between T1 and T7, another task updated entry C to a different value. In response, the GC allows the current update to entry C to be abandoned. Optionally, if the execution of the CAS instruction had written the new value (new_val) to the destination address (addr), the current processing of the GC task would have been completed.

[0222] In step 1250, in response to receiving a lowercase command (at time T1), the cached write command processing task locks the FTL entry C to process the lowercase command. In response to successful locking, the old value of the physical address (denoted as old_PBA) is retrieved from the FTL table entry C (at time T2), and this value (old_PBA) is recorded in the cache container. The cached write command processing task allocates a cache container and cache unit for the lowercase command, and fills the allocated cache unit with the data to be written by the lowercase command. At time T3, the cached write command processing task also writes the index of the allocated cache container into the FTL table entry C to replace the old value of the physical address (old_PBA), and notifies the command parsing task that the lowercase command has been submitted (or processed successfully) (at time T4). In response, the command parsing task removes the logical address L1 recorded for the lowercase command from the address barrier, and the command parsing task can continue processing the ordinary write command 1204 and send it to the write command processing task for data assembly.

[0223] According to an embodiment of this application, in step 1250, in response to the completion of the operation of updating FTL table entry C with the index of the allocated cache container, entry C is unlocked (at time T3).

[0224] In step 1250, if locking entry C fails, the cached write command processing task attempts to lock entry C again until the locking succeeds.

[0225] Next, the cached write command processing task also fills the portion of the cache cell (1252) not covered by the data to be written by the lowercase command. After the data in the address range not covered by the lowercase command has been read and filled into the cache cell, the lowercase command has effectively become a normal write command. The cached write command processing task then sends this normal write command to the write command processing task used for data assembly.

[0226] At time T5, the command parsing task sends the ordinary write command 1204 to the write command processing task for data assembly, and records the logical address L1 for the ordinary write command in the logical address barrier. In response to receiving the ordinary write command (at time T3), the write command processing task for data assembly allocates a new physical address (denoted as new_PBA_2) for the ordinary write command to carry the data to be written by the ordinary write command, and also assembles the data to be written by the ordinary write command (1260). At time T6, the write command processing task for data assembly also notifies the command parsing task that the ordinary write command 1204 has been submitted (or processed successfully). In response, the command parsing task deletes the logical address L1 recorded for the ordinary write command in the address barrier; at time T8, the write command processing task for data assembly also writes the new physical address (new_PBA_2) into the FTL table entry C (1262). Optionally, even if the time T7 during which the write command processing task for data assembly writes the new physical address (new_PBA_2) into the FTL table entry C is earlier than time T8, it does not affect the... Figure 12B The processing procedure of the embodiment.

[0227] The write command processing task used for data assembly updates entry C with a new physical address (new_PBA_2), regardless of whether entry C is locked or used by other tasks.

[0228] The write command processing task for data assembly responds to assembling the data to be written by multiple ordinary write commands into a programming unit, and provides the assembled programming unit and its physical address to the media interface controller to write the programming unit (1268) to the NVM chip.

[0229] The write command processing task for data assembly also receives a normal write command (1264) provided by the write command processing task using the cache. In response, it also allocates a new physical address (denoted as new_PBA_3) for the normal write command and assembles the data to be written by the normal write command.

[0230] In response to the normal write command being received from a write command processing task utilizing a cache, the write command processing task for data assembly also retrieves the old physical address (old_PBA) from the cache container associated with the normal write command, and, while the value of entry C is still the old physical address (old_PBA), writes the allocated new physical address (new_PBA_3) into entry C (at time T9, 1266). However, in Figure 12B In the example, because the write command processing task for data assembly updates entry C to the physical address (new_PBA_2) at time T8, the value of entry C at time T9 is different from the old physical address (old_PBA), thus the update to entry C is abandoned in step 1266. Figure 12B In the middle (represented by the "X" next to the mark T9), the assembly of the data to be written for the ordinary write command in step 1264 is also canceled.

[0231] Furthermore, in step 1266, the CAS (Compare And Swap) instruction is executed to ensure that the allocated new physical address (new_PBA_3) is written to entry C while the value of entry C is still the old physical address (old_PBA).

[0232] Optionally, the CAS instruction provides an execution result indicating whether the new value (new_val) has been written to the destination address (addr). According to an embodiment of this application, if the execution of the CAS instruction writes the new value (new_val) to the destination address (addr), it means that between T2 and T9, no other task updates entry C to a different value, thus the update of entry C in step 1266 takes effect, the physical address to be accessed (new_PBA_3) is written to entry C, and the assembly of data for the ordinary write command also takes effect. If the execution of the CAS instruction does not write the new value (new_val) to the destination address (addr), it means that between T2 and T9, there are other tasks that update entry C to a different value, and in response, the assembly of data for the ordinary write command also does not take effect.

[0233] exist Figure 12C In the example, lowercase command 1202 and normal write command 1204 access the same logical address (denoted as L1). The command parsing task receives normal write command 1204 first, and then receives lowercase command 1202. In response to receiving normal write command 1204, the command parsing task sends normal write command 1204 to the write command processing task used for data assembly (at time T1) and records logical address L1 in the logical address barrier. Because logical address L1 exists in the logical address barrier, the command parsing task suspends processing of lowercase command 1202.

[0234] SeeFigure 12C In step 1240, at time T0, the garbage collection (GC) task is triggered, which first needs to check whether the entry C to be accessed is locked. Figure 12C In the example, since entry C is not locked, the garbage collection (GC) task retrieves the old value (old_PBA) of the physical address from entry C in the FTL table and temporarily stores this value (old_PBA) (1270). Then, based on the retrieved physical address (old_PBA), it moves the valid data and writes the valid data to the new physical address (denoted as new_PBA_1) (step 1272). Next, at time T7, the GC task attempts to write the new physical address (new_PBA_1) to entry C in the FTL table (step 1274).

[0235] exist Figure 12C In the example, at time T2, between time T0 and time T7, the write command processing task for data assembly writes a new physical address (new_PBA_2) to entry C. Therefore, at time T7, the GC task recognizes that the value of entry C is different from the old value recorded in step 1270, and thus, the GC task abandons updating entry C (1274). If the GC task recognizes that the value of entry C is the same as the old value recorded when reading entry C (in step 1270) when it is about to update entry C (time T7), then the GC task completes updating entry C (1274). Optionally, step 1274 can be completed by executing a CAS (Compare And Swap) instruction.

[0236] At time T1, the command parsing task sends the ordinary write command 1204 to the write command processing task for data assembly, and records the logical address L1 for the ordinary write command in the logical address barrier. In response to receiving the ordinary write command (at time T1), the write command processing task for data assembly allocates a new physical address (denoted as new_PBA_2) for the ordinary write command to carry the data to be written by the ordinary write command, and also assembles the data to be written by the ordinary write command (1290). Unlike the operation of the write command processing task that uses the cache, the write command processing task for data assembly does not need to access the FTL table entry C or lock the entry C after receiving the ordinary write command.

[0237] Next, at time T2, the write command processing task for data assembly also notifies the command parsing task that the ordinary write command 1204 has been submitted (or processed). In response, the command parsing task deletes the logical address L1 recorded for the ordinary write command in the address barrier. At time T2, the write command processing task for data assembly also writes the new physical address (new_PBA_2) into the FTL table entry C (1292).

[0238] The write command processing task for data assembly updates entry C with a new physical address (new_PBA_2) (1292), regardless of whether entry C is locked or used by other tasks.

[0239] The write command processing task for data assembly responds to assembling the data to be written by multiple ordinary write commands into a programming unit, and provides the assembled programming unit and its physical address to the media interface controller to write the programming unit to the NVM chip (1298).

[0240] At time T2, the command parsing task receives an indication that the write command 1204 has been submitted, deletes the logical address L1 in the logical address barrier, so that it can continue to process the lowercase command 1202, and sends the lowercase command 1202 to the write command processing task for data assembly (at time T3), and records the logical address L1 in the logical address barrier.

[0241] In step 1280, in response to receiving a lowercase command (at time T3), the cached write command processing task locks FTL entry C to process the lowercase command. Upon successful locking, the old value of the physical address (denoted as old_PBA) is retrieved from FTL table entry C (at time T4), and this value (old_PBA) is recorded in the cache container. The cached write command processing task allocates a cache container and cache unit for the lowercase command, and fills the allocated cache unit with the data to be written by the lowercase command. The cached write command processing task also writes the index of the allocated cache container into FTL table entry C to replace the old value of the physical address (old_PBA), and notifies the command parsing task that the lowercase command has been submitted (or processed successfully) (at time T6). In response, the command parsing task deletes the logical address L1 recorded for the lowercase command from the address barrier.

[0242] According to an embodiment of this application, in step 1280, in response to the completion of the operation of updating FTL table entry C with the index of the allocated cache container, entry C is unlocked (at time T5). Optionally, the operation of updating entry C and unlocking entry C using the cached write command processing task may occur before or simultaneously with time T6.

[0243] In step 1280, if locking entry C fails, the cached write command processing task attempts to lock entry C again until the locking succeeds.

[0244] Next, the cached write command processing task also fills the portion of the cache cell not covered by the data to be written by the lowercase command (1282). After the data in the address range not covered by the lowercase command has been read and filled into the cache cell, the lowercase command has effectively become a normal write command. The cached write command processing task then sends this normal write command to the write command processing task used for data assembly.

[0245] The write command processing task for data assembly also receives a normal write command (1294) provided by the write command processing task using the cache. In response, it also allocates a new physical address (denoted as new_PBA_3) for the normal write command and assembles the data to be written by the normal write command.

[0246] In response to the normal write command being received from a write command processing task utilizing a cache, the write command processing task for data assembly also retrieves the old physical address (old_PBA) from the cache container associated with the normal write command, and, while the value of entry C is still the old physical address (old_PBA), writes the allocated new physical address (new_PBA_3) into entry C (time T8, 1296). Figure 12C In the example, the value of entry C at time T8 is the same as the old physical address (old_PBA) obtained at time T4, thus completing the update of entry C in step 1296. Figure 12C In the diagram, it is indicated by the "Y" next to the mark T8.

[0247] Furthermore, in step 1296, the CAS (Compare And Swap) instruction is executed to ensure that the allocated new physical address (new_PBA_3) is written to entry C while the value of entry C is still the old physical address (old_PBA).

[0248] Optionally, the CAS instruction provides an execution result indicating whether the new value (new_val) has been written to the destination address (addr). According to an embodiment of this application, if the execution of the CAS instruction writes the new value (new_val) to the destination address (addr), it means that between time T4 (when the old value of entry C is obtained) and time T8 (when entry C is updated), no other task updates entry C to a different value. Therefore, the update of entry C in step 1296 takes effect, the physical address to be accessed (new_PBA_3) is written to entry C, and the assembly of data for the ordinary write command also takes effect. If the execution of the CAS instruction does not write the new value (new_val) to the destination address (addr), it means that between time T4 and time T8, another task updates entry C to a different value. In response, the assembly of data for the ordinary write command also does not take effect.

[0249] Therefore, according to the embodiments of this application, the command parsing task, the GC task, the write command processing task utilizing the cache, and the write command processing task for data assembly are processed concurrently. The command parsing task sends lowercase commands to the write command processing task utilizing the cache and ordinary write commands to the write command processing task for data assembly. Before sending a write command, the command parsing task checks the logical address barrier and determines that the logical address range recorded in the logical address barrier is not sufficient for the logical address accessed by the write command before sending the write command to either the write command processing task utilizing the cache or the write command processing task for data assembly. After sending the write command to either the write command processing task utilizing the cache or the write command processing task for data assembly, the command parsing task also records the logical address accessed by the write command in the logical address barrier. The write command processing task utilizing the cache or the write command processing task for data assembly each indicates to the command parsing task that the write command has been submitted at an appropriate time. In response, the command parsing task deletes the logical address corresponding to the submitted write command from the logical address barrier.

[0250] When a GC task accesses an FTL table entry, it checks for locks and only accesses the entry and performs subsequent data migration operations if the entry is not locked. The cached write command processing task handles lowercase commands and locks the accessed FTL table entry before acquiring it, updating it with the allocated cache container index, and then releasing the lock. The data assembly write command processing task handles ordinary write commands. Ordinary write commands may originate from the command parsing task or from the cached write command processing task. When an ordinary write command originates from the command parsing task, the data assembly write command processing task allocates a physical address for the ordinary write command, assembles the data to be written, and writes the allocated physical address to the FTL table entry corresponding to the logical address of the write command, regardless of whether the entry is locked or accessed by other tasks.

[0251] When a regular write command originates from a write command processing task utilizing a cache, the write command processing task for data assembly allocates a physical address (new_PBA) for the regular write command, assembles the data to be written, and retrieves the old physical address (old_PBA) recorded in the cache container associated with the regular write command. Only if the current value of the FTL table entry corresponding to the logical address of the same write command is the same as the old physical address (old_PBA) will the allocated new physical address (new_PBA) be written to the FTL table entry corresponding to the logical address of the write command. If the current value of the FTL table entry corresponding to the logical address of the same write command is different from the old physical address (old_PBA), the write command processing task for data assembly discards the regular write command, including not updating the FTL table entry corresponding to the logical address of the write command with the new physical address (new_PBA) and not assembling the data to be written by the write command.

[0252] According to embodiments of this application, multiple tasks are processed in parallel, and the locking time for critical resources (entries in the FTL table) is reduced, providing parallelism for task processing and improving the performance of the storage device.

[0253] According to an embodiment of this application, a storage device is also provided, including a controller and a non-volatile memory chip, wherein the controller executes any of the processing methods provided in the embodiments of this application.

[0254] According to embodiments of this application, a program stored on a readable medium is also provided, which, when the controller of the storage device is run, causes the storage device to execute any of the processing methods provided according to embodiments of this application.

[0255] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A lock-free access method for the FTL table of a storage device, characterized in that, include: The first task is to retrieve the old value of the address from the first entry of the FTL table and save it, and then move the data corresponding to the old value of the address to the first new address. The second task writes the data to the second new address, regardless of whether the second entry in the FTL table is used by other tasks. The first task is to compare the address in the first entry of the FTL table with the old value of the stored address, and determine whether to update the first entry of the FTL table with the first new address based on the comparison result. During the update, no other operations that access the first entry are inserted. In response to the address in the first entry of the FTL table being different from the old value of the stored address, the first task abandons the current update to the first entry of the FTL table; In response to the address in the first entry of the FTL table being the same as the old value of the stored address, the first task writes the first new address into the first entry of the FTL table; The first task is a garbage collection task, the second task is a write command processing task, and the first and second entries are the same entries in the FTL table.

2. The method as described in claim 1, characterized in that, The first task is to perform the step of comparing the address in the first entry of the FTL table with the old value of the stored address by executing a comparison-swap instruction, and determining whether to update the first entry of the FTL table with the first new address based on the comparison result.

3. The method as described in claim 2, characterized in that, The comparison and exchange instruction includes an old value, a new value, and a destination address; the old address is used as the old value, the first new address is used as the new value, and the address in the first entry of the FTL table is used as the destination address.

4. The method as described in claim 2 or 3, characterized in that, If the new value is written to the destination address through the execution of the comparison-swap instruction, then the first new address is indicated to be written to the first entry of the FTL table; if the new value is not written to the destination address through the execution of the comparison-swap instruction, then the first new address is indicated not to be written to the first entry of the FTL table, and the first entry of the FTL table retains the value written to it by other tasks.

5. The method as described in claim 1, characterized in that, The first task is to use the LDREX instruction to retrieve the old value of the address from the first entry of the FTL table, move the data corresponding to the old value of the address to the first new address, and set a flag for the first entry of the FTL table.

6. The method as described in claim 5, characterized in that, The second task uses the STORE instruction to write the second new address into the second entry of the FTL table.

7. The method as described in claim 5 or 6, characterized in that, The flag is cleared when the first entry in the FTL table is successfully updated.

8. The method as described in claim 5 or 6, characterized in that, The first task uses the STREX instruction to write the first new address into the first entry of the FTL table, instead of the first task comparing the address in the first entry of the FTL table with the old value of the stored address, and determining whether to update the first entry of the FTL table with the first new address based on the comparison result.

9. The method as described in claim 8, characterized in that, If the first entry in the FTL table contains a flag set by the LDREX instruction, then the STREX instruction will successfully update the first entry in the FTL table.

10. The method as described in claim 8, characterized in that, If the first entry in the FTL table does not contain a flag set by the LDREX instruction, the STREX instruction will fail to update the FTL table entry.

11. The method according to any one of claims 1-3, characterized in that, The second task, in response to writing data to the second new address, also retrieves the old value of the address from the second entry in the FTL table, records the old value of the address in a cache container, and locks the second entry in the FTL table.

12. The method as described in claim 11, characterized in that, Before the first task retrieves the old value of the address from the first entry of the FTL table, if it is detected that the first entry of the FTL table is locked, the step of retrieving and saving the old value of the address from the first entry of the FTL table and moving the data corresponding to the old value of the address to the first new address is not performed.

13. A storage device comprising a controller and a non-volatile memory chip, wherein, The controller performs the method as described in any one of claims 1-12.

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