Display device

Abstract

A display device is provided, comprising: blocks, each block including two or more pixels commonly coupled to a first power line; and a first power voltage controller that determines a margin value of a first power voltage supplied to the first power line based on a load value of the blocks. The first power voltage controller determines the load value based on the grayscale values ​​of the pixels of each block included in the blocks. The magnitude of the first power voltage is determined to decrease as the margin value increases. The margin value includes a first margin value. The first power voltage controller determines the first margin value based on the distribution of load values ​​among the first blocks arranged in a first direction within the blocks.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0169800, filed on December 18, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device and a driving method thereof. More specifically, this disclosure relates to a display device and a driving method thereof in which a minimum electrical voltage is supplied by analyzing the pattern of an image frame. Background Technology

[0003] With the development of information technology, display devices, as the connection medium between users and information, have become increasingly important. Therefore, display devices such as liquid crystal displays, organic light-emitting diode displays, and plasma displays are being used more and more frequently.

[0004] A display device may include multiple pixels and displays image frames by combining light emitted from the pixels. When multiple image frames are displayed sequentially, a user can recognize the image frames as images (moving images or still images).

[0005] The required power voltage varies depending on the pattern of the image frames. Therefore, supplying the same power voltage to all image frames is inefficient in terms of power consumption. Thus, a novel approach is needed to reduce power consumption while improving display quality. Summary of the Invention

[0006] The embodiment provides a display device and a driving method for the display device that can reduce power consumption by analyzing the pattern of image frames to supply a minimum power voltage.

[0007] According to an aspect of this disclosure, a display device is provided, the display device comprising: a plurality of blocks, each block including two or more pixels commonly coupled to a first power line; and a first power voltage controller configured to determine a margin value of a first power voltage supplied to the first power line based on a load value of the plurality of blocks, wherein the first power voltage controller determines the load value based on a grayscale value of a pixel included in each of the plurality of blocks, wherein the magnitude of the first power voltage is determined to decrease as the margin value increases, wherein the margin value includes a first margin value, wherein the first power voltage controller determines the first margin value based on the degree of distribution of the load values ​​of the first blocks arranged in a first direction among the plurality of blocks.

[0008] The display device may further include: a plurality of first power supplies, each of which is coupled to at least one of a plurality of first power sub-lines. The plurality of first power sub-lines may be coupled together to a first power line. The plurality of first power sub-lines may be arranged in a first direction.

[0009] The first power voltage controller can determine the first margin value to become larger as the load value of the first block is distributed more widely in the first direction.

[0010] The first power voltage controller can determine the first margin value to increase as the load value of the first block changes or the standard deviation decreases.

[0011] The first power voltage controller may include multiple distribution lookup tables. The first power voltage controller may select one of the multiple distribution lookup tables based on the degree of distribution. The first power voltage controller may extract a first margin value from the selected distribution lookup table based on the average or maximum load value of the first block.

[0012] The selected distribution lookup table can provide a first margin value that decreases as the average or maximum load value of the first block increases.

[0013] The margin value may also include a second margin value. The plurality of blocks may include a plurality of second blocks arranged in a second direction perpendicular to the first direction. The first power voltage controller can determine the second margin value based on the location of a second block having the maximum value among the load values ​​of the plurality of second blocks.

[0014] The first power voltage controller can determine that the second margin value increases as the location of the second block with the maximum value becomes closer to the plurality of first power sub-lines.

[0015] The first power voltage controller may include multiple location lookup tables. The first power voltage controller can select one of the multiple location lookup tables based on the location of the second block with the maximum value. The first power voltage controller can extract a second margin value from the selected location lookup table based on the average or maximum load value of the multiple second blocks.

[0016] The selected location lookup table can provide a second margin value that decreases as the average or maximum load value of the plurality of second blocks increases.

[0017] The margin value may also include a third margin value. The first power voltage controller can calculate the gray value ratio of segments divided according to the magnitude of the gray value. The first power voltage controller can determine the third margin value based on the largest segment with the largest gray value ratio among the segments with gray value ratios larger than the reference ratio.

[0018] The first power voltage controller can determine the third margin value to decrease as the gray value ratio of the maximum segment increases.

[0019] The first power voltage controller may include multiple segment lookup tables. The first power voltage controller can select the segment lookup table corresponding to the largest segment from among the multiple segment lookup tables. The first power voltage controller can extract a third margin value from the selected segment lookup table based on the grayscale value ratio of the largest segment.

[0020] The selected segment lookup table can provide a third margin value that decreases as the grayscale value ratio of the largest segment increases.

[0021] The first power voltage controller can determine the margin value by adding at least two of the first margin value, the second margin value, and the third margin value.

[0022] The first power voltage controller can determine the load value by summing the grayscale values ​​of the pixels included in each of the plurality of blocks.

[0023] According to another aspect of this disclosure, a method for driving a display device comprising a plurality of blocks, each of the plurality of blocks comprising two or more pixels commonly coupled to a first power line, the method comprising the steps of: determining a load value of the plurality of blocks based on grayscale values ​​of the pixels; determining a margin value of a first power voltage supplied to the first power line based on the load values ​​of the plurality of blocks; and determining the magnitude of the first power voltage to decrease as the margin value increases, wherein the margin value includes a first margin value, wherein determining the margin value includes determining the first margin value to increase as the load value of the first block arranged in a first direction is more widely distributed in the first direction.

[0024] The plurality of blocks may include second blocks arranged in a second direction perpendicular to the first direction. The display device may also include a first power sub-line for supplying a first power voltage to the first power line. The margin value may also include a second margin value. Determining the margin value may further include determining the second margin value as it increases as the position of a second block having the maximum value among the load values ​​of the second block becomes closer to the first power sub-line.

[0025] The margin value may also include a third margin value. Determining the margin value may also include the following steps: calculating the gray value ratio of the segments divided according to the size of the gray value; determining the largest segment with the largest gray value ratio among the segments with a gray value ratio larger than the reference ratio; and determining the third margin value to decrease as the gray value ratio of the largest segment increases.

[0026] The margin value can be determined by calculating the margin value obtained by adding at least two of the first margin value, the second margin value, and the third margin value.

[0027] According to another aspect of this disclosure, a display device is provided, the display device comprising: a plurality of first pixels, commonly coupled to a first power line, the plurality of first pixels being coupled to a first group of data lines; a plurality of second pixels, commonly coupled to the first power line, the plurality of second pixels being coupled to a second group of data lines; a first driver unit coupled to the first power line via a first power sub-line, the first driver unit being coupled to the first group of data lines; and a second driver unit coupled to the first power line via a second power sub-line, the second driver unit being coupled to the second group of data lines, wherein, in a first pattern in which X pixels of the plurality of first pixels and Y pixels of the plurality of second pixels are illuminated while the other pixels of the plurality of first pixels and the other pixels of the plurality of second pixels are not illuminated, a first voltage is supplied to the first power line, wherein, in a second pattern in which Z pixels of the plurality of first pixels are illuminated while the other pixels of the plurality of first pixels and all of the plurality of second pixels are not illuminated, wherein the second voltage is higher than the first voltage, wherein X, Y, and Z are any integers greater than 0 and satisfy Z = X + Y.

[0028] X pixels, Y pixels, and Z pixels can all emit light based on the same grayscale value.

[0029] The first brightness when the display device displays the first pattern and the second brightness when the display device displays the second pattern can be equal to each other. Attached Figure Description

[0030] In the following description, exemplary embodiments will be described more fully with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0031] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as "between" two elements, the element may be the only element between the two elements, or there may be one or more intermediate elements. The same reference numerals always denote the same elements.

[0032] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0033] Figure 2This is a diagram illustrating pixels according to an embodiment of the present disclosure.

[0034] Figure 3 This is a diagram illustrating a data driver according to an embodiment of the present disclosure.

[0035] Figure 4 This is a diagram illustrating the arrangement of pixel units and data drivers according to an embodiment of the present disclosure.

[0036] Figure 5 , Figure 6 , Figure 7 and Figure 8 This is a diagram showing an example pattern of an image frame.

[0037] Figure 9 It shows that for Figures 5 to 8 The diagram shows the minimum initial electrical voltage required for the pattern shown.

[0038] Figure 10 This is a diagram illustrating a first power voltage controller according to an embodiment of the present disclosure.

[0039] Figure 11 This is a diagram illustrating a reference block row selector according to an embodiment of the present disclosure.

[0040] Figure 12 , Figure 13 and Figure 14 This is a diagram illustrating a distributed lookup table according to an embodiment of the present disclosure.

[0041] Figure 15 This is a diagram illustrating the arrangement of pixel units and data drivers according to another embodiment of the present disclosure.

[0042] Figure 16 , Figure 17 and Figure 18 This is a diagram showing an example pattern of an image frame.

[0043] Figure 19 It shows that for Figures 16 to 18 The diagram shows the minimum initial electrical voltage required for the pattern shown.

[0044] Figure 20 This is a diagram illustrating a first power voltage controller according to another embodiment of the present disclosure.

[0045] Figure 21 This is a diagram illustrating a reference block column selector according to an embodiment of the present disclosure.

[0046] Figure 22 This is a diagram illustrating a location lookup table according to an embodiment of the present disclosure.

[0047] Figure 23 This is a diagram illustrating a first power voltage controller according to yet another embodiment of the present disclosure.

[0048] Figure 24 This is a diagram illustrating a maximum segment detector according to an embodiment of the present disclosure.

[0049] Figure 25 This is a diagram illustrating a portion of a lookup table according to an embodiment of the present disclosure.

[0050] Figure 26 This is a diagram illustrating a first power voltage controller according to yet another embodiment of the present disclosure. Detailed Implementation

[0051] In the following description, exemplary embodiments are illustrated in detail with reference to the accompanying drawings, enabling those skilled in the art to readily practice this disclosure. This disclosure may be implemented in various different forms and is not limited to the exemplary embodiments described herein.

[0052] Parts irrelevant to the description will be omitted in order to clearly describe this disclosure, and throughout this disclosure, the same or similar constituent elements will be identified by the same reference numerals. Therefore, the same reference numerals may be used in different figures to indicate the same or similar elements.

[0053] Furthermore, for better understanding and ease of description, the dimensions and thicknesses of each component shown in the accompanying drawings are arbitrarily illustrated, but this disclosure is not limited thereto. For clarity, the thicknesses of certain parts and areas have been exaggerated.

[0054] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0055] Reference Figure 1 The display device 10 according to embodiments of the present disclosure may include a timing controller 11, a data driver 12, a scan driver 13, a pixel unit 14, and a first power voltage controller 15.

[0056] The timing controller 11 can receive grayscale values ​​and control signals for each frame from an external processor (not shown). The timing controller 11 can make the grayscale values ​​correspond to the specifications of the display device 10. For example, the external processor can provide red, green, and blue grayscale values ​​for each unit point. However, when the pixel unit 14 has a pentile structure, adjacent unit points share pixels, so pixels do not necessarily correspond one-to-one with each grayscale value. Therefore, it may be necessary to render the grayscale values. When pixels can correspond one-to-one with each grayscale value, it is not necessary to render the grayscale values. Rendered or unrendered grayscale values ​​can be provided to the data driver 12. In addition, for the purpose of frame display, the timing controller 11 can provide control signals suitable for the data driver 12 or scan driver 13 of this disclosure to the data driver 12 or scan driver 13, etc.

[0057] The data driver 12 can generate data voltages to be supplied to data lines DL1, DL2, DL3, ..., DLn by using grayscale values ​​and control signals. For example, the data driver 12 can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data lines DL1 to DLn on a pixel-row basis. Here, n can be an integer greater than 0. The data driver 12 can be a group of multiple driver units. When the driver units are grouped, the display device 10 can include multiple data drivers 12. The arrangement of the driver units will be described with reference to the following figures.

[0058] The scan driver 13 can generate scan signals to be provided to scan lines SL1, SL2, SL3, ..., SLm by receiving clock signals and scan start signals from the timing controller 11. Here, m can be an integer greater than 0.

[0059] Scan driver 13 can sequentially supply scan signals with on-level pulses to scan lines SL1 to SLm. Scan driver 13 can include scan stages constructed in the form of shift registers. Scan driver 13 can generate scan signals by sequentially transmitting a scan start signal in the form of on-level pulses under the control of a clock signal to the next scan stage.

[0060] Pixel unit 14 includes multiple pixels. Each pixel PXij can be associated with a corresponding data line and a corresponding scan line. Here, i and j can be integers greater than 0. Pixel PXij can refer to the pixel where the scan transistor is associated with the i-th scan line and the j-th data line.

[0061] Pixels can be combined to a first electric field line (not shown) and a second electric field line (not shown). Furthermore, pixel unit 14 can be divided into blocks. Each block can include two or more pixels that are combined to the first electric field line. The first electric field line and blocks will be described with reference to the following figures.

[0062] The first power lines can be coupled to first power sub-lines DSUBLs. The first power sub-lines DSUBLs can be coupled to a corresponding first power source (not shown). In this embodiment, the data driver 12 may include the first power source. Therefore, the first power sub-lines DSUBLs can be coupled to the data driver 12. In another embodiment, the data driver 12 and the first power source can be constructed separately. For example, the first power source can be coupled directly to the power management integrated chip (PMIC) instead of the data driver 12. The first power sub-lines DSUBLs may not be coupled to the data driver 12.

[0063] The second power lines can be coupled to second power sub-lines SSUBLs. The second power sub-lines SSUBLs can be coupled to a corresponding second power source (not shown). In this embodiment, the data driver 12 may include a second power source. Therefore, the second power sub-lines SSUBLs can be coupled to the data driver 12. In this embodiment, the data driver 12 and the second power source can be constructed separately. For example, the second power source can be coupled directly to the PMIC instead of the data driver 12. The second power sub-lines SSUBLs may not be coupled to the data driver 12.

[0064] The first power voltage controller 15 can determine a margin value for the first power voltage supplied to the first power line based on the load value of the block. The determined margin value can be transmitted to the first power source. The magnitude of the first power voltage can be determined to decrease as the margin value increases. The load value and margin value will be described with reference to the following figures.

[0065] Figure 2 This is a diagram illustrating pixels according to an embodiment of the present disclosure.

[0066] Reference Figure 2 Pixel PXij may include transistors T1 and T2, storage capacitor Cst, and light-emitting diode LD.

[0067] In the following description, as an example, a circuit implemented using a P-type transistor is described. However, those skilled in the art can design a circuit implemented using an N-type transistor by changing the polarity of the voltage applied to the gate terminal. Similarly, those skilled in the art can design a circuit implemented using a combination of P-type and N-type transistors. A P-type transistor is a transistor in which the amount of current flowing increases when the voltage difference between the gate electrode and the source electrode increases in the negative direction. An N-type transistor is a transistor in which the amount of current flowing increases when the voltage difference between the gate electrode and the source electrode increases in the positive direction. Transistors can be constructed in various forms, including thin-film transistors (TFTs), field-effect transistors (FETs), and bipolar junction transistors (BJTs).

[0068] like Figure 2 As depicted, the gate electrode of the first transistor T1 can be coupled to the first electrode of the storage capacitor Cst, and the first electrode of the first transistor T1 can be coupled to the first electric field line ELVDDL.

[0069] The second electrode of the first transistor T1 can be connected to the second electrode of the storage capacitor Cst. The first transistor T1 can be referred to as the driving transistor.

[0070] The gate electrode of the second transistor T2 can be coupled to the i-th scan line SLi, the first electrode of the second transistor T2 can be coupled to the j-th data line DLj, and the second electrode of the second transistor T2 can be coupled to the gate electrode of the first transistor T1. The second transistor T2 can be referred to as the scan transistor.

[0071] The anode of the light-emitting diode (LD) can be connected to the second electrode of the first transistor T1, and the cathode of the LD can be connected to the second electric field line ELVSSL. The LD can be constructed as an organic light-emitting diode, an inorganic light-emitting diode, or a quantum dot light-emitting diode, etc.

[0072] A first electrical voltage can be applied to a first electrical line ELVDDL, and a second electrical voltage can be applied to a second electrical line ELVSSL.

[0073] When a scan signal with a conduction level (high level) is applied through the scan line SL1, the second transistor T2 is turned on. The data voltage applied to the data line DLj is stored in the first electrode of the storage capacitor Cst.

[0074] A positive drive current corresponding to the voltage difference between the first and second electrodes of the storage capacitor Cst flows between the first and second electrodes of the first transistor T1. Therefore, the light-emitting diode LD emits light with a brightness corresponding to the data voltage.

[0075] Next, when a scan signal with a cutoff level (here, low level) is applied through the scan line SL1, the second transistor T2 is turned off, and the data line DLj and the first electrode of the storage capacitor Cst are electrically disconnected from each other. Therefore, although the data voltage of the data line DLj changes, the voltage stored in the first electrode of the storage capacitor Cst does not change.

[0076] The embodiments can be applied not only to Figure 2 The pixel PXij shown in the diagram can also be applied to pixels in another circuit.

[0077] The first power sub-lines DSUBLs can be jointly coupled to the first power line ELVDDL. That is, the electrical nodes of the first power line ELVDDL and the first power sub-lines DSUBLs can be shared.

[0078] The second power sub-lines SSUBLs can be jointly connected to the second power line ELVSSL. That is, the electrical nodes of the second power line ELVSSL and the second power sub-lines SSUBLs can be shared.

[0079] According to embodiments of this disclosure, the first transistor T1 can be driven in a saturated state. The amount of drive current can increase as the voltage applied to the gate electrode of the first transistor T1 increases. That is, the first transistor T1 can operate as a current source. The conditions for driving the first transistor T1 in a saturated state are shown in the following expression 1.

[0080] Expression 1

[0081] Vds≥Vgs-Vth

[0082] Vds is the drain-source voltage difference of the first transistor T1, Vgs is the gate-source voltage difference of the first transistor T1, and Vth is the threshold voltage of the first transistor T1.

[0083] As the amount of driving current increases, a light-emitting diode (LD) can emit light with high brightness. Therefore, when displaying an image with high grayscale, a higher gate voltage is required than when displaying an image with low grayscale. In other words, when displaying an image with high grayscale, a higher first power voltage is required than when displaying an image with low grayscale.

[0084] When the display device 10 supplies the minimum first power voltage required to display the image frame (when the equality of expression 1 is satisfied), power consumption can be minimized.

[0085] Figure 3 This is a diagram illustrating a data driver according to an embodiment of the present disclosure.

[0086] Reference Figure 3According to embodiments of the present disclosure, the first data driver 12a may include a plurality of driver units 121 and 122. When the display device 10 includes a plurality of driver units 121 and 122, data lines DL1 to DLn may be grouped into data line groups, and each data line group may be coupled to a corresponding driver unit.

[0087] Driver units 121 and 122 can use a single clock training line (SFC) as a common bus. For example, timing controller 11 can simultaneously transmit a signal to all driver units 121 and 122 via a single clock training line (SFC) to indicate that clock training mode will be supplied.

[0088] Driver units 121 and 122 can be coupled to timing controller 11 via dedicated clock data lines DCSL. For example, when display device 10 includes multiple driver units 121 and 122, driver units 121 and 122 can be coupled to timing controller 11 via corresponding clock data lines DCSL.

[0089] At least one clock data line DCSL can be incorporated into each of driver units 121 and 122. For example, multiple clock data lines DCSL can be incorporated into each driver unit to prepare for situations where the desired bandwidth of the transmitted signal cannot be achieved by using only one clock data line DCSL. Furthermore, each driver unit may require multiple clock data lines DCSL even when the clock data lines DCSL are configured as differential signal lines to remove common-mode noise.

[0090] Each of the driver units 121 and 122 may include a first power supply and a second power supply. Each of the first power supplies may be connected to at least one of the first power sub-lines DSUBLs. Each of the second power supplies may be connected to at least one of the second power sub-lines SSUBLs. Each of the first power supplies may be supplied with a first power voltage via the first power sub-lines DSUBLs. Each of the second power supplies may be supplied with a second power voltage via the second power sub-lines SSUBLs.

[0091] For example, driver unit 121 can supply a first power voltage to the first power line ELVDDL via the first power sub-line DSUBL1, and supply a second power voltage to the second power line ELVSSL via the second power sub-line SSUBL1. Similarly, driver unit 122 can supply a first power voltage to the first power line ELVDDL via the first power sub-line DSUBL2, and supply a second power voltage to the second power line ELVSSL via the second power sub-line SSUBL2.

[0092] Figure 4 This is a diagram illustrating the arrangement of pixel units and data drivers according to an embodiment of the present disclosure.

[0093] like Figure 4 As shown, the data driver 12 includes a first data driver 12a and a second data driver 12b.

[0094] Pixel unit 14 may have a planar shape extending in a first direction DR1 and a second direction DR2 perpendicular to the first direction DR1. In this embodiment, for ease of description, pixel unit 14 is set to a rectangular shape as an example. However, in another embodiment, pixel unit 14 may also be set to a circular shape, an elliptical shape, or a rhomboid shape, etc. Furthermore, pixel unit 14 may have a planar shape in which a portion of it is altered when pixel unit 14 is curved, foldable, or rollable.

[0095] The first data driver 12a may be parallel to the pixel unit 14 and positioned along the first direction DR1. The first data driver 12a may include a plurality of driver units 121 and 122. Driver units 121 and 122 may be coupled to first power sub-lines DSUBL1 and DSUBL2 and second power sub-lines SSUBL1 and SSUBL2 extending in the second direction DR2. The first power sub-lines DSUBL1 and DSUBL2 may be arranged along the first direction DR1. The second power sub-lines SSUBL1 and SSUBL2 may be arranged along the first direction DR1.

[0096] The second data driver 12b may be parallel to the pixel unit 14 and positioned along the first direction DR1. The second data driver 12b may include a plurality of driver units 123 and 124. Driver units 123 and 124 may include first power sub-lines DSUBL3 and DSUBL4 and second power sub-lines SSUBL3 and SSUBL4 extending in the second direction DR2. The first power sub-lines DSUBL3 and DSUBL4 may be arranged along the first direction DR1. The second power sub-lines SSUBL3 and SSUBL4 may be arranged along the first direction DR1.

[0097] Figure 5 , Figure 6 , Figure 7 and Figure 8 This is a diagram showing an example pattern of an image frame. Figure 9 It shows that for Figure 5 , Figure 6 , Figure 7 and Figure 8 The diagram shows the minimum initial electrical voltage required for the pattern shown.

[0098] Reference Figure 5An image frame with pattern "A" can be displayed in pixel unit 14. Pattern "A" has alternating black grayscale, white grayscale and black grayscale in a first direction DR1, and no grayscale change in the second direction DR2.

[0099] Reference Figure 6 An image frame having pattern "B" can be displayed in pixel unit 14. Pattern "B" has alternating black grayscale, white grayscale, and black grayscale in a first direction DR1, and alternating black grayscale, white grayscale, and black grayscale in a second direction DR2. The number of pixels displaying white grayscale in pattern "B" can be equal to the number of pixels displaying white grayscale in pattern "A".

[0100] Reference Figure 7 An image frame having pattern "C" can be displayed in pixel unit 14. Pattern "C" has alternating black grayscale, white grayscale, and black grayscale in a first direction DR1, and alternating black grayscale, white grayscale, and black grayscale in a second direction DR2. Compared to pattern "B", pattern "C" may have a white grayscale region in the first direction DR1 that is longer than the length of pattern "B" in the first direction DR1, and a white grayscale region in the second direction DR2 that is shorter than the length of pattern "B" in the second direction DR2. The number of pixels displaying white grayscale in pattern "C" may be equal to the number of pixels displaying white grayscale in patterns "A" and "B".

[0101] Reference Figure 8 An image frame with pattern "D" can be displayed in pixel unit 14. Pattern "D" has no grayscale variation in the first direction DR1 and has alternating black grayscale, white grayscale, and black grayscale in the second direction DR2. The number of pixels displaying white grayscale in pattern "D" can be equal to the number of pixels displaying white grayscale in patterns "A", "B", and "C".

[0102] Reference Figure 9 As can be seen, the minimum required first power voltage ELVDD decreases in the order of "A", "B", "C" and "D". For example, the first power voltage ELVDD used to display pattern "A" can be 25V, the first power voltage ELVDD used to display pattern "B" can be 24V, the first power voltage ELVDD used to display pattern "C" can be 22V, and the first power voltage ELVDD used to display pattern "D" can be 21V.

[0103] This is because, as the number of driver units 121, 122, 123 and 124 driven in the order of “A”, “B”, “C” and “D” increases, the resistance values ​​of driver units 121, 122, 123 and 124 facing each other decrease, and therefore the amount of IR drop decreases.

[0104] Therefore, it can be seen that, based on the maximum value ELVDD_MAX of the first power voltage ELVDD, the allowable margin values ​​MGA, MGB, MGC, and MGD of the first power voltage ELVDD increase in the order of "A", "B", "C", and "D". That is, as the margin value increases, a lower first power voltage ELVDD can be supplied.

[0105] Therefore, it can be seen that when a larger margin value is calculated as the white grayscale area of ​​the image frame is more widely distributed, the power consumption of the display device 10 can be reduced. In the exemplary embodiment, the description of "more widely distributed" means that the distribution is more uniform and not concentrated in certain areas.

[0106] exist Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 As an example, the display device 10 is shown to include 12 driver units 121, 122, 123, and 124. However, embodiments of this disclosure can also be applied when the display device 10 includes at least two driver units.

[0107] For example, a first pixel can be jointly bound to a first power line ELVDDL and also bound to a first group of data lines. A second pixel can be jointly bound to a first power line ELVDDL and also bound to a second group of data lines. The first group of data lines and the second group of data lines can be different from each other.

[0108] The first driver unit can be coupled to the first power line ELVDDL via the first power sub-lines DSUBLs and to the first set of data lines. The second driver unit can be coupled to the first power line ELVDDL via the second power sub-lines SSUBLs and to the second set of data lines. The second power sub-lines SSUBLs are a term to distinguish them from the first power sub-lines DSUBLs and do not refer to the second power sub-lines SSUBLs being coupled to the second power line ELVSSL.

[0109] In the first pattern, a first voltage can be supplied to the first electric field line ELVDDL. Under the first pattern, X pixels in the first pixel and Y pixels in the second pixel emit light, while the other pixels in the first pixel and the other pixels in the second pixel do not emit light. Additionally, in the second pattern, a second voltage can be supplied to the first electric field line ELVDDL. Under the second pattern, Z pixels in the first pixel emit light, while the other pixels in the first pixel and all second pixels do not emit light. The second voltage can be higher than the first voltage. Here, X, Y, and Z can be integers greater than 0 and satisfy Z = X + Y.

[0110] For example, X pixels, Y pixels, and Z pixels can emit light based on the same grayscale value. The first brightness when the display device 10 displays the first pattern and the second brightness when the display device 10 displays the second pattern can be equal to each other.

[0111] For example, when the first pattern is pattern "D", the second pattern can be any one of patterns "A", "B", and "C". For example, when the first pattern is pattern "C", the second pattern can be any one of patterns "A" and "B". For example, when the first pattern is pattern "B", the second pattern can be pattern "A".

[0112] Although the above embodiments have been described for the first power line ELVDDL, the above embodiments can be described for the second power line ELVSSL.

[0113] Figure 10 This is a diagram illustrating a first power voltage controller according to an embodiment of the present disclosure. Figure 11 This is a diagram illustrating a reference block row selector according to an embodiment of the present disclosure. Figure 12 , Figure 13 and Figure 14 This is a diagram illustrating a distributed lookup table according to an embodiment of the present disclosure.

[0114] Reference Figure 10 The first power voltage controller 15a may include a block load value provider 151, a reference block row selector 152, a first memory 153, and a first switching unit 154.

[0115] In an embodiment, such as Figure 10As shown, the first power voltage controller 15a may be an IC chip constructed with a plurality of sub-units 151, 152, 153, and 154 divided in hardware. In another embodiment, the first power voltage controller 15a may be an IC chip constructed with a plurality of sub-units 151, 152, 153, and 154 divided in software. In yet another embodiment, at least some of the sub-units 151, 152, 153, and 154 of the first power voltage controller 15a may be integrated or further subdivided. In yet another embodiment, the first power voltage controller 15a may be constructed as part of a timing controller 11 (hardware or software). In yet another embodiment, the first power voltage controller 15a may be constructed as part of a data driver 12 (hardware or software). As described above, the first power voltage controller 15a may be constructed in various forms within the scope of achieving the purposes of this disclosure. The foregoing can also be applied to the embodiments described later.

[0116] The first power voltage controller 15a can determine a first margin value MG1 based on the distribution of load values ​​in the first blocks BL41, BL42, BL43, BL44, BL45, BL46, and BL47 arranged in the first direction DR1. The first power voltage controller 15a can determine that increasing the first margin value MG1 allows the load values ​​of the first blocks BL41 to BL47 to be more widely distributed in the first direction DR1. For example, the first power voltage controller 15a can determine that the first margin value MG1 increases as the load values ​​of the first blocks BL41 to BL47 change or the standard deviation decreases.

[0117] The block load value provider 151 can receive grayscale values ​​GVs of image frames and provide load values ​​BLLs for blocks BL11 to BL77 based on the grayscale values ​​GVs. For example, the block load value provider 151 can calculate the load value of block BL17 by adding the grayscale values ​​GVs corresponding to the pixels PX included in block BL17.

[0118] The block load value provider 151 can apply different weights to grayscale values ​​(GVs) of different colors. For example, the block load value provider 151 can calculate the load value by multiplying the red grayscale value by a weight of 1.2, the green grayscale value by a weight of 0.8, and the blue grayscale value by a weight of 1.0, and then adding the multiplied grayscale values ​​together. In another embodiment, the block load value provider 151 can apply the same weights to grayscale values ​​(GVs) of different colors.

[0119] The reference block row selector 152 can receive load values ​​BLLs and select reference block rows based on the load values ​​BLLs. Each of the block rows BLR1, BLR2, BLR3, BLR4, BLR5, BLR6, and BLR7 can be a group of blocks arranged on the first direction DR1. For example, block row BLR4 can include blocks BL41, BL42, BL43, BL44, BL45, BL46, and BL47.

[0120] First, the reference block row selector 152 can calculate the average and maximum load values ​​of the blocks in each of the block rows BLR1 to BLR7. The reference block row selector 152 can identify the first block row with the highest average value and the second block row with the highest maximum value among the block rows BLR1 to BLR7 as candidates for reference block rows. For example, the reference block row selector 152 can identify the first block row as the reference block row when expression 2 below is satisfied, and the reference block row selector 152 can identify the second block row as the reference block row when expression 2 below is not satisfied.

[0121] Expression 2

[0122] AVG_LD2 + REF_LD ≤ AVG_LD1

[0123] AVG_LD2 can be the average value of the second block row, REF_LD can be a predetermined value used as a reference load value, and AVG_LD1 can be the average value of the first block row. In an exemplary embodiment, the average value of a block row refers to the average load value of the blocks arranged in that block row, and the maximum value of a block row refers to the maximum load value among the blocks arranged in that block row. Similarly, the block row with the highest average value refers to the block row with the highest average value among a plurality of block rows, and the block row with the highest maximum value refers to the block row with the highest maximum value among a plurality of block rows. Furthermore, the description of the subsequent block columns also applies to the above example.

[0124] In other words, when the average value of the first block row is greater than or equal to the value obtained by adding the average value of the second block row to the reference load value, the reference block row selector 152 can determine the first block row as the reference block row. When the average value of the first block row is less than the value obtained by adding the average value of the second block row to the reference load value, the reference block row selector 152 can determine the second block row as the reference block row.

[0125] In another embodiment, the reference block row selector 152 may calculate the average load value for each of the block rows BLR1 to BLR7 and determine the block row with the highest average value as the reference block row.

[0126] In another embodiment, the reference block row selector 152 can calculate the maximum value of the load value for each of the block rows BLR1 to BLR7, and determine the block row with the highest maximum value as the reference block row.

[0127] Next, the reference block row selector 152 can provide the distribution degree of the load values ​​of the selected reference block row, DISTr. For example, suppose the selected reference block row is block row BLR4. The load values ​​of the first blocks BL41 to BL47 included in block row BLR4 can be as follows: Figure 12 The distribution shown (i.e., load distribution 1) or as Figure 13 The distribution shown is (i.e., load distribution 2). It can be seen that, compared to... Figure 13 Compared to the situation shown, in Figure 12 In the case shown, the load values ​​of the first blocks BL41 to BL47 are widely distributed along the first direction DR1. Therefore, compared with... Figure 13 Compared to the situation shown, in Figure 12 In the case shown, the reference block row selector 152 can provide a large degree of distribution, DISTr.

[0128] The degree of distribution DISTr can be calculated using various methods. For example, the degree of distribution DISTr can be calculated using variation or standard deviation. For instance, it can be determined that the degree of distribution DISTr increases as the variation or standard deviation decreases. Those skilled in the art can calculate the degree of distribution DISTr using other statistical methods.

[0129] Furthermore, the reference block row selector 152 can provide the average AVGr or the maximum MAXr of the load values ​​of the selected reference block row. For example, when the first block row is determined as the reference block row, the reference block row selector 152 can provide the average AVGr of the first blocks BL41 to BL47. For example, when the second block row is determined as the reference block row, the reference block row selector 152 can provide the maximum MAXr of the first blocks BL41 to BL47.

[0130] The first memory 153 may include multiple distribution lookup tables 1531, 1532, ... . The first switching unit 154 may include multiple switches SW1, SW2, ... . The first switching unit 154 may select any one of the multiple distribution lookup tables 1531, 1532, ... based on the received distribution degree DISTr. For example, the first switching unit 154 may select distribution lookup table 1531, which provides an average higher first margin value MG1 as the distribution degree DISTr increases. For example, the first switching unit 154 may select distribution lookup table 1534, which provides an average lower first margin value MG1 as the distribution degree DISTr decreases.

[0131] Each of the distribution lookup tables 1531, 1532, 1533, 1534... can be pre-determined to provide a smaller first margin value MG1 as the average AVGr or maximum MAXr of the load values ​​of the first blocks BL41 to BL47 increases.

[0132] In the above embodiment, the first power voltage controller 15a only considers the average and maximum values ​​of the load value. However, in another embodiment, the first power voltage controller 15a may consider another parameter, such as the minimum value of the load value.

[0133] Figure 15 This is a diagram illustrating the arrangement of pixel units and data drivers according to another embodiment of the present disclosure. Figures 16 to 18 This is an illustration showing an exemplary pattern of an image frame. Figure 19 It shows that for in Figure 16 , Figure 17 and Figure 18 The diagram shows the minimum initial electrical voltage required for the pattern shown.

[0134] and Figure 4 Compared to the embodiments shown, in Figure 15 In the embodiment shown, data driver 12 includes a first data driver 12a but does not include a second data driver 12b.

[0135] Reference Figure 16 An image frame with pattern “E” can be displayed in pixel unit 14. Pattern “E” has alternating black grayscale, white grayscale and black grayscale in a first direction DR1, and white grayscale relatively close to the first power sub-line DSUBLs in a second direction DR2.

[0136] Reference Figure 17An image frame having pattern "F" can be displayed in pixel unit 14. Pattern "F" has alternating black grayscale, white grayscale, and black grayscale in a first direction DR1, and has a white grayscale region spaced apart from the first power sub-lines DSUBLs at a certain distance in a second direction DR2. The number of pixels displaying white grayscale in pattern "F" can be equal to the number of pixels displaying white grayscale in pattern "E".

[0137] Reference Figure 18 An image frame with pattern "G" can be displayed in pixel unit 14. Pattern "G" has alternating black grayscale, white grayscale, and black grayscale in a first direction DR1, and has a white grayscale area relatively far from the first power sub-lines DSUBLs in a second direction DR2. The number of pixels displaying white grayscale in pattern "G" can be equal to the number of pixels displaying white grayscale in patterns "E" and "F".

[0138] Reference Figure 19 It can be seen that the minimum required first power voltage ELVDD decreases in the order of "G", "F", and "E". This is because the amount of IR drop decreases as the white grayscale area becomes closer to the first power sub-line DSUBLs in the order of "G", "F", and "E".

[0139] Therefore, it can be seen that, based on the maximum value of the first power voltage ELVDD, ELVDD_MAX, the allowable margin values ​​MGAR1, MGAR2, and MGAR3 of the first power voltage ELVDD decrease in the order of "E", "F", and "G". That is, as the margin value increases, a lower first power voltage ELVDD can be supplied.

[0140] Therefore, it can be seen that when a large margin value is calculated as the white grayscale area gets closer to the first power sub-line DSUBLs, the power consumption of the display device 10 can be reduced.

[0141] Figure 20 This is a diagram illustrating a first power voltage controller according to another embodiment of the present disclosure. Figure 21 This is a diagram illustrating a reference block column selector according to an embodiment of the present disclosure. Figure 22 This is a diagram illustrating a location lookup table according to an embodiment of the present disclosure.

[0142] Reference Figure 20According to another embodiment of this disclosure, the first power voltage controller 15b may include a block load value provider 151, a reference block row selector 152, a first memory 153, a first switching unit 154, a reference block column selector 155, a second memory 156, a second switching unit 157, and an adder 158. Any similar or identical descriptions of the block load value provider 151, the reference block row selector 152, the first memory 153, and the first switching unit 154 will be omitted.

[0143] The first power voltage controller 15b can determine the second margin value MG2 based on the position of the second block that has the maximum value among the load values ​​of the second block arranged in the second direction DR2. The first power voltage controller 15b can determine the second margin value MG2 to increase as the position of the second block with the maximum value becomes closer to the first power sub-line DSUBLs.

[0144] The reference block column selector 155 can receive load values ​​BLLs and select a reference block column based on the load values ​​BLLs. Each of the block columns BLC1, BLC2, BLC3, BLC4, BLC5, BLC6, and BLC7 can be a group of blocks arranged on the second direction DR2. For example, block column BLC3 can include blocks BL13, BL23, BL33, BL43, BL53, BL63, and BL73.

[0145] First, the reference block column selector 155 can calculate the average and maximum load values ​​for each of the block columns BLC1 to BLC7. The reference block column selector 155 can determine the first block column with the highest average value and the second block column with the highest maximum value among the block columns BLC1 to BLC7 as candidates for reference block columns. For example, the reference block column selector 155 can determine the first block column as the reference block column when expression 3 below is satisfied, and determine the second block column as the reference block column when expression 3 below is not satisfied.

[0146] Expression 3

[0147] AVG_LD2c + REF_LDc ≤ AVG_LD1c

[0148] AVG_LD2c can be the average value of the second block column, REF_LDc can be a predetermined value used as a reference load value, and AVG_LD1c can be the average value of the first block column.

[0149] In other words, when the average value of the first block column is greater than or equal to the value obtained by adding the average value of the second block column to the reference load value, the reference block column selector 155 can determine the first block column as the reference block column. When the average value of the first block column is less than the value obtained by adding the average value of the second block column to the reference load value, the reference block column selector 155 can determine the second block column as the reference block column.

[0150] In another embodiment, the reference block column selector 155 can calculate the average load value for each of the block columns BLC1 to BLC7 and determine the block column with the highest average value as the reference block column.

[0151] In another embodiment, the reference block column selector 155 can calculate the maximum value of the load value for each of the block columns BLC1 to BLC7, and determine the block column with the highest maximum value as the reference block column.

[0152] Next, the reference block column selector 155 can provide the location POSc of the second block in the selected reference block column that has the maximum value among the load values. For example, when the selected reference block column is block column BLC3, the reference block column selector 155 can provide the location POSc of the second block in the second blocks BL13, BL23, BL33, BL43, BL53, BL63, and BL73 that has the maximum value among the load values ​​of the second blocks BL13, BL23, BL33, BL43, BL53, BL63, and BL73.

[0153] Furthermore, the reference block column selector 155 can provide the average AVGc or the maximum MAXc of the load values ​​of the selected reference block column. For example, when the first block column is determined as the reference block column, the reference block column selector 155 can provide the average AVGc of the second blocks BL13 to BL73. Similarly, when the second block column is determined as the reference block column, the reference block column selector 155 can provide the maximum MAXc of the second blocks BL13 to BL73.

[0154] The second memory 156 may include multiple location lookup tables 1561, 1562, 1563, 1564, 1565, 1566, and 1567. The second switching unit 157 may include multiple switches SW3, SW4, ... The second switching unit 157 can select any one of the multiple location lookup tables 1561 to 1567 based on the location POSc of the second block with the maximum value. For example, the second switching unit 157 can select location lookup table 1567, which provides a higher average second margin value MG2 as the location POSc of the second block with the maximum value becomes closer to the first power sub-line DSUBLs. For example, the second switching unit 157 can select location lookup table 1561, which provides a lower average second margin value MG2 as the location POSc of the second block with the maximum value becomes farther away from the first power sub-line DSUBLs.

[0155] Each of the location lookup tables 1561 to 1567 can be pre-determined to provide a smaller second margin value MG2 as the average AVGc or maximum MAXc of the load values ​​of the second blocks BL13 to BL73 increases.

[0156] In the above embodiment, the first power voltage controller 15b only considers the average and maximum values ​​of the load value. However, in another embodiment, the first power voltage controller 15b may consider another parameter, such as the minimum value of the load value.

[0157] Adder 158 can output the final margin value MGS by adding the first margin value MG1 and the second margin value MG2. For example, adder 158 can apply the same weight to the first margin value MG1 and the second margin value MG2, or apply different weights to the first margin value MG1 and the second margin value MG2. In other cases, the weight can be 0.

[0158] Figure 23 This is a diagram illustrating a first power voltage controller according to yet another embodiment of the present disclosure. Figure 24 This is a diagram illustrating a maximum segment detector according to an embodiment of the present disclosure. Figure 25 This is a diagram illustrating a segment lookup table according to an embodiment of the present disclosure.

[0159] Reference Figure 23According to another embodiment of the present disclosure, the first power voltage controller 15c may include a block load value provider 151, a reference block row selector 152, a first memory 153, a first switching unit 154, a reference block column selector 155, a second memory 156, a second switching unit 157, an adder 158', a grayscale value counter 159, a maximum segment detector 160, a third memory 161, and a third switching unit 162. Descriptions of the block load value provider 151, the reference block row selector 152, the first memory 153, the first switching unit 154, the reference block column selector 155, the second memory 156, and the second switching unit 157 will be omitted.

[0160] The first power voltage controller 15c can calculate the gray value ratio CRs of segments SC1, SC2, SC3, SC4, SC5, SC6, SC7, and SC8 based on the gray value GVs. The first power voltage controller 15c can determine the third margin value MG3 based on the largest segment SCm with the highest gray value ratio among the segments with gray value ratios CRs greater than the reference ratio Rref. The first power voltage controller 15c can determine the third margin value MG3 to decrease as the gray value ratio CRm of the largest segment SCm increases.

[0161] The segments SC1 to SC8 can be predetermined based on the size of the grayscale values ​​GVs. For ease of description, it is assumed that each grayscale value is represented by 8 bits to correspond to one of the 256 grayscale values. Grayscale 0 can be black (minimum grayscale), and grayscale 255 can be white (maximum grayscale). In another embodiment, each of the grayscale values ​​GVs can be represented by various bits such as 10 bits and 12 bits.

[0162] For example, segment SC1 can correspond to grayscale values ​​0 to 31, segment SC2 can correspond to grayscale values ​​32 to 63, segment SC3 can correspond to grayscale values ​​64 to 95, segment SC4 can correspond to grayscale values ​​96 to 127, segment SC5 can correspond to grayscale values ​​128 to 159, segment SC6 can correspond to grayscale values ​​160 to 191, segment SC7 can correspond to grayscale values ​​192 to 223, and segment SC8 can correspond to grayscale values ​​224 to 255. In this embodiment, segments SC1 to SC8 are divided at equal intervals. However, in another embodiment, segments SC1 to SC8 are divided at different intervals.

[0163] The grayscale counter 159 can calculate the grayscale ratio CRs of each corresponding grayscale value GVs in segments SC1 to SC8. For example, when the total number of grayscale values ​​GVs is 3840*2160 and the number of grayscale values ​​GVs corresponding to segment SC1 is 2160, the grayscale ratio CRs of segment SC1 can be approximately 100% to approximately 3840%.

[0164] The maximum segment detector 160 can receive grayscale ratios CRs and detect the maximum segment SCm among segments SC3, SC4, SC5, and SC6 that have a grayscale ratio greater than the reference ratio Rref. For example, the reference ratio Rref... Figure 24 The maximum segment detector 160 can identify segment SC6 as the maximum segment SCm.

[0165] According to this embodiment, it is highly likely that the grayscale values ​​GVs included in segments SC7 and SC8 will not be displayed with the expected brightness. However, when the reference ratio Rref is properly set, the number of pixels with grayscale value ratios CRs lower than the reference ratio Rref is very small; therefore, it is highly probable that the user will not perceive the display malfunction. Thus, according to this embodiment, power consumption can be reduced while minimizing display malfunctions.

[0166] The maximum segment detector 160 can provide the maximum segment SCm and the gray value ratio CRm of the maximum segment SCm.

[0167] The third memory 161 may include multiple segment lookup tables 1611, 1612, 1613, 1614, 1615, 1616, 1617, and 1618. The third switching unit 162 may include multiple switches SW5, SW6, ... The third switching unit 162 may select any one of the multiple segment lookup tables 1611 to 1618 based on the received maximum segment SCm. For example, the third switching unit 162 may select segment lookup table 1618, which provides an average smaller third margin value MG3 as the grayscale value ratio CRm of the maximum segment SCm increases. For example, the third switching unit 162 may select segment lookup table 1611, which provides an average larger third margin value MG3 as the grayscale value ratio CRm of the maximum segment SCm decreases.

[0168] Each of the segment lookup tables 1611 to 1618 can be pre-determined to provide a smaller third margin value MG3 as the gray value ratio CRm of the largest segment SCm increases.

[0169] Adder 158' outputs the final margin value MGS' by adding the first margin value MG1, the second margin value MG2, and the third margin value MG3. For example, adder 158' can apply the same weights to the first margin value MG1, the second margin value MG2, and the third margin value MG3, or apply different weights to the first margin value MG1, the second margin value MG2, and the third margin value MG3. In other cases, the weights can be 0. That is, the first power voltage controller 15c can determine the margin value MGS' by adding at least two of the first margin value MG1, the second margin value MG2, and the third margin value MG3.

[0170] Figure 26 This is a diagram illustrating a first power voltage controller according to yet another embodiment of the present disclosure.

[0171] Figure 26 The first power voltage controller 15d shown is with Figure 23 The difference between the first power voltage controller 15c shown is that the first power voltage controller 15d does not include the reference block column selector 155, the second memory 156, and the second switching unit 157. Therefore, the adder 158” can output the final margin value MGS based on the first margin value MG1 and the third margin value MG3.

[0172] When data drive 12 includes, for example Figure 4 When the first data driver 12a and the second data driver 12b shown are used, no event may occur. Figures 16 to 19 The problem shown is addressed here. Therefore, the first power voltage controller 15d of this embodiment does not include the relatively minor reference block column selector 155, the second memory 156, and the second switching unit 157, thereby reducing the manufacturing cost of the display device 10.

[0173] In the display device and driving method of the present disclosure, a minimum power voltage is supplied by analyzing the pattern of the image frame, thereby reducing power consumption.

[0174] Example embodiments have been disclosed herein. Although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, unless specifically indicated otherwise, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, since the filing of this application. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the claims.

Claims

1. A display device, the display device comprising: Multiple blocks, each block comprising two or more pixels that are collectively bound to a first power line; A data driver, comprising multiple driver units positioned along a first direction; as well as A first power voltage controller is configured to determine a margin value for the first power voltage supplied to the first power line based on the load values ​​of the plurality of blocks. Wherein, the margin value is the difference between the maximum value of the first power voltage supplied to the first power line and the minimum value required to display the image frame. The first power voltage controller determines the load value based on the grayscale value of the pixel included in each of the plurality of blocks. Specifically, the magnitude of the first electrical voltage is determined to decrease as the margin value increases. Wherein, the margin value includes a first margin value, and The first power voltage controller determines the first margin value based on the distribution degree of the load value of the first block arranged in the first direction among the plurality of blocks. The distribution degree increases as the load value changes or the standard deviation decreases. The first power voltage controller determines the first margin value to increase as the load value of the first block arranged in the first direction among the plurality of blocks changes or the standard deviation decreases.

2. The display device according to claim 1, further comprising: A plurality of first power sources, each of which is coupled to at least one of a plurality of first power sub-lines. Among them, the plurality of first power sub-lines are jointly connected to the first power line, and The plurality of first power sub-lines are arranged in the first direction.

3. The display device according to claim 2, wherein, The first power voltage controller includes multiple distributed lookup tables. The first power voltage controller selects one of the plurality of distribution lookup tables based on the degree of distribution, and The first power voltage controller extracts the first margin value from a selected distribution lookup table based on the average or maximum value of the load value of the first block.

4. The display device according to claim 3, wherein, The selected distribution lookup table provides the first margin value as it decreases as the average or maximum value of the load value of the first block increases.

5. The display device according to claim 4, wherein, The margin value also includes a second margin value. The plurality of blocks includes a plurality of second blocks arranged in a second direction perpendicular to the first direction, and The first power voltage controller determines the second margin value based on the location of the second block that has the maximum load value among the plurality of second blocks.

6. The display device according to claim 5, wherein, The first power voltage controller determines the second margin value to increase as the location of the second block with the maximum value becomes closer to the plurality of first power sub-lines.

7. The display device according to claim 6, wherein, The first power voltage controller includes multiple location lookup tables. The first power voltage controller selects one of the plurality of location lookup tables based on the location of the second block with the maximum value. The first power voltage controller extracts the second margin value from the selected location lookup table based on the average or maximum value of the load values ​​of the plurality of second blocks.

8. The display device according to claim 7, wherein, The selected location lookup table provides the second margin value as it decreases as the average or maximum value of the load values ​​of the plurality of second blocks increases. The margin value also includes a third margin value. Specifically, the first power voltage controller calculates the grayscale value ratio of the segments divided according to the magnitude of the grayscale value. The first power voltage controller determines the third margin value based on the largest segment with the highest gray value ratio among segments with a gray value ratio greater than the reference ratio. Specifically, the first power voltage controller determines the third margin value to decrease as the grayscale value ratio of the maximum segment increases. The first power voltage controller includes multiple segment lookup tables. Specifically, the first power voltage controller selects the segment lookup table from the plurality of segment lookup tables that corresponds to the largest segment. Specifically, the first power voltage controller extracts the third margin value from the selected segment lookup table based on the grayscale value ratio of the maximum segment. The selected segment lookup table provides the third margin value as it decreases as the grayscale value ratio of the largest segment increases, and The first power voltage controller determines the margin value by adding at least two of the first margin value, the second margin value, and the third margin value.

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