A reconfigurable chip easy compilation method and system

By establishing the mapping relationship between computing nodes and edges on CGRA and optimizing the compilation configuration file, the problem of resource scheduling and architecture differences in CGRA compilation technology is solved, and efficient compilation process and computing performance are achieved.

CN113094030BActive Publication Date: 2024-12-31BEIJING TSINGMICRO INTELLIGENT TECH CO LTD +1
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Patent Information

Application Number
CN202110176676.6
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-02-09
Publication Date
2024-12-31
Estimated Expiration
2041-02-09

AI Technical Summary

Technical Problem

The existing CGRA compilation technology is difficult to effectively schedule its computing resources, resulting in performance drag. Since the hardware architecture is different from that of general-purpose processors, the original compilation technology cannot be completely ported, making it difficult to achieve the goal of high performance and high energy efficiency.

Method used

By establishing the mapping and mathematical dependencies between the computing node set, edge set and the accelerated computing unit in the DFG data flow graph, the fast compilation of the program structure is realized, and the easy compilation method and system are adopted to generate the corresponding compilation configuration files and optimize the loading. , the mapping relationship between storage and computing units reduces the compilation time.

Benefits of technology

It realizes that the algorithm is simple and easy to implement, the solution time is short, and the coarse-grained reconfigurable after compilation can achieve better computing performance, strong applicability, and is suitable for software structures with multiple logical relationships.

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Abstract

The present invention provides an easy compilation method for a reconfigurable chip, which comprises: obtaining a DFG data flow graph of a software model to be compiled. Obtaining a computing node set and an edge set in the DFG data flow graph, wherein the edges can express the data dependency between computing nodes and computing nodes. Establishing a mathematical dependency between a computing node set, an edge set, a loading unit, a storage unit, and an operation unit. Establishing and obtaining a compilation configuration file that can be mapped to an accelerated computing unit through a linear compiler linear compilation loading mapping relationship, a storage mapping relationship, and an operation mapping relationship. The present invention achieves fast and easy compilation of its program structure by establishing a mapping and a mathematical dependency relationship between a computing node set, an edge set, and each computing unit in an accelerated computing unit in a DFG data flow graph, an algorithm that is simple and easy to implement, and a short solution time. The present invention also provides an easy compilation system for a reconfigurable chip.
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