Display substrate, driving method thereof, and display device

Abstract

The present disclosure provides a display substrate, comprising: a display area and a non-display area located around the display area, wherein the display area is provided with a plurality of pixel units arranged in an array, a plurality of gate lines extending along the row direction of the array, and a plurality of data lines extending along the column direction of the array; each row of pixel units is configured with at least one corresponding gate line, and each gate line is connected to at least some of the pixel units in a row of pixel units corresponding to it; each column of pixel units is configured with at least two corresponding data lines, and each data line is connected to some of the pixel units in a column of pixel units corresponding to it; each pixel unit is connected to one gate line and one data line, and two pixel units located in the same column and in adjacent rows are connected to different data lines. The present disclosure also provides a display substrate driving method and a display device.

Description

Technical Field

[0001] The present disclosure relates to the field of display, and in particular to a display substrate and a driving method thereof, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) is a current-driven light-emitting device that requires a pixel driving circuit to provide driving current. The driving transistor is the core device in the pixel driving circuit, which can provide driving current to the OLED.

[0003] Due to factors such as the manufacturing process and the drift of electrical characteristics during use, the threshold voltages of the driving transistors on the OLED panel are different. Therefore, threshold compensation of the driving transistors is required during the driving process to compensate for the difference.

[0004] However, it is found in actual applications that as the resolution increases, the writing time of the gate scanning drive signal for each gate line is shortened. Since the threshold compensation time of the pixel driving circuit is equal to the writing time of the gate scanning drive signal of the gate line, the threshold compensation time of the pixel driving circuit is also shortened accordingly, resulting in a worse compensation effect. Summary of the invention

[0005] Embodiments of the present disclosure provide a display substrate, a driving method thereof, and a display device.

[0006] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising: a display area and a non-display area located around the display area, wherein the display area is provided with a plurality of pixel units arranged in an array, a plurality of gate lines extending along a row direction of the array, and a plurality of data lines extending along a column direction of the array;

[0007] Each row of pixel units is configured with at least one corresponding gate line, and each gate line is connected to at least part of the pixel units in the row of pixel units corresponding to it;

[0008] Each column of pixel units is configured with corresponding at least two of the data lines, and each of the data lines is connected to part of the pixel units in the corresponding column of pixel units;

[0009] Each of the pixel units is connected to one of the gate lines and one of the data lines, and two pixel units located in the same column and in adjacent rows are connected to different data lines.

[0010] In some embodiments, a plurality of multi-way selection circuits are arranged in the non-display area, and each of the multi-way selection circuits corresponds to at least one column of pixel units;

[0011] The multi-way selection circuit is configured with a data signal input terminal and multiple data signal output terminals, and the multiple data signal output terminals are respectively connected to multiple data lines configured for the at least one column of pixel units corresponding to the multi-way selection circuit, and the data signal output terminals correspond one-to-one to the data lines.

[0012] In some embodiments, each row of pixel units is configured with corresponding m gate lines, and the kth gate line among the m gate lines is connected to the pixel units in the b*m+kth row among the corresponding row of pixel units;

[0013] Wherein, m is an integer and 1≤k≤m, b is a non-negative integer and b*m+k≤M, M is a pixel unit in the array. In some embodiments, m is 2, and the two gate lines corresponding to each row of pixel units are the first gate line and the second gate line respectively;

[0014] The first gate line is connected to the pixel units in the odd columns in the corresponding row of pixel units, and the second gate line is connected to the pixel units in the even columns in the corresponding row of pixel units.

[0015] In some embodiments, each column of pixel units is configured with two corresponding data lines, namely a first data line and a second data line;

[0016] The first data line is connected to the pixel units in the odd-numbered rows in the corresponding column of pixel units, and the second data line is connected to the pixel units in the even-numbered rows in the corresponding column of pixel units.

[0017] In some embodiments, every two adjacent columns of pixel units correspond to one multiplexer circuit;

[0018] The multi-way selection circuit includes: a first switch, a second switch, a third switch and a fourth switch;

[0019] The first end of the first switch, the first end of the second switch, the first end of the third switch, and the first end of the fourth switch are all connected to the signal input end;

[0020] The second end of the first switch and the second end of the second switch are respectively connected to the two first data lines configured for the two columns of pixel units corresponding to the multiplexer circuit, and the second end of the third switch and the second end of the fourth switch are respectively connected to the two second data lines configured for the two columns of pixel units corresponding to the multiplexer circuit.

[0021] In some embodiments, each column of pixel units is configured with corresponding n data lines, where n is an integer and n≥2;

[0022] The i-th data line among the n data lines is connected to the pixel unit in the a*n+i-th row among the corresponding column of pixel units;

[0023] Wherein, i is an integer and 1≤i≤n, a is a non-negative integer and a*n+i≤N, and N is the total number of rows of pixel units in the array.

[0024] In some embodiments, each row of pixel units is configured with a corresponding gate line, and the gate line is connected to all pixel units in the corresponding row of pixel units.

[0025] In some embodiments, each column of pixel units corresponds to a multiplexer circuit, and the multiplexer circuit includes: n switches,

[0026] The first ends of the n switches are all connected to the signal input end;

[0027] A second end of the j-th switch among the n switches is connected to the j-th data line configured for the corresponding column of pixel units;

[0028] Wherein, j is an integer and 1≤j≤n.

[0029] In some embodiments, n is 4.

[0030] In some embodiments, the four data lines corresponding to the same column of pixel units are evenly distributed on two opposite sides of the corresponding column of pixel units.

[0031] In a second aspect, an embodiment of the present disclosure provides a display device, comprising: a display substrate as provided in any of the above embodiments.

[0032] In a third aspect, an embodiment of the present disclosure provides a method for driving a display substrate, wherein the display substrate is the display substrate provided by any of the above embodiments, and the driving method includes:

[0033] Writing scanning driving signals to each of the gate lines in sequence according to a predetermined order to drive the corresponding pixel unit, and writing corresponding data signals to the data lines connected to the driven pixel units;

[0034] The writing time of each data signal to the data line is H / c, and the interval between the writing start time of two consecutive data signals to the same data line is T, H is the total time taken to complete the data writing of a pre-configured row of pixel units, c is the number of gate lines configured for a row of pixel units, and T>H;

[0035] The writing time length of each time the gate scanning driving signal is written into the gate line is T', H<T'≤T.

[0036] In some embodiments, when each row of pixel units is configured with corresponding 2 gate lines and each column of pixel units is configured with corresponding 2 data lines; the writing duration of each data signal written to the data line is H / 2; the interval T between the writing start time of two consecutive data signals written to the same data line is 2H; the writing duration of each gate scanning drive signal written to the gate line is T', which is 2H.

[0037] In some embodiments, when each row of pixel units is configured with a corresponding gate line, each column of pixel units is configured with corresponding n data lines, n is an integer and n≥2;

[0038] The writing time length of each data line is H; the interval T between two consecutive writing start times of the data signal to the same data line is n*H; the writing time length of each gate scanning drive signal to the gate line is T', which is n*H. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of a circuit structure of a display substrate provided in an embodiment of the present disclosure;

[0040] Figure 2 A schematic diagram of a circuit structure of a pixel driving circuit provided in an embodiment of the present disclosure;

[0041] Figure 3 for Figure 2 A working timing diagram of the pixel driving circuit shown;

[0042] Figure 4 A schematic diagram of a structure of a display substrate in the related art;

[0043] Figure 5 for Figure 1 A driving timing diagram of the display substrate is shown;

[0044] Figure 6 A schematic diagram of a circuit structure of a display substrate provided in an embodiment of the present disclosure;

[0045] Figure 7 for Figure 6 A driving timing diagram of the display substrate is shown;

[0046] Figure 8 A schematic diagram of a circuit structure of a display substrate provided in an embodiment of the present disclosure;

[0047] Fig. 9 for Figure 8 A driving timing diagram of the display substrate is shown. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, a display substrate and a driving method thereof, a display panel and a display device provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0049] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0050] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprise" and / or "comprising" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0051] It will be understood that although the terms first, second, etc. may be used herein to describe various elements / structures, these elements / structures should not be limited by these terms. These terms are only used to distinguish one element / structure from another element / structure.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0053] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same or similar characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode. In addition, transistors can be divided into N-type and P-type according to the characteristics of the transistor. The following embodiments are explained with P-type transistors. When P-type transistors are used, the first electrode is the drain of the P-type transistor, the second electrode is the source of the P-type transistor, and the N-type is the opposite. It can be thought that the use of N-type transistors to implement the technical solutions of the following embodiments is something that a person skilled in the art can easily think of without creative work, and therefore it is also within the scope of protection of the embodiments of the present disclosure.

[0054] The “effective level” in the present disclosure refers to a level that can control the conduction of a corresponding transistor; specifically, for a P-type transistor, the corresponding effective level is a low level; for an N-type transistor, the corresponding effective level is a high level.

[0055] Figure 1 A schematic diagram of a circuit structure of a display substrate provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the display substrate includes: a display area (Active Area, also called display effective area) AA and a non-display area located around the display area. The display area AA is provided with a plurality of pixel units Pixel arranged in an array, a plurality of gate lines G1_1 to GN_2 extending along the row direction of the array, and a plurality of data lines D1_1 to DM_2 extending along the column direction of the array. In the embodiment of the present disclosure, an exemplary description is given by taking an array including N rows, M columns, and a total of N*M pixel units Pixel as an example.

[0056] Among them, each row of pixel units Pixel is configured with at least one corresponding gate line G1_1 / G1_2 / … / GN_1 / GN_2, and each gate line G1_1 / G1_2 / … / GN_1 / GN_2 is connected to at least some pixel units Pixel in a corresponding row of pixel units Pixel; each column of pixel units Pixel is configured with at least two corresponding data lines D1_1, D1_2 / D2_1, D2_2 / … / DM_1, DM_2, and each data line D1_1 / D1_2 / … / DN_1 / DN_2 is connected to some pixel units Pixel in a corresponding column of pixel units Pixel; each pixel unit Pixel is connected to a gate line G1_1 / G1_2 / … / GN_1 / GN_2 and a data line D1_1 / D1_2 / … / DN_1 / DN_2, and two pixel units located in the same column and in adjacent rows are connected to different data lines D1_1 / D1_2 / … / DN_1 / DN_2.

[0057] Among them, the pixel unit Pixel includes: a pixel driving circuit and a light-emitting device; the pixel driving circuit is connected to the corresponding gate line G1_1 / G1_2 / … / GN_1 / GN_2 and the data line D1_1 / D1_2 / … / DN_1 / DN_2, and can provide a driving current to the light-emitting device according to the data signal provided by the data line D1_1 / D1_2 / … / DN_1 / DN_2 to drive the light-emitting device to emit light; the light-emitting device is a current-driven light-emitting device, such as OLED, a light-emitting diode (Light Emitting Diode, LED for short), and the light-emitting device is OLED as an example for exemplary description in this disclosure.

[0058] Based on the display substrate provided by the embodiment of the present disclosure, during the display driving process, the writing time of the gate scanning driving signal for each gate line G1_1 / G1_2 / … / GN_1 / GN_2 can be increased, and the threshold compensation time of the pixel driving circuit in the pixel unit Pixel is also increased accordingly, thereby improving the compensation effect.

[0059] The technical solution of the present disclosure will be described in detail below with reference to specific examples and drawings.

[0060] Figure 2 A circuit structure diagram of a pixel driving circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, in some embodiments, the pixel driving circuit includes: a first reset sub-circuit 1, a second reset sub-circuit 2, a data writing sub-circuit 3, a threshold compensation sub-circuit 4 and a driving transistor DTFT.

[0061] The first reset subcircuit 1 is connected to the first power supply terminal, the control electrode of the driving transistor DTFT, and the corresponding first reset signal line RST1. The first reset subcircuit 1 is configured to write the first voltage provided by the first power supply terminal into the gate of the driving transistor DTFT in response to the control of the first reset signal line RST1.

[0062] The second reset subcircuit 2 is connected to the first power supply terminal, the first terminal of the light-emitting device OLED, and the corresponding second reset signal line RST2. The second reset subcircuit 2 is configured to write the first voltage to the first terminal of the light-emitting device OLED in response to the control of the second reset signal line RST2.

[0063] The data writing subcircuit 3 is connected to the first electrode of the driving transistor DTFT, the corresponding data line DATA, and the corresponding gate line GATE. The data writing subcircuit 3 is configured to write the data voltage provided by the data line DATA into the first electrode of the driving transistor DTFT in response to the control of the gate line GATE.

[0064] The threshold compensation sub-circuit 4 is connected to the second power supply terminal, the control electrode of the driving transistor DTFT, the first electrode of the driving transistor DTFT, the second electrode of the driving transistor DTFT, and the corresponding gate line GATE. The threshold compensation sub-circuit 4 is configured to write the data compensation voltage to the control electrode of the driving transistor DTFT in response to the control of the gate line GATE, and the data supplement voltage is equal to the sum of the data voltage and the threshold voltage of the driving transistor DTFT.

[0065] The second electrode of the driving transistor DTFT is connected to the first terminal of the light emitting device OLED. The driving transistor DTFT is configured to output a corresponding driving current in response to the control of the data compensation voltage. The second terminal of the light emitting device OLED is connected to the third power terminal.

[0066] Continue to see Figure 2 As shown, in some embodiments, the first reset subcircuit 1 includes a first transistor M1, the second reset subcircuit 2 includes a second transistor M2, the data writing subcircuit 3 includes a third transistor M3, and the threshold compensation subcircuit 4 includes a fourth transistor M4 and a fifth transistor M5.

[0067] The control electrode of the first transistor M1 is connected to the first reset signal line RST1 , the first electrode of the first transistor M1 is connected to the first power supply terminal, and the second electrode of the first transistor M1 is connected to the control electrode of the driving transistor DTFT.

[0068] The control electrode of the second transistor M2 is connected to the second reset signal line RST2, the first electrode of the second transistor M2 is connected to the first power supply terminal, and the second electrode of the second transistor M2 is connected to the first terminal of the light emitting device.

[0069] A control electrode of the third transistor M3 is connected to the gate line GATE, a first electrode of the third transistor M3 is connected to the data line, and a second electrode of the third transistor M3 is connected to a first electrode of the driving transistor DTFT.

[0070] A control electrode of the fourth transistor M4 is connected to the light emitting control signal line EM, a first electrode of the fourth transistor M4 is connected to the second power supply terminal, and a second electrode of the fourth transistor M4 is connected to a first electrode of the driving transistor DTFT.

[0071] A control electrode of the fifth transistor M5 is connected to the gate line GATE, a first electrode of the fifth transistor M5 is connected to the control electrode of the driving transistor DTFT, and a second electrode of the fifth transistor M5 is connected to the second electrode of the driving transistor DTFT.

[0072] In some embodiments, the pixel driving circuit further includes: a sixth transistor M6, and the second electrode of the driving transistor DTFT is connected to the first end of the light-emitting device through the sixth transistor M6; specifically, the control electrode of the sixth transistor M6 is connected to the light-emitting control signal line EM, the first electrode of the sixth transistor M6 is connected to the second electrode of the driving transistor DTFT, and the second electrode of the sixth transistor M6 is connected to the first end of the light-emitting device.

[0073] The following will be combined with the attached drawings Figure 2 The working process of the pixel driving circuit is described in detail. It is assumed that the first power supply terminal provides a first voltage as a reset voltage VINT, the second power supply terminal provides a second voltage as an operating voltage VDD, and the third power supply terminal provides a third voltage as an operating voltage VSS.

[0074] Figure 3 for Figure 2 A working timing diagram of the pixel driving circuit shown in FIG. Figure 3As shown, the working process of the pixel driving circuit includes: a reset phase t1, a data writing and compensation phase t2, and a light emitting phase t3.

[0075] In the reset phase t1 , the first reset signal line RST1 provides a low level signal, the second reset signal line RST2 provides a high level signal, the gate line GATE provides a high level signal, and the light emission control signal line EM provides a high level signal.

[0076] Since the first reset signal line RST1 provides a low level signal, the first transistor M1 is turned on, and the reset voltage VINT is written to the node N1 through the first transistor M1 to achieve the reset process of the control electrode of the driving transistor DTFT. At the same time, since the second reset signal line RST2, the gate line GATE and the light emitting control signal line EM all provide high level signals, the second transistor M2 to the sixth transistor M6 are all turned off.

[0077] In the data writing and compensation phase t2 , the first reset signal line RST1 provides a high level signal, the second reset signal line RST2 provides a low level signal, the gate line GATE provides a low level signal, and the light emitting control signal line EM provides a high level signal.

[0078] Since the first reset signal line RST1 provides a high level signal, the first transistor M1 is turned off. At the same time, since the gate line GATE provides a low level signal, the third transistor M3 and the fifth transistor M5 are both turned on, and the data voltage provided by the data line is written to the node N2 through the third transistor M3. At this time, the driving transistor DTFT is in the on state, and the node N1 is charged through the fifth transistor M5 until the voltage at the node N1 is charged to Vdata+Vth, the driving transistor DTFT is turned off, and the charging is completed. Among them, Vdata is the data voltage, and Vth is the threshold voltage of the driving transistor DTFT.

[0079] At this time, since the second reset signal line RST2 provides a low level signal, the second transistor M2 is turned on, and the reset voltage VINT is written to the first end of the light emitting device OLED through the second transistor M2 to reset the first end of the light emitting device OLED.

[0080] It should be noted that, when the driving transistor DTFT outputs current to charge the node N1, the sixth transistor M6 is turned off, thereby preventing the light emitting device OLED from emitting light by mistake, thereby improving the display effect. Of course, in some embodiments, the sixth transistor M6 may not be required.

[0081] In the light emitting stage t3 , the first reset signal line RST1 provides a high level signal, the second reset signal line RST2 provides a high level signal, the gate line GATE provides a high level signal, and the light emitting control signal line EM provides a low level signal.

[0082] Since the light emitting control signal line EM provides a low level signal, the fourth transistor M4 and the sixth transistor M6 are turned on, and the driving transistor DTFT outputs a driving current I according to the voltage at the node N1 to drive the light emitting device OLED to emit light. According to the saturation driving current formula of the driving transistor DTFT, it can be obtained that

[0083] I=K*(Vgc-Vth) 2

[0084] =K*(Vdata+Vth-VDD-Vth) 2

[0085] =K*(Vdata-VDD) 2

[0086] Among them, K is a constant (the size of which is related to the electrical characteristics of the driving transistor DTFT), and Vgs is the gate-source voltage of the driving transistor DTFT. It can be seen from the above formula that the driving current of the driving transistor DTFT is only related to the data voltage Vdata and the operating voltage VDD, but has nothing to do with the threshold voltage Vth of the driving transistor DTFT, thereby preventing the driving current flowing through the light-emitting device OLED from being affected by the unevenness and drift of the threshold voltage, thereby effectively improving the uniformity of the driving current flowing through the light-emitting device OLED.

[0087] In some embodiments, to ensure that the voltage at the N1 node in the light-emitting stage t3 is always Vdata+Vth, a storage capacitor C1 may be further provided in the pixel driving circuit, wherein the first end of the storage capacitor C1 is connected to the second power supply end, and the second end of the storage capacitor C1 is connected to the control electrode of the driving transistor.

[0088] It should be noted that the pixel driving circuit in the embodiment of the present disclosure adopts Figure 2 The situation shown is only an optional solution of the present disclosure and will not limit the technical solution of the present disclosure.

[0089] Based on the above content, it can be seen that during the driving process of the pixel unit, the threshold compensation duration of the pixel driving circuit is equal to the writing duration of the gate scanning driving signal of the gate line, that is, the duration of the data writing and compensation stage t2 (the duration when the gate line is in a valid level state).

[0090] Figure 4 A schematic diagram of a structure of a display substrate in the related art is shown in FIG. Figure 4As shown, in the related art, each row of pixel units Pixel is configured with a corresponding gate line G1 / G2 / ... / GN, and each column of pixel units Pixel is configured with a corresponding data line D1 / D2 / ... / DM.

[0091] In order to ensure that the display device has a sufficient refresh rate (for example, 60HZ) during the display process, the total time required for a complete row of pixel units Pixel to complete data writing during the driving process will be configured. Assuming that the total time required for a complete row of pixel units Pixel to complete data writing is H, then Figure 4 The writing duration of the gate scanning drive signal corresponding to a gate line G1 / G2 / … / GN in the related technology shown is H, and the writing duration of the source driver (Source Driver) writing the data signal to the data line D1 / D2 / … / DM each time is H; that is, the duration of the data writing and compensation stage t2 in the pixel driving process is H.

[0092] In the embodiment disclosed in the present invention, it is assumed that the number of gate lines configured for a row of pixel units Pixel is c, and the writing duration of each time the source driver (Gate Driver) writes a data signal to the data line is H / c. Since two pixel units Pixel located in the same column and in adjacent rows are connected to different data lines, the interval between the start time of two consecutive writes of the data signal by the source driver to the same data line is T, which can be greater than H. At this time, the writing duration T' of each time the gate driver (not shown in the figure) writes a gate scanning drive signal to the gate line can also be greater than H, and it is only necessary to ensure that T'≤T. It should be noted that the source driver and the gate driver are not shown in the accompanying drawings.

[0093] It can be seen from the foregoing that, compared with the related art, when display driving is performed based on the display substrate provided by the embodiment of the present disclosure, the writing time of the gate scanning drive signal for each gate line can be increased, that is, the data writing and compensation stage t2 duration of the pixel driving circuit during the driving process can be increased, thereby ensuring the full implementation of the threshold compensation process, which is beneficial to improving the compensation effect.

[0094] Continue to see Figure 1 As shown, the technical solution disclosed in the present invention will increase the number of data lines on the display substrate, and the number of peripheral leads of the display substrate will increase, which is not conducive to the narrow frame design. At the same time, the number of signal output terminals of the required source driver will also increase, and the performance requirements for the source driver will increase.

[0095] In order to solve the above technical problems, the technical solution disclosed in the present invention sets a plurality of multiplexer circuits 5 in the non-display area, each of which corresponds to at least one column of pixel units Pixel; the multiplexer circuit 5 is configured with a data signal input terminal INPUT and a plurality of data signal output terminals, the plurality of data signal output terminals are respectively connected to a plurality of data lines configured for at least one column of pixel units corresponding to the multiplexer circuit, and the data signal output terminals correspond to the data lines one by one; wherein the data signal input terminal INPUT is specifically a signal output terminal of a source driver. The multiplexer circuit 5 is used to write a plurality of data signals provided by the data signal input terminal INPUT into the data lines connected to each data signal output terminal.

[0096] The technical solution disclosed in the present invention can reduce the number of peripheral leads of the display substrate by setting a multi-way selection circuit 5, which is beneficial to the narrow frame design; at the same time, the number of signal output terminals of the required source driver is also reduced, and the performance requirements for the source driver are reduced.

[0097] Generally speaking, the more data signal output terminals the multiplexer circuit 5 has, the more types of gating control signal lines need to be configured for the multiplexer circuit 5 (one data signal output terminal in the multiplexer circuit 5 corresponds to one type of gating control signal line), and the higher the requirements for the control chip that provides the gating control signal. Preferably, the number of data signal output terminals configured for the multiplexer circuit 5 should be less than or equal to 8.

[0098] In some embodiments, each row of pixel units is configured with corresponding m gate lines, and the kth gate line among the m gate lines is connected to the pixel unit in the b*m+kth row of the corresponding row of pixel units; wherein m is an integer and 1≤k≤m, b is a non-negative integer and b*m+k≤M, and N is the total number of columns of pixel units in the array.

[0099] The more gate lines are configured for each row of pixel units, the fewer pixel units are connected to each gate line, so the load on each gate line is less, which is conducive to the writing of gate scanning drive signals. However, too much gate line data will lead to a decrease in pixel aperture ratio. Therefore, in the embodiment of the present disclosure, preferably, 1≤m≤4.

[0100] Continue to see Figure 1As shown, in some embodiments, each row of pixel units Pixel is configured with two corresponding gate lines G1_1, G1_2 / G2_1, G2_2 / … / GN_1, GN_2, which are respectively the first gate line G1_1 / G2_1 / … / GN_1 and the second gate line G1_2 / G2_2 / … / GN_2; the first gate line G1_1 / G2_1 / … / GN_1 is connected to the pixel units Pixel in the odd columns of the corresponding row of pixel units Pixel, and the second gate line G1_2 / G2_2 / … / GN_2 is connected to the pixel units Pixel in the even columns of the corresponding row of pixel units Pixel. Connection; each column of pixel units Pixel is configured with corresponding two data lines D1_1, D1_2 / D2_1, D2_2 / … / DM_1, DN_2, which are respectively the first data line D1_1 / D2_1 / … / DM_1 and the second data line D1_2 / D2_2 / … / DM_2; the first data line D1_1 / D2_1 / … / DM_1 is connected to the pixel units Pixel in odd rows in the corresponding column of pixel units Pixel, and the second data line D1_2 / D2_2 / … / DM_2 is connected to the pixel units Pixel in even rows in the corresponding column of pixel units Pixel.

[0101] In some embodiments, the first gate line G1_1 / G2_1 / ... / GN_1 and the second gate line G1_2 / G2_2 / ... / GN_2 are located at the same side of the corresponding row of pixel units Pixel; Figure 1 For example, the first gate line G1_1 / G2_1 / … / GN_1 and the second gate line G1_2 / G2_2 / … / GN_2 are located on the “upper” side of the corresponding pixel unit Pixel. Of course, in the present disclosure, the first gate line G1_1 / G2_1 / … / GN_1 and the second gate line G1_2 / G2_2 / … / GN_2 may also be located on the opposite side of the corresponding row pixel unit Pixel, but no corresponding figure is given for this case.

[0102] In some embodiments, each two adjacent columns of pixel units Pixel correspond to a multiplexer circuit 5, and each multiplexer circuit 5 is connected to the four data lines configured for the two columns of pixel units Pixel corresponding to it; the multiplexer circuit 5 is also connected to the data signal input terminal INPUT, and is configured to write the four data signals provided by the data signal input terminal INPUT into the four data lines connected to it respectively.

[0103] In some embodiments, the multiplexer circuit 5 includes: a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The first end of the first switch S1, the first end of the second switch S2, the first end of the third switch S3, and the first end of the fourth switch S4 are all connected to the signal input end; the second end of the first switch S1 and the second end of the second switch S2 are respectively connected to the two first data lines D1_1 / D2_1 / … / DM_1 configured for the two columns of pixel units Pixel corresponding to the multiplexer circuit 5, and the second end of the third switch S3 and the second end of the fourth switch S4 are respectively connected to the two second data lines D1_2 / D2_2 / … / DM_2 configured for the two columns of pixel units Pixel corresponding to the multiplexer circuit 5.

[0104] The first switch S1 to the fourth switch S4 are all configured to control the on-off between the first end and the second end thereof.

[0105] In some embodiments, the first switch S1 to the fourth switch S4 are all switch transistors, and the control electrodes of the first switch S1 to the fourth switch S4 are connected to the first selection control signal line MUX1 to the fourth selection control signal line MUX4 respectively.

[0106] In the present disclosure, by setting up a multi-way selection circuit 5, the number of signal output terminals of the source driver can be effectively reduced, which is beneficial to the simplification of the source driver structure; at the same time, setting up the multi-way selection circuit 5 can also reduce the peripheral wiring of the non-display area, which is beneficial to the narrow frame design.

[0107] by Figure 1 Taking the situation shown in as an example, the four data lines correspond to a signal output terminal (a data signal input terminal INPUT) of the source driver, and the four data lines D1_1, D1_2, D2_1, D2_2 / … / DM-1_1, DM-1_2, DM_1, DM_2 can be connected to the source driver through the same signal routing (the signal routing located between the multiplexer circuit 5 and the signal output terminal of the source driver).

[0108] The driving process of the display substrate provided by the embodiment of the present disclosure will be described in principle below by taking the driving process of some pixel units Pixel in the display substrate as an example.

[0109] Figure 5 for Figure 1 A driving timing diagram of the display substrate is shown as follows: Figure 5As shown, the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 in the multiplexer circuit 5 are respectively controlled by the control signals provided by the first selection control signal line MUX1, the second selection control signal line MUX2, the third selection control signal line MUX3 and the fourth selection control signal line MUX4, and are turned on in sequence, so as to realize writing the data signal provided by the source driver into the first data line D1_1 / D2_1 / … / DM_1 or the second data line D1_2 / D2_2 / … / DM_2 connected to each of the first switch S1 to the fourth switch S4.

[0110] Since each row of pixel units Pixel corresponds to 2 gate lines, the total time required to complete data writing of all pre-configured pixel units Pixel in a row is H, so the writing time of writing data signals to the first data line D1_1 / D2_1 / … / DM_1 or the second data line D1_2 / D2_2 / … / DM_2 is H / 2, that is, the duration of each switch from the first switch S1 to the fourth switch S4 switching to the on state is H / 2. At this time, the interval T between the writing start time of two consecutive writing of data signals to the same data line by the source driver is 2H, so the maximum value of the writing time T' of the gate driver writing the gate scanning drive signal to each gate line is 2H.

[0111] It should be noted that Figure 5 The example only illustrates the case where the gate driver writes the gate scanning drive signal to each gate line with a writing duration T' of 2H. Those skilled in the art should know that in the disclosed embodiment, it is only necessary to ensure that the writing duration T' satisfies: H<T'≤T, T=2H, that is, the duration of the data writing and compensation phase can be increased to a certain extent (the threshold compensation duration of the pixel driving circuit in the pixel unit Pixel also increases accordingly), thereby improving the compensation effect.

[0112] In addition, based on Figure 5 During the driving process with the timing shown, the time required to complete a data signal writing process to a data line D1_1 / D1_2 / D2_1 / D2_2 / … / DM_1 / DM_2 is H / 2, and the data line is in a floating state during the subsequent 3H / 2 period. The load capacitance formed on the data line can maintain the same data signal continuously loaded on the data line.

[0113] Taking writing a data signal to the data line D1_1 as an example, in the first H / 2 time, when the first switch S1 is controlled by the first selection control signal line MUX1 and turned on, the source driver outputs the data signal and writes it to the first data line D1_1 through the first switch S1. In the second H / 2 time, when the first switch S1 is controlled by the first selection control signal line MUX1 and turned off, and the second switch S2 is controlled by the second selection control signal line MUX2 and turned on, the source driver outputs the data signal and writes it to the first data line D2_1 through the second switch S2. At this time, the first data line D1_1 is in a floating state, and the load capacitor formed on the first data line D1_1 can maintain the same data signal continuously loaded on the first data line D1_1. By analogy, when the fifth H / 2 time is reached, the first switch S1 is controlled by the first selection control signal line MUX1 and is turned on again, and the source driver writes a new data signal to the first data line D1_1. The interval between the start time of the source driver writing the data signal to the same first data line D1_1 twice in a row is 2H.

[0114] Figure 6 A schematic diagram of a circuit structure of a display substrate provided in an embodiment of the present disclosure is shown in FIG. Figure 6 As shown, what is different from the above-mentioned embodiment is that each column of pixel units Pixel corresponds to a multiplexer selection circuit 5 .

[0115] In some embodiments, each row of pixel units Pixel is configured with a corresponding gate line G1 / G2 / … / GN, and each gate line G1 / G2 / … / GN is connected to all pixel units Pixel in a corresponding row of pixel units Pixel; each column of pixel units Pixel is configured with corresponding n data lines, n is an integer and n≥2; the i-th data line among the n data lines is connected to the pixel unit Pixel in the a*n+i-th row in the corresponding column of pixel units Pixel; wherein i is an integer and 1≤i≤n, a is a non-negative integer and a*n+i≤N, and N is the total number of rows of pixel units Pixel in the array.

[0116] In some embodiments, each multiplexer circuit 5 is connected to the n data lines configured for a corresponding column of pixel units Pixel; the multiplexer circuit 5 is also connected to the data signal input terminal INPUT, and is configured to write the n data signals provided by the data signal input terminal INPUT to the n data lines connected thereto respectively.

[0117] Furthermore, the multi-way selection circuit 5 includes: n switches, the first ends of the n switches are all connected to the signal input end; the second end of the j-th switch among the n switches is connected to the j-th data line configured for the corresponding column pixel unit Pixel; wherein j is an integer and 1≤j≤n, and N is the total number of rows of pixel units Pixel in the array.

[0118] In some embodiments, the switches in the multiplexer circuit 5 are all switch transistors.

[0119] It should be noted that Figure 6 Only the case where n is 2 is illustrated, that is, each column of pixel units Pixel is configured with corresponding two data lines D1_1, D1_2 / D2_1, D2_2 / … / DM_1, DM_2, respectively denoted as the first data line D1_1 / D2_1 / … / DM_1 and the second data line D1_2 / D2_2 / … / DM_2. The multiplexer circuit 5 includes two switches, respectively denoted as the first switch S1 and the second switch S2.

[0120] Figure 7 for Figure 6 A driving timing diagram of the display substrate is shown as follows: Figure 7 As shown, the first switch S1 and the second switch S2 are respectively controlled by the control signals provided by the first selection control signal line MUX1 and the second selection control signal line MUX2 and are turned on in sequence, thereby realizing that the data signal provided by the source driver is written into the first data line D1_1 / D2_1 / … / DM_1 and the second data line D1_2 / D2_2 / … / DM_2 connected to the first switch S1 and the second switch S2 respectively.

[0121] Since each row of pixel units Pixel corresponds to one gate line, the total time taken to complete data writing of all pre-configured pixel units Pixel in a row is H, so the writing time of writing data signals to the first data line D1_1 / D2_1 / … / DM_1 or the second data line D1_2 / D2_2 / … / DM_2 is H each time, that is, the duration of each switch of the first switch S1 and the second switch S2 to the on state is H. At this time, the interval T between the writing start time of two consecutive writing of data signals to the same data line by the source driver is 2H, so the maximum value of the writing time T' of the gate driver writing the gate scanning drive signal to each gate line G1 / G2 / … / GN is 2H.

[0122] It should be noted that Figure 7The example only illustrates the case where the gate driver writes the gate scanning drive signal to each gate line G1 / G2 / … / GN with a writing duration T' of 2H. Those skilled in the art should know that in the disclosed embodiment, it is only necessary to ensure that the writing duration T' satisfies: H<T'≤T, T=2H, that is, the duration of the data writing and compensation phase can be increased to a certain extent (the threshold compensation duration of the pixel driving circuit in the pixel unit Pixel also increases accordingly), thereby improving the compensation effect.

[0123] Figure 8 A schematic diagram of a circuit structure of a display substrate provided in an embodiment of the present disclosure is shown in FIG. Figure 8 As shown, n is 4, that is, each column of pixel units Pixel is configured with corresponding 4 data lines D1_1, D1_2, D1_3, D1_4 / D2_1, D2_2, D2_3, D2_4 / … / DM_1, DM_2, DM_3, DM_4, respectively denoted as the first data line D1_1 / D2_1 / … / DM_1, the second data line D1_2 / D2_2 / … / DM_2, the third data line D1_3 / D2_3 / … / DM_3 and the fourth data line D1_4 / D2_4 / … / DM_4. The multiplexer circuit 5 includes 4 switches, respectively denoted as the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4.

[0124] In some embodiments, the four data lines D1_1, D1_2, D1_3, D1_4 / D2_1, D2_2, D2_3, D2_4 / … / DM_1, DM_2, DM_3, DM_4 corresponding to the same column of pixel units Pixel are evenly distributed on opposite sides of the corresponding column of pixel units Pixel. The figure illustrates that the first data line D1_1 / D2_1 / … / DM_1 and the second data line D1_2 / D2_2 / … / DM_2 are located on the left side of the corresponding column of pixel units Pixel, and the third data line D1_3 / D2_3 / … / DM_3 and the fourth data line D1_4 / D2_4 / … / DM_4 are located on the right side of the corresponding column of pixel units Pixel.

[0125] Fig. 9 for Figure 8 A driving timing diagram of the display substrate is shown as follows: Fig. 9As shown, the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 in the multiplexer circuit 5 are respectively controlled by the control signals provided by the first selection control signal line MUX1, the second selection control signal line MUX2, the third selection control signal line MUX3 and the fourth selection control signal line MUX4, and are turned on in sequence, so as to realize that the data signal provided by the source driver is written into the first data line D1_1 / D2_1 / … / DM_1 to the fourth data line D1_4 / D2_4 / … / DM_4 connected to the first switch S1 to the fourth switch S4 respectively.

[0126] Since each row of pixel units Pixel corresponds to one gate line, the total time taken to complete data writing of all pre-configured pixel units Pixel in one row is H, so the writing time of writing a data signal to a data line each time is H, that is, the duration of each switch from the first switch S1 to the fourth switch S4 switching to the on state is H. At this time, the interval T between the writing start time of two consecutive writing of data signals to the same data line by the source driver is 4H, so the maximum value of the writing time T' of the gate driver writing the gate scanning drive signal to each gate line G1 / G2 / … / GN is 4H.

[0127] It should be noted that Fig. 9 The example only illustrates the case where the gate driver writes the gate scanning drive signal to each gate line G1 / G2 / … / GN with a write duration T' of 4H. Those skilled in the art should know that in the disclosed embodiment, it is only necessary to ensure that the write duration T' satisfies: H<T'≤T, T=4H, that is, the duration of the data writing and compensation phase can be increased to a certain extent (the threshold compensation duration of the pixel drive circuit in the pixel unit Pixel also increases accordingly), thereby improving the compensation effect.

[0128] In the present disclosure, different data lines corresponding to the same column of pixel units Pixel can be arranged in the same layer or in different layers. "Arranged in the same layer" in the present disclosure means being located in the same functional film layer structure; wherein the preparation materials of different structures arranged in the same layer are the same, and thus can be prepared simultaneously using a single patterning process; the distances between different structures arranged in the same layer and the substrate can be the same or different. Figure 8 For example, the first data line and the third data line are arranged in the same layer, the second data line and the fourth data line are arranged in the same layer, and the first data line and the second data line are arranged in different layers. In order to improve the aperture ratio of the pixel, the orthographic projections of the first data line and the second data line on the plane where the display substrate is located can be overlapped, and the orthographic projections of the third data line and the fourth data line on the plane where the display substrate is located can be overlapped.

[0129] The embodiment of the present disclosure further provides a method for driving a display substrate, wherein the display substrate adopts the display substrate provided by any of the above embodiments, and the driving method includes:

[0130] Step Q1: write a scan drive signal to each gate line in sequence according to a predetermined order to drive the corresponding pixel unit, and write a corresponding data signal to the data line connected to the driven pixel unit.

[0131] Among them, the scanning order of the gate lines can be pre-set according to actual needs; for example, scanning in the forward direction (from the 1st gate line to the Nth gate line), scanning in the reverse direction (from the Nth gate line to the 1st gate line), or scanning according to certain rules.

[0132] In step Q1, the writing time of the source driver writing the data signal to the data line each time is H / c, and the interval between the writing start time of writing the data signal to the same data line twice in a row is T; wherein, T>H, H is the total time consumed to complete the data writing of a pre-configured row of pixel units, c is the number of gate lines configured for a row of pixel units, and T>H; the writing time of the gate driver writing the gate scanning drive signal to the gate line each time is T', and H<T'≤T.

[0133] In the embodiment of the present disclosure, assuming that the number of data lines configured for each column of pixel units is n, the maximum value of the interval T of the writing start time of the source driver writing the data signal to the same data line twice in a row can be set to n*H. In the present disclosure, it is only necessary to ensure that the interval T takes a value greater than H, so that the writing duration T' of the gate driver writing the gate scanning drive signal to the gate line each time can be set to be greater than H (when the interval T is determined, the maximum value of the writing duration T' can be H), thereby increasing the writing duration of each gate line writing the gate scanning drive signal. As a preferred solution, when the interval T takes a maximum value of n*H, the maximum value of the writing duration T' of the gate driver writing the gate scanning drive signal to the gate line each time can also be set to n*H, that is, the writing duration of each gate scanning drive signal to the gate line can be improved to the greatest extent.

[0134] Compared with the related art, when display driving is performed based on the driving method of the display substrate provided in the embodiment of the present disclosure, the writing time of the gate scanning driving signal for each gate line can be increased, that is, the data writing and compensation stage duration of the pixel driving circuit during the driving process can be increased, thereby ensuring the full implementation of the threshold compensation process, which is beneficial to improving the compensation effect.

[0135] In some embodiments, when the display substrate adopts Figure 1When the display substrate is shown in , the number of gate lines configured for each row of pixel units is 2, the number of data lines configured for each column of pixel units is 2, the writing time length of each time the source driver writes a data signal to the data line is H / 2, and the interval T between the writing start times of two consecutive writings of the data signal to the same data line is 2H (that is, when each column of pixel units is configured with 2 data lines, the interval between the writing start times of two consecutive writings of the data signal to the same data line can be the maximum value); the writing time length of each time the gate driver writes a gate scanning drive signal to the gate line is T', which is 2H.

[0136] In some embodiments, when the display substrate adopts Figure 6 and Figure 8 When the display substrate is shown in , the number of gate lines configured for each row of pixel units is 1, the number of data lines configured for each column of pixel units is n, the writing time length of each time the source driver writes a data signal to the data line is H, and the interval T between the writing start times of two consecutive writing of data signals to the same data line is n*H (that is, when each column of pixel units is configured with n data lines, the interval between the writing start times of two consecutive writing of data signals to the same data line can take the maximum value); the writing time length of each time the gate driver writes a gate scanning drive signal to the gate line is T', which is n*H.

[0137] For the detailed description of the above step Q1, please refer to the corresponding content in the above embodiment, which will not be repeated here.

[0138] An embodiment of the present disclosure further provides a display device, including: the display device includes the display substrate provided by any of the aforementioned embodiments.

[0139] In order to realize the driving of the display substrate, the display device may also include a source driver and a gate driver. Generally speaking, the source driver and the gate driver exist in the form of a chip; of course, a gate drive circuit may also be formed in the non-display area of ​​the display substrate based on the GOA (Gate Drive On Array) process to serve as a gate driver. The technical solution disclosed in the present invention does not limit the setting method of the source driver and the gate driver.

[0140] The display device may be any product or component with a display function, such as electronic paper, an OLED panel, an AMOLED panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.

[0141] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A display substrate, characterized in that: include: A display area and a non-display area located around the display area, wherein the display area is provided with a plurality of pixel units arranged in an array, a plurality of gate lines extending along the row direction of the array, and a plurality of data lines extending along the column direction of the array; a plurality of multiplexer selection circuits are provided in the non-display area, and each of the multiplexer selection circuits corresponds to at least one column of pixel units; the multiplexer selection circuit is configured with a data signal input terminal and a plurality of data signal output terminals, and the plurality of data signal output terminals are respectively connected to a plurality of data lines configured for the at least one column of pixel units corresponding to the multiplexer selection circuit, and the data signal output terminals correspond to the data lines one by one; and the number of the data signal output terminals is less than or equal to 8; Each row of pixel units is configured with corresponding m gate lines, and the kth gate line among the m gate lines is connected to the pixel unit in the b*m+kth column of the corresponding row of pixel units; wherein m is an integer greater than or equal to 2 and 1≤k≤m, b is a non-negative integer and b*m+k≤M, and M is the total number of columns of pixel units in the array; Each column of pixel units is configured with corresponding at least two of the data lines, and each of the data lines is connected to part of the pixel units in the corresponding column of pixel units; Each of the pixel units is connected to one of the gate lines and one of the data lines, and two pixel units located in the same column and in adjacent rows are connected to different data lines.

2. The display substrate according to claim 1, characterized in that: When the value of m is 2, the two gate lines corresponding to each row of pixel units are the first gate line and the second gate line respectively; The first gate line is connected to the pixel units in the odd columns in the corresponding row of pixel units, and the second gate line is connected to the pixel units in the even columns in the corresponding row of pixel units.

3. The display substrate according to claim 2, characterized in that: Each column of pixel units is configured with two corresponding data lines, namely a first data line and a second data line; The first data line is connected to the pixel units in the odd-numbered rows in the corresponding column of pixel units, and the second data line is connected to the pixel units in the even-numbered rows in the corresponding column of pixel units.

4. The display substrate according to claim 3, characterized in that: Every two adjacent columns of pixel units correspond to a multiplex selection circuit; The multi-way selection circuit includes: a first switch, a second switch, a third switch and a fourth switch; The first end of the first switch, the first end of the second switch, the first end of the third switch, and the first end of the fourth switch are all connected to the signal input end; The second end of the first switch and the second end of the second switch are respectively connected to the two first data lines configured for the two columns of pixel units corresponding to the multiplexer circuit, and the second end of the third switch and the second end of the fourth switch are respectively connected to the two second data lines configured for the two columns of pixel units corresponding to the multiplexer circuit.

5. The display substrate according to claim 1, characterized in that: Each column of pixel units is configured with corresponding n data lines, where n is an integer and n≥2; The i-th data line among the n data lines is connected to the pixel unit in the a*n+i-th row among the corresponding column of pixel units; Wherein, i is an integer and 1≤i≤n, a is a non-negative integer and a*n+i≤N, and N is the total number of rows of pixel units in the array.

6. The display substrate according to claim 5, characterized in that: Each row of pixel units is configured with a corresponding gate line, and the gate line is connected to all pixel units in the corresponding row of pixel units.

7. The display substrate according to claim 6, characterized in that: Each column of pixel units corresponds to a multiplexer circuit, and the multiplexer circuit includes: n switches, The first ends of the n switches are all connected to the signal input end; A second end of the j-th switch among the n switches is connected to the j-th data line configured for the corresponding column of pixel units; Wherein, j is an integer and 1≤j≤n.

8. The display substrate according to claim 6, characterized in that: The value of n is 4.

9. The display substrate according to claim 8, characterized in that: The four data lines corresponding to the same column of pixel units are evenly distributed on two opposite sides of the corresponding column of pixel units.

10. A display device, characterized in that: include: A display substrate as claimed in any one of claims 1 to 9.

11. A method for driving a display substrate, characterized in that: The display substrate adopts the display substrate according to any one of claims 1 to 10, and the driving method comprises: Writing a scan drive signal to each of the gate lines in sequence according to a predetermined order to drive a corresponding pixel unit, and writing a corresponding data signal to a data line connected to the driven pixel unit; The writing time of each data signal to the data line is H / c, and the interval between the writing start time of two consecutive data signals to the same data line is T, H is the total time taken to complete the data writing of a pre-configured row of pixel units, c is the number of gate lines configured for a row of pixel units, and T>H; The writing time length of each time the gate scanning driving signal is written into the gate line is T', H<T'≤T.

12. The method for driving a display substrate according to claim 11, wherein: The display substrate adopts the display substrate as claimed in claim 4, and the writing time length of each data signal written to the data line is H / 2; The interval T between the start time of writing data signals to the same data line twice in a row is 2H; The writing duration T' for writing the gate scanning driving signal to the gate line each time is 2H.

13. The method for driving a display substrate according to claim 11, wherein: The display substrate adopts the display substrate described in claim 7, and the writing time length of each data signal written to the data line is H; The interval T between the start time of writing data signals to the same data line twice in succession is n*H; The writing time length of each time the gate scanning driving signal is written to the gate line is T', which has a value of n*H.

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