Adhesive member, display device including the same, and method of manufacturing display device

Abstract

The present application relates to an adhesive member, a display device including the same, and a method of manufacturing a display device. The adhesive member is positioned between an electronic component and an electronic panel, and the electronic component and the electronic panel are connected to each other by the adhesive member. The adhesive member has a second surface and a first surface. The adhesive member includes a first recessed pattern recessed from the first surface and a second recessed pattern recessed from the first surface. The second recessed pattern is spaced apart from the first recessed pattern in a first direction. A sum of a planar area of the first recessed pattern and a planar area of the second recessed pattern is in a range of about 20% to about 70% of a planar area of the first surface.

Description

[0001] This application claims priority to and all benefits arising therefrom of Korean Patent Application No. 10-2020-0007408, filed on January 20, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of the present invention relate to display devices, and more specifically, to adhesive members for connecting electronic components and display panels to each other, display devices including the adhesive members, and methods for manufacturing display devices. Background Technology

[0003] Various display devices are being developed for multimedia devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles.

[0004] The display device includes a display panel for displaying images. The display panel includes multiple gate lines, multiple data lines, and multiple pixels connected to the multiple gate lines and multiple data lines. The display device may include electronic components that provide electrical signals required for displaying images to the gate lines or data lines.

[0005] Electronic components can be electrically connected to the display panel via anisotropic conductive films or by ultrasonic bonding. Compared to using anisotropic conductive films, ultrasonic bonding increases conductivity and simplifies the process for connecting the display panel and electronic components. Summary of the Invention

[0006] Some embodiments of the present invention provide an adhesive member capable of increasing the reliability of the connection between electronic components and a display panel, a display device including the adhesive member, and a method for manufacturing the display device.

[0007] Embodiments of the present invention provide an adhesive member for connecting electronic components and electronic panels to each other. The adhesive member includes a second surface and a first surface opposite to each other. The adhesive member defines a first recessed pattern recessed from the first surface and a second recessed pattern recessed from the first surface. The second recessed pattern is spaced apart from the first recessed pattern in a first direction. The sum of the planar areas of the first and second recessed patterns is in the range of about 20% to about 70% of the planar area of ​​the first surface.

[0008] In an implementation, the height of the first recessed pattern recessed from the first surface may be different from the height of the second recessed pattern recessed from the first surface.

[0009] In an implementation, the planar area of ​​the first recessed pattern in the planar view may be different from the planar area of ​​the second recessed pattern.

[0010] In an embodiment, each of the first recessed pattern and the second recessed pattern may have a shape extending along a second direction perpendicular to the first direction.

[0011] In one embodiment, the first recessed pattern may include a plurality of first sub-recessed patterns, which are recessed from the first surface and arranged at a first interval along a second direction perpendicular to the first direction. The second recessed pattern may include a plurality of second sub-recessed patterns, which are recessed from the first surface and arranged at a second interval along a second direction.

[0012] In an implementation, the planar area of ​​one of the plurality of second sub-recessed patterns may be greater than the planar area of ​​each of the plurality of first sub-recessed patterns.

[0013] In an implementation, the second interval may be larger than the first interval.

[0014] In one embodiment, the adhesive component may include a thermal initiator. The adhesive component may have non-conductive properties and may surround the electronic component.

[0015] In an implementation, the first recessed pattern may include a first sub-recessed pattern extending in a second direction perpendicular to the first direction and a second sub-recessed pattern parallel to the second direction.

[0016] Embodiments of the present invention provide a display device, comprising: a base substrate defining a display area and a non-display area adjacent to the display area, the non-display area including a first pad area, a second pad area, and a non-pad area located between the first pad area and the second pad area; a plurality of first pads located on the base substrate, the plurality of first pads overlapping the first pad area; a plurality of second pads located on the base substrate, the plurality of second pads overlapping the second pad area; an electronic component including a plurality of first protrusions electrically contacting corresponding first pads of the plurality of first pads, a plurality of second protrusions electrically contacting corresponding second pads of the plurality of second pads, and a substrate, the first protrusions and second protrusions being disposed on the substrate, the electronic component and the base substrate facing each other in the thickness direction of the base substrate; and a first adhesive member located between the base substrate and the electronic component. An internal space is defined by the substrate, the first adhesive member, and two adjacent first protrusions overlapping the first pad area.

[0017] In one embodiment, the first pad region and the second pad region may be spaced apart across the non-pad region in a first direction. The first pad may be arranged along a second direction perpendicular to the first direction. The second pad may be arranged along the second direction.

[0018] In one embodiment, a plurality of first pads may be arranged along a second direction at a first interval. A plurality of second pads may be arranged along a second direction at a second interval. The second interval may be larger than the first interval.

[0019] In one implementation, one of the plurality of second pads has a planar area larger than that of each of the plurality of first pads.

[0020] In one embodiment, the first adhesive member may partially cover at least one of the first protrusion and the second protrusion.

[0021] In an embodiment, the display device may further include: a plurality of connection pads spaced apart from electronic components in a plan view and disposed on a base substrate, the plurality of connection pads overlapping a non-display area; a circuit board overlapping the non-display area and including a plurality of circuit pads electrically contacting corresponding connection pads among the plurality of connection pads; and a second adhesive member located between the circuit board and the base substrate.

[0022] In one embodiment, the second adhesive member may partially cover at least one of the plurality of circuit pads.

[0023] One embodiment of the present invention provides a method of manufacturing a display device, comprising: providing a display panel and an electronic component, the display panel including pads and the electronic component including protrusions facing the pads; disposing an adhesive member between the display panel and the electronic component, the adhesive member including a first surface and a second surface; defining a recessed pattern recessed from the first surface of the adhesive member; aligning the adhesive member such that the recessed pattern overlaps with the pads and the protrusions; applying thermal pressure to the electronic component such that the protrusions make electrical contact with the pads; and providing ultrasonic vibration to the interface between the pads and the protrusions.

[0024] In this implementation, the adhesive member may define a recessed area overlapping the pad and a non-recessed area adjacent to the recessed area. Before applying thermal pressure to the electronic components, when viewed along the thickness direction of the display panel, the thickness of the adhesive member overlapping the non-recessed area may be greater than the sum of the height of the pad and the height of the protrusion.

[0025] In an embodiment, the planar area of ​​the recessed pattern may fall within the range of about 20% to about 70% of the planar area of ​​the first surface.

[0026] In one embodiment, the method may further include defining another recessed pattern, which is spaced apart from the recessed pattern in a predetermined direction and recessed from the first surface of the adhesive member. When viewed along the thickness direction of the display panel, the height of the recessed pattern may differ from the height of the other recessed pattern. Attached Figure Description

[0027] The above and other embodiments, advantages, and features of this disclosure will become more apparent from the accompanying drawings, which describe embodiments of the present disclosure in more detail:

[0028] Figure 1A A perspective view illustrating an embodiment of the display device according to the present invention is shown;

[0029] Figure 1B An exploded perspective view illustrating an embodiment of a display device according to the present invention is shown;

[0030] Figure 2 A cross-sectional view illustrating an embodiment of the display module according to the present invention is shown;

[0031] Figure 3 A plan view illustrating an embodiment of a display panel according to the present invention is shown;

[0032] Figure 4A It shows Figure 3 The equivalent circuit diagram of the pixels shown;

[0033] Figure 4B A cross-sectional view is shown, partially illustrating an embodiment of a display panel that overlaps with the display area according to the present invention;

[0034] Figure 5A It shows Figure 3 A magnified view of part AA;

[0035] Figure 5B It shows along Figure 5A A sectional view taken by line I-I';

[0036] Figure 6 An exploded perspective view illustrating an embodiment of a display device according to the present invention is shown;

[0037] Figure 7 A plan view illustrating an embodiment of an electronic component according to the present invention is shown;

[0038] Figure 8A A perspective view illustrating an embodiment of the first adhesive member according to the present invention is shown;

[0039] Figure 8B A perspective view illustrating an embodiment of the first adhesive member according to the present invention is shown;

[0040] Figure 9A The invention illustrates the following: Figure 7 A cross-sectional view of the embodiment taken by line II-II';

[0041] Figure 9B The invention illustrates the following: Figure 7A cross-sectional view of the embodiment taken by line II-II';

[0042] Figure 10A The invention illustrates the following: Figure 8A A cross-sectional view of the embodiment taken by line III-III';

[0043] Figure 10B The invention illustrates the following: Figure 8A A cross-sectional view of the embodiment taken by line III-III';

[0044] Figure 10C The invention illustrates the following: Figure 8A A cross-sectional view of the embodiment taken by line III-III';

[0045] Figure 11 A perspective view illustrating an embodiment of the second adhesive member according to the present invention is shown;

[0046] Figure 12 A perspective view illustrating an embodiment of the first adhesive member according to the present invention is shown; and

[0047] Figures 13A to 13C A cross-sectional view illustrating an embodiment of a method for manufacturing a display device according to the present invention is shown. Detailed Implementation

[0048] In this specification, when a component (or area, layer, part, etc.) is referred to as being on, connected to, or linked to other components (multiple components), that component may be directly disposed on, directly connected to, or directly linked to other components (multiple components), or there may be at least one intermediate component among them.

[0049] The same symbols represent the same components. Furthermore, in the accompanying drawings, the thickness, proportions, and dimensions of the components are exaggerated to effectively explain the technical content.

[0050] The term "and / or" includes one or more combinations defined by the relevant components.

[0051] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component without departing from the scope of the invention, and vice versa. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0052] Furthermore, the terms "below," "under," "above," "upper," etc., are used herein to describe the relationship between one component and other components (multiple components) shown in the accompanying drawings. In addition to the orientations depicted in the drawings, relative terms are intended to include different orientations.

[0053] As used herein, “about” or “approximately” includes the value and the average of the specific value within an acceptable range of deviations from the value, as determined by a person skilled in the art considering the measurements discussed and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations or within ±30%, ±20%, ±10%, ±5% of the value.

[0054] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore, terms commonly defined in dictionaries shall be understood to have the same meaning as defined in the context of the art, and shall not be construed as having an ideal or overly formal meaning unless expressly defined herein.

[0055] It should be understood that the terms “comprising,” “including,” “having,” etc., are used to specify the presence of the stated features, wholes, steps, operations, components, elements, or combinations thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, components, elements, or combinations thereof.

[0056] Now, some embodiments of the present invention will be described below with reference to the accompanying drawings.

[0057] Figure 1A A perspective view illustrating an embodiment of the display device according to the present invention is shown. Figure 1B An exploded perspective view of an embodiment of the display device according to the present invention is shown. Figure 2 A cross-sectional view illustrating an embodiment of the display module according to the present invention is shown.

[0058] This specification exemplarily illustrates a display device DD suitable for a mobile phone terminal. Although not shown, the mobile phone terminal may include the display device DD in a bracket / housing that houses a motherboard on which electronic modules, camera modules, power modules, etc., are mounted. The display device DD according to the invention can be applied not only to large electronic products such as televisions and monitors, but also to small and medium-sized electronic products such as tablet computers, car navigation systems, game consoles, and smartwatches.

[0059] Reference Figure 1AThe display device DD can display an image IM on the display surface DD-IS. An icon is shown as an example of an image IM. The display surface DD-IS is parallel to the plane defined by the first direction DR1 and the second direction DR2. The third direction DR3 represents the normal direction with respect to the display surface DD-IS, or the thickness direction of the display device DD. In this specification, the phrase "plan view" may mean "a view on the third direction DR3". The third direction DR3 distinguishes the front (or top) surface and the rear (or bottom) surface of each layer or unit described below from each other. The directions represented by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may refer to corresponding opposite directions.

[0060] The display surface DD-IS includes a display area DD-DA on which an image IM is displayed, and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA is the area on which no image is displayed. However, the invention is not limited thereto, and the non-display area DD-NDA may be adjacent to one side of the display area DD-DA or may be omitted.

[0061] Reference Figure 1B The display device DD may include a window WM, a display module DM, a driver chip DC, a circuit board PB, and a housing component BC. The housing component BC may receive the display module DM and may be associated with the window WM.

[0062] A window WM can be positioned above a display module DM and can transmit an image IM provided from the display module DM to the outside. The window WM includes a transmissive region TA and a non-transmissive region NTA. The transmissive region TA can overlap with the display regions DD-DA and can have a shape corresponding to the shape of the display regions DD-DA. The image IM displayed on the display regions DD-DA of the display device DD is visible to the outside through the transmissive region TA of the window WM.

[0063] The non-transmissive region NTA can overlap with the non-display region DD-NDA and can have a shape corresponding to the shape of the non-display region DD-NDA. The non-transmissive region NTA can be a region with a relatively small light transmittance compared to the transmissive region TA. However, the technical concept of the present invention is not limited thereto, and the non-transmissive region NTA can be omitted.

[0064] In embodiments, the window WM may include, for example, glass, sapphire, or plastic. Although the window WM is shown as a single layer, it may include multiple layers. The window WM may include a base layer and at least one printed layer that overlaps with the non-transparent region NTA and is disposed on the back surface of the base layer. The printed layer may have a predetermined color. In embodiments, for example, the printed layer may be black or any color other than black.

[0065] The display module DM is positioned between the window WM and the receiving component BC. The display module DM includes a display panel DP and an input sensing layer ISU. The display panel DP can generate an image IM and can transmit the generated image IM to the window WM.

[0066] In some embodiments, the display panel DP can be a light-emitting display panel, and is not particularly limited to a specific type. In embodiments, for example, the display panel DP can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The emitting layer of a quantum dot light-emitting display panel may include quantum dots or quantum rods. Examples of using an organic light-emitting display panel as the display panel DP will be described below.

[0067] The following describes an organic light-emitting display panel used as the display panel DP according to the present invention. However, the technical concept of the present invention is not limited thereto, and various types of display panels can be applied to the present invention based on the embodiments.

[0068] Reference Figure 2 The display panel DP includes a base substrate SUB, and also includes a circuit element layer DP-CL, a display element layer DP-OLED, and a dielectric layer TFL, all of which are disposed on the base substrate SUB.

[0069] The display panel DP includes the display area DP-DA and the non-display area DP-NDA. The display area DP-DA of the display panel DP corresponds to... Figure 1A The display area shown is DD-DA or Figure 1B The transmission area TA shown, and the non-display area DP-NDA of the display panel DP, correspond to... Figure 1A The non-display area DD-NDA shown is... Figure 1B The non-transmissive region NTA is shown in the figure.

[0070] The base substrate SUB may include at least one plastic film. In embodiments, the base substrate SUB may include a flexible substrate, such as a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0071] The circuit element layer DP-CL includes at least one intermediate dielectric layer and circuit elements. The intermediate dielectric layer includes at least one intermediate inorganic layer and at least one intermediate organic layer. The circuit elements include signal lines and pixel driver circuitry.

[0072] The DP-OLED display element layer includes a plurality of organic light-emitting diodes. The DP-OLED display element layer may also include an organic layer such as a pixel defining layer. In other embodiments, when the display panel DP is configured as a liquid crystal display panel, the DP-OLED display element layer may be configured as a liquid crystal layer.

[0073] A dielectric layer TFL encapsulates the display element layer DP-OLED. In embodiments, the dielectric layer TFL can be, for example, a thin-film encapsulation layer. The dielectric layer TFL protects the display element layer DP-OLED from impurities such as moisture, oxygen, and dust particles. However, the invention is not limited thereto, and the dielectric layer TFL can be replaced by an encapsulation substrate. In this case, the encapsulation substrate can be opposite to the base substrate SUB, and the circuit element layer DP-CL and the display element layer DP-OLED can be disposed between the encapsulation substrate and the base substrate SUB.

[0074] An input sensing layer (ISU) can be positioned between the window (WM) and the display panel (DP). The ISU detects externally applied input. Externally applied input can be of various types. In this embodiment, externally applied input includes the user's body, a stylus, light, heat, pressure, or any other type of external input. Furthermore, for example, externally applied input can include not only the user's touch but also proximity-based spatial touch (e.g., hover touch).

[0075] The input sensing layer (ISU) can be directly disposed on the display panel (DP). In this specification, the phrase "A is directly disposed on B" means that no adhesive layer is disposed between A and B. In the illustrated embodiment, the input sensing layer (ISU) and the display panel (DP) can be manufactured in a continuous process. However, the inventive concept is not limited thereto. The input sensing layer (ISU) can be configured as a separate panel and can be attached to the display panel (DP) via an adhesive layer. In another embodiment, the input sensing layer (ISU) can be omitted.

[0076] Refer again Figure 1B The driver chip DC can be disposed on the display panel DP, overlapping with the non-display area DP-NDA. In an embodiment, for example, the driver chip DC can generate drive signals required for the operation of the display panel DP in response to control signals transmitted from the circuit board PB. The driver chip DC can transmit the generated drive signals to the circuit element layer DP-CL of the display panel DP. In this specification, the driver chip DC can be interpreted as an electronic component.

[0077] In some embodiments, an ultrasonic bonding method can be used to electrically bond the driver chip DC to the base substrate SUB. In one embodiment, for example, the display panel DP according to the invention may include pads electrically connected to the display element layer DP-OLED, and the driver chip DC may include protrusions electrically contacting the pads. According to the invention, the pads of the display panel DP and the protrusions of the driver chip DC may be directly connected to each other, rather than indirectly connected by separate conductive materials.

[0078] A circuit board PB can be disposed at one end of the base substrate SUB and electrically connected to the circuit element layer DP-CL. The circuit board PB can be rigid or flexible. In embodiments, for example, when the circuit board PB is flexible, it can be configured as a flexible printed circuit board. The circuit board PB may include timing control circuitry for controlling the operation of the display panel DP. The timing control circuitry may be configured as an integrated circuit chip disposed (e.g., mounted) on the circuit board PB. Furthermore, although not shown, the circuit board PB may include input sensing circuitry for controlling the input sensing layer ISU.

[0079] In some embodiments, an ultrasonic bonding method can also be used to electrically bond the circuit board PB to the base substrate SUB of the display panel DP. The structure of ultrasonically bonding the circuit board PB and the driver chip DC to the base substrate SUB will be described in detail below.

[0080] Figure 3 A plan view illustrating an embodiment of the display panel according to the present invention is shown. Figure 4A It shows Figure 3 The equivalent circuit diagram of the implementation of the pixel shown is shown. Figure 4B A cross-sectional view is shown, partially illustrating an embodiment of a display panel that overlaps with the display area according to the present invention.

[0081] Reference Figure 3 The display panel DP may include driver circuit GDC, multiple signal lines SGL, multiple pads DP-PD, multiple connection pads DP-CPD, and multiple pixels PX.

[0082] Pixels PX are disposed in the display area DP-DA. Each pixel PX includes an organic light-emitting diode and pixel driver circuitry connected to the organic light-emitting diode. The driver circuitry GDC, signal line SGL, pad DP-PD, connection pad DP-CPD, and pixel driver circuitry can be included in the circuit element layer DP-CL shown in Figure 2.

[0083] In this specification, the display panel DP can be interpreted as a display substrate, and the display substrate may include a base substrate SUB and multiple pads DP-PD and multiple connection pads DP-CPD disposed on the base substrate SUB.

[0084] The driver circuit GDC sequentially outputs gate signals to multiple gate lines GL. The driver circuit GDC can also output different control signals to the pixel PX. The driver circuit GDC may include multiple thin-film transistors provided by, for example, one of the low-temperature polycrystalline silicon ("LTPS") process and low-temperature polycrystalline oxide ("LTPO") process, the same process used to form the driver circuit for the pixel PX.

[0085] The signal line SGL includes gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each gate line GL is connected to a corresponding pixel in pixel PX, and each data line DL is connected to a corresponding pixel in pixel PX. The power line PL is connected to pixel PX. The control signal line CSL provides control signals to the scan driver circuitry.

[0086] The signal line SGL overlaps with the display area DP-DA and the non-display area DP-NDA. Each signal line SGL may include a pad portion and a line portion. The line portion overlaps with the display area DP-DA and the non-display area DP-NDA. The pad portion is connected to the distal end of the line portion. The pad portion may overlap with the non-display area DP-NDA. The specification states that the signal line SGL includes a line portion and a pad portion; however, the line portion and the pad portion may be located in separate components.

[0087] According to the present invention, the non-display area DP-NDA includes a chip area NDA-CA and a connection pad area NDA-PA, wherein the pad DP-PD overlaps with the chip area NDA-CA, and the connection pad DP-CPD overlaps with the connection pad area NDA-PA. According to the present invention, the chip area NDA-CA may be disposed thereon (e.g., mounted). Figure 1B The driver chip DC area is shown, and the connection pad area NDA-PA can be set on it (e.g., mounted). Figure 1B This is a portion of the circuit board PB shown in the diagram.

[0088] In an implementation, for example, the chip region NDA-CA includes a first pad region SA1 and a second pad region SA2 spaced apart from each other in a first direction DR1. Although not shown, the non-pad region can be defined as the area between the first pad region SA1 and the second pad region SA2.

[0089] The pad DP-PD is electrically connected to the driver chip DC and provides the electrical signal received from the driver chip DC to the signal line SGL. In an embodiment, for example, the pad DP-PD includes a first pad DP-PD1 that overlaps with a first pad region SA1 and a second pad DP-PD2 that overlaps with a second pad region SA2.

[0090] The first pad DP-PD1 can be arranged along the second direction DR2 at a first interval, and can be disposed on the base substrate SUB while overlapping with the first pad region SA1. In an embodiment, for example, the first pad DP-PD1 can include pads in a plurality of rows divided along the first direction DR1. The second pad DP-PD2 can be arranged along the second direction DR2 at a second interval, and can be disposed on the base substrate SUB while overlapping with the second pad region SA2.

[0091] according to Figure 3 In the embodiment shown, the first pad DP-PD1 may include a first row of pads and a second row of pads separated from the first row of pads in the first direction DR1, and the second pad DP-PD2 may include a single row of pads. Thus, the number of first pads DP-PD1 corresponds to the number of signal lines SGL, and therefore the number of first pads DP-PD1 can be greater than the number of second pads DP-PD2.

[0092] According to the present invention, the second pad DP-PD2 may correspond to an input pad electrically connected to the corresponding connection pad DP-CPD, and the first pad DP-PD1 may correspond to an output pad electrically connected to the corresponding signal line SGL. In an embodiment, for example, the first pad DP-PD1 may correspond to the corresponding pad portion of the aforementioned signal line SGL.

[0093] The connection pads DP-CPD can be arranged at regular intervals along the second direction DR2, and can be disposed on the base substrate SUB while overlapping with the connection pad areas NDA-PA. The connection pads DP-CPD in the connection pad DP-CPD can be electrically connected to the corresponding second pads DP-PD2 disposed in the second pad area SA2, and the remaining connection pads DP-CPD in the connection pad DP-CPD can be electrically connected to the corresponding signal lines SGL. In an embodiment, for example, one of the connection pads DP-CPD is connected to the control signal line CSL.

[0094] The circuit board PB includes circuit pads PB-PD that are electrically in contact with corresponding connection pads DP-CPD, such that the circuit pads PB-PD and the corresponding connection pads DP-CPD face each other on a third-direction DR3. The circuit pads PB-PD may be located in the circuit pad area NDA-PCA defined in the circuit board PB.

[0095] Reference Figure 4A The display area DP-DA can be defined as the area defined by pixels PX. Each pixel PX includes an organic light-emitting diode (OLED) and pixel driver circuitry connected to the OLED.

[0096] In an implementation, for example, a pixel PX may include a first transistor T1, a second transistor T2, a capacitor CP, and an organic light-emitting diode (OLED). A pixel driver circuit comprising a switching transistor and a driver transistor is sufficient, but the invention is not limited thereto. Figure 4A The implementation shown is based on... Figure 4A In the embodiment shown, the first transistor T1 and the second transistor T2 are shown as p-channel (+) metal-oxide-semiconductor ("PMOS") transistors, but the first transistor T1 and the second transistor T2 can be configured as n-channel (-) metal-oxide-semiconductor ("NMOS") transistors.

[0097] The first transistor T1 is connected to the gate line GL and the data line DL. The organic light-emitting diode (OLED) receives a first power voltage ELVDD and a second power voltage ELVSS from the power line PL. The first power voltage ELVDD is supplied to the first electrode of the OLED through the second transistor T2, and the second power voltage ELVSS is supplied to the second electrode of the OLED. The second power voltage ELVSS may be less than the first power voltage ELVDD.

[0098] Reference Figure 4B A display panel (DP) can include multiple dielectric layers, semiconductor patterns, conductive patterns, and signal lines. The dielectric, semiconductor, and conductive layers are provided by coating or deposition. Then, the dielectric, semiconductor, and conductive layers can be selectively patterned using photolithography. The processes mentioned above can form the semiconductor patterns, conductive patterns, and signal lines included in the circuit element layer (DP-CL) and the display element layer (DP-OLED). In the description... Figure 4B When the display panel DP is shown, Figure 4A The pixel driver circuit shown includes components other than the first transistor T1 and the second transistor T2. The base substrate SUB can support the circuit element layer DP-CL and the display element layer DP-OLED.

[0099] In embodiments, the base substrate SUB may include a synthetic resin film. The synthetic resin film may include, for example, a thermosetting resin. The base substrate SUB may have a multilayer structure. In embodiments, for example, the base substrate SUB may have a three-layer structure including a synthetic resin layer, an adhesive layer, and a synthetic resin layer. In embodiments, for example, the synthetic resin layer may be a polyimide-based resin layer, and there are no particular limitations on its material. In embodiments, for example, the synthetic resin layer may include one or more of acrylic resins, methacrylate resins, polyisoprene, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and dinaphthalene-based resins. In optional embodiments, the base substrate SUB may include one or more of a glass substrate, a metal substrate, and an organic / inorganic composite substrate.

[0100] At least one inorganic layer may be disposed on the top surface of the base substrate SUB. In embodiments, for example, the inorganic layer may include one or more of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be multilayered. Multiple inorganic layers may constitute a barrier layer and / or a buffer layer. In the illustrated embodiment, the display panel DP is shown as including a buffer layer BFL.

[0101] The buffer layer (BFL) increases the adhesion between the base substrate (SUB) and the semiconductor pattern. The BFL may comprise a silicon oxide layer and a silicon nitride layer. The silicon oxide and silicon nitride layers can be stacked alternately.

[0102] A semiconductor pattern is disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, the invention is not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide.

[0103] Figure 4B Only an example of a semiconductor pattern is shown; in the planar view, the semiconductor pattern can also be disposed on different regions of the pixel PX. The semiconductor pattern can be specifically arranged above the pixel PX. The semiconductor pattern can have different electrical characteristics depending on whether the semiconductor pattern is doped. The semiconductor pattern can include doped regions and undoped regions. The doped regions can be implanted with n-type or p-type impurities. A p-type transistor includes a doped region implanted with p-type impurities.

[0104] Doped regions have higher conductivity than undoped regions and are essentially used as electrodes or signal lines. Undoped regions essentially correspond to the active region (or channel) of a transistor. In implementations, for example, a portion of the semiconductor pattern may be the active region of a transistor, another portion of the semiconductor pattern may be the source or drain of a transistor, and yet another portion of the semiconductor pattern may be a connection electrode or a connection signal line.

[0105] like Figure 4B As shown, the source S1, active region A1, and drain D1 of the first transistor T1 comprise semiconductor patterns, and the source S2, active region A2, and drain D2 of the second transistor T2 comprise semiconductor patterns. When viewed in cross-section, the source S1 and drain D1 extend in the direction opposite to the active region A1, and similarly, the source S2 and drain D2 extend in the direction opposite to the active region A2. Figure 4B The connection signal line SCL, which includes a semiconductor pattern, is partially shown. Although not shown, in the plan view, the connection signal line SCL can be connected to the drain D2 of the second transistor T2.

[0106] A first dielectric layer 10 is disposed on a buffer layer BFL. The first dielectric layer 10 collectively overlaps with a plurality of pixels PX and covers a semiconductor pattern. The first dielectric layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. In embodiments, for example, the first dielectric layer 10 may include one or more of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In the illustrated embodiment, the first dielectric layer 10 may be a single-layer silicon oxide layer. Similarly, the dielectric layer of the circuit element layer DP-CL may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The inorganic layer may include one or more of the materials mentioned above.

[0107] Gates G1 and G2 are disposed on the first dielectric layer 10. Each of gates G1 and G2 may be part of a metal pattern. Gates G1 and G2 overlap with active regions A1 and A2, respectively. Gates G1 and G2 may be used as masks in a process of doping the semiconductor pattern.

[0108] A second dielectric layer 20 covering gates G1 and G2 is disposed on the first dielectric layer 10. The second dielectric layer 20 overlaps with the pixel PX. The second dielectric layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. In the illustrated embodiment, the second dielectric layer 20 may be a single-layer silicon oxide layer.

[0109] The upper electrode UE can be disposed on the second dielectric layer 20. The upper electrode UE can overlap with the gate G2 of the second transistor T2. The upper electrode UE can be part of a metal pattern. Capacitor (refer to) Figure 4A The CP can be defined by a portion of the gate G2 and an upper electrode UE that overlaps with that portion of the gate G2.

[0110] A third dielectric layer 30 covering the top electrode UE is disposed on the second dielectric layer 20. In the illustrated embodiment, the third dielectric layer 30 may be a single layer of silicon oxide. A first connection electrode CNE1 may be disposed on the third dielectric layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL through a contact hole CNT-1, which penetrates the first dielectric layer 10, the second dielectric layer 20, and the third dielectric layer 30.

[0111] A fourth dielectric layer 40 covering the first connecting electrode CNE1 is disposed on the third dielectric layer 30. The fourth dielectric layer 40 may be a single layer of silicon oxide. A fifth dielectric layer 50 is disposed on the fourth dielectric layer 40. The fifth dielectric layer 50 may be an organic layer. A second connecting electrode CNE2 may be disposed on the fifth dielectric layer 50. The second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 through a contact hole CNT-2 penetrating the fourth dielectric layer 40 and the fifth dielectric layer 50.

[0112] A sixth dielectric layer 60 covering the second connection electrode CNE2 is disposed on the fifth dielectric layer 50. The sixth dielectric layer 60 may be an organic layer. A first electrode AE ​​is disposed on the sixth dielectric layer 60. The first electrode AE ​​is connected to the second connection electrode CNE2 through a contact hole CNT-3 penetrating the sixth dielectric layer 60. An opening OP is defined in the pixel defining layer PDL. The opening OP of the pixel defining layer PDL exposes at least a portion of the first electrode AE.

[0113] like Figure 4B As shown, the display area DP-DA may include an emitting area PXA and a shielding area NPXA adjacent to the emitting area PXA. The shielding area NPXA may surround the emitting area PXA. In the illustrated embodiment, the first electrode AE ​​includes a portion exposed to the opening OP, and the emitting area PXA is defined as the portion corresponding to the first electrode AE.

[0114] A hole control layer (HCL) can be commonly disposed in both the emission region (PXA) and the masking region (NPXA). The HCL may include a hole transport layer and may further include a hole injection layer. An emission layer (EML) is disposed on the HCL. The EML may be disposed in the region corresponding to the opening (OP). In an implementation, for example, the EML may be disposed on each pixel (see reference). Figure 4A PX).

[0115] An electronic control layer (ECL) is disposed on the emitter layer (EML). The ECL may include an electron transport layer and may further include an electron injection layer. An aperture mask may be used so that the hole control layer (HCL) and the ECL are jointly disposed on multiple pixels (PX). A second electrode (CE) is disposed on the ECL. The second electrode (CE) has a single, integral shape and is disposed on multiple pixels (PX).

[0116] A dielectric layer TFL is disposed on the second electrode CE. The dielectric layer TFL may comprise multiple thin layers.

[0117] Figure 5A It shows Figure 3 A magnified view of part AA. Figure 5B It shows along Figure 5A A sectional view taken from line I-I'.

[0118] Figure 5A An example is shown of the line portion DL-L and the pad portion DL-P of two data lines in a data line DL. Figure 5A Also shown exemplarily are two first pads DP-PD1 located on the preceding row, electrically connected to the corresponding pad portion DL-P. Each pad portion DL-P may have an area per unit length larger than the area per unit length of each line portion DL-L. Each pad portion DL-P is shown as having a quadrilateral shape, but the shape of the pad portion DL-P may be changed during the manufacturing process.

[0119] According to the present invention, the first pad DP-PD1 and the second pad DP-PD2 may have a reference Figure 5A and Figure 5B The structure described.

[0120] refer to Figure 5B The pad portion DL-P of the data line DL can be disposed on the second dielectric layer 20. The third dielectric layer 30 can cover the pad portion DL-P of the data line DL. The first pads DP-PD1 are disposed on the third dielectric layer 30. Contact holes CNT are defined in the third dielectric layer 30 to expose the corresponding pad portion DL-P. Each of the first pads DP-PD1 can make an electrical contact with a corresponding pad portion DL-P through the contact hole CNT penetrating the third dielectric layer 30.

[0121] Figure 6 An exploded perspective view illustrating an embodiment of the display device according to the present invention is shown. Figure 7 A plan view illustrating an embodiment of an electronic component according to the present invention is shown. Figure 8A A perspective view illustrating an embodiment of the first adhesive member according to the present invention is shown. Figure 8BA perspective view illustrating an embodiment of the first adhesive member according to the present invention is shown. (Refer to the above.) Figure 1B As described herein, the driver chip DC will be referred to as the electronic component described below, and the same reference numeral "DC" is used throughout this document to denote the driver chip or electronic component.

[0122] Reference Figure 6 The display panel DP may further include a first adhesive member NF-D and a second adhesive member NF-P. The first adhesive member NF-D may be disposed between the electronic component DC and the base substrate SUB, thereby connecting the electronic component DC to the base substrate SUB. The second adhesive member NF-P may be disposed between the circuit board PB and the base substrate SUB, thereby attaching the circuit board PB to the base substrate SUB. In an embodiment, for example, in a plan view, the first adhesive member NF-D may surround the electronic component DC.

[0123] In some embodiments, each of the first adhesive member NF-D and the second adhesive member NF-P may have non-conductive properties and may be configured as an adhesive resin comprising a thermal initiator. The first adhesive member NF-D and the second adhesive member NF-P may have curing properties that change according to external heat.

[0124] The driver chip DC includes a top surface DC-US and a bottom surface DC-DS facing the first adhesive member NF-D. In an embodiment, for example, refer to... Figure 7 The driver chip DC may include multiple protrusions DC-BP that are electrically in contact with corresponding pads DP-PD disposed on the base substrate SUB.

[0125] The driver chip DC includes corresponding Figure 3 The first raised area DCA1 of the first pad area SA1 shown in the figure and the corresponding Figure 3 The second pad region SA2 shown is a second raised region DCA2. The raised region DC-BP may include a first raised region DC-BP1 that overlaps with the first raised region DCA1 and a second raised region DC-BP2 that overlaps with the second raised region DCA2.

[0126] The first protrusion DC-BP1 may include a first row protrusion and a second row protrusion arranged in two rows R1 and R2 and corresponding to the first pad DP-PD1. The second protrusion DC-BP2 may include a protrusion arranged in a single row and corresponding to the second pad DP-PD2. As a result, in the plan view, the first protrusion region DCA1 may have a larger area than the second protrusion region DCA2.

[0127] The first interval DK1 between two adjacent first protrusions DC-BP1 on the second direction DR2 can be smaller than the second interval DK2 between two adjacent second protrusions DC-BP2 on the second direction DR2. In an embodiment, for example, along the second direction DR2, the second interval DK2 can be larger than the first interval DK1.

[0128] Thus, the number of first protrusions DC-BP1 is greater than the number of second protrusions DC-BP2, and therefore the second interval DK2 between the second protrusions DC-BP2 can be set to be greater than the first interval DK1 between the first protrusions DC-BP1.

[0129] Furthermore, in the plan view, one of the first protrusions DC-BP1 may have an area different from that of one of the second protrusions DC-BP2. In the implementation, according to... Figure 7 In the illustrated embodiment, for example, each of the second protrusions DC-BP2 is shown to have an area larger than that of each of the first protrusions DC-BP1.

[0130] Similarly, as Figure 6 As shown, the first interval between two adjacent first pads DP-PD1 on the second direction DR2 can be smaller than the second interval between two adjacent second pads DP-PD2 on the second direction DR2. In an embodiment, for example, along the second direction DR2, the second interval can be larger than the first interval.

[0131] Thus, the first pad DP-PD1 and the first protrusion DC-BP1 face each other and are electrically contacted on the third-direction DR3, and therefore the spacing between two adjacent first pads DP-PD1 can substantially correspond to the spacing between two adjacent first protrusions DC-BP1. Furthermore, the second pad DP-PD2 and the second protrusion DC-BP2 face each other and are electrically contacted on the third-direction DR3, and therefore the spacing between two adjacent second pads DP-PD2 can substantially correspond to the spacing between two adjacent second protrusions DC-BP2.

[0132] Furthermore, in the plan view, the area of ​​one pad in the first pad DP-PD1 may differ from the area of ​​one pad in the second pad DP-PD2. In an implementation, for example, the area of ​​each second pad DP-PD2 may be larger than the area of ​​each first pad DP-PD1.

[0133] See again Figure 6 Because the pads DP-PD and DC-BP are covered by the first adhesive component NF-D, the pads DP-PD and DC-BP can be isolated from the outside air. As a result, oxidation of the DC-BP and pads DP-PD by the outside air can be prevented.

[0134] Circuit pads of circuit board PB (reference) Figure 3 The PB-PD can face the DP-CPD on the third-party DR3 and can be electrically connected to the corresponding DP-CPD. According to the invention, because the circuit pad PB-PD and the DP-CPD are covered by the second adhesive member NF-P, the circuit pad PB-PD and the DP-CPD can be isolated from external air. As a result, oxidation of the circuit pad PB-PD and the DP-CPD by external air can be prevented.

[0135] According to the present invention, a first adhesive member NF-D may be disposed between the pad DP-PD and the bump DC-BP before establishing an electrical contact between them. Similarly, a second adhesive member NF-P may be disposed between the circuit pad PB-PD and the connection pad DP-CPD before establishing an electrical contact between them.

[0136] In some embodiments, an ultrasonic bonding method can be used to thermally compress the pads DP-PD and DC-BP relative to each other. In this case, the first adhesive member NF-D between the pads DP-PD and DC-BP can migrate to another space during the thermal compression of the pads DP-PD and DC-BP relative to each other. In this specification, the other space may refer to the gap disposed between the base substrate SUB and the driver chip DC that does not overlap with the pads DP-PD and DC-BP. In embodiments, for example, the other space may correspond to a non-pad area between the pads DP-PD or between the first pad region SA1 and the second pad region SA2.

[0137] In some embodiments, the ultrasonic bonding method can thermally compress the connection pad DP-CPD and the circuit pad PB-PD relative to each other. Similarly, during the thermal compression of the connection pad DP-CPD and the circuit pad PB-PD relative to each other, the second adhesive member NF-P between the connection pad DP-CPD and the circuit pad PB-PD can migrate to another space.

[0138] As described above, each of the first adhesive member NF-D and the second adhesive member NF-P according to the present invention can be configured as a film type. In this case, the first adhesive member NF-D can have a thickness suitable for adhesion between the driver chip DC and the base substrate SUB. Furthermore, the second adhesive member NF-P can have a thickness suitable for adhesion between the circuit board PB and the base substrate SUB.

[0139] Conversely, when the entire first adhesive component has the same or substantially the same thickness, it can remain between the pad and the bump even after a compression process based on ultrasonic bonding. In this case, electrical contact between the pad and the bump may not be established due to the first adhesive component remaining between them after the compression process.

[0140] According to some embodiments of the present invention, along the third direction DR3, the first adhesive member NF-D may have a thickness overlapping with the first pad region SA1, which is less than the thickness of the first adhesive member NF-D overlapping with the non-pad region between the first pad region SA1 and the second pad region SA2. When viewed along the third direction DR3, the first adhesive member NF-D may have a thickness overlapping with the second pad region SA2, which is less than the thickness of the first adhesive member NF-D overlapping with the non-pad region. In this case, the first adhesive member NF-D may be configured to have a thickness overlapping with the pads DP-PD, which is less than the thickness of the first adhesive member NF-D overlapping with the non-pad region.

[0141] According to some embodiments of the present invention, the second adhesive member NF-P may have a thickness that overlaps with the connection pad DP-CPD, which is less than the thickness of the second adhesive member NF-P that does not overlap with the connection pad DP-CPD.

[0142] In the implementation method, refer to Figure 8A For example, the first adhesive member NF-D includes a top surface NF-DU and a bottom surface NF-DN. According to the invention, at least one recessed pattern may be defined in the first adhesive member NF-D. In embodiments, such as... Figure 8A As shown, for example, a first recessed pattern PT-OP that overlaps with the first pad region SA1 and a second recessed pattern PT-OI that overlaps with the second pad region SA2 are defined in the first adhesive member NF-D.

[0143] The first recessed pattern PT-OP may completely overlap with the first pad DP-PD1 and may have a shape that is recessed downward from the top surface NF-DU and extends in the second direction DR2. The second recessed pattern PT-OI may be spaced apart from the first recessed pattern PT-OP in the first direction DR1. The second recessed pattern PT-OI may completely overlap with the second pad DP-PD2 and may have a shape that is recessed downward from the top surface NF-DU and extends in the second direction DR2.

[0144] Although the first recessed pattern PT-OP and the second recessed pattern PT-OI are each shown as having a rectangular shape in the plan view, the first recessed pattern PT-OP and the second recessed pattern PT-OI can be modified in various ways in terms of shape.

[0145] In some embodiments, the sum of the planar areas of the first recessed pattern PT-OP and the second recessed pattern PT-OI may fall within the range of approximately 20% to approximately 70% (70%) of the total planar area of ​​the top surface NF-DU. In embodiments, such as Figure 3 As shown, for example, the number of first pads DP-PD1 overlapping with the first recessed pattern PT-OP can be greater than the number of second pads DP-PD2 overlapping with the second recessed pattern PT-OI. Therefore, the planar area of ​​the first recessed pattern PT-OP can be greater than the planar area of ​​the second recessed pattern PT-OI.

[0146] and Figure 8A Compared to the first adhesive member NF-D shown, Figure 8B The first adhesive member NF-D1 depicted in the diagram can be configured such that the first recessed pattern PT-OPa is defined to have a relationship with... Figure 8A The first recessed pattern PT-OP shown has a different shape, and the second recessed pattern PT-OI is defined to have the same shape as... Figure 8A The second recessed pattern PT-OI shown has a shape that is basically the same as the shape shown.

[0147] Reference Figure 8B The first recessed pattern PT-OPa includes a first sub-recessed pattern PT-OPa1 and a second sub-recessed pattern PT-OPa2. The second sub-recessed pattern PT-OPa2 may be defined between the first sub-recessed pattern PT-OPa1 and the second recessed pattern PT-OI.

[0148] According to the present invention, the first sub-recessed pattern PT-OPa1 may overlap with the first row of pads of the first pad DP-PD1 and may have a shape extending in the second direction DR2. The second sub-recessed pattern PT-OPa2 may overlap with the second row of pads of the first pad DP-PD1 and may have a shape extending in the second direction DR2.

[0149] In one embodiment, for example, the first sub-recessed pattern PT-OPa1 and the second sub-recessed pattern PT-OPa2 may have shapes that are spaced apart from each other in a first direction DR1. In the illustrated embodiment, along the first direction DR1, the spacing between the second sub-recessed pattern PT-OPa2 and the second sub-recessed pattern PT-OI is greater than the spacing between the first sub-recessed pattern PT-OPa1 and the second sub-recessed pattern PT-OPa2. However, the invention is not limited thereto, and in another embodiment, along the first direction DR1, the spacing between the second sub-recessed pattern PT-OPa2 and the second sub-recessed pattern PT-OI may be smaller than the spacing between the first sub-recessed pattern PT-OPa1 and the second sub-recessed pattern PT-OPa2.

[0150] As described above, the first adhesive member NF-D can have a thickness in the portion overlapping the first pad region SA1 and the second pad region SA2 to which the pads DP-PD and DC-BP are connected, such that the thickness of this portion of the first adhesive member NF-D can be less than the thickness of other portions of the first adhesive member NF-D. Therefore, the first adhesive member NF-D, which overlaps with and between the pads DP-PD and DC-BP, can easily migrate to another space during the compression process based on the ultrasonic bonding method. As a result, the driver chip DC and the display panel DP can have improved connection reliability between them.

[0151] Figure 9A The invention illustrates the following: Figure 7 A cross-sectional view of the embodiment taken by line II-II'. Figure 9B The invention illustrates the following: Figure 7 A cross-sectional view of the embodiment taken by line II-II'.

[0152] Reference Figure 9A The electronic component DC includes a substrate DC-BS, a drive pad portion DC-P, and a pad dielectric layer DC-IL. The drive pad portion DC-P includes a drive pad DC-PD and a first bump DC-BP1 (also called a bump).

[0153] The substrate DC-BS may have a top surface corresponding to the top surface DC-US of the electronic component DC. The pad dielectric layer DC-IL may have a bottom surface facing the display panel DP and corresponding to the bottom surface DC-DS of the electronic component DC. In an embodiment, for example, the substrate DC-BS may include silicon.

[0154] The drive pad DC-PD can be disposed on the bottom surface of the substrate DC-BS. The drive pad DC-PD can be electrically connected to the circuit elements (not shown) of the electronic component DC. The pad dielectric layer DC-IL can be disposed on the bottom surface of the substrate DC-BS, and vias can be defined in the pad dielectric layer DC-IL to expose a portion of the drive pad DC-PD. The bump DC-BP1 can be directly disposed on the drive pad DC-PD.

[0155] In some embodiments, an ultrasonic bonding method can be used to make the protrusion DC-BP1 electrically contact the first pad DP-PD1 (also referred to as the pad). In embodiments, for example, frictional heat generated by ultrasonic vibration occurs at the interface between the protrusion DC-BP1 and the pad DP-PD1. Furthermore, thermal pressure can be applied externally to the top surface of the substrate DC-BS, allowing the protrusion DC-BP1 and the pad DP-PD1 to be attached (or soldered) to each other due to frictional heat at their interface.

[0156] The first adhesive member NF-D disposed between pad DP-PD1 and bump DC-BP1 can migrate into the space between two adjacent pads in pad DP-PD1 during a thermal compression process based on an ultrasonic bonding method. In an alternative embodiment, the first adhesive member NF-D disposed between pad DP-PD1 and bump DC-BP1 can migrate into the space defined between the base substrate SUB and the driver chip DC, and overlap with the non-pad area between the first pad area SA1 and the second pad area SA2.

[0157] The following will refer to Figure 9A and 9B The description of the first adhesive member NF-D includes an example of a recessed region HA and a non-recessed region NHA. The recessed region HA corresponds to the above reference. Figure 6 The first pad region SA1 and the second pad region SA2 are described, and the non-recessed region NHA corresponds to the region of the first adhesive member NF-D other than the recessed region HA. Furthermore, the recessed region HA may correspond to the region described above. Figure 7 The first protruding region DCA1 and the second protruding region DCA2 are described.

[0158] In some embodiments, the density of the first adhesive member NF-D at the recessed region HA may be less than its density at the non-recessed region NHA. This density difference occurs because the first adhesive member NF-D is configured to have a larger thickness at the non-recessed region NHA and a smaller thickness at the recessed region HA. As a result, the first adhesive member NF-D may have a lower density at its portion corresponding to the recessed region HA and a higher density at its portion corresponding to the non-recessed region NHA. In this specification, density may refer to the mass per unit volume of the first adhesive member NF-D disposed between the driver chip DC and the base substrate SUB.

[0159] Furthermore, prior to ultrasonic bonding, the thickness of the first adhesive member NF-D overlapping the non-recessed region NHA on the third-direction DR3 can be greater than the sum of the heights of the first protrusion DC-BP1 and the first pad DP-PD1.

[0160] like Figure 9B As shown, the internal space INP can be defined by two adjacent first protrusions in the first protrusions DC-BP1, the first adhesive member NF-D, and the substrate DC-BS. In an embodiment, the first adhesive member NF-D can partially, but not completely, fill the gap located between the first protrusions DC-BP1 and between the driver chip DC and the display panel DP. Thus, for example, the first adhesive member NF-D can partially cover at least one of the first protrusions DC-BP1.

[0161] Figure 10A The invention illustrates the following: Figure 8A A cross-sectional view of the embodiment taken by line III-III'. Figure 10B The invention illustrates the following: Figure 8A A cross-sectional view of the embodiment taken by line III-III'. Figure 10C The invention illustrates the following: Figure 8A A cross-sectional view of the embodiment taken by line III-III'.

[0162] Reference Figures 10A to 10C The various shapes of the first recessed pattern PT-OP and the second recessed pattern PT-OI defined in the first adhesive member NF-D will be described in detail below. The first recessed pattern PT-OP and the second recessed pattern PT-OI, which overlap with the first pad region SA1 and the second pad region SA2 respectively, can correspond to the above reference. Figure 9A The described depression region HA.

[0163] Reference Figure 10A The first recessed pattern PT-OP may have a first height HT1 on the third-direction DR3, and the first height HT1 may indicate the recess depth from the top surface NF-DU of the first adhesive member NF-D on the third-direction DR3. The second recessed pattern PT-OI may have a second height HT2 on the third-direction DR3, and the second height HT2 may indicate the recess depth from the top surface NF-DU of the first adhesive member NF-D on the third-direction DR3.

[0164] In some embodiments, the first height HT1 of the first recessed pattern PT-OP may be the same as the second height HT2 of the second recessed pattern PT-OI. In embodiments, for example, the depth of the first recessed pattern PT-OP recessed from the top surface NF-DU of the first adhesive member NF-D may be substantially the same as the depth of the second recessed pattern PT-OI recessed from the top surface NF-DU of the first adhesive member NF-D. Although the first height HT1 and the second height HT2 of the first recessed pattern PT-OP and the second recessed pattern PT-OI are shown as being the same, equivalence in height may include process tolerances.

[0165] Reference Figure 10B and Figure 10C The first height HT1 of the first recessed pattern PT-OP can be different from the second height HT2 of the second recessed pattern PT-OI. In an embodiment, such as Figure 10B As shown, the second height HT2 of the second recessed pattern PT-OI can, for example, be greater than the first height HT1 of the first recessed pattern PT-OP. In another embodiment, as... Figure 10C As shown, the first height HT1 of the first recessed pattern PT-OP can be greater than the second height HT2 of the second recessed pattern PT-OI.

[0166] Figure 11 A perspective view illustrating an embodiment of the second adhesive member according to the present invention is shown.

[0167] Reference Figure 11 The second adhesive member NF-P includes a top surface NF-PU and a bottom surface NF-PN. According to the present invention, the second adhesive member NF-P and... Figure 6 The connection pad areas NDA-PA shown overlap, and a recessed pattern PT-P is defined in the second adhesive member NF-P, recessed downwards from the top surface NF-PU. This is provided on the base substrate (reference). Figure 6 The connection pad DP-CPD on the SUB and overlapping with the connection pad area NDA-PA can completely overlap with the recessed pattern PT-P. The recessed pattern PT-P can have a shape extending in the second direction DR2, and the connection pad DP-CPD is arranged along the second direction DR2.

[0168] Figure 12 A perspective view illustrating an embodiment of the first adhesive member according to the present invention is shown.

[0169] and Figure 8A Compared to the first adhesive member NF-D shown, Figure 12 The first adhesive member NF-Dz shown defines a structure having a relationship with Figure 8A The concave patterns depicted are concave patterns of different shapes.

[0170] Reference Figure 12 The first adhesive member NF-Dz includes a plurality of first sub-recessed patterns PT-OPz and a plurality of second sub-recessed patterns PT-OIz. The plurality of first sub-recessed patterns PT-OPz are arranged along a second direction DR2 at a first interval, and the plurality of second sub-recessed patterns PT-OIz are arranged along the second direction DR2 at a second interval greater than the first interval. In an embodiment, for example, the first sub-recessed patterns PT-OPz may be defined as a first row of sub-recessed patterns and a second row of sub-recessed patterns separated along the first direction DR1.

[0171] According to the present invention, the first sub-recessed pattern PT-OPz can overlap with the corresponding first pad DP-PD1, and the first pad DP-PD1 and Figure 6 The first pad region SA1 shown overlaps with the second sub-dimpled pattern PT-OIz. The second sub-dimpled pattern PT-OIz can overlap with the corresponding second pad DP-PD2. The second pad DP-PD2 and... Figure 6 The second pad region SA2 shown overlaps.

[0172] One of the first sub-dimpled patterns PT-OPz may have a planar area corresponding to the planar area of ​​the corresponding one of the first pads DP-PD1. One of the second sub-dimpled patterns PT-OIz may have a planar area corresponding to the planar area of ​​the corresponding one of the second pads DP-PD2.

[0173] Furthermore, according to the present invention, the planar area of ​​one of the second sub-recessed patterns PT-OIz can be greater than the planar area of ​​one of the first sub-recessed patterns PT-OPz. Thus, the planar area of ​​the second pad DP-PD2 can be greater than the planar area of ​​the first pad DP-PD1, and therefore the planar areas of the first sub-recessed pattern PT-OPz and the second sub-recessed pattern PT-OIz can be different from each other.

[0174] Figures 13A to 13C A cross-sectional view illustrating an embodiment of a method for manufacturing a display device according to the present invention is shown. Although the following description refers to the first adhesive member NF-D for ultrasonic bonding between the driver chip DC and the display panel DP, the description is substantially equally applicable to the second adhesive member NF-P for ultrasonic bonding between the circuit board PB and the display panel DP.

[0175] Reference Figure 13A Prepare the driver chip DC (also known as the electronic component), the display panel DP, and the first bonding member NF-D. The display panel DP includes pads DP-PD, and the electronic component DC includes raised DC-BP.

[0176] According to the present invention, a first adhesive member NF-D can be disposed between the electronic component DC and the display panel DP. A recessed pattern PT, overlapping with the pad DP-PD and the protrusion DC-BP and recessed from the top surface NF-DU, can be defined in the first adhesive member NF-D. Figure 13A As shown, before ultrasonically bonding the pads DP-PD and DC-BP to each other, the recessed pattern PT of the first adhesive member NF-D can be aligned to overlap with the pads DP-PD and DC-BP.

[0177] Reference Figure 13BA thermal compression tool PS can be placed on the electronic component DC to apply thermal pressure HTK to the electronic component DC. The thermal pressure HTK applied to the upper part of the electronic component DC can make the protrusion DC-BP and the pad DP-PD make electrical contact with each other. In this case, due to the physical pressure between the protrusion DC-BP and the pad DP-PD, the first adhesive member NF-D, which is located between the protrusion DC-BP and the pad DP-PD and overlaps with the protrusion DC-BP and the pad DP-PD, can easily migrate to another space.

[0178] Furthermore, the thermocompression tool PS can apply thermal pressure HTK to the interface between the first adhesive component NF-D and the protrusion DC-BP and pad DP-PD. The thermal pressure HTK applied by the thermocompression tool PS can alter the curing characteristics of the first adhesive component NF-D.

[0179] Then, refer to Figure 13C Ultrasonic vibration (UK) can be applied to the interface between the pad DP-PD and the bump DC-BP. (See reference...) Figure 13C The ultrasonic vibration UK described can be applied simultaneously with the thermal pressure HTK from the thermal compression tool PS.

[0180] According to some embodiments of the invention, a recessed pattern is defined in the adhesive member that overlaps with the pad area of ​​the display panel. The adhesive member may have a smaller thickness at the portion where the recessed pattern is defined, and a larger thickness at other portions where the recessed pattern is not defined.

[0181] Therefore, the adhesive components positioned between the pads of the driver chip and the display panel can be easily moved to another space during the thermal compression process based on the ultrasonic bonding method. In summary, it is possible to easily establish electrical contacts between the pads and bumps, improving the connection reliability between the driver chip and the display panel.

[0182] Some embodiments have been described in the specification and drawings. Although specific terminology is used herein, it is for descriptive purposes only and not to limit the technical meaning or scope of the invention as disclosed in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments can be made according to the invention. In conclusion, the true technical scope of the invention to be protected should be determined by the technical concept.

Claims

1. An adhesive member located between an electronic component and an electronic panel, the electronic component and the electronic panel being connected to each other via the adhesive member, the adhesive member comprising: A first surface, a first recessed pattern and a second recessed pattern recessed from the first surface, the second recessed pattern being spaced apart from the first recessed pattern in a first direction; as well as The second surface is opposite to the first surface. Wherein, the sum of the planar areas of the first recessed pattern and the second recessed pattern is in the range of 20% to 70% of the planar area of ​​the first surface, and The first recessed pattern and the second recessed pattern are defined in an integral layer formed of a non-conductive material.

2. The adhesive member according to claim 1, wherein, The height of the first recessed pattern from the first surface is different from the height of the second recessed pattern from the first surface.

3. The adhesive member according to claim 1, wherein, In the planar view, the planar area of ​​the first recessed pattern is different from the planar area of ​​the second recessed pattern.

4. The adhesive member according to claim 1, wherein, Each of the first recessed pattern and the second recessed pattern has a shape that extends along a second direction perpendicular to the first direction.

5. The adhesive member according to claim 1, wherein, The first recessed pattern includes a plurality of first sub-recessed patterns, the plurality of first sub-recessed patterns being recessed from the first surface and arranged at a first interval along a second direction perpendicular to the first direction, and The second recessed pattern includes a plurality of second sub-recessed patterns, which are recessed from the first surface and arranged at a second interval along the second direction.

6. The adhesive member according to claim 5, wherein, The planar area of ​​one of the plurality of second sub-recessed patterns is greater than the planar area of ​​each of the plurality of first sub-recessed patterns.

7. The adhesive member according to claim 5, wherein, The second interval is greater than the first interval.

8. The adhesive member according to claim 1, comprising a thermal initiator, wherein, The adhesive component has non-conductive properties and surrounds the electronic component.

9. The adhesive member according to claim 1, wherein, The first recessed pattern includes: The first sub-recessed pattern extends in a second direction perpendicular to the first direction; and The second sub-recessed pattern is parallel to the second direction.

10. A display device, comprising: A base substrate defines a display area and a non-display area adjacent to the display area, the non-display area including a first pad area, a second pad area, and a non-pad area between the first pad area and the second pad area; Multiple first pads are located on the base substrate, and the multiple first pads overlap with the first pad area; Multiple second pads are located on the base substrate, and the multiple second pads overlap with the second pad area; An electronic component includes a plurality of first protrusions electrically contacting corresponding first pads among the plurality of first pads, a plurality of second protrusions electrically contacting corresponding second pads among the plurality of second pads, and a substrate, wherein the first protrusions and the second protrusions are disposed on the substrate, and the electronic component and the substrate face each other in the thickness direction of the substrate. as well as The first adhesive component is located between the base substrate and the electronic component. The internal space is defined by the substrate, the first adhesive member, and two adjacent first protrusions that overlap with the first pad area. In the plan view, the first adhesive member overlaps with the interior space.

11. The display device according to claim 10, wherein, The first pad region and the second pad region are spaced apart across the non-pad region in a first direction. The plurality of first pads are arranged along a second direction perpendicular to the first direction, and The plurality of second pads are arranged along the second direction.

12. The display device according to claim 11, wherein, The plurality of first pads are arranged at a first interval along the second direction, and The plurality of second pads are arranged at a second interval along the second direction. The second interval is greater than the first interval.

13. The display device according to claim 11, wherein, One of the plurality of second pads has a planar area larger than that of each of the plurality of first pads.

14. The display device according to claim 10, wherein, The first adhesive member partially covers at least one of the first protrusion and the second protrusion.

15. The display device according to claim 10, further comprising: Multiple connection pads are spaced apart from the electronic components in the plan view and disposed on the base substrate, and the multiple connection pads overlap with the non-display area; A circuit board, overlapping the non-display area and including a plurality of circuit pads electrically contacting corresponding connection pads among the plurality of connection pads; and The second adhesive component is located between the circuit board and the base substrate.

16. The display device according to claim 15, wherein, The second adhesive member partially covers at least one of the plurality of circuit pads.

17. A method for manufacturing a display device, the method comprising: A display panel and electronic components are provided, the display panel including pads, and the electronic components including protrusions facing the pads; An adhesive component is disposed between the display panel and the electronic component, the adhesive component comprising a first surface and a second surface; A recessed pattern is defined in the first surface of the adhesive member; Align the adhesive member such that the recessed pattern overlaps with the pad and the protrusion; Apply thermal pressure to the electronic component to make the protrusion make electrical contact with the pad; as well as Ultrasonic vibration is provided to the interface between the pad and the protrusion.

18. The method according to claim 17, wherein, The adhesive member defines a recessed region overlapping the pad and a non-recessed region adjacent to the recessed region. Specifically, before thermal pressure is applied to the electronic components, the thickness of the adhesive member overlapping the non-recessed area along the thickness direction of the display panel is greater than the sum of the height of the pad and the height of the protrusion.

19. The method of claim 17, wherein, The planar area of ​​the recessed pattern is in the range of 20% to 70% of the planar area of ​​the first surface.

20. The method of claim 17, further comprising: Define another recessed pattern, which is spaced apart from the first recessed pattern in a predetermined direction and recessed from the first surface of the adhesive member. Wherein, along the thickness direction of the display panel, the height of the recessed pattern is different from the height of the other recessed pattern.

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