A model training method and device

Abstract

The present application discloses a model training method, which is applied to the field of artificial intelligence. The method includes: a computing core in a first processor obtains an embedding for model training, and after completing the model training, the updated embedding is written to a first memory in the first processor instead of being transferred to a second processor. In the present application, after completing the update of the embedding, the first processor stores the updated embedding in the first memory of the first processor. Under the premise that the first processor can obtain the latest updated embedding, the first processor does not need to wait for the second processor to complete the process of transferring the second target embedding to the GPU, and can directly obtain the updated embedding, and perform the next round of model training based on the updated embedding. The present application can improve the processing speed of the training data of the processor during model training.

Description

Technical Field

[0001] The present application relates to the field of artificial intelligence, and in particular to a model training method and device. Background Art

[0002] Artificial intelligence (AI) is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a branch of computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is also the study of the design principles and implementation methods of various intelligent machines, so that machines have the functions of perception, reasoning and decision-making.

[0003] Based on the interaction behavior information of massive users and recommended objects, the recommendation model parameters are trained through methods such as gradient descent. When the model parameters converge, personalized recommendations can be made to users. Taking the click-through rate in the personalized recommendation system as an example, the input features include user features, product features, user historical behavior features, and context features, where features are divided into continuous features and discrete features. For discrete features, one-hot sparse coding is used, and then the embedding vector expression is taken from the embeddingtable through the encoding id, the original discrete feature id is vectorized, and then input into the recommendation model for training and learning for prediction.

[0004] The size of the training model and the amount of data have a direct impact on the effectiveness of the model's online service. In the recommendation system, in order for the model to predict user interests more accurately, it is often necessary to use massive features and data. Massive features bring corresponding massive parameters, making the model scale reach hundreds of GB or even TB, and massive data increases the computing power required for model training. Moreover, in order to capture user interests more quickly and provide users with better user experience and recommendation effects, deep models need to be updated frequently and quickly. These requirements bring about a thorny problem: the recommendation model training needs to be completed quickly based on massive features and massive data.

[0005] Researchers proposed that the embedding layer compresses high-dimensional sparse one-hot vectors into low-dimensional dense vectors, also known as embedding. The main parameters in the recommendation model are also located in the embedding layer (hundreds of GB or even TB). In addition, in order to improve the prediction accuracy of the model, the recommendation model generally constructs a feature combination mining module based on the multiplication network and the MLP network. This module is generally more complex and requires a relatively large amount of calculation. It can be used for feature interactions and nonlinear mappings between data features. Unlike visual and natural language processing (NLP) models, recommendation models have their own unique characteristics. Take the click-through rate (CTR) model as an example (such as Figure 4 ), the recommendation model consists of two parts: embedding layer and multi-layer perception (MLP). The data of the recommendation task contains a large number of high-dimensional and sparse ID-type features, which are generally encoded using one-hot encoding. Directly using these features for model training will make it difficult to learn the deep part parameters. To solve this problem, researchers proposed an embedding layer to compress the high-dimensional and sparse one-hot vector into a low-dimensional and dense vector, also known as embedding feature embedding.

[0006] In the existing implementation, when performing model training, after completing the model training of a batch of batches, the computing core of the graphics processing unit (GPU) needs to return the updated embeddings to the CPU (for example, including the updated embedding1). The CPU maintains an embedding table, where the embeddingtable may include some or all of the embeddings required for model training. If the model training of the next batch of batches also requires (embedding1), in order to ensure the consistency of the parameters of interest, the CPU is required to pass the updated embedding1 to the GPU, and then the computing core of the computing unit of the GPU can obtain the updated embedding1 from the cache, and perform model training for the next batch of batches based on the updated embedding1. Therefore, the GPU needs to wait for the CPU to complete the process of passing the updated embedding1 to the GPU, which will cause time delays and greatly increase the training time. Summary of the invention

[0007] In the first aspect, the present application provides a model training method, characterized in that it is applied to a first processor, the first processor is communicatively connected to a second processor, the first processor includes a computing core and a first memory, and the second processor includes a second memory; the first processor and the second processor are processors of different types, wherein the first processor can be a graphics processor GPU, an embedded neural network processor (neural network processing unit, NPU) or a tensor processor (tensor processing unit, TPU), the first memory can be a cache, and the second processor can be a central processing unit (central processing unit, CPU).

[0008] The method comprises:

[0009] The computing core obtains a first target embedding feature embedding through the second memory;

[0010] The computing core trains the model to be trained according to the first target embedding to obtain an updated model to be trained and a second target embedding, where the second target embedding is the updated first target embedding;

[0011] In an embodiment of the present application, after the computing core obtains the embedding (including the first target embedding) required for the current batch model training, the model to be trained can be trained according to the embedding (including the first target embedding) required for the current batch model training to obtain an updated model to be trained and an updated embedding (including the second target embedding).

[0012] The computing core writes the second target embedding into the first memory.

[0013] It can be seen that in the embodiment of the present application, after completing the update of the first target embedding, the first processor stores the second target embedding in the first memory of the first processor. Under the premise that the first processor can obtain the latest updated target embedding (second target embedding), the first processor does not need to wait for the second processor to complete the process of passing the second target embedding to the GPU, and can directly obtain the second target embedding and perform model training based on the second target embedding. The throughput of training data is increased, thereby improving the speed of model training.

[0014] In a possible implementation, the computing core trains the to-be-trained model according to the first target embedding, including:

[0015] The computing core performs model training of the Mth batch of the model to be trained according to the first target embedding; M is a positive integer greater than 1;

[0016] After the computing core writes the second target embedding into the first memory, the method further includes:

[0017] The computing core obtains the second target embedding from the first memory;

[0018] The computing core performs model training for the M+1th batch on the updated model to be trained according to the second target embedding.

[0019] If the first target embedding is also the embedding required for the next batch model training, the computing core can directly obtain the updated first target embedding (that is, the second target embedding) from the first memory. If the first memory does not store a part of the embedding required for the model training of the M+1th batch, the second processor can transfer this part of the embedding to the first memory.

[0020] In a possible implementation, after the computing core performs model training of the M+1th batch on the updated model to be trained according to the second target embedding, a third target embedding is obtained, and the third target embedding is the updated second target embedding; the computing core can write the third target embedding into the first memory.

[0021] In a possible implementation, the computing core obtains the first target embedding through the second memory, including:

[0022] When the first target embedding is the embedding required for model training of the Mth batch and the first target embedding is not stored in the first memory, the first memory obtains the first target embedding from the second memory; wherein, when the first target embedding is the embedding required for model training of the Mth batch and the first target embedding is not stored in the first memory, the second processor may transfer the first target embedding from the second memory to the first memory, which is equivalent to the first memory receiving the first target embedding from the second memory.

[0023] The computing core obtains a first target embedding from the first memory.

[0024] For example, the embedding required for the model training of the Mth batch includes the first target embedding. If the second processor determines that the first target embedding is not stored in the first memory, the first target embedding can be written from the second memory in the second processor to the first memory. In terms of the selection of the writing time point, the second processor can write the target embedding from the second memory to the first memory during the process of the calculation core performing the model training of the M-1th batch of the model to be trained.

[0025] In this embodiment, during the training of the previous batch of batch models, the second processor will transfer the embeddings that are not stored in the first memory and are required for the training of the next batch of batch models to the first memory, so that the computing core can obtain all the embeddings required for the training of the next batch of batch models from the first memory.

[0026] In a possible implementation, the method further includes:

[0027] Before the computing core obtains the first target embedding from the first memory, the computing core obtains a first vector and a target vector from the second processor, wherein the first vector is used to indicate the embedding required for the model training of the M-th batch, each element in the first vector is used to indicate an embedding, and different elements indicate different embeddings, and the target vector is used to indicate the arrangement relationship of the embeddings indicated by each element in the first vector when performing the model training of the M-th batch, and the embedding indicated by each element appears at least once in the arrangement relationship; wherein the arrangement relationship can be the number of times the embedding indicated by each element in the first vector is used during the model training of the M-th batch, and the order of the embeddings indicated by each element in the first vector during the model training of the M-th batch.

[0028] The computing core obtains a first target embedding from the first memory, including:

[0029] The computing core obtains, from the first memory according to the first vector, the embedding required for model training of the Mth batch;

[0030] The computing core determines, according to the target vector and the embeddings required for the model training of the Mth batch, an arrangement relationship of each embedding required for the model training of the Mth batch.

[0031] In one implementation, the embeddings required for the same batch of batch model training may include the same embeddings. For example, the embeddings required for the same batch of batch model training may be: D = [embedding1, embedding2, embedding3, embedding3, embedding2, embedding4], then embedding2 and embedding3 are both repeated. In order to reduce the amount of parameters read by the computing core of the subsequent first processor for embedding, the second processor may perform a deduplication operation on the embeddings required for the same batch of batch model training. Specifically, the second processor may obtain a first vector, the elements included in the first vector being the embeddings required for the model training of the Mth batch; and the first vector may indicate information about the embeddings required for model training after deduplication.

[0032] Exemplarily, the first vector before deduplication can be: D = [embedding1, embedding2, embedding3, embedding3, embedding2, embedding4], the first vector is deduplicated to obtain the first vector after deduplication U = [embedding1, embedding2, embedding3, embedding4], and the target vector Mask = [0, 1, 2, 2, 1, 3] is calculated, where the first element of the target vector is 0, indicating that the first element in the first vector is the first element in the second vector, and the second element of the target vector is 1, indicating that the second element in the first vector is the second element in the second vector, the third element of the target vector is 2, indicating that the third element in the first vector is the third element in the second vector, the fourth element of the target vector is 2, indicating that the fourth element in the first vector is the third element in the second vector, the fifth element of the target vector is 1, indicating that the fifth element in the first vector is the second element in the second vector, and the sixth element of the target vector is 3, indicating that the sixth element in the first vector is the fourth element in the second vector. In this way, the first vector before deduplication can be restored based on the first vector and the target vector, wherein the first vector before deduplication is used to determine the arrangement relationship of each embedding required for performing the model training of the Mth batch.

[0033] In a possible implementation, before the computing core trains the to-be-trained model according to the first target embedding, the method further includes:

[0034] The computing core obtains a third target embedding from a third memory in a third processor, the third target embedding and the first target embedding are the embeddings required for the Mth batch model training, and the first processor and the third processor are processors of the same type;

[0035] The computing core trains the model to be trained according to the first target embedding, including:

[0036] The computing core processes the first target embedding and the third target embedding through the model to be trained to obtain a target output, and determines a first gradient based on the target output;

[0037] The computing core updates the model to be trained and the first target embedding based on the first gradient.

[0038] In a scenario including multiple computing nodes, each computing node can be responsible for a portion of the embeddings required for the current batch model training, and is responsible for updating a portion of the embeddings. In one possible implementation, the computing core needs to obtain the third target embedding from the third memory of the third processor of other server nodes, and perform a feedforward process in the model training process based on the first target embedding and the third target embedding. However, when updating, the computing core in the first processor only needs to update the first target embedding based on the first gradient.

[0039] In a possible implementation, determining the first gradient based on the target output includes: determining the first gradient and the second gradient based on the target output;

[0040] After determining the first gradient and the second gradient based on the target output, the method further includes:

[0041] The second gradient is transmitted to a computing core of a third processor, so that the computing core of the third processor updates the third target embedding according to the second gradient.

[0042] Specifically, data communication (such as allreduce communication) between the first processor and the third processor can be used to synchronize the gradient of the embedding, so that the third processor can obtain the gradient calculated by the first processor after the current batch model is trained, and then the third processor can update the embedding (third target embedding) for which it is responsible.

[0043] In a possible implementation, the first processor is a graphics processor GPU, an embedded neural network processor NPU or a tensor processor TPU, the first memory is a cache, and the second processor is a central processing unit CPU.

[0044] In a second aspect, an embodiment of the present application provides a model training method, which is applied to a second processor, the second processor is communicatively connected to a first processor, the first processor includes a computing core and a first memory, the second processor includes a second memory, and the first processor and the second processor are processors of different types; the method includes:

[0045] The second processor obtains the embedding information required by the computing core for performing the Mth batch model training and the embedding information stored in the first memory, where M is a positive integer greater than 1;

[0046] Among them, the embedding information required for the Mth batch model training can indicate the embedding required for the Mth batch model training. For example, the information can be but is not limited to identification information or pointer information indicating the embedding, which is not limited here.

[0047] The second processor writes a first target embedding into the first memory according to the embedding information required by the computing core for the Mth batch model training and the embedding information stored in the first memory, where the first target embedding is the embedding required for the Mth batch model training and not stored in the first memory.

[0048] In a possible implementation, writing the first target embedding into the first memory includes:

[0049] In the process of computing and verifying the model to be trained to perform model training for the M-1th batch, the first target embedding is written into the first memory.

[0050] In a possible implementation, before writing the first target embedding into the first memory, the method further includes:

[0051] When the available storage space in the first memory is lower than the storage space required to store the first target embedding, the second processor deletes at least one embedding in the first memory and writes the at least one embedding into the second memory, wherein the at least one embedding is an embedding required for model training that does not belong to the Mth batch.

[0052] Since the storage space in the first memory is limited, if the second processor uses the first memory as the basis, the available storage space is lower than the storage space required to store the first target embedding, then it is necessary to delete at least one embedding stored in the first memory so that there is enough space in the first memory to store the embedding passed from the second processor.

[0053] For example, the embeddings required for model training of the Mth batch include the first target embedding, embedding1, embedding2, and embedding3. The first memory stores embedding3, embedding4, and embedding5, but does not store the first target embedding, embedding1, and embedding2. The storage size of the first memory is 4. The available storage space (1) in the first memory is less than the storage space (3) required to store the first target embedding. Then, the two embeddings (including embedding4 and embedding5) stored in the first memory can be deleted so that there is enough space in the first memory to store the embeddings (including the first target embedding, embedding1, and embedding2) transferred from the second processor.

[0054] In order to ensure parameter consistency, the computing core can also write the deleted embedding into the second memory, so that when the second processor passes the embedding to the first memory of the first processor next time, the passed embedding is the latest updated embedding. Specifically, the second processor can write at least one embedding into the second memory.

[0055] Specifically, the embedding to be deleted is definitely not the embedding required for the model training of the current batch. Otherwise, if the embedding required for the model training of the current batch is deleted, the second processor will need extra time to transfer the embedding to the first memory of the first processor.

[0056] In addition, during the model training process for the model to be trained, the embedding that has not been used for the longest time among the multiple embeddings can be selected as the embedding that needs to be deleted. During the model training process for the model to be trained, the embedding that has not been used for the longest time among the multiple embeddings can be considered as an embedding that is not frequently used. After deleting these embeddings, the embeddings required for model training for a long time may not include these embeddings, which means that the frequency of data transmission from the second processor to the first processor is reduced. Through this selection method, the data transmission overhead from the second processor to the first processor can be reduced, which means that the communication volume of the computing system is reduced, thereby further improving the speed of system model training.

[0057] In a possible implementation, the method further includes:

[0058] Before writing the first target embedding into the first memory, the second processor acquires a first vector and a target vector, wherein the first vector is used to indicate the embedding required for the model training of the M-th batch, each element in the first vector is used to indicate an embedding, and different elements indicate different embeddings, and the target vector is used to indicate the arrangement relationship of the embeddings indicated by each element in the first vector when performing the model training of the M-th batch, and the embedding indicated by each element appears at least once in the arrangement relationship;

[0059] The second processor passes the first vector and the destination vector to the first processor.

[0060] In a possible implementation, the first processor is a graphics processor GPU, an embedded neural network processor NPU or a tensor processor TPU, the first memory is a cache, and the second processor is a central processing unit CPU.

[0061] In a third aspect, the present application provides a model training device, applied to a first processor, the first processor is communicatively connected to a second processor, the first processor includes a computing core and a first memory, and the second processor includes a second memory; the first processor and the second processor are processors of different types, wherein the computing core includes:

[0062] An acquiring unit, configured to acquire a first target embedding feature embedding through the second memory;

[0063] A model training unit, configured to train a model to be trained according to the first target embedding to obtain an updated model to be trained and a second target embedding, wherein the second target embedding is the updated first target embedding;

[0064] A data writing unit is used to write the second target embedding into the first memory.

[0065] In a possible implementation, the model training unit is used to perform an M-th batch model training on the to-be-trained model according to the first target embedding, where M is a positive integer greater than 1;

[0066] The acquisition unit is configured to acquire the second target embedding from the first memory after the computing core writes the second target embedding into the first memory;

[0067] The model training unit is further used for:

[0068] According to the second target embedding, the updated model to be trained is trained for the M+1th batch.

[0069] In a possible implementation, the model training unit is further used to:

[0070] According to the second target embedding, after performing model training of the M+1th batch on the updated model to be trained, a third target embedding is obtained, and the third target embedding is the updated second target embedding;

[0071] The data writing unit is further used to write the third target embedding into the first memory.

[0072] In a possible implementation, when the first target embedding is the embedding required for model training of the Mth batch, and the first memory does not store the first target embedding, the first memory obtains the first target embedding from the second memory;

[0073] The acquisition unit is specifically used for:

[0074] Obtain a first target embedding from the first memory.

[0075] In a possible implementation, the first memory obtains the first target embedding from the second memory, including:

[0076] In the process of the calculation core performing model training of the M-1th batch of the model to be trained, the first memory obtains the first target embedding from the second memory.

[0077] In a possible implementation, the acquisition unit is further used to acquire a first vector and a target vector from the second processor before the computing core acquires the first target embedding from the first memory, wherein the first vector is used to indicate the embedding required for the model training of the M-th batch, each element in the first vector is used to indicate an embedding, and different elements indicate different embeddings, and the target vector is used to indicate an arrangement relationship of the embeddings indicated by each element in the first vector when performing the model training of the M-th batch, and the embedding indicated by each element appears at least once in the arrangement relationship;

[0078] Obtaining, from the first memory according to the first vector, the embedding required for model training of the Mth batch;

[0079] According to the target vector and the embedding required for the model training of the M-th batch, an arrangement relationship of each embedding required for the model training of the M-th batch is determined.

[0080] In a possible implementation, the acquisition unit is further configured to:

[0081] Before the computing core trains the model to be trained according to the first target embedding, a third target embedding is obtained from a third memory in a third processor, wherein the third target embedding and the first target embedding are the embeddings required for the Mth batch model training, and the first processor and the third processor are processors of the same type;

[0082] The model training unit is specifically used for:

[0083] Processing the first target embedding and the third target embedding by the model to be trained to obtain a target output, and determining a first gradient based on the target output;

[0084] Update the model to be trained and the first target embedding based on the first gradient.

[0085] In a possible implementation, the model training unit is specifically used to:

[0086] determining the first gradient and the second gradient based on the target output;

[0087] The computing core also includes: a second data transmission unit, which is used to transmit the second gradient to the computing core of the third processor after determining the first gradient and the second gradient based on the target output, so that the computing core of the third processor updates the third target embedding according to the second gradient.

[0088] In a possible implementation, the first processor is a graphics processor GPU, an embedded neural network processor NPU or a tensor processor TPU, the first memory is a cache, and the second processor is a central processing unit CPU.

[0089] In a fourth aspect, the present application provides a model training device, applied to a second processor, the second processor is communicatively connected to a first processor, the first processor includes a computing core and a first memory, the second processor includes a second memory, and the first processor and the second processor are processors of different types; the device includes:

[0090] an acquisition unit, configured to acquire the embedding information required by the computing core for performing the Mth batch model training and the embedding information stored in the first memory, where M is a positive integer greater than 1;

[0091] A data writing unit is used to write a first target embedding into the first memory according to the embedding information required by the computing core for the Mth batch model training and the embedding information stored in the first memory, wherein the first target embedding is the embedding required for the Mth batch model training and not stored in the first memory.

[0092] In a possible implementation, the data writing unit is used to write the first target embedding into the first memory during the process of the calculation core performing model training of the M-1th batch of the model to be trained.

[0093] In a possible implementation, the data writing unit is further used to, before writing the first target embedding into the first memory, delete at least one embedding in the first memory and write the at least one embedding into the second memory when the available storage space in the first memory is lower than the storage space required to store the first target embedding, wherein the at least one embedding is an embedding required for model training that does not belong to the Mth batch.

[0094] In a possible implementation, the acquisition unit is further used to acquire a first vector and a target vector before writing the first target embedding into the first memory, wherein the first vector is used to indicate the embedding required for the model training of the M-th batch, each element in the first vector is used to indicate an embedding, and different elements indicate different embeddings, and the target vector is used to indicate the arrangement relationship of the embedding indicated by each element in the first vector when performing the model training of the M-th batch, and the embedding indicated by each element appears at least once in the arrangement relationship;

[0095] The data writing unit is further configured to transfer the first vector and the target vector to the first processor.

[0096] In a possible implementation, the first processor is a graphics processor GPU, an embedded neural network processor NPU or a tensor processor TPU, the first memory is a cache, and the second processor is a central processing unit CPU.

[0097] In the fifth aspect, an embodiment of the present application provides a model training device, which may include a memory, a processor, and a bus system, wherein the memory is used to store programs, and the processor is used to execute the programs in the memory to execute the above-mentioned first aspect, second aspect and any optional method thereof.

[0098] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, in which a computer program is stored. When the computer-readable storage medium is run on a computer, the computer executes the above-mentioned first aspect, second aspect and any optional method thereof.

[0099] In a seventh aspect, the present application provides a computer program product, comprising codes, which, when executed on a computer, enables the computer to execute the above-mentioned first aspect, second aspect and any optional method thereof.

[0100] In an eighth aspect, the present application provides a chip system, which includes a processor for supporting an execution device or a training device to implement the functions involved in the above aspects, such as sending or processing the data involved in the above methods; or information. In one possible design, the chip system also includes a memory, which is used to store program instructions and data necessary for the execution device or the training device. The chip system can be composed of chips, or it can include chips and other discrete devices.

[0101] The embodiment of the present application provides a model training method, which is applied to a first processor, the first processor is connected to the second processor in communication, the first processor includes a computing core and a first memory, and the second processor includes a second memory; the first processor and the second processor are different types of processors, and the method includes: the computing core obtains the first target embedding feature embedding through the second memory; the computing core trains the model to be trained according to the first target embedding to obtain the updated model to be trained and the second target embedding, and the second target embedding is the updated first target embedding; the computing core writes the second target embedding into the first memory. In the above manner, after completing the update of the embedding, the first processor stores the updated embedding in the first memory of the first processor. Under the premise that the first processor can obtain the latest updated embedding, the first processor does not need to wait for the second processor to complete the process of passing the second target embedding to the GPU, and can directly obtain the updated embedding, and perform the next round of model training based on the updated embedding. The present application can improve the processing speed of the training data of the processor when performing model training. BRIEF DESCRIPTION OF THE DRAWINGS

[0102] Figure 1 A structural diagram of the main framework of artificial intelligence;

[0103] Figure 2 It is a schematic diagram of an application architecture;

[0104] Figure 3 It is a schematic diagram of an application architecture;

[0105] Figure 4 A schematic diagram of the structure of a model;

[0106] Figure 5 An example of a model training method provided in an embodiment of the present application is shown;

[0107] Figure 6 This is an illustration of a model training method;

[0108] Figures 7 to 12 This is an example of a model training method in an embodiment of the present application;

[0109] Figures 13 to 16 This is an illustration of the effects of the embodiments of the present application;

[0110] Fig.17 and Fig.18aThis is a schematic diagram of the software modules of the embodiment of the present application;

[0111] Fig.18b This is an example of a model training method in an embodiment of the present application;

[0112] Fig.19 and Fig. 20 A schematic diagram of a model training device provided in an embodiment of the present application;

[0113] Fig.21 It is a structural schematic diagram of a training device provided in an embodiment of the present application;

[0114] Fig. 22 A schematic diagram of the structure of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0115] The embodiments of the present invention are described below in conjunction with the accompanying drawings in the embodiments of the present invention. The terms used in the implementation mode of the present invention are only used to explain the specific embodiments of the present invention, and are not intended to limit the present invention.

[0116] The embodiments of the present application are described below in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0117] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0118] First, the overall workflow of the artificial intelligence system is described. Figure 1 , Figure 1The figure shows a structural diagram of the main framework of artificial intelligence. The following is an explanation of the above artificial intelligence theme framework from the two dimensions of "intelligent information chain" (horizontal axis) and "IT value chain" (vertical axis). Among them, the "intelligent information chain" reflects a series of processes from data acquisition to processing. For example, it can be a general process of intelligent information perception, intelligent information representation and formation, intelligent reasoning, intelligent decision-making, intelligent execution and output. In this process, the data has undergone a condensation process of "data-information-knowledge-wisdom". The "IT value chain" reflects the value that artificial intelligence brings to the information technology industry from the underlying infrastructure of human intelligence, information (providing and processing technology implementation) to the industrial ecology process of the system.

[0119] (1) Infrastructure

[0120] The infrastructure provides computing power support for the AI ​​system, enables communication with the outside world, and supports it through the basic platform. It communicates with the outside world through sensors; computing power is provided by smart chips (CPU, NPU, GPU, ASIC, FPGA and other hardware acceleration chips); the basic platform includes distributed computing frameworks and networks and other related platform guarantees and support, which can include cloud storage and computing, interconnected networks, etc. For example, sensors communicate with the outside world to obtain data, and these data are provided to the smart chips in the distributed computing system provided by the basic platform for calculation.

[0121] (2) Data

[0122] The data on the upper layer of the infrastructure is used to represent the data sources in the field of artificial intelligence. The data involves graphics, images, voice, text, and IoT data of traditional devices, including business data of existing systems and perception data such as force, displacement, liquid level, temperature, and humidity.

[0123] (3) Data processing

[0124] Data processing usually includes data training, machine learning, deep learning, search, reasoning, decision-making and other methods.

[0125] Among them, machine learning and deep learning can symbolize and formalize data for intelligent information modeling, extraction, preprocessing, and training.

[0126] Reasoning refers to the process of simulating human intelligent reasoning in computers or intelligent systems, using formalized information to perform machine thinking and solve problems based on reasoning control strategies. Typical functions are search and matching.

[0127] Decision-making refers to the process of making decisions after intelligent information is reasoned, usually providing functions such as classification, sorting, and prediction.

[0128] (4) General ability

[0129] After the data has undergone the data processing mentioned above, some general capabilities can be further formed based on the results of the data processing, such as an algorithm or a general system, for example, translation, text analysis, computer vision processing, speech recognition, image recognition, etc.

[0130] (5) Smart products and industry applications

[0131] Smart products and industry applications refer to the products and applications of artificial intelligence systems in various fields. They are the encapsulation of the overall artificial intelligence solution, which productizes intelligent information decision-making and realizes practical applications. Its application areas mainly include: smart terminals, smart transportation, smart medical care, autonomous driving, safe cities, etc.

[0132] Next, the application scenarios of the embodiments of the present application are described.

[0133] The embodiments of the present application can be applied to a computing system, wherein the computing system can be a server or a terminal device, wherein the terminal device can be a movable device, a computer, etc., and the computing system can include a first processor and a second processor, wherein the first processor can be a graphics processor GPU, an embedded neural network processor NPU or a tensor processor TPU, etc., and the second processor can be a central processing unit CPU.

[0134] Take the computing system as a server, the first processor as a GPU, and the second processor as a CPU as an example. Figure 2 , Figure 2 A schematic diagram of the architecture of a server provided in an embodiment of the present application is shown as follows: Figure 2 As shown, the server may include a CPU and multiple GPUs interconnected with the CPU, wherein the CPU may include a memory (which may be referred to as a second memory in subsequent embodiments), the CPU may read and write the memory through a bus, and the GPU may include a computing core and a cache (or referred to as a video memory) (which may be referred to as a first memory in subsequent embodiments). The CPU and the GPU may transmit / exchange data through a bus such as PCie, and the GPUs may be interconnected through a PCie Switch / NVSwitch.

[0135] Reference Figure 3 , Figure 3 The server cluster architecture provided in this application embodiment is as follows: Figure 3 As shown, a server cluster may include multiple interconnected server nodes, wherein a server node is a virtual concept, including a multi-core multi-threaded CPU node and several GPU nodes. Multiple server nodes may be interconnected using a network such as Ethernet / InfiniBand.

[0136] The computing system used in the embodiment of the present application can be a server or multiple server nodes, wherein the embedded feature embedding (or referred to as embedding parameters) is stored in the memory of the CPU node, and the cache of the GPU node can be used to cache part of the embedding. The hard disk of the CPU node is used to store training samples, and the computing core or thread of the CPU node is mainly used for data reading and embedding transfer between the CPU and GPU. The computing core of the GPU node is used for forward and reverse calculations of the neural network, and data exchange / communication is performed between GPU nodes through PCie and other methods.

[0137] Since the embodiments of the present application involve the application of a large number of neural networks, in order to facilitate understanding, the relevant terms and related concepts such as neural networks involved in the embodiments of the present application are first introduced below.

[0138] (1) Neural Network

[0139] A neural network may be composed of neural units, and a neural unit may refer to an operation unit with xs and intercept 1 as input, and the output of the operation unit may be:

[0140] Where s=1, 2, ...n, n is a natural number greater than 1, Ws is the weight of xs, and b is the bias of the neural unit. f is the activation function of the neural unit, which is used to introduce nonlinear characteristics into the neural network to convert the input signal in the neural unit into the output signal. The output signal of the activation function can be used as the input of the next convolution layer, and the activation function can be a sigmoid function. A neural network is a network formed by connecting multiple single neural units mentioned above, that is, the output of one neural unit can be the input of another neural unit. The input of each neural unit can be connected to the local receptive field of the previous layer to extract the characteristics of the local receptive field. The local receptive field can be an area composed of several neural units.

[0141] (2) Embedding layer

[0142] The embedding layer may be referred to as an input embedding layer. The current input may be a text input, for example, a paragraph of text or a sentence. The text may be a Chinese text, an English text, or a text in another language. After obtaining the current input, the embedding layer may embed each word in the current input, and obtain a feature vector of each word. In some embodiments, the embedding layer includes an input embedding layer and a positional encoding layer. In the input embedding layer, each word in the current input may be subjected to word embedding processing to obtain a word embedding vector of each word. In the position encoding layer, the position of each word in the current input may be obtained, and then a position vector may be generated for the position of each word. In some examples, the position of each word may be the absolute position of each word in the current input. Taking the current input as "How many numbers should I return Huabei" as an example, the position of "how many" may be represented as the first position, the position of "number" may be represented as the second position, and so on. In some examples, the position of each word may be the relative position between each word. Still taking the current input of "repayment due on which date" as an example, the position of "how many" can be expressed as before "number", the position of "number" can be expressed as after "how many" and before "should", etc. When the word embedding vector and position vector of each word in the current input are obtained, the position vector of each word and the corresponding word embedding vector can be combined to obtain each word feature vector, that is, to obtain multiple feature vectors corresponding to the current input. Multiple feature vectors can be expressed as embedding vectors with preset dimensions. The number of feature vectors in the multiple feature vectors can be set to M, and the preset dimension can be H, then the multiple feature vectors can be expressed as M×H embedding vectors.

[0143] (3) Deep Learning Recommendation System

[0144] Based on the interaction behavior information of massive users and recommended objects, the recommendation model parameters are trained through methods such as gradient descent. When the model parameters converge, personalized recommendations can be made to users. Taking the click-through rate in the personalized recommendation system as an example, the input features include user features, product features, user historical behavior features, and context features, where features are divided into continuous features and discrete features. For discrete features, one-hot sparse coding is used, and then the embedding vector expression is taken from the embeddingtable through the encoding id, the original discrete feature id is vectorized, and then input into the recommendation model for training and learning for prediction.

[0145] In the training process of deep learning recommendation systems, the size of the training model and the amount of data have a direct impact on the effect of the model's online service. In the recommendation system, in order to enable the model to more accurately predict user interests, massive features and data are often required. Massive features bring corresponding massive parameters, making the model scale reach hundreds of GB or even TB, and massive data increases the computing power required for model training. Moreover, in order to capture user interests more quickly and provide users with better user experience and recommendation effects, deep models need to be updated frequently and quickly. These requirements bring about a thorny problem: the recommendation model training needs to be completed quickly based on massive features and massive data.

[0146] Different from visual and natural language processing (NLP) models, recommendation models have their own unique characteristics. Take the click-through rate (CTR) model as an example (e.g. Figure 4 ), the recommendation model consists of two parts: embedding layer embeddingLayer and multi-layer perception (muli-layer perception, MLP). The data of the recommendation task contains a large number of high-dimensional sparse id-type features, which are generally encoded using one-hot. Directly using these features for model training will make it difficult to learn some deep parameters. To solve this problem, researchers proposed an embedding layer to compress high-dimensional sparse one-hot vectors into low-dimensional dense vectors, also known as embedded feature embedding. The main parameters in the recommendation model are also located in the embedding layer (hundreds of GB or even TB). In addition, in order to improve the prediction accuracy of the model, the recommendation model generally constructs a feature combination mining module based on the multiplication network and the MLP network. This module is generally more complex and requires a relatively large amount of computation. It can be used for feature interactions and nonlinear mappings between data features.

[0147] Reference Figure 5 , Figure 5 A model training method is provided in an embodiment of the present application, wherein the first processor is communicatively connected with the second processor, the first processor includes a computing core and a first memory, and the second processor includes a second memory; the first processor and the second processor are processors of different types, wherein the first processor may be a GPU, an NPU or a TPU, the first memory may be a cache, and the second processor may be a CPU.

[0148] like Figure 5 As shown, a model training method provided in an embodiment of the present application includes:

[0149] 501. The computing core obtains a first target embedding feature embedding through the second memory.

[0150] In an embodiment of the present application, when the computing core is performing model training, the model to be trained can be obtained, where the model to be trained may include an embedding layer and other network layers. Taking the recommendation model as an example, the model to be trained may include an MLP layer.

[0151] In order to train the model to be trained, the computing core can obtain the embeddings (including the first target embeddings) required for the current batch from the first memory of the first processor. For the convenience of description, the following is an example in which the first processor is a GPU and the second processor is a CPU.

[0152] In the existing implementation, after completing the model training of a batch, the computing core needs to return the updated embeddings to the CPU (for example, including the updated embedding1). The CPU maintains an embedding table, where the embeddingtable can include some or all of the embeddings required for model training. If the model training of the next batch also requires (embedding1), in order to ensure the consistency of the parameters of interest, the CPU needs to pass the updated embedding1 to the GPU, and then the computing core of the GPU can obtain the updated embedding1 from the cache and perform model training for the next batch based on the updated embedding1. Therefore, the GPU needs to wait for the CPU to complete the process of passing the updated embedding1 to the GPU, which will cause time delays and greatly increase the training time.

[0153] For details, please refer to Figure 6At time 1, the CPU can determine that the embeddings required for model training of the next batch are data 1, 2, 3. At time 2, the CPU can pass data 1, 2, 3 to the GPU. At time 3, the GPU's computing core can complete model training based on data 1, 2, 3, and pass the updated data 1, 2, 3 to the CPU. At the same time, at time 3, the CPU can determine that the embeddings required for model training of the next batch are data 2, 3, 4. At time 4, the CPU can pass data 2, 3, 4 to the GPU. At time 5, the GPU's computing core can complete model training based on data 2, 3, 4, and pass the updated data 2, 3, 4 to the CPU. At the same time, at time 5, the CPU can determine that the embeddings required for model training of the next batch are data 1, 3, 4. At time 6, the CPU can pass data 1, 3, 4 to the GPU. At times 2, 4, and 6, the GPU needs to wait for the CPU to complete the process of passing the embeddings to the GPU, which greatly increases the training time.

[0154] The model training method provided in the embodiments of the present application can solve the above problems.

[0155] Specifically, refer to Fig. 9 In one implementation, if the model training to be performed currently is the model training of the Mth batch, the second processor can determine whether the first memory stores the embeddings required for the model training of the Mth batch. If the second processor determines that the first memory does not store part or all of the embeddings required for the model training of the Mth batch, the embeddings that are not stored in the first memory and are required for the model training can be obtained from the second storage, and the embeddings that are not stored in the first memory and are required for the model training can be transferred to the first memory.

[0156] For example, the embedding required for model training of the Mth batch includes the first target embedding. If the second processor determines that the first target embedding is not stored in the first memory, the second processor may write the first target embedding from the second memory to the cache.

[0157] In terms of the selection of the writing time point, the second processor may write the first target embedding from the second memory to the first memory during the process of the calculation core performing model training of the M-1th batch of the model to be trained.

[0158] Since the storage space in the first memory is limited, if the second processor uses the first memory as the basis, the available storage space is lower than the storage space required to store the target embedding, then it is necessary to delete at least one embedding stored in the first memory so that there is enough space in the first memory to store the embedding passed from the second processor.

[0159] For example, the embeddings required for model training of the Mth batch include the first target embedding, embedding1, embedding2, and embedding3. The first memory stores embedding3, embedding4, and embedding5, but does not store the first target embedding, embedding1, and embedding2. The storage size of the first memory is 4. The available storage space (1) in the first memory is less than the storage space (3) required to store the first target embedding. Then, the two embeddings (including embedding4 and embedding5) stored in the first memory can be deleted so that there is enough space in the first memory to store the embeddings (including the first target embedding, embedding1, and embedding2) transferred from the second processor.

[0160] Reference Fig.10 In order to ensure parameter consistency, the computing core can also write the deleted embedding into the second memory, so that when the second processor transfers the embedding to the first memory of the first processor next time, the transferred embedding is the latest updated embedding. Specifically, the second processor can write at least one embedding into the second memory.

[0161] Next, it is described how the second processor determines which embeddings in the first memory should be deleted.

[0162] In an embodiment of the present application, at least one embedding can be obtained from multiple embeddings stored in the first memory according to preset conditions, wherein the preset conditions include at least one of the following conditions: an embedding that has not been used for the longest time among the multiple embeddings during model training for the model to be trained; and an embedding that is not required for model training of the Mth batch.

[0163] Specifically, the embedding to be deleted is definitely not the embedding required for the model training of the current batch. Otherwise, if the embedding required for the model training of the current batch is deleted, the CPU will need extra time to transfer the embedding to the first memory of the first processor.

[0164] In addition, during the model training process for the model to be trained, the embeddings that have not been used for the longest time among the multiple embeddings can be considered as embeddings that are not frequently used. After deleting these embeddings, the embeddings required for model training may not include these embeddings for a long time, which means that the frequency of CPU transmitting data to the first processor is reduced. Through this selection method, the data transmission overhead from the CPU to the first processor can be reduced, which means that the communication volume of the computing system is reduced, thereby further improving the speed of system model training.

[0165] During the model training process, in order to enable the computing core of the first processor to know the embeddings required for the model training of the current batch, the second processor needs to pass the information indicating the embeddings required for the model training of the current batch to the computing core, and then the computing core can read the embeddings required for the model training of the current batch and the arrangement relationship between the embeddings from the first memory based on the above information.

[0166] Specifically, before the computing core obtains the first target embedding from the first memory, the computing core may obtain a first vector and a target vector from the second processor, wherein the first vector is used to indicate the embedding required for the model training of the Mth batch, each element in the first vector is used to indicate an embedding, and different elements indicate different embeddings, and the target vector is used to indicate the arrangement relationship of the embeddings indicated by each element in the first vector when performing the model training of the Mth batch, and the embedding indicated by each element appears at least once in the arrangement relationship; wherein the arrangement relationship may be the number of times the embedding indicated by each element in the first vector is used during the model training of the Mth batch, and the order of the embeddings indicated by each element in the first vector during the model training of the Mth batch.

[0167] In one implementation, the embeddings required for the same batch of batch model training may include the same embeddings. For example, the embeddings required for the same batch of batch model training may be: D = [embedding1, embedding2, embedding3, embedding3, embedding2, embedding4], then embedding2 and embedding3 are both repeated. In order to reduce the amount of parameters read by the computing core of the subsequent first processor for embedding, the second processor may perform a deduplication operation on the embeddings required for the same batch of batch model training. Specifically, the second processor may obtain a first vector, the elements included in the first vector being the embeddings required for the model training of the Mth batch; and the first vector may indicate information about the embeddings required for model training after deduplication.

[0168] Exemplarily, the first vector before deduplication may be: D = [embedding1, embedding2, embedding3, embedding3, embedding2, embedding4], and the first vector after deduplication is obtained by performing a deduplication operation on the first vector U = [embedding dding1, embedding2, embedding3, embedding4], and calculate the target vector Mask = [0,1,2,2,1,3], wherein the first element of the target vector is 0, indicating that the first element in the first vector is the first element in the second vector, the second element of the target vector is 1, indicating that the second element in the first vector is the second element in the second vector, the third element of the target vector is 2, indicating that the third element in the first vector is the third element in the second vector, the fourth element of the target vector is 2, indicating that the fourth element in the first vector is the third element in the second vector, the fifth element of the target vector is 1, indicating that the fifth element in the first vector is the second element in the second vector, and the sixth element of the target vector is 3, indicating that the sixth element in the first vector is the fourth element in the second vector. In this way, the first vector before deduplication can be restored based on the first vector and the target vector, wherein the first vector before deduplication is used to determine the arrangement relationship of each embedding required when performing the model training of the Mth batch.

[0169] In one implementation, the first processor can obtain the embeddings required for model training of the Mth batch from the first memory according to the first vector, and then determine the arrangement relationship of each embedding required for model training of the Mth batch according to the target vector and the embeddings required for model training of the Mth batch.

[0170] 502. The computing core trains the model to be trained according to the first target embedding to obtain an updated model to be trained and a second target embedding, where the second target embedding is the updated first target embedding.

[0171] In an embodiment of the present application, after the computing core obtains the embedding (including the first target embedding) required for the current batch model training, the model to be trained can be trained according to the embedding (including the first target embedding) required for the current batch model training to obtain an updated model to be trained and an updated embedding (including the second target embedding).

[0172] In one implementation, the computing core can perform forward and backward calculations based on the embeddings required for the current batch model training (including the first target embedding) and the model to be trained to obtain the gradient corresponding to the model to be trained and the gradients corresponding to the embeddings used in the current batch model training. Taking the model to be trained including MLP as an example, the network gradient of the model to be trained can include the neural network gradient (MLP_G); then, the parameters of the model to be trained and the embedding can be updated based on the network gradient of the model to be trained and the gradient of the embedding required for the current batch model training.

[0173] In one implementation, if the computing system can further include a third processor of the same processor type as the first processor, the first processor can complete the calculation of the gradient of a portion of the embedding required for the current batch model training. After obtaining the embedding gradient, the embedding gradient can be synchronized through communication between the first processors.

[0174] Specifically, the computing core obtains a third target embedding from a third memory in a third processor, the third target embedding and the first target embedding are the embeddings required for the Mth batch model training, and the first processor and the third processor are processors of the same type; the computing core processes the first target embedding and the third target embedding through the model to be trained to obtain a target output, and determines a first gradient and a second gradient based on the target output; the computing core can update the model to be trained and the first target embedding based on the first gradient, and pass the second gradient to the computing core of the third processor, so that the computing core of the third processor updates the third target embedding according to the second gradient.

[0175] In a scenario including multiple computing nodes, each computing node can be responsible for a portion of the embeddings required for the current batch model training, and is responsible for updating a portion of the embeddings. In one possible implementation, the computing core needs to obtain the third target embedding from the third memory of the third processor of other server nodes, and perform a feedforward process in the model training process based on the first target embedding and the third target embedding. However, when updating, the computing core in the first processor only needs to update the first target embedding based on the first gradient.

[0176] 503. The computing core writes the second target embedding into the first memory.

[0177] Reference Figure 7 In an embodiment of the present application, the computing core can write the updated model to be trained and the updated embedding (including the second target embedding) into the first memory.

[0178] If the first target embedding is also the embedding required for the next batch model training, the computing core can directly obtain the updated first target embedding (that is, the second target embedding) from the first memory. If the first memory does not store a part of the embedding required for the model training of the M+1th batch, the second processor can transfer this part of the embedding to the first memory.

[0179] Reference Figure 8Specifically, the first target embedding is the embedding required for model training of the Mth batch and the M+1th batch, where M is a positive integer greater than 1. The computing core can perform model training of the Mth batch on the model to be trained according to the first target embedding. When performing model training of the M+1th batch, the computing core obtains the second target embedding from the first memory, and performs model training of the M+1th batch on the updated model to be trained according to the second target embedding to obtain a third target embedding, and then the computing core can write the third target embedding into the first memory.

[0180] For example, the first processor is a GPU and the second processor is a CPU. Fig.11 As shown, assuming that the size of the first memory of the GPU is 6, at the beginning of the model training, at time 1, the CPU can determine that the embeddings required for the model training of the next batch are embedding1, embedding2, and embedding3 ( Fig.11 The data shown are 1, 2, 3);

[0181] At time 2, the CPU may transfer data 1, 2, and 3 to the first memory of the GPU;

[0182] At time 3, the computing core of the GPU can complete the model training based on data 1, 2, and 3. The CPU can determine that the embeddings required for the model training of the next batch are data 2, 3, and 4. Since data 4 is not stored in the first memory and the available storage space of the first memory is sufficient, the CPU can transfer data 4 to the first memory of the GPU.

[0183] At time 4, the computing core of the GPU can complete the model training based on data 2, 3, and 4. The CPU can determine that the embeddings required for the model training of the next batch are data 1, 3, and 5. Since data 5 is not stored in the first memory and the available storage space of the first memory is sufficient, the CPU can transfer data 5 to the first memory of the GPU.

[0184] At time 5, the computing core of the GPU can complete the model training based on data 1, 3, and 5. The CPU can determine that the embeddings required for the model training of the next batch are data 1, 6, and 7. Since data 6 and 7 are not stored in the first memory, and the available storage space of the first memory is insufficient (one is missing), the CPU can delete data 4 and transfer it back to the second memory of the CPU. Then, the CPU can transfer data 6 and 7 to the first memory of the GPU.

[0185] At time 6, the GPU's computing core can complete model training based on data 1, 6, and 7.

[0186] It can be seen that in the embodiment of the present application, after completing the update of the first target embedding, the first processor stores the second target embedding in the first memory of the first processor. Under the premise that the first processor can obtain the latest updated target embedding (second target embedding), the first processor does not need to wait for the second processor to complete the process of passing the second target embedding to the GPU, and can directly obtain the second target embedding and perform model training based on the second target embedding. The throughput of training data is increased, thereby improving the speed of model training.

[0187] In addition, during the training of the previous batch of batch models, the second processor will transfer the embeddings that are not stored in the first memory and are required for the training of the next batch of batch models to the first memory, so that the computing core of the second processor can obtain all the embeddings required for the training of the next batch of batch models from the first memory.

[0188] Reference Fig.12 In a scenario including multiple computing nodes, each computing node can be responsible for a part of the embeddings required for the current batch model training, and is responsible for updating a part of the embeddings. In a possible implementation, the computing core needs to obtain the third target embedding from the third memory of the third processor of other server nodes, and perform a feedforward process in the model training process based on the first target embedding and the third target embedding. However, when updating, the computing core in the first processor only needs to update the first target embedding based on the first gradient.

[0189] Specifically, during the model training process, the computing core can process the first target embedding and the third target embedding through the model to be trained to obtain the target output, and determine the first gradient and the second gradient based on the target output. The computing core can update the model to be trained and the first target embedding based on the first gradient, and pass the second gradient to the computing core of the third processor, so that the computing core of the third processor updates the third target embedding according to the second gradient.

[0190] In one implementation, data communication (such as allreduce communication) between the first processor and the third processor can be used to synchronize the gradient of the embedding, so that the third processor can obtain the second gradient calculated by the first processor after the current batch model is trained, and then the third processor can update the embedding (third target embedding) for which it is responsible based on the second gradient.

[0191] Exemplarily, each server node has 3 features, and the embedding required for the current batch model training is [1, 2, 3, 3, 2, 4]. It should be understood that 1 here can represent embedding1, 2 can represent embedding2, 3 can represent embedding3, and 4 can represent embedding4. The first three belong to the first server node, and the last three belong to the second server node: each server node reads the data [1, 2, 3, 3, 2, 4], and the CPU can transmit [0, 1, 2] to GPU node 1, and [2, 1, 3] to GPU node 2;

[0192] At this time, the first memory of GPU node 1 stores the embeddings of 2 and 4, and the first memory of GPU node 2 stores the embeddings of 1 and 3. By using data communication between GPUs (such as Allreduce communication) to exchange the embedding data of the two GPU nodes, each GPU can obtain E=[1,2,3,4].

[0193] Specifically, data communication between GPUs (such as Allreduce communication) can be used to synchronize the gradients of embeddings so that each GPU can obtain the gradients calculated by all GPU nodes in the current batch. After that, each GPU node can update the embedding it is responsible for. For example, GPU node 1 is responsible for updating the parameters of features 2 and 4.

[0194] Next, based on the implementation results, the model training method provided in the embodiment of the present application is verified.

[0195] Specifically, the TB-level Criteo dataset can be used for verification. Through feature screening, 10GB embeddingTable (33M feature IDs) and 100GB embeddingTable data (330M feature IDs) are constructed respectively. The model tested is the DeepFM model. The experimental hardware environment is that each server has two 2 18-core 36-thread CPUs, 8 V100 cards with 32G video memory, GPUs are interconnected through PCie, servers are connected through 100Gb RDMA, and each server has nearly 1T of memory.

[0196] like Fig.13 As described above, with respect to the throughput experiment, the embodiment of the present application achieved a higher training throughput, which was 4.7 times and 1.7 times that of HugeCTR and parameter server (PS) on the 10GB model, and 7.4 and 1.4 times that of HugeCTR and parameter server on the 100GB model.

[0197] like Fig.14 As shown in the figure, after adding the deduplication operation, the amount of GPU-CPU and GPU-GPU communication is greatly reduced.

[0198] like Fig.15 As shown, compared with the traditional Pre-fetch and parameter server (Host), it can be found that the training speed of the embodiment of the present application is the fastest. Fig.16 By comparing the model convergence curves of the three technologies, it can be found that the embodiment of the present application (corresponding to the Cache curve) has the fastest convergence speed.

[0199] Next, the model training method in the embodiment of the present application is described from the perspective of the software module:

[0200] Reference Fig.17 and Fig.18a, the training data (embedding) is stored in the hard disk or other storage location of the CPU node, and the embedding table is stored in the memory of the CPU; the data reading module can be used to read the training samples; the sparse data coding compression module is used to perform deduplication operation (or compression coding) on ​​the training samples of the current batch, and output the target vector Mask and the second vector; the parameter pre-fetching management module can maintain the cache cache to ensure that the embedding table is maintained in the CPU, so it can support ultra-large scale; the model to be trained has a backup in each GPU node; the GPU can include an embeddingCache (cache), and each GPU has a Cache to cache a part of the embedding; the embedding pulling module is used to obtain the second vector; the sparse data decoding module is used to obtain the embedding (first vector) required for forward calculation based on the target vector Mask and the second vector, the training module is used to perform forward and reverse gradient calculations and parameter updates; the collective communication module is used to synchronize the model to be trained and the gradient information of the embedding.

[0201] The embodiment of the present application provides a model training method, which is applied to a first processor, the first processor is connected to the second processor in communication, the first processor includes a computing core and a first memory, and the second processor includes a second memory; the first processor and the second processor are different types of processors, and the method includes: the computing core obtains the first target embedding feature embedding through the second memory; the computing core trains the model to be trained according to the first target embedding to obtain the updated model to be trained and the second target embedding, and the second target embedding is the updated first target embedding; the computing core writes the second target embedding into the first memory. In the above manner, after completing the update of the embedding, the first processor stores the updated embedding in the first memory of the first processor. Under the premise that the first processor can obtain the latest updated embedding, the first processor does not need to wait for the second processor to complete the process of passing the second target embedding to the GPU, and can directly obtain the updated embedding, and perform the next round of model training based on the updated embedding. The present application can improve the processing speed of the training data of the processor when performing model training.

[0202] The above describes the model training method in the embodiment of the present application with the first processor as the execution body. Next, the model training method in the embodiment of the present application will be described with the second processor as the execution body.

[0203] Reference Fig.18b , Fig.18b A flow chart of a model training method provided in an embodiment of the present application is shown as follows: Fig.18b As shown, a model training method provided in an embodiment of the present application is applied to a second processor, the second processor is communicatively connected to a first processor, the first processor includes a computing core and a first memory, the second processor includes a second memory, and the first processor and the second processor are processors of different types; the method includes:

[0204] 1801. The second processor obtains the embedding information required by the computing core for performing the Mth batch model training and the embedding information stored in the first memory, where M is a positive integer greater than 1.

[0205] Among them, the embedding information required for the Mth batch model training may indicate the embedding required for the Mth batch model training. For example, the information may be but is not limited to identification information indicating the embedding.

[0206] 1802. The second processor writes a first target embedding into the first memory according to the embedding information required by the computing core for the Mth batch model training and the embedding information stored in the first memory, where the first target embedding is the embedding required for the Mth batch model training and not stored in the first memory.

[0207] If the model training to be performed currently is the model training of the Mth batch, the second processor can determine whether the first memory stores the embeddings required for the model training of the Mth batch. If the second processor determines that the first memory does not store part or all of the embeddings required for the model training of the Mth batch, the embeddings that are not stored in the first memory and are required for the model training can be obtained from the second storage, and the embeddings that are not stored in the first memory and are required for the model training can be passed to the first memory.

[0208] For example, the embedding required for model training of the Mth batch includes the first target embedding. If the second processor determines that the first target embedding is not stored in the first memory, the second processor may write the first target embedding from the second memory to the cache.

[0209] In terms of the selection of the writing time point, the second processor may write the first target embedding from the second memory to the first memory during the process of the calculation core performing model training of the M-1th batch of the model to be trained.

[0210] In one possible implementation, before writing the first target embedding into the first memory, when the available storage space in the first memory is lower than the storage space required to store the first target embedding, the second processor deletes at least one embedding in the first memory and writes the at least one embedding into the second memory, wherein the at least one embedding is an embedding required for model training that does not belong to the Mth batch.

[0211] Since the storage space in the first memory is limited, if the second processor uses the first memory as the basis, the available storage space is lower than the storage space required to store the first target embedding, then it is necessary to delete at least one embedding stored in the first memory so that there is enough space in the first memory to store the embedding passed from the second processor.

[0212] For example, the embeddings required for model training of the Mth batch include the first target embedding, embedding1, embedding2, and embedding3. The first memory stores embedding3, embedding4, and embedding5, but does not store the first target embedding, embedding1, and embedding2. The storage size of the first memory is 4. The available storage space (1) in the first memory is less than the storage space (3) required to store the first target embedding. Then, the two embeddings (including embedding4 and embedding5) stored in the first memory can be deleted so that there is enough space in the first memory to store the embeddings (including the first target embedding, embedding1, and embedding2) transferred from the second processor.

[0213] In order to ensure parameter consistency, the computing core can also write the deleted embedding into the second memory, so that when the second processor passes the embedding to the first memory of the first processor next time, the passed embedding is the latest updated embedding. Specifically, the second processor can write at least one embedding into the second memory.

[0214] Specifically, the embedding to be deleted is definitely not the embedding required for the model training of the current batch. Otherwise, if the embedding required for the model training of the current batch is deleted, the second processor will need extra time to transfer the embedding to the first memory of the first processor.

[0215] In addition, during the model training process for the model to be trained, the embedding that has not been used for the longest time among the multiple embeddings can be selected as the embedding that needs to be deleted. During the model training process for the model to be trained, the embedding that has not been used for the longest time among the multiple embeddings can be considered as an embedding that is not frequently used. After deleting these embeddings, the embeddings required for model training for a long time may not include these embeddings, which means that the frequency of data transmission from the second processor to the first processor is reduced. Through this selection method, the data transmission overhead from the second processor to the first processor can be reduced, which means that the communication volume of the computing system is reduced, thereby further improving the speed of system model training.

[0216] In a possible implementation, before writing the first target embedding into the first memory, the second processor may obtain a first vector and a target vector, wherein the first vector is used to indicate the embedding required for the model training of the Mth batch, each element in the first vector is used to indicate an embedding, and different elements indicate different embeddings, and the target vector is used to indicate the arrangement relationship of the embeddings indicated by each element in the first vector when performing the model training of the Mth batch, and the embedding indicated by each element appears at least once in the arrangement relationship, and then the second processor may pass the first vector and the target vector to the first processor.

[0217] For a detailed description of the first vector and the target vector, please refer to Figure 5 The relevant descriptions in the corresponding embodiments are not repeated here.

[0218] In a possible implementation, the first processor is a graphics processor GPU, an embedded neural network processor NPU or a tensor processor TPU, the first memory is a cache, and the second processor is a central processing unit CPU.

[0219] Reference Fig.19 , Fig.19 A model training device provided in an embodiment of the present application is applied to a first processor, the first processor is communicatively connected to a second processor, the first processor includes a computing core and a first memory, and the second processor includes a second memory; the first processor and the second processor are processors of different types, wherein the computing core 1900 includes:

[0220] An acquiring unit 1901 is configured to acquire a first target embedding feature embedding through the second memory;

[0221] For the specific description of the acquisition unit 1901, please refer to the description of step 501, which will not be repeated here.

[0222] A model training unit 1902 is used to train the model to be trained according to the first target embedding to obtain an updated model to be trained and a second target embedding, where the second target embedding is the updated first target embedding;

[0223] For the specific description of the model training unit 1902, please refer to the description of step 502, which will not be repeated here.

[0224] The data writing unit 1903 is used to write the second target embedding into the first memory.

[0225] For the detailed description of the data writing unit 1903 , please refer to the description of step 503 , which will not be repeated here.

[0226] In a possible implementation, the model training unit is further used to:

[0227] According to the second target embedding, after performing model training of the M+1th batch on the updated model to be trained, a third target embedding is obtained, and the third target embedding is the updated second target embedding;

[0228] The data writing unit is further used to write the third target embedding into the first memory.

[0229] In a possible implementation, when the first target embedding is the embedding required for model training of the Mth batch, and the first memory does not store the first target embedding, the first memory obtains the first target embedding from the second memory;

[0230] The acquisition unit is specifically used for:

[0231] Obtain a first target embedding from the first memory.

[0232] In a possible implementation, the first memory obtains the first target embedding from the second memory, including:

[0233] In the process of the calculation core performing model training of the M-1th batch of the model to be trained, the first memory obtains the first target embedding from the second memory.

[0234] In a possible implementation, the acquisition unit is further used to acquire a first vector and a target vector from the second processor before the computing core acquires the first target embedding from the first memory, wherein the first vector is used to indicate the embedding required for the model training of the M-th batch, each element in the first vector is used to indicate an embedding, and different elements indicate different embeddings, and the target vector is used to indicate an arrangement relationship of the embeddings indicated by each element in the first vector when performing the model training of the M-th batch, and the embedding indicated by each element appears at least once in the arrangement relationship;

[0235] Obtaining, from the first memory according to the first vector, the embedding required for model training of the Mth batch;

[0236] According to the target vector and the embedding required for the model training of the M-th batch, an arrangement relationship of each embedding required for the model training of the M-th batch is determined.

[0237] In a possible implementation, the acquisition unit is further configured to:

[0238] Before the computing core trains the model to be trained according to the first target embedding, a third target embedding is obtained from a third memory in a third processor, wherein the third target embedding and the first target embedding are the embeddings required for the Mth batch model training, and the first processor and the third processor are processors of the same type;

[0239] The model training unit is specifically used for:

[0240] Processing the first target embedding and the third target embedding by the model to be trained to obtain a target output, and determining a first gradient based on the target output;

[0241] Update the model to be trained and the first target embedding based on the first gradient.

[0242] In a possible implementation, the model training unit is specifically used to:

[0243] determining the first gradient and the second gradient based on the target output;

[0244] The computing core also includes: a second data transmission unit, which is used to transmit the second gradient to the computing core of the third processor after determining the first gradient and the second gradient based on the target output, so that the computing core of the third processor updates the third target embedding according to the second gradient.

[0245] In a possible implementation, the first processor is a graphics processor GPU, an embedded neural network processor NPU or a tensor processor TPU, the first memory is a cache, and the second processor is a central processing unit CPU.

[0246] Reference Fig. 20 The present application also provides a model training device, which is applied to a second processor, the second processor is communicatively connected to a first processor, the first processor includes a computing core and a first memory, the second processor includes a second memory, and the first processor and the second processor are processors of different types; the device 2000 includes:

[0247] An acquisition unit 2001 is used to acquire the embedding information required by the computing core for performing the Mth batch model training and the embedding information stored in the first memory, where M is a positive integer greater than 1;

[0248] For the specific description of the acquisition unit 2001, please refer to the description of step 1801, which will not be repeated here.

[0249] The data writing unit 2002 is used to write a first target embedding into the first memory according to the embedding information required by the computing core for the Mth batch model training and the embedding information stored in the first memory, wherein the first target embedding is the embedding required for the Mth batch model training and not stored in the first memory.

[0250] For the specific description of the data writing unit 2002, please refer to the description of step 1802, which will not be repeated here.

[0251] In a possible implementation, the data writing unit is used to write the first target embedding into the first memory during the process of the calculation core performing model training of the M-1th batch of the model to be trained.

[0252] In a possible implementation, the data writing unit is further used to, before writing the first target embedding into the first memory, delete at least one embedding in the first memory and write the at least one embedding into the second memory when the available storage space in the first memory is lower than the storage space required to store the first target embedding, wherein the at least one embedding is an embedding required for model training that does not belong to the Mth batch.

[0253] In a possible implementation, the acquisition unit is further used to acquire a first vector and a target vector before writing the first target embedding into the first memory, wherein the first vector is used to indicate the embedding required for the model training of the M-th batch, each element in the first vector is used to indicate an embedding, and different elements indicate different embeddings, and the target vector is used to indicate the arrangement relationship of the embedding indicated by each element in the first vector when performing the model training of the M-th batch, and the embedding indicated by each element appears at least once in the arrangement relationship;

[0254] The data writing unit is further configured to transfer the first vector and the target vector to the first processor.

[0255] In a possible implementation, the first processor is a graphics processor GPU, an embedded neural network processor NPU or a tensor processor TPU, the first memory is a cache, and the second processor is a central processing unit CPU.

[0256] The present application also provides a training device. Fig.21 , Fig.21 It is a structural diagram of a training device provided in an embodiment of the present application. Specifically, the training device 2100 is implemented by one or more servers. The training device 2100 may have relatively large differences due to different configurations or performances, and may include one or more processors (central processing units, CPU) 2121 (for example, one or more processors) and memory 2132, and one or more storage media 2130 (for example, one or more mass storage devices) storing application programs 2142 or data 2144. Among them, the memory 2132 and the storage medium 2130 can be short-term storage or permanent storage. The program stored in the storage medium 2130 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations in the training device. Furthermore, the processor 2121 can be configured to communicate with the storage medium 2130 to execute a series of instruction operations in the storage medium 2130 on the training device 2100.

[0257] Among them, the processor can be the first processor or the second processor in the embodiment of the present application.

[0258] The training device 2100 may also include one or more power supplies 2126, one or more wired or wireless network interfaces 2150, one or more input and output interfaces 2158; or, one or more operating systems 2141, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.

[0259] Specifically, the training device can perform Figure 5 as well as Fig.18b The model training method in the corresponding embodiment.

[0260] Also provided in an embodiment of the present application is a computer program product which, when executed on a computer, enables the computer to execute the steps executed by the aforementioned execution device, or enables the computer to execute the steps executed by the aforementioned training device.

[0261] A computer-readable storage medium is also provided in an embodiment of the present application, which stores a program for signal processing. When the computer-readable storage medium is run on a computer, it enables the computer to execute the steps executed by the aforementioned execution device, or enables the computer to execute the steps executed by the aforementioned training device.

[0262] The execution device, training device or terminal device provided in the embodiments of the present application may specifically be a chip, and the chip includes: a processing unit and a communication unit, wherein the processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, a pin or a circuit, etc. The processing unit may execute the computer execution instructions stored in the storage unit so that the chip in the execution device executes the data processing method described in the above embodiment, or so that the chip in the training device executes the data processing method described in the above embodiment. Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, etc. The storage unit may also be a storage unit located outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc.

[0263] For details, please refer to Fig. 22 , Fig. 22 A schematic diagram of the structure of a chip provided in an embodiment of the present application, the chip can be expressed as a neural network processor NPU 2200, NPU 2200 is mounted on the host CPU (Host CPU) as a coprocessor, and the host CPU assigns tasks. The core part of the NPU is the operation circuit 2203, which is controlled by the controller 2204 to extract vector data from the memory and perform multiplication operations.

[0264] Among them, NPU 2200 can be the first processor in the embodiment of the present application.

[0265] In some implementations, the operation circuit 2203 includes multiple processing units (Process Engine, PE) inside. In some implementations, the operation circuit 2203 is a two-dimensional systolic array. The operation circuit 2203 can also be a one-dimensional systolic array or other electronic circuits capable of performing mathematical operations such as multiplication and addition. In some implementations, the operation circuit 2203 is a general-purpose vector processor.

[0266] For example, assume there is an input vector A, a weight vector B, and an output vector C. The operation circuit takes the data corresponding to vector B from the weight memory 2202 and caches it on each PE in the operation circuit. The operation circuit takes the vector A data from the input memory 2201 and performs vector operation with vector B, and the partial result or final result of the vector is stored in the accumulator 2208.

[0267] The unified memory 2206 is used to store input data and output data. The weight data is directly transferred to the weight memory 2202 through the direct memory access controller (DMAC) 2205. The input data is also transferred to the unified memory 2206 through the DMAC.

[0268] BIU stands for Bus Interface Unit, i.e., bus interface unit 2210 , which is used for interaction between AXI bus and DMAC and instruction fetch buffer (IFB) 2209 .

[0269] The bus interface unit 2210 (Bus Interface Unit, BIU for short) is used for the instruction fetch memory 2209 to obtain instructions from the external memory, and is also used for the storage unit access controller 2205 to obtain the original data of the input vector A or the weight vector B from the external memory.

[0270] DMAC is mainly used to transfer input data in the external memory DDR to the unified memory 2206 or to transfer weight data to the weight memory 2202 or to transfer input data to the input memory 2201.

[0271] The vector calculation unit 2207 includes multiple operation processing units, and further processes the output of the operation circuit 2203 when necessary, such as vector multiplication, vector addition, exponential operation, logarithmic operation, size comparison, etc. It is mainly used for non-convolutional / fully connected layer network calculations in neural networks, such as Batch Normalization, pixel-level summation, upsampling of feature planes, etc.

[0272] In some implementations, the vector calculation unit 2207 can store the processed output vector to the unified memory 2206. For example, the vector calculation unit 2207 can apply a linear function; or a nonlinear function to the output of the operation circuit 2203, such as linear interpolation of the feature plane extracted by the convolution layer, and then, for example, a vector of accumulated values ​​to generate an activation value. In some implementations, the vector calculation unit 2207 generates a normalized value, a pixel-level summed value, or both. In some implementations, the processed output vector can be used as an activation input to the operation circuit 2203, for example, for use in a subsequent layer in a neural network.

[0273] An instruction fetch buffer 2209 connected to the controller 2204 is used to store instructions used by the controller 2204;

[0274] Unified memory 2206, input memory 2201, weight memory 2202 and instruction fetch memory 2209 are all on-chip memories. External memories are private to the NPU hardware architecture.

[0275] The processor mentioned in any of the above places may be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the above program.

[0276] It should also be noted that the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the drawings of the device embodiments provided by the present application, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines.

[0277] Through the description of the above implementation mode, the technicians in the field can clearly understand that the present application can be implemented by means of software plus necessary general hardware, and of course, it can also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. In general, all functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be various, such as analog circuits, digital circuits or special circuits. However, for the present application, software program implementation is a better implementation mode in more cases. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer floppy disk, a U disk, a mobile hard disk, a ROM, a RAM, a disk or an optical disk, etc., including a number of instructions to enable a computer device (which can be a personal computer, a training device, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0278] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0279] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a training device, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, training device, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device, a data center, etc. that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

Claims

1. A model training method, characterized in that: Applied to a first processor, the first processor is communicatively connected with a second processor, the first processor includes a computing core and a first memory, the second processor includes a second memory; the first processor and the second processor are processors of different types, the method includes: The computing core obtains a first target embedding feature embedding through the second memory; The computing core trains the model to be trained according to the first target embedding to obtain an updated model to be trained and a second target embedding, where the second target embedding is the updated first target embedding; The computing core writes the second target embedding into the first memory.

2. The method according to claim 1, characterized in that The computing core trains the model to be trained according to the first target embedding, including: The computing core performs an M-th batch of model training on the model to be trained according to the first target embedding, where M is a positive integer greater than 1; After the computing core writes the second target embedding into the first memory, the method further includes: The computing core obtains the second target embedding from the first memory; The computing core performs model training for the M+1th batch on the updated model to be trained according to the second target embedding.

3. The method according to claim 2, characterized in that The method further comprises: The computing core performs model training of the updated model to be trained for the M+1th batch according to the second target embedding, thereby obtaining a third target embedding, where the third target embedding is the updated second target embedding; The computing core writes the third target embedding into the first memory.

4. The method according to claim 3, characterized in that The computing core obtains the first target embedding through the second memory, including: When the first target embedding is the embedding required for the model training of the Mth batch, and the first memory does not store the first target embedding, the first memory obtains the first target embedding from the second memory; The computing core obtains a first target embedding from the first memory.

5. The method according to claim 4, characterized in that The first memory obtains the first target embedding from the second memory, including: In the process of the calculation core performing model training of the M-1th batch of the model to be trained, the first memory obtains the first target embedding from the second memory.

6. The method according to claim 4 or 5, characterized in that: The method further comprises: Before the computing core obtains the first target embedding from the first memory, the computing core obtains a first vector and a target vector from the second processor, wherein the first vector is used to indicate the embedding required for the model training of the M-th batch, each element in the first vector is used to indicate an embedding, and different elements indicate different embeddings, and the target vector is used to indicate the arrangement relationship of the embeddings indicated by each element in the first vector when performing the model training of the M-th batch, and the embedding indicated by each element appears at least once in the arrangement relationship; The computing core obtains a first target embedding from the first memory, including: The computing core obtains, from the first memory according to the first vector, the embedding required for model training of the Mth batch; The computing core determines, according to the target vector and the embeddings required for the model training of the Mth batch, an arrangement relationship of each embedding required for the model training of the Mth batch.

7. The method according to any one of claims 2 to 5, characterized in that: Before the computing core trains the model to be trained according to the first target embedding, the method further includes: The computing core obtains a third target embedding from a third memory in a third processor, the third target embedding and the first target embedding are the embeddings required for the Mth batch model training, and the first processor and the third processor are processors of the same type; The computing core trains the model to be trained according to the first target embedding, including: The computing core processes the first target embedding and the third target embedding through the model to be trained to obtain a target output, and determines a first gradient based on the target output; The computing core updates the model to be trained and the first target embedding based on the first gradient.

8. The method according to claim 7, characterized in that The determining the first gradient based on the target output comprises: determining the first gradient and the second gradient based on the target output; After determining the first gradient and the second gradient based on the target output, the method further includes: The second gradient is transmitted to a computing core of a third processor, so that the computing core of the third processor updates the third target embedding according to the second gradient.

9. The method according to any one of claims 1 to 5, characterized in that: The first processor is a graphics processor GPU, an embedded neural network processor NPU or a tensor processor TPU, the first memory is a cache, and the second processor is a central processing unit CPU.

10. A model training method, characterized in that: Applied to a second processor, the second processor is communicatively connected to a first processor, the first processor includes a computing core and a first memory, the second processor includes a second memory, and the first processor and the second processor are processors of different types; the method includes: The second processor obtains the embedding information required by the computing core for performing the Mth batch model training and the embedding information stored in the first memory, where M is a positive integer greater than 1; The second processor writes a first target embedding into the first memory according to the embedding information required by the computing core for the Mth batch model training and the embedding information stored in the first memory, where the first target embedding is the embedding required for the Mth batch model training and not stored in the first memory.

11. The method according to claim 10, characterized in that Writing the first target embedding into the first memory includes: During the process in which the computing core performs model training of the M-1th batch on the model to be trained, the first target embedding is written into the first memory.

12. The method according to claim 10 or 11, characterized in that: Before writing the first target embedding into the first memory, the method further includes: When the available storage space in the first memory is lower than the storage space required to store the first target embedding, the second processor deletes at least one embedding in the first memory and writes the at least one embedding into the second memory, wherein the at least one embedding is an embedding required for model training that does not belong to the Mth batch.

13. The method according to any one of claims 10 to 11, characterized in that: The method further comprises: Before writing the first target embedding into the first memory, the second processor acquires a first vector and a target vector, wherein the first vector is used to indicate the embedding required for the model training of the M-th batch, each element in the first vector is used to indicate an embedding, and different elements indicate different embeddings, and the target vector is used to indicate the arrangement relationship of the embeddings indicated by each element in the first vector when performing the model training of the M-th batch, and the embedding indicated by each element appears at least once in the arrangement relationship; The second processor passes the first vector and the destination vector to the first processor.

14. The method according to any one of claims 10 to 11, characterized in that: The first processor is a graphics processor GPU, an embedded neural network processor NPU or a tensor processor TPU, the first memory is a cache, and the second processor is a central processing unit CPU.

15. A model training device, characterized in that: Applied to a first processor, the first processor is communicatively connected with a second processor, the first processor includes a computing core and a first memory, the second processor includes a second memory; the first processor and the second processor are processors of different types, wherein the computing core includes: An acquiring unit, configured to acquire a first target embedding feature embedding through the second memory; A model training unit, configured to train a model to be trained according to the first target embedding to obtain an updated model to be trained and a second target embedding, wherein the second target embedding is the updated first target embedding; A data writing unit is used to write the second target embedding into the first memory.

16. The device according to claim 15, characterized in that The model training unit is used to perform an M-th batch model training on the model to be trained according to the first target embedding, where M is a positive integer greater than 1; The acquisition unit is configured to acquire the second target embedding from the first memory after the computing core writes the second target embedding into the first memory; The model training unit is further used for: According to the second target embedding, the updated model to be trained is trained for the M+1th batch.

17. The device according to claim 16, characterized in that The model training unit is further used for: According to the second target embedding, after performing model training of the M+1th batch on the updated model to be trained, a third target embedding is obtained, and the third target embedding is the updated second target embedding; The data writing unit is further used to write the third target embedding into the first memory.

18. The device according to claim 17, characterized in that When the first target embedding is the embedding required for the model training of the Mth batch, and the first memory does not store the first target embedding, the first memory obtains the first target embedding from the second memory; The acquisition unit is specifically used for: Obtain a first target embedding from the first memory.

19. The device according to claim 18, characterized in that The first memory obtains the first target embedding from the second memory, including: In the process of the calculation core performing model training of the M-1th batch of the model to be trained, the first memory obtains the first target embedding from the second memory.

20. The device according to claim 18 or 19, characterized in that The acquisition unit is further used to acquire a first vector and a target vector from the second processor before the computing core acquires the first target embedding from the first memory, wherein the first vector is used to indicate the embedding required for the model training of the M-th batch, each element in the first vector is used to indicate an embedding, and different elements indicate different embeddings, and the target vector is used to indicate the arrangement relationship of the embeddings indicated by each element in the first vector when performing the model training of the M-th batch, and the embedding indicated by each element appears at least once in the arrangement relationship; Obtaining, from the first memory according to the first vector, the embedding required for model training of the Mth batch; According to the target vector and the embeddings required for the model training of the M-th batch, an arrangement relationship of each embedding required for the model training of the M-th batch is determined.

21. The device according to any one of claims 16 to 19, characterized in that The acquisition unit is further used for: Before the computing core trains the model to be trained according to the first target embedding, a third target embedding is obtained from a third memory in a third processor, wherein the third target embedding and the first target embedding are the embeddings required for the Mth batch model training, and the first processor and the third processor are processors of the same type; The model training unit is specifically used for: Processing the first target embedding and the third target embedding by the model to be trained to obtain a target output, and determining a first gradient based on the target output; Update the model to be trained and the first target embedding based on the first gradient.

22. The device according to claim 21, characterized in that The model training unit is specifically used for: determining the first gradient and the second gradient based on the target output; The computing core also includes: a second data transmission unit, which is used to transmit the second gradient to the computing core of the third processor after determining the first gradient and the second gradient based on the target output, so that the computing core of the third processor updates the third target embedding according to the second gradient.

23. The device according to any one of claims 15 to 19, characterized in that The first processor is a graphics processor GPU, an embedded neural network processor NPU or a tensor processor TPU, the first memory is a cache, and the second processor is a central processing unit CPU.

24. A model training device, characterized in that: Applied to a second processor, the second processor is communicatively connected to a first processor, the first processor includes a computing core and a first memory, the second processor includes a second memory, and the first processor and the second processor are processors of different types; the device includes: an acquisition unit, configured to acquire the embedding information required by the computing core for performing the Mth batch model training and the embedding information stored in the first memory, where M is a positive integer greater than 1; A data writing unit is used to write a first target embedding into the first memory according to the embedding information required by the computing core for the Mth batch model training and the embedding information stored in the first memory, wherein the first target embedding is the embedding required for the Mth batch model training and not stored in the first memory.

25. The device according to claim 24, characterized in that The data writing unit is used to write the first target embedding into the first memory during the process in which the computing core performs model training of the M-1th batch of the to-be-trained model.

26. The device according to claim 24 or 25, characterized in that The data writing unit is further used to, before writing the first target embedding into the first memory, delete at least one embedding in the first memory and write the at least one embedding into the second memory when the available storage space in the first memory is lower than the storage space required to store the first target embedding, wherein the at least one embedding is an embedding required for model training that does not belong to the Mth batch.

27. The device according to any one of claims 24 to 25, characterized in that The acquisition unit is further used to acquire a first vector and a target vector before writing the first target embedding into the first memory, wherein the first vector is used to indicate the embedding required for the model training of the M-th batch, each element in the first vector is used to indicate an embedding, and different elements indicate different embeddings, and the target vector is used to indicate the arrangement relationship of the embeddings indicated by each element in the first vector when performing the model training of the M-th batch, and the embedding indicated by each element appears at least once in the arrangement relationship; The data writing unit is further configured to transfer the first vector and the target vector to the first processor.

28. The device according to any one of claims 24 to 25, characterized in that The first processor is a graphics processor GPU, an embedded neural network processor NPU or a tensor processor TPU, the first memory is a cache, and the second processor is a central processing unit CPU.

29. A model training device, characterized in that: The device includes a memory and a processor; the memory stores codes, and the processor is configured to obtain the codes and execute the method according to any one of claims 1 to 14.

30. A computer storage medium, characterized in that The computer storage medium stores one or more instructions, which, when executed by one or more computers, enable the one or more computers to implement the method of any one of claims 1 to 14.

31. A computer program product, characterized in that The computer program product comprises codes for implementing the steps of the method according to any one of claims 1 to 14 when the codes are executed.

Images