Integrated circuit comprising integrated standard cell structures

Abstract

The present disclosure provides integrated circuits including integrated standard cell structures. An integrated circuit includes: a first active region and a second active region extending in a first direction and spaced apart from each other in a second direction crossing the first direction; a power rail and a ground rail extending in the first direction and spaced apart from the first active region and the second active region and from each other in the second direction; a source / drain contact extending in the second direction on at least a portion of the first active region or the second active region; a gate structure extending in the second direction and on at least a portion of the first active region and the second active region; the power rail configured to supply power through the source / drain contact via; and the ground rail configured to supply a ground voltage through the source / drain contact via.

Description

Technical Field

[0001] This disclosure relates to integrated circuits including integrated standard cell structures. Background Technology

[0002] Integrated circuits can be designed based on standard cells. More specifically, the layout of an integrated circuit can be generated by arranging standard cells according to the data defining the integrated circuit and routing the arranged standard cells. Such standard cells are pre-designed and stored in a cell library.

[0003] As semiconductor manufacturing processes become miniaturized, the size of patterns in standard cells can be reduced, and the size of standard cells can also be reduced. Summary of the Invention

[0004] This disclosure aims to provide an integrated circuit that allows for increased layout density, improved stability of the process for manufacturing semiconductor devices, and improved performance and reliability of the designed semiconductor devices by means of source / drain contact-to-source / drain wiring.

[0005] However, the inventive concept is not limited to the aspects set forth herein. These and other aspects of the inventive concept will become more apparent to those skilled in the art upon which it pertains by referring to the following detailed description of the inventive concept.

[0006] According to some exemplary embodiments, an integrated circuit is provided, comprising: a first active region and a second active region extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a power rail extending in the first direction and spaced apart from the first active region in the second direction; a ground rail extending in the first direction and spaced apart from the second active region and the power rail in the second direction; a first source / drain contact extending in the second direction on at least a portion of the first active region and configured to receive power from the power rail through a first source / drain contact path; and a second source / drain contact extending in the second direction on at least a portion of the second active region and spaced apart from the first source / drain contact in the second direction. The contacts are spaced apart and connected to a ground rail via a second source / drain contact path to be grounded; a first gate structure extends in a second direction and is spaced apart from the first source / drain contact in a first direction on at least a portion of the first active region and at least a portion of the second active region; a third source / drain contact extends in a second direction and is spaced apart from the first gate structure in a first direction on at least a portion of the first active region and at least a portion of the second active region; a second gate structure extends in a second direction and is spaced apart from the third source / drain contact in a first direction on at least a portion of the first active region; a third gate structure extends in a second direction and is spaced apart from the first gate structure in a second direction on at least a portion of the first active region; At least a portion of the second active region is spaced apart from the third source / drain contact in a first direction and from the second gate structure in a second direction; a fourth source / drain contact is spaced apart from the second and third gate structures in a first direction on at least a portion of the first and second active regions; a fourth gate structure extends in a second direction and is spaced apart from the fourth source / drain contact in a first direction on at least a portion of the first active region; a fifth gate structure extends in a second direction and is spaced apart from the fourth source / drain contact in a first direction and from the fourth gate structure in a second direction on at least a portion of the second active region; the fifth source / drain contact... A sixth gate structure, extending in a second direction and spaced apart from the fourth and fifth gate structures on at least a portion of the first and second active regions, on at least a portion of the first and second active regions, on the first direction, from the fifth source / drain contact; a sixth source / drain contact, extending in a second direction and spaced apart from the sixth gate structure on at least a portion of the first active region; and a seventh source / drain contact, extending in a second direction and spaced apart from the sixth gate structure on at least a portion of the second active region, on the first direction and on the second direction, from the sixth source / drain contact.

[0007] According to some example embodiments, an integrated circuit is provided, comprising: a first inverter including a first p-channel metal-oxide-semiconductor (PMOS) transistor and a first n-channel metal-oxide-semiconductor (NMOS) transistor, the first PMOS transistor and the first NMOS transistor being selected via a first metal line, a first input voltage being configured to be applied to the first metal line, and the first inverter being configured to output a first inverted voltage by inverting the first input voltage, wherein the drains of the first NMOS transistor and the drains of the first PMOS transistor are connected via a first source / drain contact, the first metal line extending in a first direction, and the first source / drain contact extending in a second direction perpendicular to the first direction; a first transmission gate including a second PMOS transistor and a second NMOS transistor, the second PMOS transistor being selected via a second metal line, a first active voltage being configured to be applied to the second metal line, the second NMOS transistor being selected via a third metal line, and a second active voltage being configured to be applied to the second metal line. The second active voltage is configured to be applied to the third metal line, wherein the source of the second PMOS transistor and the drain of the second NMOS transistor are connected through a first source / drain contact, and the drain of the second PMOS transistor and the source of the second NMOS transistor are connected through a second source / drain contact; and a first tri-state inverter, including a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor, and a fourth NMOS transistor, wherein the third PMOS transistor is selected through the fourth metal line, a second active voltage is configured to be applied to the fourth metal line, the third NMOS transistor is selected through a fifth metal line, a first active voltage is configured to be applied to the fifth metal line, the fourth PMOS transistor and the fourth NMOS transistor are selected through a sixth metal line, a second input voltage is configured to be applied to the sixth metal line, and the first tri-state inverter is configured to invert the second input voltage, wherein the drain of the third PMOS transistor and the drain of the third NMOS transistor are connected through a second source / drain contact.

[0008] According to some example embodiments, an integrated circuit is provided, comprising: a first inverter configured to invert a first input voltage and output a first inverted voltage; a first transmission gate configured to receive the first inverted voltage; a second inverter configured to invert a second input voltage and output a second inverted voltage; and a second transmission gate configured to receive the second inverted voltage, wherein the first transmission gate includes a first n-channel metal-oxide-semiconductor (NMOS) transistor and a first p-channel metal-oxide-semiconductor (PMOS) transistor spaced apart from each other in a first direction, wherein the drain of the first NMOS transistor and the source of the first PMOS transistor are connected by a first source / drain contact extending in the first direction, and the first transmission gate receives the first inverted voltage through the first source / drain contact. The inverting voltage, the second transmission gate includes a second NMOS transistor and a second PMOS transistor spaced apart from each other in a first direction, wherein the drain of the second NMOS transistor and the source of the second PMOS transistor are connected by a second source / drain contact extending in the first direction, and the second transmission gate receives a second inverting voltage through the second source / drain contact, the source of the first NMOS transistor, the drain of the first PMOS transistor, the source of the second NMOS transistor and the drain of the second PMOS transistor are connected to each other through a third source / drain contact extending in the first direction, the first NMOS transistor and the second PMOS transistor are selected by a first active voltage, and the first PMOS transistor and the second NMOS transistor are selected by a second active voltage. Attached Figure Description

[0009] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 This is a circuit diagram used to describe a three-state inverter according to some example implementations.

[0011] Figure 2 It is used to describe implementations based on some example methods. Figure 1 A perspective view of region R of the tri-state inverter shown.

[0012] Figure 3 It is used to describe implementations based on some example methods. Figure 1 The diagram shows the layout of region R of the three-state inverter.

[0013] Figure 4 It is used to describe implementations based on some example methods. Figure 1 A perspective view of region R of the tri-state inverter shown.

[0014] Figure 5 It is used to describe implementations based on some example methods. Figure 1The diagram shows the layout of region R of the three-state inverter.

[0015] Figure 6 It is a layout diagram of an integrated circuit according to some example implementations.

[0016] Figure 7 This illustrates some example implementations. Figure 6 The block diagram of the first unit C_1 is shown.

[0017] Figure 8 Based on some example implementations Figure 7 The circuit diagram.

[0018] Figure 9 This illustrates some example implementations. Figure 8 The circuit diagram of the scanning circuit S_C is shown.

[0019] Figure 10 Based on some example implementations Figure 9 Layout diagram.

[0020] Figures 11 to 13 Based on some example implementations Figure 9 Layout diagram.

[0021] Figure 14 This illustrates some example implementations. Figure 10 The layout diagram of FEOL.

[0022] Figure 15 This illustrates some example implementations. Figure 10 Another layout diagram of FEOL.

[0023] Figure 16 This illustrates some example implementations. Figure 10 The layout diagram of MOL.

[0024] Figure 17 This illustrates some example implementations. Figure 10 The layout diagram of BEOL.

[0025] Figure 18 and Figure 19 It is along Figure 10 A cross-sectional view taken from line A-A'.

[0026] Figure 20 and Figure 21 It is along Figure 10 The cross-sectional view taken by line B-B'.

[0027] Figure 22 and Figure 23 It is along Figure 10 A cross-sectional view taken from line C-C'.

[0028] Figure 24 and Figure 25 It is used to describe implementations based on some example methods. Figure 10 A magnified view of the SDTR region shown.

[0029] Figure 26 and Figure 27 It is used to describe implementations based on some example methods. Figure 10 A magnified view of the GTR region shown.

[0030] Figure 28 This illustrates some example implementations. Figure 8 The circuit diagram of the scanning circuit S_C is shown.

[0031] Figures 29 to 31 Based on some example implementations Figure 28 Layout diagram.

[0032] Figure 32 It is shown Figure 8 The circuit diagram of the scanning circuit S_C is shown.

[0033] Figures 33 to 35 Based on some example implementations Figure 32 Layout diagram.

[0034] Figure 36 This illustrates some example implementations. Figure 8 The circuit diagram of the main latch M_L is shown.

[0035] Figure 37 and Figure 38 Based on some example implementations Figure 36 Layout diagram.

[0036] Figure 39 This illustrates some example implementations. Figure 8 The circuit diagram of the main latch M_L is shown.

[0037] Figure 40 and Figure 41 Based on some example implementations Figure 39 Layout diagram.

[0038] Figure 42 This illustrates some example implementations. Figure 8 The circuit diagram of the main latch M_L is shown.

[0039] Figure 43 and Figure 44 Based on some example implementations Figure 42 Layout diagram. Detailed Implementation

[0040] Figure 1 This is a circuit diagram used to describe a three-state inverter according to some example implementations.

[0041] Reference Figure 1 The tri-state inverter 1 includes a first p-channel metal-oxide-semiconductor (PMOS) transistor P1, a second PMOS transistor P2, a first n-channel metal-oxide-semiconductor (NMOS) transistor N1, and a second NMOS transistor N2.

[0042] The source of the first PMOS transistor P1 is connected to the power supply voltage Vdd, and the drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2. The drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2, and the source of the second NMOS transistor N2 is connected to the drain of the first NMOS transistor N1. The source of the first NMOS transistor N1 is grounded.

[0043] The first PMOS transistor P1 and the first NMOS transistor N1 are selected by the input voltage Vin, and the second PMOS transistor P2 is selected by the inverting active signal. The second NMOS transistor N2 is selected via the active signal EN.

[0044] In other words, when the active signal EN is at a logic high level, the tri-state inverter 1 inverts the input voltage and outputs the inverted input voltage as the output voltage Vout. Conversely, when the active signal EN is at a logic low level, the tri-state inverter 1 is at a high impedance and outputs the voltage Vout.

[0045] The drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2 at the node where the output voltage Vout of the tri-state inverter 1 is located, and this region is defined as region R. (Refer to...) Figure 2 and Figure 3 This will describe the connection state of region R.

[0046] Figure 2 It is used to describe implementations based on some example methods. Figure 1 A perspective view of region R of the tri-state inverter shown.

[0047] Reference Figure 2 The region R1 used for region R can be mainly composed of three layers on the third direction z.

[0048] The lowest layer on the third direction z includes a first PMOS transistor gate structure 200 and a first source / drain contact 100 constituting the second PMOS transistor P2. Furthermore, this lowest layer includes a first NMOS transistor gate structure 210 and a second source / drain contact 110 constituting the second NMOS transistor N2.

[0049] To electrically connect the first source / drain contact 100 to the second source / drain contact 110, a first-first-path V1_1 and a first-second-path V1_2 extending in the third direction z are provided in region R1. The first-first-path V1_1 and the first-second-path V1_2 are respectively connected to the first source / drain contact 100 and the second source / drain contact 110.

[0050] To electrically connect the first source / drain contact 100 to the second source / drain contact 110, a first metal line M1_1 and a second metal line M1_2 extending in the first direction x are disposed in region R1, in an intermediate height layer in the third direction z. The first metal line M1_1 and the first metal line M1_2 are respectively connected to the first path V1_1 and the first path V1_2.

[0051] To electrically connect the first source / drain contact 100 to the second source / drain contact 110, a second first path V2_1 and a second second path V2_2 extending in the third direction z are provided in region R1. The second first path V2_1 and the second second path V2_2 are respectively connected to the first first metal line M1_1 and the first second metal line M1_2.

[0052] To electrically connect the first source / drain contact 100 to the second source / drain contact 110, a second metal line M2 extending in the second direction y is disposed in region R1, in the highest layer in the third direction z. The second metal line M2 connects the second_first path V2_1 to the second_second path V2_2.

[0053] That is, region R1 for region R is formed by a total of three layers in the third direction z to allow the drain of the second PMOS transistor P2 to be connected to the drain of the second NMOS transistor N2.

[0054] Reference Figure 3 Describe the layout of region R1.

[0055] Figure 3 It is used to describe Figure 1 The diagram shows the layout of region R of the three-state inverter.

[0056] Reference Figure 3A first active region ACT1, defined by extending in the first direction x, is disposed in region R1. Furthermore, a second active region ACT2, defined by extending in the first direction x, is disposed in region R1. The first active region ACT1 may be a region in which a p-type transistor is formed. For example, the first active region ACT1 may include a well region doped with an n-type impurity. The second active region ACT2 may be a region in which an n-type transistor is formed. For example, the second active region ACT2 may include a well region doped with a p-type impurity. The first active region ACT1 and the second active region ACT2 may be spaced apart from each other in the second direction y.

[0057] The first PMOS transistor gate structure 200 can be disposed on the first active region ACT1 at its lowest height in the third direction z. The first source / drain contact 100 can be disposed spaced apart from the first PMOS transistor gate structure 200 in the first direction x. A first path V1_1 extending in the third direction z can be disposed on the first source / drain contact 100. A first metal line M1_1 extending in the first direction x can be disposed on the first path V1_1. A second path V2_1 extending in the third direction z is connected to the first metal line M1_1.

[0058] The first NMOS transistor gate structure 210 can be disposed on the second active region ACT2 at its lowest height in the third direction z. The second source / drain contact 110 can be disposed spaced apart from the first NMOS transistor gate structure 210 in the first direction x. The first and second paths V1_2 extending in the third direction z can be disposed on the second source / drain contact 110. The first and second metal lines M1_2 extending in the first direction x can be disposed on the first and second paths V1_2. The second and second paths V2_2 extending in the third direction z are connected to the first and second metal lines M1_2.

[0059] Next, by setting a second metal line M2 that extends in the second direction y and connects the second_first path V2_1 to the second_second path V2_2, the first source / drain contact 100 is electrically connected to the second source / drain contact 110.

[0060] As described in reference region R1 above, to connect multiple source / drain contacts, a structure with a height primarily of three layers in the third direction z is required. That is, as the layer height increases, the stability of the manufacturing process for the designed semiconductor integrated circuit may decrease. Furthermore, the degrees of freedom of the metal lines may decrease, and pin congestion may increase.

[0061] Therefore, in use as Figure 1In some example implementations of region R shown, multiple source / drain contacts can be connected while reducing the layer height, as will be shown below. Figure 4 and Figure 5 The same applies to the region R2 described.

[0062] Figure 4 It is used to describe implementations based on some example methods. Figure 1 A perspective view of region R of the tri-state inverter shown.

[0063] Reference Figure 4 The region R2 used for region R can mainly consist of two layers on the third direction z.

[0064] The lowest layer on the third direction z includes a first PMOS transistor gate structure 200 constituting the second PMOS transistor P2. Furthermore, this lowest layer includes a first NMOS transistor gate structure 210 constituting the second NMOS transistor N2.

[0065] Unlike region R1 described above, region R2, according to some example embodiments, connects the second PMOS transistor P2 to the second NMOS transistor N2 via a first source / drain contact 100. Therefore, a first path V1 extending in the third direction z is provided in region R2. A first metal line M1 extending in the first direction x is provided on the first path V1.

[0066] That is, region R2 for region R is formed by a total of two layers on the third direction z to allow the drain of the second PMOS transistor P2 to be connected to the drain of the second NMOS transistor N2.

[0067] Reference Figure 5 Describe the layout of region R2.

[0068] Figure 5 It is used to describe Figure 1 The diagram shows the layout of region R of the three-state inverter.

[0069] Reference Figure 5 A first active region ACT1, defined by extending in the first direction x, is disposed in region R2. Furthermore, a second active region ACT2, defined by extending in the first direction x, is disposed in region R2. The first active region ACT1 may be a region in which a p-type transistor is formed. For example, the first active region ACT1 may include a well region doped with an n-type impurity. The second active region ACT2 may be a region in which an n-type transistor is formed. For example, the second active region ACT2 may include a well region doped with a p-type impurity. The first active region ACT1 and the second active region ACT2 may be spaced apart from each other in the second direction y.

[0070] The first PMOS transistor gate structure 200 can be disposed on the first active region ACT1 at its lowest height in the third direction z. The first NMOS transistor gate structure 210 can be disposed on the second active region ACT2 at its lowest height in the third direction z. Subsequently, a first source / drain contact 100 is provided to connect the second PMOS transistor P2 to the second NMOS transistor N2 and extend in the second direction y. The first source / drain contact 100 can be configured to be spaced apart from the first PMOS transistor gate structure 200 and the first NMOS transistor gate structure 210 in the first direction x. A first path V1 extending in the third direction z is connected to the first source / drain contact 100. A first metal line M1 extending in the first direction x can be disposed on the first path V1 to electrically connect to the second PMOS transistor P2 and the second NMOS transistor N2.

[0071] As described in reference region R2 above, to connect multiple source / drain contacts, a structure with a height primarily of two layers in the third direction z is required. That is, due to the reduced layer height, the stability of the manufacturing process for the designed semiconductor integrated circuit can be improved. Furthermore, the degrees of freedom of the metal lines can be increased, and pin congestion can be reduced.

[0072] Of course, the circuit diagrams, layout diagrams and perspective views of the three-state inverters described above are not limited to those shown in the attached figures, and can be connected to each other in various ways.

[0073] The following will describe an integrated circuit according to some example embodiments, including the connection method of the aforementioned region R2.

[0074] Figure 6 It is a layout diagram of an integrated circuit according to some example implementations.

[0075] Reference Figure 6 The layout 2 of the integrated circuit, including some example embodiments, includes a power rail 10 configured to supply a power supply voltage and a ground rail 20 connected to a ground power supply.

[0076] Layout 2, according to some example embodiments, includes multiple units (e.g., first units C_1 to fourth units C_4). The number and / or configuration of the multiple units are not limited to those shown in this figure.

[0077] The first unit C_1 and the second unit C_2 are adjacent to each other and can be arranged between the power rail 10 and the ground rail 20. The third unit C_3 and the fourth unit C_4 are adjacent to each other and can be arranged between the power rail 10 and the ground rail 20.

[0078] Each of the first units C_1 to the fourth units C_4 may include an input circuit In, a master latch circuit M_L, a slave latch circuit S_L, an output circuit Out, and a clock generation circuit CLK_gen. That is, although each of the first units C_1 to the fourth units C_4 is shown as a master-slave flip-flop, the circuits constituting the first units C_1 to the fourth units C_4 are not limited to this.

[0079] Each unit can be supplied with power voltage via power rail 10 and grounded via ground rail 20.

[0080] In the following text, to avoid repetitive descriptions, a layout diagram of an integrated circuit according to some exemplary embodiments will be described in detail, using the master-slave flip-flop of the first unit C_1 as an example. Of course, the description of the first unit C_1 can also be applied to the remaining units (the second units C_2 to the fourth units C_4).

[0081] Figure 7 It is shown Figure 6 The block diagram of the first unit C_1 is shown. Figure 8 yes Figure 7 The circuit diagram is shown below. For reference and ease of description, only the input circuit In, the master latch circuit M_L, and the slave latch circuit S_L in the master-slave flip-flop of the first unit C_1 will be described as examples.

[0082] Reference Figure 7 and Figure 8 The master-slave flip-flop of the first unit C_1 of the integrated circuit, according to some example embodiments, may include a scan circuit S_C, a master latch M_L, and a slave latch S_L. For reference, the scan circuit S_C may represent... Figure 6 The input circuit In is shown.

[0083] The scanning circuit S_C may include a scan multiplexer SM. The scan multiplexer SM can receive the data signal D, the active scan signal Se, and the scan input signal Si, and can output either the data signal D or the scan input signal Si to the signal node SN according to the control signal.

[0084] More specifically, when the active scan signal Se is at a logic high (H) level, the scan multiplexer SM outputs the scan input signal Si to the signal node SN. On the other hand, when the active scan signal Se is at a logic low (L) level, the scan multiplexer SM can output the data signal D to the signal node SN.

[0085] More specifically, the scan multiplexer SM can be described as follows: Figure 9 The diagram shows multiple transmission gates, or as... Figure 28 and Figure 32The diagram includes a three-state inverter and a transmission gate.

[0086] In the following text, reference will be made to Figures 9 to 35 The description includes a scan multiplexer SM of an integrated circuit according to some example implementations.

[0087] Figure 9 It is shown Figure 8 The circuit diagram of the scanning circuit S_C is shown.

[0088] Reference Figure 9 The scanning circuit S_C(R3_1) includes a fourth inverter INV4 configured to receive and invert the data signal D, and a fifth inverter INV5 configured to receive and invert the scan input signal Si. Furthermore, the scanning circuit S_C(R3_1) includes a first transmission gate TG1 configured to transmit the inverted data signal D, and a second transmission gate TG2 configured to transmit the inverted scan input signal Si.

[0089] The third PMOS transistor P3 of the first transmission gate TG1 and the fourth NMOS transistor N4 of the second transmission gate TG2 share the first common node CN1 and can be selected by the scan active signal Se. Furthermore, the first transmission gate TG1 and the second transmission gate TG2 can output either the data signal D or the scan input signal Si through the signal node SN.

[0090] Here, the drains of each of the first PMOS transistor P1 and the first NMOS transistor N1 constituting the fourth inverter INV4, the drain of the third NMOS transistor N3 constituting the first transmission gate TG1, and the source of the third PMOS transistor P3 constituting the first transmission gate TG1 can be connected by a source / drain contact.

[0091] Furthermore, the drains of each of the second PMOS transistor P2 and the second NMOS transistor N2 constituting the fifth inverter INV5, the drain of the fourth NMOS transistor N4 constituting the second transmission gate TG2, and the source of the fourth PMOS transistor P4 constituting the second transmission gate TG2 can be connected by a source / drain contact.

[0092] In the following text, reference will be made to Figure 10 The layout diagram describes a structure in which multiple transistors are connected through a source / drain contact.

[0093] Figure 10 yes Figure 9 Layout diagram. Figures 11 to 13 Based on some example implementations Figure 9 The layout diagram. In the following text, to avoid repetition, only the layout diagram will be described. Figure 10 describe Figures 10 to 13The common parts will be described, and the differences will be briefly described with reference to the corresponding figures.

[0094] Reference Figure 10 The first PMOS transistor P1 to the fourth PMOS transistor P4 can be formed on the first active region ACT1 extending in the first direction x. In addition, the first NMOS transistor N1 to the fourth NMOS transistor N4 can be formed on the second active region ACT2, which extends in the first direction x and is configured to be spaced apart from the first active region ACT1 in the second direction y.

[0095] For reference, such as Figure 11 As shown, a first active fin (e.g., first fin F1 and second fin F2) protruding from the first active region ACT1 in the third active direction z can be formed on the first active region ACT1. Furthermore, a second active fin (e.g., third fin F3 and fourth fin F4) protruding from the second active region ACT2 in the third active direction z can be formed on the second active region ACT2. The first active fin (e.g., first fin F1 and second fin F2) and the second active fin (e.g., third fin F3 and fourth fin F4) can be arranged to be spaced apart from each other in the second direction y. Each of the first active fin (e.g., first fin F1 and second fin F2) and the second active fin (e.g., third fin F3 and fourth fin F4) can extend in the first direction x.

[0096] Refer again Figure 10 The power rail 10 can be disposed above the first active region ACT1 in the second direction y. Furthermore, the ground rail 20 can be disposed below the second active region ACT2 in the second direction y.

[0097] The first active region ACT1 and the second active region ACT2 can be spaced apart from each other by a fifth distance S5 in the second direction y, which intersects the first direction x. The first active region ACT1 and the power rail 10 can be spaced apart from each other by a first distance S1 in the second direction y, and the second active region ACT2 and the ground rail 20 can be spaced apart from each other by a fourth distance S4 in the second direction y.

[0098] The first distance S1 can be equal to the fourth distance S4. The sum of the first distance S1 and the fourth distance S4 can be greater than the fifth distance S5. The sum of the first distance S1 and the fourth distance S4 can be less than the fifth distance S5. The scan circuit S_C(R3_1a) of the integrated circuit according to some example embodiments can include a plurality of gate structures and a plurality of source / drain contacts extending in the second direction y and spaced apart from each other in the first direction x.

[0099] For example, the first source / drain contact 100 and the second source / drain contact 110 can be respectively disposed on the first active region ACT1 and the second active region ACT2, spaced apart from each other in the second direction y. That is, the first source / drain contact 100 can be connected to the power rail 10 through the first source / drain contact path VSD1 to supply the power supply voltage to the first PMOS transistor P1. In addition, the second source / drain contact 110 can be connected to the ground rail 20 through the third source / drain contact path VSD3 to ground the first NMOS transistor N1.

[0100] The first gate structure 200 is configured to be spaced apart from the first source / drain contact 100 and the second source / drain contact 110 in the first direction x. The first gate structure 200 may be disposed on the first active region ACT1 and the second active region ACT2.

[0101] The third source / drain contact 120 can be configured to be spaced apart from the first gate structure 200 in the first direction x. The third source / drain contact 120 can extend in the second direction y and can be disposed on the first active region ACT1 and the second active region ACT2. That is, the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 can be connected to each other through the third source / drain contact 120. In addition, the source of the third PMOS transistor P3 can be connected to the drain of the third NMOS transistor N3 through the third source / drain contact 120. That is, the drain of the first PMOS transistor P1, the drain of the first NMOS transistor N1, the source of the third PMOS transistor P3, and the drain of the third NMOS transistor N3 can be connected to each other through the third source / drain contact 120. By connecting multiple transistors via a single source / drain contact (e.g., the third source / drain contact 120), the height of the integrated circuit according to some example embodiments can be reduced.

[0102] Therefore, the stability of the process used to manufacture semiconductor integrated circuits, including those designed according to some example embodiments, can be improved. Furthermore, the degrees of freedom of metal lines can be increased, and pin congestion can be reduced.

[0103] The second gate structure 210 can be disposed on the first active region ACT1 and spaced apart from the third source / drain contact 120 in the first direction x. Furthermore, the third gate structure 220 can be disposed on the second active region ACT2 and spaced apart from the third source / drain contact 120 in the first direction x.

[0104] The fourth source / drain contact 130 can be configured to extend in the second direction y and be spaced apart from the second gate structure 210 and the third gate structure 220 in the first direction x. The drain of the third PMOS transistor P3 can be connected to the source of the third NMOS transistor N3 through the fourth source / drain contact 130. Furthermore, the drain of the fourth PMOS transistor P4 can be connected to the source of the fourth NMOS transistor N4 through the fourth source / drain contact 130. That is, the drain of the third PMOS transistor P3, the source of the third NMOS transistor N3, the drain of the fourth PMOS transistor P4, and the source of the fourth NMOS transistor N4 can be connected to each other through the fourth source / drain contact 130. By connecting multiple transistors via a single source / drain contact (e.g., the fourth source / drain contact 130), the height of the integrated circuit according to some example embodiments can be reduced.

[0105] Therefore, the stability of the process used to manufacture semiconductor integrated circuits, including those designed according to some example embodiments, can be improved. Furthermore, the degrees of freedom of metal lines can be increased, and pin congestion can be reduced.

[0106] The fourth gate structure 230 may be disposed on the first active region ACT1 and spaced apart from the fourth source / drain contact 130 in the first direction x. Furthermore, the fifth gate structure 240 may be disposed on the second active region ACT2 and spaced apart from the fourth source / drain contact 130 in the first direction x.

[0107] The fifth source / drain contact 140 can be configured to be spaced apart from the fourth gate structure 230 and the fifth gate structure 240 in the first direction x. The fifth source / drain contact 140 can extend in the second direction y and can be disposed on the first active region ACT1 and the second active region ACT2. That is, the source of the fourth PMOS transistor P4 and the drain of the fourth NMOS transistor N4 can be connected to each other through the fifth source / drain contact 140. Furthermore, the drain of the second PMOS transistor P2 can be connected to the drain of the second NMOS transistor N2 through the fifth source / drain contact 140. In other words, the source of the fourth PMOS transistor P4, the drain of the fourth NMOS transistor N4, the drain of the second PMOS transistor P2, and the drain of the second NMOS transistor N2 can be connected to each other through the fifth source / drain contact 140. By connecting multiple transistors via a single source / drain contact (e.g., the fifth source / drain contact 140), the height of the integrated circuit according to some example embodiments can be reduced.

[0108] Therefore, the stability of the process used to manufacture semiconductor integrated circuits, including those designed according to some example embodiments, can be improved. Furthermore, the degrees of freedom of metal lines can be increased, and pin congestion can be reduced.

[0109] A sixth gate structure 250 can be disposed on the first active region ACT1 and the second active region ACT2, spaced apart from the fifth source / drain contact 140 in the first direction x. Furthermore, a sixth source / drain contact 150 can be disposed on the first active region ACT1, spaced apart from the sixth gate structure 250 in the first direction x. The sixth source / drain contact 150 can be connected to the power rail 10 via the second source / drain contact path VSD2 to supply power voltage to the second PMOS transistor P2. Additionally, a seventh source / drain contact 160 can be disposed on the second active region ACT2, spaced apart from the sixth gate structure 250 in the first direction x. The seventh source / drain contact 160 can be connected to the ground rail 20 via the fourth source / drain contact path VSD4 to ground the second NMOS transistor N2.

[0110] Next, we will describe the structure and operation in which the signal is applied, as well as the structure extending to z from the third party.

[0111] A fifth gate contact GC5 extending in the z-direction can be disposed on the first gate structure 200. Furthermore, a first gate contact path VG1 extending in the z-direction can be disposed on the fifth gate contact GC5. The first gate contact path VG1 can be connected to a first metal line M1_1 extending in the x-direction. That is, the first gate structure 200 can be electrically connected to the first metal line M1_1, the first gate contact path VG1, and the fifth gate contact GC5 to receive the data signal D. Therefore, the first PMOS transistor P1 and the first NMOS transistor N1 can be selected by the data signal D.

[0112] The fifth gate contact GC5 and the first gate contact path VG1, which are electrically connected to the first gate structure 200, are shown in this figure as being disposed on the second active region ACT2, but are not limited thereto, and can be as follows: Figure 12 and Figure 13 The settings shown are on the first active region ACT1.

[0113] A first gate contact GC1 extending in the z-direction can be disposed on the second gate structure 210. Furthermore, a second gate contact path VG2 extending in the z-direction can be disposed on the first gate contact GC1. The second gate contact path VG2 can be connected to a first-second metal line M1_2 extending in the first direction x. The distance across the second direction y between the edge of the first active region ACT1 and the edge of the first-second metal line M1_2 is a second distance S2. That is, the second gate structure 210 can be electrically connected to the first-second metal line M1_2, the second gate contact path VG2, and the first gate contact GC1 to receive a scan active signal Se. Therefore, the third PMOS transistor P3 can be selected by the scan active signal Se.

[0114] The locations of the first gate contact GC1 and the second gate contact path VG2 electrically connected to the second gate structure 210 are not limited to this.

[0115] A third gate contact GC3 extending in the z-direction can be disposed on the third gate structure 220. Furthermore, a third gate contact path VG3 extending in the z-direction can be disposed on the third gate contact GC3. The third gate contact path VG3 can be connected to a first-third metal line M1_3 extending in the first direction x. The distance across the second direction y between the edge of the second active region ACT2 and the edge of the first-third metal line M1_3 is a third distance S3. That is, the third gate structure 220 can be electrically connected to the first-third metal line M1_3, the third gate contact path VG3, and the third gate contact GC3 to receive an inverted active signal. Therefore, the third NMOS transistor N3 can be activated by an inverted active signal. Selected.

[0116] The locations of the third gate contact GC3 and the third gate contact path VG3 electrically connected to the third gate structure 220 are not limited to this.

[0117] A second gate contact GC2 extending in the z-direction can be disposed on the fourth gate structure 230. Furthermore, a fourth gate contact path VG4 extending in the z-direction can be disposed on the second gate contact GC2. The fourth gate contact path VG4 can be electrically connected to a first-fifth metal line M1_5 extending in the first direction x. That is, the fourth gate structure 230 can be electrically connected to the first-fifth metal line M1_5, the fourth gate contact path VG4, and the second gate contact GC2 to receive an inverted active signal. Therefore, the fourth PMOS transistor P4 can be activated by an inverted active signal. Selected.

[0118] The locations of the second gate contact GC2 and the fourth gate contact path VG4 electrically connected to the fourth gate structure 230 are not limited to this.

[0119] A fourth gate contact GC4 extending in the z-direction can be disposed on the fifth gate structure 240. Furthermore, a fifth gate contact path VG5 extending in the z-direction can be disposed on the fourth gate contact GC4. The fifth gate contact path VG5 can be connected to a first-sixth metal line M1_6 extending in the first direction x. That is, the fifth gate structure 240 is electrically connected to the first-sixth metal line M1_6, the fifth gate contact path VG5, and the fourth gate contact GC4 to receive a scan active signal Se. Therefore, the fourth NMOS transistor N4 can be selected by the scan active signal Se.

[0120] The locations of the fourth gate contact GC4 and the fifth gate contact path VG5 electrically connected to the fifth gate structure 240 are not limited to this.

[0121] A sixth gate contact GC6 extending in the z-direction can be disposed on the sixth gate structure 250. Furthermore, a sixth gate contact path VG6 extending in the z-direction can be disposed on the sixth gate contact GC6. The sixth gate contact path VG6 can be connected to a first-seventh metal line M1_7 extending in the first direction x. That is, the sixth gate structure 250 can be electrically connected to the first-seventh metal line M1_7, the sixth gate contact path VG6, and the sixth gate contact GC6 to receive a scan input signal Si. Therefore, the second PMOS transistor P2 and the second NMOS transistor N2 can be selected by the scan input signal Si.

[0122] The sixth gate contact GC6 and the sixth gate contact path VG6, electrically connected to the sixth gate structure 250, are shown in this figure as being disposed on the first active region ACT1, but are not limited thereto, and can be as follows: Figure 12 and Figure 13 The settings shown are on the second active region ACT2.

[0123] The fifth source / drain contact path VSD5 extending in the z-direction can be disposed on the fourth source / drain contact 130. Furthermore, the first and fourth metal lines M1_4 extending in the x-direction can be disposed on the fifth source / drain contact path VSD5 and can be connected to an external source.

[0124] The fifth source / drain contact path VSD5, electrically connected to the fourth source / drain contact 130, is shown in this figure as being disposed on the first active region ACT1, but is not limited thereto, and can be as follows: Figure 13 The settings shown are on the second active region ACT2.

[0125] A plurality of gate structures (e.g., first gate structures 200 to sixth gate structures 250) and a plurality of source / drain contacts (e.g., first source / drain contacts 100 to seventh source / drain contacts 160) that are adjacent to each other in a first direction x can be spaced apart from each other by a contact-type polysilicon pitch (CPP). As an example, the first gate structure 200 and the first source / drain contact 100 that are adjacent to each other can be spaced apart from each other by 1 CPP.

[0126] For example, suppose the first gate structure 200 and the first source / drain contact 100 are adjacent to each other. When the distance between the center line of the first gate structure 200 extending in the second direction y and the center line of the first source / drain contact 100 extending in the second direction y is 1 CPP, this means that no other gate structure or source / drain contact is provided between the first gate structure 200 and the first source / drain contact 100.

[0127] Furthermore, metal lines that are adjacent to each other in the second direction y (e.g., first metal line M1_1 to first seventh metal line M1_7) can be spaced apart by 1 CPP. As an example, the first metal line M1_1 and the first third metal line M1_3 that are adjacent to each other can be spaced apart by 1 CPP.

[0128] For example, suppose the first metal wire M1_1 and the first third metal wire M1_3 are adjacent to each other. When the distance between the center line of the first metal wire M1_1 extending in the first direction x and the center line of the first third metal wire M1_3 extending in the first direction x is 1 CPP, this means that no other metal wire is set between the first metal wire M1_1 and the first third metal wire M1_3.

[0129] For reference, see Figure 11 The first gate structure 200 and the sixth gate structure 250 may surround the first active fin (e.g., the first fin F1 and the second fin F2) and the second active fin (e.g., the third fin F3 and the fourth fin F4). Furthermore, the second gate structure 210 and the fourth gate structure 230 may surround the first active fin (e.g., the first fin F1 and the second fin F2). Additionally, the third gate structure 220 and the fifth gate structure 240 may surround the second active fin (e.g., the third fin F3 and the fourth fin F4).

[0130] Figures 10 to 13 Each step in the layout diagram is divided into front-end process (FEOL), intermediate process (MOL), and back-end process (BEOL), and will refer to... Figures 14 to 17 A description will be provided. To avoid repetitive descriptions, refer to... Figure 10 The layout diagram is described.

[0131] Figure 14 It is shown Figure 10 The layout diagram of FEOL. Figure 15 This illustrates some example implementations. Figure 10 Another layout diagram of FEOL. Figure 16 It is shown Figure 10 The layout diagram of MOL. Figure 17 It is shown Figure 10 The layout diagram of BEOL.

[0132] Reference Figure 14 The first active region ACT1 and the second active region ACT2, which extend in the first direction x, are set to be spaced apart from each other in the second direction y.

[0133] The first active region ACT1 can be the region in which a p-type transistor is formed. For example, the first active region ACT1 can include a well region doped with an n-type impurity. The second active region ACT2 can be the region in which an n-type transistor is formed. For example, the second active region ACT2 can include a well region doped with a p-type impurity.

[0134] Although not shown in the accompanying drawings, a first active fin protruding from the first active region ACT1 in the third direction z can be formed on the first active region ACT1. Furthermore, a second active fin protruding from the second active region ACT2 in the third direction z can be formed on the second active region ACT2. The first and second active fins can be formed to be spaced apart from each other in the second direction y. Additionally, each of the first and second active fins can extend in the first direction x.

[0135] Reference Figure 15 The active regions in multiple elements (e.g., element 1a C1a, element 1b C1b, and element 1c C1c) can have different thicknesses in the second direction y.

[0136] For example, the first active region ACT1a of the first unit C1a can be formed from the boundary A1 of the first unit C1a to the boundary A4 of the first unit C1a, and is spaced apart from the second active region ACT2a. Similarly, the second active region ACT2a of the first unit C1a can be formed from the boundary B1 of the first unit C1a to the boundary B4 of the first unit C1a, and is spaced apart from the first active region ACT1a. That is, the first active region ACT1a and the second active region ACT2a can be set to be spaced apart from each other by a first length D1 in the second direction y.

[0137] The first active region ACT1b of the first b unit C1b adjacent to the first b unit C1a can be formed from the boundary A1 of the first b unit C1b to the boundary A3 of the first b unit C1b, and is spaced apart from the second active region ACT2b. Similarly, the second active region ACT2b of the first b unit C1b can be formed from the boundary B1 of the first b unit C1b to the boundary B3 of the first b unit C1b, and is spaced apart from the first active region ACT1b. That is, the first active region ACT1b and the second active region ACT2b can be set to be spaced apart from each other by a second length D2 in the second direction y.

[0138] The first active region ACT1c of the first c unit C1c, adjacent to the first b unit C1b, can be formed from boundary A1 to boundary A2 of the first c unit C1c, and is spaced apart from the second active region ACT2c. Similarly, the second active region ACT2c of the first c unit C1c can be formed from boundary B1 to boundary B2 of the first c unit C1c, and is spaced apart from the first active region ACT1c. That is, the first active region ACT1c and the second active region ACT2c can be set to be spaced apart from each other by a third length D3 in the second direction y.

[0139] The shape and arrangement of the active regions in the continuous cells are not limited to those shown in this figure.

[0140] Reference Figure 16 Multiple source / drain contacts (e.g., first source / drain contacts 100 to seventh source / drain contacts 160) and multiple gate structures (e.g., first gate structure 200 to sixth gate structure 250) may be configured to be spaced apart from each other in a first direction x. Each of the multiple source / drain contacts (e.g., first source / drain contacts 100 to seventh source / drain contacts 160) and multiple gate structures (e.g., first gate structure 200 to sixth gate structure 250) may extend in a second direction y.

[0141] A plurality of gate structures (e.g., first gate structures 200 to sixth gate structures 250) and a plurality of source / drain contacts (e.g., first source / drain contacts 100 to seventh source / drain contacts 160) that are adjacent to each other in the first direction x can be spaced apart from each other by 1 CPP. As an example, the first gate structure 200 and the first source / drain contact 100 that are adjacent to each other can be spaced apart from each other by 1 CPP.

[0142] For example, suppose the first gate structure 200 and the first source / drain contact 100 are adjacent to each other. When the distance between the center line of the first gate structure 200 extending in the second direction y and the center line of the first source / drain contact 100 extending in the second direction y is 1 CPP, this means that no other gate structure or source / drain contact is provided between the first gate structure 200 and the first source / drain contact 100.

[0143] Reference Figure 17 Multiple metal wires (e.g., first metal wire M1_1 to first seventh metal wire M1_7), power rail 10, and ground rail 20 can be configured to be spaced apart from each other in the second direction y. Each of the multiple metal wires (e.g., first metal wire M1_1 to first seventh metal wire M1_7), power rail 10, and ground rail 20 can extend in the first direction x.

[0144] The first source / drain contact path VSD1 and the second source / drain contact path VSD2, used to transmit the power supply voltage to the source / drain contact, can be provided on the power rail 10. Furthermore, the third source / drain contact path VSD3 and the fourth source / drain contact path VSD4, used to ground the source / drain contact, can be provided on the ground rail 20.

[0145] The first metal line M1_1, the first second metal line M1_2, the first third metal line M1_3, the first fifth metal line M1_5, the first sixth metal line M1_6, and the first seventh metal line M1_7 can be respectively connected to a plurality of gate contacts (e.g., first gate contact GC1 to sixth gate contact GC6) for a gate selection structure and a plurality of gate contact paths (e.g., first gate contact path VG1 to sixth gate contact path VG6) disposed in the plurality of gate contacts. The plurality of gate contacts (e.g., first gate contact GC1 to sixth gate contact GC6) and the plurality of gate contact paths (e.g., first gate contact path VG1 to sixth gate contact path VG6) can extend in a third direction z.

[0146] Metal lines that are adjacent to each other in the second direction y (e.g., first metal line M1_1 to first seventh metal line M1_7) can be spaced apart by 1 CPP. As an example, the first metal line M1_1 and the first third metal line M1_3 that are adjacent to each other can be spaced apart by 1 CPP.

[0147] For example, suppose the first metal wire M1_1 and the first third metal wire M1_3 are adjacent to each other. When the distance between the center line of the first metal wire M1_1 extending in the first direction x and the center line of the first third metal wire M1_3 extending in the first direction x is 1 CPP, this means that no other metal wire is set between the first metal wire M1_1 and the first third metal wire M1_3.

[0148] Reference Figures 18 to 23 describe Figures 10 to 13 A cross-sectional view of the layout diagram. To avoid repetition, refer to... Figure 10 The layout diagram is described.

[0149] Figure 18 and Figure 19 It is along Figure 10 A cross-sectional view taken from line A-A'. Figure 20 and Figure 21 It is along Figure 10 The cross-sectional view taken by line B-B'. Figure 22 and Figure 23 It is along Figure 10 A cross-sectional view taken from line C-C'.

[0150] Reference Figure 18 Semiconductor integrated circuits, including those according to some example embodiments, can have a fin field-effect transistor (FinFET) structure that includes a channel region with a fin pattern shape.

[0151] According to some example embodiments, a fin field-effect transistor can be formed on a substrate Sub and on an active region (e.g., a first active region ACT1) disposed on the substrate Sub.

[0152] The substrate Sub may be a silicon substrate or silicon-on-insulator (SOI). Alternatively, the substrate Sub may include silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide and / or gallium antimonide, but this disclosure is not limited thereto.

[0153] The first active region ACT1 may be defined along a first direction x. The first active region ACT1 may be defined by a deep trench. The first active region ACT1 may be a region in which a p-type transistor is formed. For example, the first active region ACT1 may include a well region doped with n-type impurities. The first active region ACT1 may protrude from the substrate Sub. The first active region ACT1 may include an epitaxial layer grown from the substrate Sub.

[0154] According to some example embodiments, a fin field-effect transistor includes multiple gate structures (e.g., a first gate structure 200, a second gate structure 210, a fourth gate structure 230, and a sixth gate structure 250), a source / drain region 300, a silicide layer 310, a first interlayer insulating film 400, and a second interlayer insulating film 500.

[0155] Each of the plurality of gate structures (e.g., first gate structure 200, second gate structure 210, fourth gate structure 230 and sixth gate structure 250) may include a gate spacer 202, a gate insulating film 204, a gate electrode 206 and a cap pattern 208.

[0156] The structure of each of the multiple gate structures is not limited to the structure shown in this figure.

[0157] Multiple gate structures (e.g., first gate structure 200, second gate structure 210, fourth gate structure 230 and sixth gate structure 250) and source / drain regions 300 may extend in the second direction y on the first active region ACT1.

[0158] The gate spacer 202 may extend along the two sidewalls of the gate insulating film 204 in the third z-direction. The gate insulating film 204 may be disposed between the gate electrode 206 and the gate spacer 202 and below the cap pattern 208. The cap pattern 208 may be disposed on each of the gate electrode 206 and the gate insulating film 204. The gate spacer 202, the gate insulating film 204, and the cap pattern 208 may include insulating material.

[0159] The source / drain region 300 can be formed by removing a portion of the first active region ACT1 to form a depression, and then filling the depression by an epitaxial process. The source / drain region 300 can be formed on the first active region ACT1. The source / drain region 300 can be doped with impurities of a different conductivity type than the semiconductor material forming the first active region ACT1.

[0160] According to some exemplary embodiments, the fin field-effect transistor also includes multiple gate contacts (e.g., first gate contact GC1 and second gate contact GC2), multiple gate contact paths (e.g., second gate contact path VG2 and fourth gate contact path VG4), multiple source / drain contacts (e.g., first source / drain contact 100, third source / drain contact 120, fifth source / drain contact 140 and sixth source / drain contact 150), a third interlayer insulating film 600, a fourth interlayer insulating film 700, and multiple metal lines (e.g., first-second metal line M1_2 and first-fifth metal line M1_5) for receiving electrical signals.

[0161] The silicide layer 310 may be disposed between the source / drain region 300 and each of the plurality of source / drain contacts (e.g., the first source / drain contact 100, the third source / drain contact 120, the fifth source / drain contact 140, and the sixth source / drain contact 150).

[0162] Multiple source / drain contacts (e.g., first source / drain contact 100, third source / drain contact 120, fifth source / drain contact 140, and sixth source / drain contact 150) and source / drain regions 300 can be electrically connected to each other through a silicide layer 310. Each of the multiple source / drain contacts (e.g., first source / drain contact 100, third source / drain contact 120, fifth source / drain contact 140, and sixth source / drain contact 150) can be formed in a third direction z and can extend in a second direction y.

[0163] Multiple gate contacts (e.g., first gate contact GC1 and second gate contact GC2) can be electrically connected to gate structures (e.g., second gate structure 210 and fourth gate structure 230), respectively. Multiple gate contact paths (e.g., second gate contact path VG2 and fourth gate contact path VG4) can be electrically connected to multiple gate contacts (e.g., first gate contact GC1 and second gate contact GC2), respectively. Multiple gate contact paths (e.g., second gate contact path VG2 and fourth gate contact path VG4) can be electrically connected to metal lines (e.g., first-second metal line M1_2 and first-fifth metal line M1_5), respectively.

[0164] The first interlayer insulating film 400 may surround multiple gate structures (e.g., first gate structure 200, second gate structure 210, fourth gate structure 230 and sixth gate structure 250) and multiple source / drain contacts (e.g., first source / drain contact 100, third source / drain contact 120, fifth source / drain contact 140 and sixth source / drain contact 150).

[0165] The second interlayer insulating film 500 can be formed on the first interlayer insulating film 400. The second interlayer insulating film 500 can surround a plurality of source / drain contacts (e.g., first source / drain contact 100, third source / drain contact 120, fifth source / drain contact 140 and sixth source / drain contact 150).

[0166] The third interlayer insulating film 600 can be formed on the second interlayer insulating film 500. The third interlayer insulating film 600 can surround multiple gate contact paths (e.g., the second gate contact path VG2 and the fourth gate contact path VG4).

[0167] The fourth interlayer insulating film 700 can be formed on the third interlayer insulating film 600. The fourth interlayer insulating film 700 can surround the metal wires (e.g., the first and second metal wires M1_2 and the first and fifth metal wires M1_5).

[0168] The first interlayer insulating film 400 to the fourth interlayer insulating film 700 may include insulating materials.

[0169] Reference Figure 19 Semiconductor integrated circuits, including those according to some example embodiments, can have a multi-bridge channel field-effect transistor (MBCFET) structure comprising multiple nanowires. (The remaining text will be omitted.) Figure 18 The description is repetitive, and it will focus primarily on the differences.

[0170] The first nanowire 201, the second nanowire 203, and the third nanowire 205 can be sequentially arranged to be spaced apart from each other on the substrate Sub or the first active region ACT1 in the third direction z. The first nanowire 201 to the third nanowire 205 can extend in the first direction x.

[0171] The gate electrode 206, the gate insulating film 204 surrounding the gate electrode 206, and the gate spacer 202 formed on the sidewall of the gate insulating film 204 may surround each of the first nanowires 201 to the third nanowires 205.

[0172] The gate spacer 202 is shown as being formed of a single layer, but this disclosure is not limited thereto. That is, in some example embodiments, the gate spacer 202 may be formed of multiple films.

[0173] The gate insulating film 204 can be disposed between the gate electrode 206 and the gate spacer 202, between the gate electrode 206 and the third nanowire 205, between the gate electrode 206 and the second nanowire 203, between the gate electrode 206 and the first nanowire 201, and between the gate electrode 206 and the first active region ACT1.

[0174] The source / drain region 300 may be disposed on at least one side of each of the first nanowires 201 to the third nanowires 205. Furthermore, the source / drain region 300 may be in contact with each of the first nanowires 201 to the third nanowires 205.

[0175] Reference Figure 20 Multiple source / drain regions 300 and 302 can be formed on the first active region ACT1 and the second active region ACT2 disposed on the substrate Sub, respectively. Descriptions that are repeated above will be omitted.

[0176] At least a portion of the plurality of source / drain regions 300 and 302 may be included in the source / drain regions of the plurality of transistors. The source / drain region 300 formed on the first active region ACT1 and the source / drain region 302 formed on the second active region ACT2 may be doped with impurities of different conductivity types.

[0177] A cell isolation film 350 may be formed on a substrate Sub. The cell isolation film 350 may fill a deep trench separating a first active region ACT1 and a second active region ACT2. The cell isolation film 350 may extend in a first direction x. The cell isolation film 350 may include an insulating material.

[0178] The source / drain contact dicing pattern 410 can be disposed on the cell isolation membrane 350. The source / drain contact dicing pattern 410 can extend in a first direction x. The source / drain contact dicing pattern 410 may include insulating material.

[0179] The source / drain contact cut pattern 410 can cut the source / drain contact at the boundary of the cell. The source / drain contact cut pattern 410 can contact the source / drain contact (e.g., the first source / drain contact 100 and the second source / drain contact 110).

[0180] First source / drain upper contact 102 is formed on first source / drain contact 100, and the first source / drain upper contact 102 and the first source / drain contact 100 can fill the trench defined by silicide layer 310.

[0181] Similarly, a second source / drain contact 112 is formed on the second source / drain contact 110, and the second source / drain contact 112 and the second source / drain contact 110 can fill the trench defined by the silicide layer 312.

[0182] The second interlayer insulating film 500 is disposed between the first source / drain contact 102, the first source / drain contact 100, the second source / drain contact 112, and the second source / drain contact 110. The second interlayer insulating film 500 may be disposed on the first interlayer insulating film 400.

[0183] The first source / drain contact path VSD1 can be set on the first source / drain contact 102. In addition, the third source / drain contact path VSD3 can be set on the second source / drain contact 112.

[0184] The power rail 10 can be set on the first source / drain contact path VSD1, and the ground rail 20 can be set on the third source / drain contact path VSD3.

[0185] The third interlayer insulating film 600 can be disposed on the second interlayer insulating film 500, and the fourth interlayer insulating film 700 can be disposed on the third interlayer insulating film 600.

[0186] Reference Figure 21 The main description is related to Figure 20 The differences. Figure 21 In, with Figure 20 Unlike other methods, silicide layers 310 and 312 can be formed only between source / drain regions 300 and 302. That is, silicide layer 310 may not be formed on the outer wall of each of the first source / drain contact 100 and the first source / drain contact 102 in the second direction y. Furthermore, silicide layer 312 may not be formed on the outer wall of each of the second source / drain contact 110 and the second source / drain contact 112 in the second direction y.

[0187] Reference Figure 22 Semiconductor integrated circuits, including those according to some example embodiments, can have a fin field-effect transistor (FinFET) structure that includes a channel region with a fin pattern shape. In the following text, terms related to... Figure 18 Repeated description.

[0188] According to some exemplary embodiments, a fin field-effect transistor can be formed on a substrate Sub and on an active region (e.g., a first active region ACT1 and a second active region ACT2) disposed on the substrate Sub.

[0189] A first active upper region ACT1_U can be formed on the first active region ACT1. Furthermore, a second active upper region ACT2_U can be formed on the second active region ACT2. A gate insulating film 204 can be formed along the first active upper region ACT1_U and the second active upper region ACT2_U. Additionally, the gate insulating film 204 can also be formed in the region where the gate electrode 206 is connected to the cell isolation film 350.

[0190] The gate electrode 206 can be formed on the gate insulating film 204. The gate electrode 206 can be cut by the gate dicing pattern 404 and the gate dicing pattern spacers 402 formed on the sidewalls of the gate dicing pattern 404. Furthermore, the cap pattern 208 on the gate electrode 206 can also be cut by the gate dicing pattern 404 and the gate dicing pattern spacers 402 formed on the sidewalls of the gate dicing pattern 404. The gate dicing pattern 404 and the gate dicing pattern spacers 402 can include insulating material.

[0191] The second gate contact GC2 and the third gate contact GC3 can be electrically connected to the gate electrode 206 through the cover pattern 208. The fourth gate contact path VG4 and the fifth gate contact path VG5 can be electrically connected to the second gate contact GC2 and the third gate contact GC3, respectively. The first and fifth metal lines M1_5 are disposed on the fourth gate contact path VG4, so that the inverted scan active signal It can be applied to the gate electrode 206 disposed on the first active region ACT1. In addition, the first-sixth metal line M1-6 is disposed on the fifth gate contact path VG5, so that the scan active signal Se can be applied to the gate electrode 206 disposed on the second active region ACT2.

[0192] The second interlayer insulating film 500 is formed on the cover pattern 208, the gate dicing pattern 404 and the gate dicing pattern spacer 402, the third interlayer insulating film 600 is formed on the second interlayer insulating film 500, and the fourth interlayer insulating film 700 is formed on the third interlayer insulating film 600.

[0193] Reference Figure 23 Semiconductor integrated circuits, including those according to some example embodiments, can have an MBCFET structure comprising multiple nanowires. The description will focus primarily on... Figure 22 On the differences.

[0194] exist Figure 23 In, with Figure 22 Unlike other regions, the first nanowire 201 to the third nanowire 205 can be included on each of the first active upper region ACT1_U and the second active upper region ACT2_U. Each nanowire is surrounded by a gate electrode 206 and a gate insulating film 204.

[0195] Reference Figures 24 to 27 Describes magnified top views from the top when the source / drain contacts are cut and magnified top views from the top when the gate structure is cut.

[0196] Figure 24 and Figure 25 It is used to describe Figure 10 A magnified view of the SDTR region shown. Figure 26 and Figure 27 It is used to describe Figure 10 A magnified view of the GTR region shown.

[0197] Reference Figure 24 The region SDTRa of the region SDTR is shown, in which the previously cut first source / drain contact 100 and sixth source / drain contact 150 are set on the layout diagram.

[0198] The cut portions of the first source / drain contact 100 and the sixth source / drain contact 150 may have a raised shape. The cut portion of each of the first source / drain contact 100 and the sixth source / drain contact 150 may be its end in the second direction y.

[0199] On the other hand, refer to Figure 25 The diagram shows a cross-sectional view where the first source / drain contact 100 and the sixth source / drain contact 150 are cut across both the first active region ACT1 and the second active region ACT2 along the y-direction. That is, the region SDTRb of the region SDTR is shown.

[0200] The cut portions of the first source / drain contact 100 and the sixth source / drain contact 150 may have a concave shape. The cut portion of each of the first source / drain contact 100 and the sixth source / drain contact 150 may be its end in the second direction y.

[0201] Reference Figure 26 The region GTR is shown as the region GTR, where the previously cut second gate structure 210 and third gate structure 220 are arranged on the layout diagram.

[0202] The cut portions of the second gate structure 210 and the third gate structure 220 facing each other have a raised shape. The cut portions of the second gate structure 210 and the third gate structure 220 facing each other can be the ends of the second gate structure 210 and the third gate structure 220, respectively.

[0203] On the other hand, refer to Figure 27 The diagram shows a cross-sectional view where the second gate structure 210 and the third gate structure 220 are cut after being continuously formed along the second direction y across both the first active region ACT1 and the second active region ACT2. That is, region GTRb of region GTR is shown.

[0204] The cut portions of the second gate structure 210 and the third gate structure 220 may have a recessed shape. The cut portions of the second gate structure 210 and the third gate structure 220 facing each other may be the ends of the second gate structure 210 and the third gate structure 220, respectively. The second gate structure 210 and the third gate structure 220, which are continuously formed in the second direction y, spanning both the first active region ACT1 and the second active region ACT2, can be formed by cutting, as if stamping with a press.

[0205] Figure 28 It is shown Figure 8 The circuit diagram of the scanning circuit S_C is shown.

[0206] Reference Figure 28,and Figure 9 The scanning circuit S_C(R3_1) shown is different; the circuit that receives the data signal D can be configured as the first tri-state inverter TRI1.

[0207] That is, the scanning circuit S_C(R3_2) of the integrated circuit according to some example embodiments can be inverted and output a data signal D under the control of the scanning active signal. The description of the tri-state inverter is as follows... Figure 1 The description is repeated, so it will be omitted.

[0208] Figures 29 to 31 The layout diagrams are illustrated exemplary based on some example implementation methods. Figure 28 In the following text, to avoid repetition, only through... Figure 29 describe Figures 29 to 31 The common parts will be described briefly with reference to the corresponding figures.

[0209] Reference Figure 29 The first PMOS transistor P1 to the fourth PMOS transistor P4 can be formed on the first active region ACT1 extending in the first direction x. Furthermore, the first NMOS transistor N1 to the fourth NMOS transistor N4 can be formed on the second active region ACT2 extending in the first direction x and spaced apart from the first active region ACT1 in the second direction y.

[0210] The power rail 10 can be disposed above the first active region ACT1 in the second direction y. Furthermore, the ground rail 20 can be disposed below the second active region ACT2 in the second direction y.

[0211] The scan circuit S_C(R3_2a) of an integrated circuit according to some example embodiments may include a plurality of gate structures and a plurality of source / drain contacts that extend in a second direction y and are spaced apart from each other in a first direction x.

[0212] For example, the first source / drain contact 100 and the second source / drain contact 110 can be respectively disposed on the first active region ACT1 and the second active region ACT2, spaced apart from each other in the second direction y. That is, the first source / drain contact 100 can be connected to the power rail 10 through the first source / drain contact path VSD1 to supply the power supply voltage to the first PMOS transistor P1. In addition, the second source / drain contact 110 can be connected to the ground rail 20 through the third source / drain contact path VSD3 to ground the first NMOS transistor N1.

[0213] The first gate structure 200 is configured to be spaced apart from the first source / drain contact 100 and the second source / drain contact 110 in the first direction x. The first gate structure 200 may be disposed on the first active region ACT1 and the second active region ACT2.

[0214] The third source / drain contact 120 and the fourth source / drain contact 130 can be respectively disposed on the first active region ACT1 and the second active region ACT2, spaced apart from each other in the second direction y and spaced apart from the first gate structure 200 in the first direction x.

[0215] The second gate structure 210 can be disposed on the first active region ACT1 and spaced apart from the third source / drain contact 120 and the fourth source / drain contact 130 in the first direction x. Furthermore, the third gate structure 220 can be disposed on the second active region ACT2 and spaced apart from the third source / drain contact 120 and the fourth source / drain contact 130 in the first direction x.

[0216] The fifth source / drain contact 140 can be configured to extend in the second direction y and be spaced apart from the second gate structure 210 and the third gate structure 220 in the first direction x. The drain of the third PMOS transistor P3 can be connected to the drain of the third NMOS transistor N3 through the fifth source / drain contact 140. Furthermore, the drain of the fourth PMOS transistor P4 can be connected to the source of the fourth NMOS transistor N4 through the fifth source / drain contact 140. That is, the drains of the third PMOS transistor P3, the third NMOS transistor N3, the fourth PMOS transistor P4, and the source of the fourth NMOS transistor N4 can be connected to each other through the fifth source / drain contact 140. By connecting multiple transistors via a single source / drain contact (e.g., the fifth source / drain contact 140), the height of the integrated circuit according to some example embodiments can be reduced.

[0217] Therefore, the stability of the process used to manufacture semiconductor integrated circuits, including those designed according to some example embodiments, can be improved. Furthermore, the degrees of freedom of metal lines can be increased, and pin congestion can be reduced.

[0218] The fourth gate structure 230 may be disposed on the first active region ACT1 and spaced apart from the fifth source / drain contact 140 in the first direction x. Furthermore, the fifth gate structure 240 may be disposed on the second active region ACT2 and spaced apart from the fifth source / drain contact 140 in the first direction x.

[0219] The sixth source / drain contact 150 can be configured to be spaced apart from the fourth gate structure 230 and the fifth gate structure 240 in the first direction x. The sixth source / drain contact 150 can extend in the second direction y and can be disposed on the first active region ACT1 and the second active region ACT2. That is, the source of the fourth PMOS transistor P4 and the drain of the fourth NMOS transistor N4 can be connected to each other through the sixth source / drain contact 150. In addition, the drain of the second PMOS transistor P2 can be connected to the drain of the second NMOS transistor N2 through the sixth source / drain contact 150. That is, the source of the fourth PMOS transistor P4, the drain of the fourth NMOS transistor N4, the drain of the second PMOS transistor P2, and the drain of the second NMOS transistor N2 can be connected to each other through the sixth source / drain contact 150. By connecting multiple transistors via a single source / drain contact (e.g., the sixth source / drain contact 150), the height of the integrated circuit according to some example embodiments can be reduced.

[0220] Therefore, the stability of the process used to manufacture semiconductor integrated circuits, including those designed according to some example embodiments, can be improved. Furthermore, the degrees of freedom of metal lines can be increased, and pin congestion can be reduced.

[0221] A sixth gate structure 250 can be disposed on the first active region ACT1 and the second active region ACT2, spaced apart from the sixth source / drain contact 150 in the first direction x. Furthermore, a seventh source / drain contact 160 can be disposed on the first active region ACT1, spaced apart from the sixth gate structure 250 in the first direction x. The seventh source / drain contact 160 can be connected to the power rail 10 via the second source / drain contact path VSD2 to supply power voltage to the second PMOS transistor P2. Furthermore, an eighth source / drain contact 170 can be disposed on the second active region ACT2, spaced apart from the sixth gate structure 250 in the first direction x. The eighth source / drain contact 170 can be connected to the ground rail 20 via the fourth source / drain contact path VSD4 to ground the second NMOS transistor N2.

[0222] Next, we will describe the structure and operation to which the signal is applied, as well as the structure extending to z from the third party.

[0223] A fifth gate contact GC5 extending in the z-direction can be disposed on the first gate structure 200. Furthermore, a first gate contact path VG1 extending in the z-direction can be disposed on the fifth gate contact GC5. The first gate contact path VG1 can be connected to a first metal line M1_1 extending in the x-direction. That is, the first gate structure 200 can be electrically connected to the first metal line M1_1, the first gate contact path VG1, and the fifth gate contact GC5 to receive the data signal D. Therefore, the first PMOS transistor P1 and the first NMOS transistor N1 can be selected by the data signal D.

[0224] The fifth gate contact GC5 and the first gate contact path VG1, which are electrically connected to the first gate structure 200, are shown in this figure as being disposed on the second active region ACT2, but are not limited thereto, and can be as follows: Figure 30 and Figure 31 The settings shown are on the first active region ACT1.

[0225] A first gate contact GC1 extending in the z-direction can be disposed on the second gate structure 210. Furthermore, a second gate contact path VG2 extending in the z-direction can be disposed on the first gate contact GC1. The second gate contact path VG2 can be connected to a first / second metal line M1_2 extending in the x-direction. That is, the second gate structure 210 can be electrically connected to the first / second metal line M1_2, the second gate contact path VG2, and the first gate contact GC1 to receive a scan active signal Se. Therefore, the third PMOS transistor P3 can be selected by the scan active signal Se.

[0226] The locations of the first gate contact GC1 and the second gate contact path VG2 electrically connected to the second gate structure 210 are not limited to this.

[0227] A third gate contact GC3 extending in the z-direction can be disposed on the third gate structure 220. Furthermore, a third gate contact path VG3 extending in the z-direction can be disposed on the third gate contact GC3. The third gate contact path VG3 can be connected to a first-third metal line M1_3 extending in the first direction x. That is, the third gate structure 220 can be electrically connected to the first-third metal line M1_3, the third gate contact path VG3, and the third gate contact GC3 to receive an inverted active signal. Therefore, the third NMOS transistor N3 can be activated by an inverted active signal. Selected.

[0228] The locations of the third gate contact GC3 and the third gate contact path VG3 electrically connected to the third gate structure 220 are not limited to this.

[0229] A second gate contact GC2 extending in the z-direction can be disposed on the fourth gate structure 230. Furthermore, a fourth gate contact path VG4 extending in the z-direction can be disposed on the second gate contact GC2. The fourth gate contact path VG4 can be connected to a first-fifth metal line M1_5 extending in the first direction x. That is, the fourth gate structure 230 can be electrically connected to the first-fifth metal line M1_5, the fourth gate contact path VG4, and the second gate contact GC2 to receive an inverted active signal. Therefore, the fourth PMOS transistor P4 can be activated by an inverted active signal. Selected.

[0230] The locations of the second gate contact GC2 and the fourth gate contact path VG4 electrically connected to the fourth gate structure 230 are not limited to this.

[0231] A fourth gate contact GC4 extending in the z-direction can be disposed on the fifth gate structure 240. Furthermore, a fifth gate contact path VG5 extending in the z-direction can be disposed on the fourth gate contact GC4. The fifth gate contact path VG5 can be connected to a first-sixth metal line M1_6 extending in the first direction x. That is, the fifth gate structure 240 is electrically connected to the first-sixth metal line M1_6, the fifth gate contact path VG5, and the fourth gate contact GC4 to receive a scan active signal Se. Therefore, the fourth NMOS transistor N4 can be selected by the scan active signal Se.

[0232] The locations of the fourth gate contact GC4 and the fifth gate contact path VG5 electrically connected to the fifth gate structure 240 are not limited to this.

[0233] A sixth gate contact GC6 extending in the z-direction can be disposed on the sixth gate structure 250. Furthermore, a sixth gate contact path VG6 extending in the z-direction can be disposed on the sixth gate contact GC6. The sixth gate contact path VG6 can be connected to a first-seventh metal line M1_7 extending in the first direction x. That is, the sixth gate structure 250 can be electrically connected to the first-seventh metal line M1_7, the sixth gate contact path VG6, and the sixth gate contact GC6 to receive a scan input signal Si. Therefore, the second PMOS transistor P2 and the second NMOS transistor N2 can be selected by the scan input signal Si.

[0234] The sixth gate contact GC6 and the sixth gate contact path VG6, electrically connected to the sixth gate structure 250, are shown in this figure as being disposed on the first active region ACT1, but are not limited thereto, and can be as follows: Figure 30 and Figure 31 The settings shown are on the second active region ACT2.

[0235] A fifth source / drain contact path VSD5 extending in the z-direction can be disposed on the fifth source / drain contact 140. Furthermore, a first / fourth metal line M1_4 extending in the x-direction can be disposed on the fifth source / drain contact path VSD5 and can be connected to an external source.

[0236] The fifth source / drain contact path VSD5, electrically connected to the fifth source / drain contact 140, is shown in this figure as being disposed on the first active region ACT1, but is not limited thereto, and can be as follows: Figure 31 The settings shown are on the second active region ACT2.

[0237] A plurality of gate structures (e.g., first gate structures 200 to sixth gate structures 250) and a plurality of source / drain contacts (e.g., first source / drain contacts 100 to eighth source / drain contacts 170) that are adjacent to each other in the first direction x can be spaced apart from each other by 1 CPP. As an example, the first gate structure 200 and the first source / drain contact 100 that are adjacent to each other can be spaced apart from each other by 1 CPP.

[0238] For example, suppose the first gate structure 200 and the first source / drain contact 100 are adjacent to each other. When the distance between the center line of the first gate structure 200 extending in the second direction y and the center line of the first source / drain contact 100 extending in the second direction y is 1 CPP, this means that no other gate structure or source / drain contact is provided between the first gate structure 200 and the first source / drain contact 100.

[0239] Furthermore, metal lines that are adjacent to each other in the second direction y (e.g., first metal line M1_1 to first seventh metal line M1_7) can be spaced apart by 1 CPP. As an example, the first metal line M1_1 and the first second metal line M1_2 that are adjacent to each other can be spaced apart by 1 CPP.

[0240] For example, suppose the first metal wire M1_1 and the first metal wire M1_2 are adjacent to each other. When the distance between the center line of the first metal wire M1_1 extending in the first direction x and the center line of the first metal wire M1_2 extending in the first direction x is 1 CPP, this means that no other metal wire is set between the first metal wire M1_1 and the first metal wire M1_2.

[0241] Figure 32 It is shown Figure 8 The circuit diagram of the scanning circuit S_C is shown.

[0242] Reference Figure 32 ,and Figure 9 The scanning circuit S_C(R3_1) shown is different; the circuit that receives the scanning input signal Si can be configured as a second tri-state inverter TRI2.

[0243] That is, the scanning circuit S_C(R3_3) of the integrated circuit according to some example embodiments can be inverted and output the scanning input signal Si under the control of the scanning active signal. The description of the tri-state inverter is as follows... Figure 1 The description is repeated, so it will be omitted.

[0244] Figures 33 to 35 The layout diagrams are illustrated exemplary based on some example implementation methods. Figure 32 In the following text, to avoid repetition, only through... Figure 33 To describe Figures 33 to 35 The common parts will be described, and the differences will be briefly described with reference to the corresponding figures.

[0245] Reference Figure 33 The first PMOS transistor P1 to the fourth PMOS transistor P4 can be formed on the first active region ACT1 extending in the first direction x. Furthermore, the first NMOS transistor N1 to the fourth NMOS transistor N4 can be formed on the second active region ACT2 extending in the first direction x and spaced apart from the first active region ACT1 in the second direction y.

[0246] The power rail 10 can be disposed above the first active region ACT1 in the second direction y. Furthermore, the ground rail 20 can be disposed below the second active region ACT2 in the second direction y.

[0247] The scan circuit S_C(R3_3a) of an integrated circuit according to some example embodiments may include a plurality of gate structures and a plurality of source / drain contacts that extend in a second direction y and are spaced apart from each other in a first direction x.

[0248] For example, the first source / drain contact 100 and the second source / drain contact 110 can be respectively disposed on the first active region ACT1 and the second active region ACT2, spaced apart from each other in the second direction y. That is, the first source / drain contact 100 can be connected to the power rail 10 through the first source / drain contact path VSD1 to supply the power supply voltage to the first PMOS transistor P1. In addition, the second source / drain contact 110 can be connected to the ground rail 20 through the third source / drain contact path VSD3 to ground the first NMOS transistor N1.

[0249] The first gate structure 200 is configured to be spaced apart from the first source / drain contact 100 and the second source / drain contact 110 in the first direction x. The first gate structure 200 may be disposed on the first active region ACT1 and the second active region ACT2.

[0250] The third source / drain contact 120 can be configured to be spaced apart from the first gate structure 200 in the first direction x. The third source / drain contact 120 can extend in the second direction y and can be disposed on the first active region ACT1 and the second active region ACT2. That is, the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 can be connected to each other through the third source / drain contact 120. In addition, the source of the third PMOS transistor P3 can be connected to the drain of the third NMOS transistor N3 through the third source / drain contact 120. That is, the drain of the first PMOS transistor P1, the drain of the first NMOS transistor N1, the source of the third PMOS transistor P3, and the drain of the third NMOS transistor N3 can be connected to each other through the third source / drain contact 120. By connecting multiple transistors via a single source / drain contact (e.g., the third source / drain contact 120), the height of the integrated circuit according to some example embodiments can be reduced.

[0251] Therefore, the stability of the process used to manufacture semiconductor integrated circuits, including those designed according to some example embodiments, can be improved. Furthermore, the degrees of freedom of metal lines can be increased, and pin congestion can be reduced.

[0252] The second gate structure 210 can be disposed on the first active region ACT1 and spaced apart from the third source / drain contact 120 in the first direction x. Furthermore, the third gate structure 220 can be disposed on the second active region ACT2 and spaced apart from the third source / drain contact 120 in the first direction x.

[0253] The fourth source / drain contact 130 can be configured to extend in the second direction y and be spaced apart from the second gate structure 210 and the third gate structure 220 in the first direction x. The drain of the third PMOS transistor P3 can be connected to the source of the third NMOS transistor N3 through the fourth source / drain contact 130. Furthermore, the drain of the fourth PMOS transistor P4 can be connected to the source of the fourth NMOS transistor N4 through the fourth source / drain contact 130. That is, the drain of the third PMOS transistor P3, the source of the third NMOS transistor N3, the drain of the fourth PMOS transistor P4, and the source of the fourth NMOS transistor N4 can be connected to each other through the fourth source / drain contact 130. By connecting multiple transistors via a single source / drain contact (e.g., the fourth source / drain contact 130), the height of the integrated circuit according to some example embodiments can be reduced.

[0254] Therefore, the stability of the process used to manufacture semiconductor integrated circuits, including those designed according to some example embodiments, can be improved. Furthermore, the degrees of freedom of metal lines can be increased, and pin congestion can be reduced.

[0255] The fourth gate structure 230 may be disposed on the first active region ACT1 and spaced apart from the fourth source / drain contact 130 in the first direction x. Furthermore, the fifth gate structure 240 may be disposed on the second active region ACT2 and spaced apart from the fourth source / drain contact 130 in the first direction x.

[0256] The fifth source / drain contact 140 and the sixth source / drain contact 150 can be configured to be spaced apart from the fourth gate structure 230 and the fifth gate structure 240 in the first direction x. The fifth source / drain contact 140 can extend in the second direction y and can be disposed on the first active region ACT1. The sixth source / drain contact 150 can extend in the second direction y and can be disposed on the second active region ACT2.

[0257] A sixth gate structure 250 can be disposed on the first active region ACT1 and the second active region ACT2, spaced apart from the fifth source / drain contact 140 and the sixth source / drain contact 150 in the first direction x. Furthermore, a seventh source / drain contact 160 can be disposed on the first active region ACT1, spaced apart from the sixth gate structure 250 in the first direction x. The seventh source / drain contact 160 can be connected to the power rail 10 via the second source / drain contact path VSD2 to supply power voltage to the second PMOS transistor P2. Furthermore, an eighth source / drain contact 170 can be disposed on the second active region ACT2, spaced apart from the sixth gate structure 250 in the first direction x. The eighth source / drain contact 170 can be connected to the ground rail 20 via the fourth source / drain contact path VSD4 to ground the second NMOS transistor N2.

[0258] Next, we will describe the structure and operation in which the signal is applied, as well as the structure extending to z from the third party.

[0259] A fifth gate contact GC5 extending in the z-direction can be disposed on the first gate structure 200. Furthermore, a first gate contact path VG1 extending in the z-direction can be disposed on the fifth gate contact GC5. The first gate contact path VG1 can be connected to a first metal line M1_1 extending in the x-direction. That is, the first gate structure 200 can be electrically connected to the first metal line M1_1, the first gate contact path VG1, and the fifth gate contact GC5 to receive the data signal D. Therefore, the first PMOS transistor P1 and the first NMOS transistor N1 can be selected by the data signal D.

[0260] The fifth gate contact GC5 and the first gate contact path VG1, which are electrically connected to the first gate structure 200, are shown in this figure as being disposed on the second active region ACT2, but are not limited thereto, and can be disposed as follows: Figure 34 and Figure 35 The settings shown are on the first active region ACT1.

[0261] A first gate contact GC1 extending in the z-direction can be disposed on the second gate structure 210. Furthermore, a second gate contact path VG2 extending in the z-direction can be disposed on the first gate contact GC1. The second gate contact path VG2 can be connected to a first / second metal line M1_2 extending in the x-direction. That is, the second gate structure 210 can be electrically connected to the first / second metal line M1_2, the second gate contact path VG2, and the first gate contact GC1 to receive a scan active signal Se. Therefore, the third PMOS transistor P3 can be selected by the scan active signal Se.

[0262] The locations of the first gate contact GC1 and the second gate contact path VG2 electrically connected to the second gate structure 210 are not limited to this.

[0263] A third gate contact GC3 extending in the z-direction can be disposed on the third gate structure 220. Furthermore, a third gate contact path VG3 extending in the z-direction can be disposed on the third gate contact GC3. The third gate contact path VG3 can be connected to a first-third metal line M1_3 extending in the first direction x. That is, the third gate structure 220 can be electrically connected to the first-third metal line M1_3, the third gate contact path VG3, and the third gate contact GC3 to receive an inverted active signal. Therefore, the third NMOS transistor N3 can be activated by an inverted active signal. Selected.

[0264] The locations of the third gate contact GC3 and the third gate contact path VG3 electrically connected to the third gate structure 220 are not limited to this.

[0265] A second gate contact GC2 extending in the z-direction can be disposed on the fourth gate structure 230. Furthermore, a fourth gate contact path VG4 extending in the z-direction can be disposed on the second gate contact GC2. The fourth gate contact path VG4 can be connected to a first-fifth metal line M1_5 extending in the first direction x. That is, the fourth gate structure 230 can be electrically connected to the first-fifth metal line M1_5, the fourth gate contact path VG4, and the second gate contact GC2 to receive an inverted active signal. Therefore, the fourth PMOS transistor P4 can be activated by an inverted active signal. Selected.

[0266] The locations of the second gate contact GC2 and the fourth gate contact path VG4 electrically connected to the fourth gate structure 230 are not limited to this.

[0267] A fourth gate contact GC4 extending in the z-direction can be disposed on the fifth gate structure 240. Furthermore, a fifth gate contact path VG5 extending in the z-direction can be disposed on the fourth gate contact GC4. The fifth gate contact path VG5 can be connected to a first-sixth metal line M1_6 extending in the first direction x. That is, the fifth gate structure 240 is electrically connected to the first-sixth metal line M1_6, the fifth gate contact path VG5, and the fourth gate contact GC4 to receive a scan active signal Se. Therefore, the fourth NMOS transistor N4 can be selected by the scan active signal Se.

[0268] The locations of the fourth gate contact GC4 and the fifth gate contact path VG5 electrically connected to the fifth gate structure 240 are not limited to this.

[0269] A sixth gate contact GC6 extending in the z-direction can be disposed on the sixth gate structure 250. Furthermore, a sixth gate contact path VG6 extending in the z-direction can be disposed on the sixth gate contact GC6. The sixth gate contact path VG6 can be connected to a first-seventh metal line M1_7 extending in the first direction x. That is, the sixth gate structure 250 can be electrically connected to the first-seventh metal line M1_7, the sixth gate contact path VG6, and the sixth gate contact GC6 to receive a scan input signal Si. Therefore, the second PMOS transistor P2 and the second NMOS transistor N2 can be selected by the scan input signal Si.

[0270] The sixth gate contact GC6 and the sixth gate contact path VG6, electrically connected to the sixth gate structure 250, are shown in this figure as being disposed on the first active region ACT1, but are not limited thereto, and can be as follows: Figure 34 and Figure 35 The settings shown are on the second active region ACT2.

[0271] The fifth source / drain contact path VSD5 extending in the z-direction can be disposed on the fourth source / drain contact 130. Furthermore, the first and fourth metal lines M1_4 extending in the x-direction can be disposed on the fifth source / drain contact path VSD5 and can be connected to an external source.

[0272] The fifth source / drain contact path VSD5, electrically connected to the fourth source / drain contact 130, is shown in this figure as being disposed on the first active region ACT1, but is not limited thereto, and can be as follows: Figure 34 The settings shown are on the second active region ACT2.

[0273] A plurality of gate structures (e.g., first gate structures 200 to sixth gate structures 250) and a plurality of source / drain contacts (e.g., first source / drain contacts 100 to eighth source / drain contacts 170) that are adjacent to each other in the first direction x can be spaced apart from each other by 1 CPP. As an example, the first gate structure 200 and the first source / drain contact 100 that are adjacent to each other can be spaced apart from each other by 1 CPP.

[0274] For example, suppose the first gate structure 200 and the first source / drain contact 100 are adjacent to each other. When the distance between the center line of the first gate structure 200 extending in the second direction y and the center line of the first source / drain contact 100 extending in the second direction y is 1 CPP, this means that no other gate structure or source / drain contact is provided between the first gate structure 200 and the first source / drain contact 100.

[0275] Furthermore, metal lines that are adjacent to each other in the second direction y (e.g., first metal line M1_1 to first seventh metal line M1_7) can be spaced apart by 1 CPP. As an example, the first metal line M1_1 and the first second metal line M1_2 that are adjacent to each other can be spaced apart by 1 CPP (see reference). Figure 34 and Figure 35 ).

[0276] For example, suppose the first metal wire M1_1 and the first metal wire M1_2 are adjacent to each other. When the distance between the center line of the first metal wire M1_1 extending in the first direction x and the center line of the first metal wire M1_2 extending in the first direction x is 1 CPP, this means that no other metal wire is set between the first metal wire M1_1 and the first metal wire M1_2.

[0277] Refer again Figure 8 The master latch M_L may include a first transmission unit TSU1, a first latch unit LU1, and a first inverter INV1.

[0278] The master latch M_L can store the data signal D input through the signal node SN and output the data signal D to the first master latch node MLN1. More specifically, the master latch M_L can be based on a first clock signal En and a second clock signal. The input data signal D is output, along with the second clock signal. It is the inverted first clock signal.

[0279] The first transmission unit TSU1 of the main latch M_L can be configured to include a transmission gate of an integrated circuit according to some example embodiments, or it can be configured as a tri-state inverter. The first latch unit LU1 of the main latch M_L can be configured to include a transmission gate of an integrated circuit according to some example embodiments, or it can be configured as a tri-state inverter.

[0280] In the following text, reference will be made to Figures 36 to 44 The description includes the main latch M_L of an integrated circuit according to some example implementations.

[0281] Figure 36 It is shown that it is used for Figure 8 The circuit diagram of the master latch M_L1 is shown. For example, the description of the slave latch S_L is repeated with the description of the master latch M_L1; therefore, the master latch M_L1 will be described as an example. Furthermore, the description of the master latch M_L1 can also be applied to the slave latch S_L.

[0282] Reference Figure 36The first transmission unit TSU1 includes a fourth inverter INV4 and a first transmission gate TG1, and the first latch unit LU1 includes a third tri-state inverter TRI3.

[0283] The first transmission unit TSU1, including an integrated circuit according to some example embodiments, receives a data signal D through a signal node SN and sends the data signal D to a first master latch node MLN1. More specifically, the signal input to the signal node SN is inverted by a fourth inverter INV4 composed of a first PMOS transistor P1 and a first NMOS transistor N1. Furthermore, the inverted signal input to the signal node SN can be output to the first master latch node MLN1 through a first transmission gate TG1 composed of a second PMOS transistor P2 and a second NMOS transistor N2.

[0284] The third tri-state inverter TRI3, composed of the third PMOS transistor P3, the third NMOS transistor N3, the fourth PMOS transistor P4, and the fourth NMOS transistor N4, can operate on the first clock signal En and the second clock signal... Under the control of [the system], the data input to the first master latch node MLN1 is latched. The description of the tri-state inverter is as follows... Figure 1 The description is repeated, so it will be omitted.

[0285] Figure 37 and Figure 38 It is an exemplary demonstration Figure 36 The layout diagram is based on some example implementations. In the following, to avoid repetitive descriptions, only... Figure 37 To describe Figure 37 and Figure 38 The common parts will be described, and the differences will be briefly described with reference to the accompanying drawings. Furthermore, for simplicity, the layout diagram of region R4_1 of the master latch M_L1 will be described primarily.

[0286] When reference Figure 37 When describing region R4_1a of region R4_1, the first PMOS transistor P1 to the fourth PMOS transistor P4 can be disposed on the first active region ACT1 extending in the first direction x. Furthermore, the first NMOS transistor N1 to the fourth NMOS transistor N4 can be formed on the second active region ACT2 extending in the first direction x and disposed on the second active region ACT1 spaced apart from the first active region ACT1 in the second direction y.

[0287] The power rail 10 can be disposed above the first active region ACT1 in the second direction y. Furthermore, the ground rail 20 can be disposed below the second active region ACT2 in the second direction y.

[0288] Region R4_1a of the main latch M_L1 of an integrated circuit according to some example embodiments may include a plurality of gate structures and a plurality of source / drain contacts that extend in a second direction y and are spaced apart from each other in a first direction x.

[0289] For example, the first source / drain contact 100 and the second source / drain contact 110 can be respectively disposed on the first active region ACT1 and the second active region ACT2, spaced apart from each other in the second direction y. That is, the first source / drain contact 100 can be connected to the power rail 10 through the first source / drain contact path VSD1 to supply the power supply voltage to the first PMOS transistor P1. In addition, the second source / drain contact 110 can be connected to the ground rail 20 through the third source / drain contact path VSD3 to ground the first NMOS transistor N1.

[0290] The first gate structure 200 is configured to be spaced apart from the first source / drain contact 100 and the second source / drain contact 110 in the first direction x. The first gate structure 200 may be disposed on the first active region ACT1 and the second active region ACT2.

[0291] The third source / drain contact 120 can be configured to be spaced apart from the first gate structure 200 in the first direction x. The third source / drain contact 120 can extend in the second direction y and can be disposed on the first active region ACT1 and the second active region ACT2. That is, the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 can be connected to each other through the third source / drain contact 120. In addition, the source of the second PMOS transistor P2 can be connected to the drain of the second NMOS transistor N2 through the third source / drain contact 120. That is, the drain of the first PMOS transistor P1, the drain of the first NMOS transistor N1, the source of the second PMOS transistor P2 and the drain of the second NMOS transistor N2 can be connected to each other through the third source / drain contact 120. By connecting multiple transistors via a single source / drain contact (e.g., the third source / drain contact 120), the height of the integrated circuit according to some example embodiments can be reduced.

[0292] Therefore, the stability of the process used to manufacture semiconductor integrated circuits, including those designed according to some example embodiments, can be improved. Furthermore, the degrees of freedom of metal lines can be increased, and pin congestion can be reduced.

[0293] The second gate structure 210 can be disposed on the first active region ACT1 and spaced apart from the third source / drain contact 120 in the first direction x. Furthermore, the third gate structure 220 can be disposed on the second active region ACT2 and spaced apart from the third source / drain contact 120 in the first direction x.

[0294] The fourth source / drain contact 130 can be configured to extend in the second direction y and be spaced apart from the second gate structure 210 and the third gate structure 220 in the first direction x. The drain of the second PMOS transistor P2 can be connected to the source of the second NMOS transistor N2 through the fourth source / drain contact 130. The drain of the third PMOS transistor P3 can be connected to the drain of the third NMOS transistor N3 through the fourth source / drain contact 130. That is, the drains of the second PMOS transistor P2, the source of the second NMOS transistor N2, the drains of the third PMOS transistor P3, and the drains of the third NMOS transistor N3 can be connected to each other through the fourth source / drain contact 130. By connecting multiple transistors via a single source / drain contact (e.g., the fourth source / drain contact 130), the height of the integrated circuit according to some example embodiments can be reduced.

[0295] Therefore, the stability of the process used to manufacture semiconductor integrated circuits, including those designed according to some example embodiments, can be improved. Furthermore, the degrees of freedom of metal lines can be increased, and pin congestion can be reduced.

[0296] The fourth gate structure 230 may be disposed on the first active region ACT1 and spaced apart from the fourth source / drain contact 130 in the first direction x. Furthermore, the fifth gate structure 240 may be disposed on the second active region ACT2 and spaced apart from the fourth source / drain contact 130 in the first direction x.

[0297] The fifth source / drain contact 140 and the sixth source / drain contact 150 can be configured to be spaced apart from the fourth gate structure 230 and the fifth gate structure 240 in the first direction x. The fifth source / drain contact 140 can extend in the second direction y and can be disposed on the first active region ACT1. The sixth source / drain contact 150 can extend in the second direction y and can be disposed on the second active region ACT2.

[0298] A sixth gate structure 250 can be disposed on the first active region ACT1 and the second active region ACT2, spaced apart from the fifth source / drain contact 140 and the sixth source / drain contact 150 in the first direction x. Furthermore, a seventh source / drain contact 160 can be disposed on the first active region ACT1, spaced apart from the sixth gate structure 250 in the first direction x. The seventh source / drain contact 160 can be connected to the power rail 10 via the second source / drain contact path VSD2 to supply power voltage to the fourth PMOS transistor P4. Furthermore, an eighth source / drain contact 170 can be disposed on the second active region ACT2, spaced apart from the sixth gate structure 250 in the first direction x. The eighth source / drain contact 170 can be connected to the ground rail 20 via the fourth source / drain contact path VSD4 to ground the fourth NMOS transistor N4.

[0299] Next, we will describe the structure and operation in which the signal is applied, as well as the structure extending to z from the third party.

[0300] A fifth gate contact GC5 extending in the z-direction can be disposed on the first gate structure 200. Furthermore, a first gate contact path VG1 extending in the z-direction can be disposed on the fifth gate contact GC5. The first gate contact path VG1 can be connected to a first metal line M1_1 extending in the x-direction. That is, the first gate structure 200 can be electrically connected to the first metal line M1_1, the first gate contact path VG1, and the fifth gate contact GC5 to receive the data signal D. Therefore, the first PMOS transistor P1 and the first NMOS transistor N1 can be selected by the data signal D.

[0301] The fifth gate contact GC5 and the first gate contact path VG1, which are electrically connected to the first gate structure 200, are shown in this figure as being disposed on the first active region ACT1, but are not limited thereto, and can be disposed as follows: Figure 38 The settings shown are on the second active region ACT2.

[0302] A first gate contact GC1 extending in the z-direction can be disposed on the second gate structure 210. Furthermore, a second gate contact path VG2 extending in the z-direction can be disposed on the first gate contact GC1. The second gate contact path VG2 can be connected to a first / second metal line M1_2 extending in the first direction x. That is, the second gate structure 210 can be electrically connected to the first / second metal line M1_2, the second gate contact path VG2, and the first gate contact GC1 to receive a first clock signal En. Therefore, the second PMOS transistor P2 can be selected by the first clock signal En.

[0303] The locations of the first gate contact GC1 and the second gate contact path VG2 electrically connected to the second gate structure 210 are not limited to this.

[0304] A third gate contact GC3 extending in the z-direction can be disposed on the third gate structure 220. Furthermore, a third gate contact path VG3 extending in the z-direction can be disposed on the third gate contact GC3. The third gate contact path VG3 can be connected to a first-third metal line M1_3 extending in the first direction x. That is, the third gate structure 220 can be electrically connected to the first-third metal line M1_3, the third gate contact path VG3, and the third gate contact GC3 to receive a second clock signal. Therefore, the second NMOS transistor N2 can be controlled by the second clock signal. Selected.

[0305] The locations of the third gate contact GC3 and the third gate contact path VG3 electrically connected to the third gate structure 220 are not limited to this.

[0306] A second gate contact GC2 extending in the z-direction can be disposed on the fourth gate structure 230. Furthermore, a fourth gate contact path VG4 extending in the z-direction can be disposed on the second gate contact GC2. The fourth gate contact path VG4 can be connected to a first-fifth metal line M1_5 extending in the first direction x. That is, the fourth gate structure 230 can be electrically connected to the first-fifth metal line M1_5, the fourth gate contact path VG4, and the second gate contact GC2 to receive a second clock signal. Therefore, the third PMOS transistor P3 can be controlled by the second clock signal. Selected.

[0307] The locations of the second gate contact GC2 and the fourth gate contact path VG4 electrically connected to the fourth gate structure 230 are not limited to this.

[0308] A fourth gate contact GC4 extending in the z-direction can be disposed on the fifth gate structure 240. Furthermore, a fifth gate contact path VG5 extending in the z-direction can be disposed on the fourth gate contact GC4. The fifth gate contact path VG5 can be connected to a first-sixth metal line M1_6 extending in the first direction x. That is, the fifth gate structure 240 is electrically connected to the first-sixth metal line M1_6, the fifth gate contact path VG5, and the fourth gate contact GC4 to receive a first clock signal En. Therefore, the third NMOS transistor N3 can be selected by the first clock signal En.

[0309] The locations of the fourth gate contact GC4 and the fifth gate contact path VG5 electrically connected to the fifth gate structure 240 are not limited to this.

[0310] A sixth gate contact GC6 extending in the z-direction can be disposed on the sixth gate structure 250. Furthermore, a sixth gate contact path VG6 extending in the z-direction can be disposed on the sixth gate contact GC6. The sixth gate contact path VG6 can be connected to a first-seventh metal line M1_7 extending in the first direction x. That is, the sixth gate structure 250 can be electrically connected to the first-seventh metal line M1_7, the sixth gate contact path VG6, and the sixth gate contact GC6 to receive signals at the second master latch node. Therefore, the fourth PMOS transistor P4 and the fourth NMOS transistor N4 can be selected by the signals at the second master latch node.

[0311] The sixth gate contact GC6 and the sixth gate contact path VG6, electrically connected to the sixth gate structure 250, are shown in this figure as being disposed on the second active region ACT2, but are not limited thereto, and can be as follows: Figure 38 The settings shown are on the first active region ACT1.

[0312] The fifth source / drain contact path VSD5 extending in the z-direction can be disposed on the fourth source / drain contact 130. Furthermore, the first and fourth metal lines M1_4 extending in the x-direction can be disposed on the fifth source / drain contact path VSD5 and can be connected to an external source.

[0313] The fifth source / drain contact path VSD5, electrically connected to the fourth source / drain contact 130, is shown in this figure as being disposed on the first active region ACT1, but is not limited thereto, and can be as follows: Figure 38 The settings shown are on the second active region ACT2.

[0314] A plurality of gate structures (e.g., first gate structures 200 to sixth gate structures 250) and a plurality of source / drain contacts (e.g., first source / drain contacts 100 to eighth source / drain contacts 170) that are adjacent to each other in the first direction x can be spaced apart from each other by 1 CPP. As an example, the first gate structure 200 and the first source / drain contact 100 that are adjacent to each other can be spaced apart from each other by 1 CPP.

[0315] For example, suppose the first gate structure 200 and the first source / drain contact 100 are adjacent to each other. When the distance between the center line of the first gate structure 200 extending in the second direction y and the center line of the first source / drain contact 100 extending in the second direction y is 1 CPP, this means that no other gate structure or source / drain contact is provided between the first gate structure 200 and the first source / drain contact 100.

[0316] Furthermore, metal lines that are adjacent to each other in the second direction y (e.g., first metal line M1_1 to first seventh metal line M1_7) can be spaced apart by 1 CPP. As an example, first sixth metal line M1_6 and first seventh metal line M1_7 that are adjacent to each other can be spaced apart by 1 CPP.

[0317] For example, suppose the first and sixth metal wires M1_6 and the first and seventh metal wires M1_7 are adjacent to each other. When the distance between the center line of the first and sixth metal wires M1_6 extending in the first direction x and the center line of the first and seventh metal wires M1_7 extending in the first direction x is 1 CPP, this means that no other metal wires are set between the first and sixth metal wires M1_6 and the first and seventh metal wires M1_7.

[0318] Figure 39 It is shown that it is used for Figure 8 The circuit diagram of the main latch M_L2 is shown.

[0319] When reference Figure 39 The main latch M_L2 is mainly described Figure 39 Master latch M_L2 and Figure 36 When there is a difference between the main latches M_L1, the first latch unit LU1 includes the second transmission gate TG2 and the fifth inverter INV5.

[0320] The first latch unit LU1 of the integrated circuit, including some example embodiments, can latch a signal at the first main latch node MLN1. More specifically, the signal at the second main latch node MLN2 is inverted by a fifth inverter INV5 composed of a fourth PMOS transistor P4 and a fourth NMOS transistor N4. Furthermore, the signal inverted at the second main latch node MLN2 can be output to the first main latch node MLN1 through a second transmission gate TG2 composed of a third PMOS transistor P3 and a third NMOS transistor N3.

[0321] The first latch unit LU1 can be connected to the first clock signal En and the second clock signal. Under the control of the latch, the data signal D input to the first master latch node MLN1 is latched.

[0322] Figure 40 and Figure 41 The layout diagrams are illustrated exemplary based on some example implementation methods. Figure 39 In the following text, to avoid repetition, only by way of description will it be used. Figure 40 describe Figure 40 and Figure 41The common parts will be described, and the differences will be briefly described with reference to the corresponding figures. Furthermore, for simplicity, the layout diagram of region R4_2 of the main latch M_L2 will be described primarily.

[0323] When reference Figure 40 When describing region R4_2a of region R4_2, the first PMOS transistor P1 to the fourth PMOS transistor P4 can be disposed on the first active region ACT1 extending in the first direction x. Furthermore, the first NMOS transistor N1 to the fourth NMOS transistor N4 can be formed on the second active region ACT2 extending in the first direction x and disposed on the second active region ACT1 spaced apart from the first active region ACT1 in the second direction y.

[0324] The power rail 10 can be disposed above the first active region ACT1 in the second direction y. Furthermore, the ground rail 20 can be disposed below the second active region ACT2 in the second direction y.

[0325] Region R4_2a of the main latch M_L2 of an integrated circuit according to some example embodiments may include a plurality of gate structures and a plurality of source / drain contacts that extend in a second direction y and are spaced apart from each other in a first direction x.

[0326] For example, the first source / drain contact 100 and the second source / drain contact 110 can be respectively disposed on the first active region ACT1 and the second active region ACT2, spaced apart from each other in the second direction y. That is, the first source / drain contact 100 can be connected to the power rail 10 through the first source / drain contact path VSD1 to supply the power supply voltage to the first PMOS transistor P1. In addition, the second source / drain contact 110 can be connected to the ground rail 20 through the third source / drain contact path VSD3 to ground the first NMOS transistor N1.

[0327] The first gate structure 200 is configured to be spaced apart from the first source / drain contact 100 and the second source / drain contact 110 in the first direction x. The first gate structure 200 may be disposed on the first active region ACT1 and the second active region ACT2.

[0328] The third source / drain contact 120 can be configured to be spaced apart from the first gate structure 200 in the first direction x. The third source / drain contact 120 can extend in the second direction y and can be disposed on the first active region ACT1 and the second active region ACT2. That is, the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 can be connected to each other through the third source / drain contact 120. In addition, the source of the second PMOS transistor P2 can be connected to the drain of the second NMOS transistor N2 through the third source / drain contact 120. That is, the drain of the first PMOS transistor P1, the drain of the first NMOS transistor N1, the source of the second PMOS transistor P2 and the drain of the second NMOS transistor N2 can be connected to each other through the third source / drain contact 120. By connecting multiple transistors via a single source / drain contact (e.g., the third source / drain contact 120), the height of the integrated circuit according to some example embodiments can be reduced.

[0329] Therefore, the stability of the process used to manufacture semiconductor integrated circuits, including those designed according to some example embodiments, can be improved. Furthermore, the degrees of freedom of metal lines can be increased, and pin congestion can be reduced.

[0330] The second gate structure 210 can be disposed on the first active region ACT1 and spaced apart from the third source / drain contact 120 in the first direction x. Furthermore, the third gate structure 220 can be disposed on the second active region ACT2 and spaced apart from the third source / drain contact 120 in the first direction x.

[0331] The fourth source / drain contact 130 can be configured to extend in the second direction y and be spaced apart from the second gate structure 210 and the third gate structure 220 in the first direction x. The drain of the second PMOS transistor P2 can be connected to the source of the second NMOS transistor N2 through the fourth source / drain contact 130. Furthermore, the drain of the third PMOS transistor P3 can be connected to the source of the third NMOS transistor N3 through the fourth source / drain contact 130. That is, the drains of the second PMOS transistor P2, the sources of the second NMOS transistor N2, the drains of the third PMOS transistor P3, and the sources of the third NMOS transistor N3 can be connected to each other through the fourth source / drain contact 130. By connecting multiple transistors via a single source / drain contact (e.g., the fourth source / drain contact 130), the height of the integrated circuit according to some example embodiments can be reduced.

[0332] Therefore, the stability of the process used to manufacture semiconductor integrated circuits, including those designed according to some example embodiments, can be improved. Furthermore, the degrees of freedom of metal lines can be increased, and pin congestion can be reduced.

[0333] The fourth gate structure 230 may be disposed on the first active region ACT1 and spaced apart from the fourth source / drain contact 130 in the first direction x. Furthermore, the fifth gate structure 240 may be disposed on the second active region ACT2 and spaced apart from the fourth source / drain contact 130 in the first direction x.

[0334] The fifth source / drain contact 140 can be configured to be spaced apart from the fourth gate structure 230 and the fifth gate structure 240 in the first direction x. The fifth source / drain contact 140 can extend in the second direction y and can be disposed on the first active region ACT1 and the second active region ACT2. That is, the source of the third PMOS transistor P3 and the drain of the third NMOS transistor N3 can be connected to each other through the fifth source / drain contact 140. In addition, the drain of the fourth PMOS transistor P4 can be connected to the drain of the fourth NMOS transistor N4 through the fifth source / drain contact 140. That is, the source of the third PMOS transistor P3, the drain of the third NMOS transistor N3, the drain of the fourth PMOS transistor P4, and the drain of the fourth NMOS transistor N4 can be connected to each other through the fifth source / drain contact 140. By connecting multiple transistors via a single source / drain contact (e.g., the fifth source / drain contact 140), the height of the integrated circuit according to some example embodiments can be reduced.

[0335] Therefore, the stability of the process used to manufacture semiconductor integrated circuits, including those designed according to some example embodiments, can be improved. Furthermore, the degrees of freedom of metal lines can be increased, and pin congestion can be reduced.

[0336] A sixth gate structure 250 can be disposed on the first active region ACT1 and the second active region ACT2, spaced apart from the fifth source / drain contact 140 in the first direction x. Furthermore, a sixth source / drain contact 150 can be disposed on the first active region ACT1, spaced apart from the sixth gate structure 250 in the first direction x. The sixth source / drain contact 150 can be connected to the power rail 10 via the second source / drain contact path VSD2 to supply power voltage to the fourth PMOS transistor P4. Furthermore, a seventh source / drain contact 160 can be disposed on the second active region ACT2, spaced apart from the sixth gate structure 250 in the first direction x. The seventh source / drain contact 160 can be connected to the ground rail 20 via the fourth source / drain contact path VSD4 to ground the fourth NMOS transistor N4.

[0337] Next, we will describe the structure and operation in which the signal is applied, as well as the structure extending to z from the third party.

[0338] A fifth gate contact GC5 extending in the z-direction can be disposed on the first gate structure 200. Furthermore, a first gate contact path VG1 extending in the z-direction can be disposed on the fifth gate contact GC5. The first gate contact path VG1 can be connected to a first metal line M1_1 extending in the x-direction. That is, the first gate structure 200 can be electrically connected to the first metal line M1_1, the first gate contact path VG1, and the fifth gate contact GC5 to receive the data signal D. Therefore, the first PMOS transistor P1 and the first NMOS transistor N1 can be selected by the data signal D.

[0339] The fifth gate contact GC5 and the first gate contact path VG1, which are electrically connected to the first gate structure 200, are shown in this figure as being disposed on the first active region ACT1, but are not limited thereto, and can be disposed as follows: Figure 41 The settings shown are on the second active region ACT2.

[0340] A first gate contact GC1 extending in the z-direction can be disposed on the second gate structure 210. Furthermore, a second gate contact path VG2 extending in the z-direction can be disposed on the first gate contact GC1. The second gate contact path VG2 can be connected to a first / second metal line M1_2 extending in the first direction x. That is, the second gate structure 210 can be electrically connected to the first / second metal line M1_2, the second gate contact path VG2, and the first gate contact GC1 to receive a first clock signal En. Therefore, the second PMOS transistor P2 can be selected by the first clock signal En.

[0341] The locations of the first gate contact GC1 and the second gate contact path VG2 electrically connected to the second gate structure 210 are not limited to this.

[0342] A third gate contact GC3 extending in the z-direction can be disposed on the third gate structure 220. Furthermore, a third gate contact path VG3 extending in the z-direction can be disposed on the third gate contact GC3. The third gate contact path VG3 can be connected to a first-third metal line M1_3 extending in the first direction x. That is, the third gate structure 220 can be electrically connected to the first-third metal line M1_3, the third gate contact path VG3, and the third gate contact GC3 to receive a second clock signal. Therefore, the second NMOS transistor N2 can be controlled by the second clock signal. Selected.

[0343] The locations of the third gate contact GC3 and the third gate contact path VG3 electrically connected to the third gate structure 220 are not limited to this.

[0344] A second gate contact GC2 extending in the z-direction can be disposed on the fourth gate structure 230. Furthermore, a fourth gate contact path VG4 extending in the z-direction can be disposed on the second gate contact GC2. The fourth gate contact path VG4 can be electrically connected to a first-fifth metal line M1_5 extending in the first direction x. That is, the fourth gate structure 230 can be electrically connected to the first-fifth metal line M1_5, the fourth gate contact path VG4, and the second gate contact GC2 to receive a second clock signal. Therefore, the third PMOS transistor P3 can be controlled by the second clock signal. Selected.

[0345] The locations of the second gate contact GC2 and the fourth gate contact path VG4 electrically connected to the fourth gate structure 230 are not limited to this.

[0346] A fourth gate contact GC4 extending in the z-direction can be disposed on the fifth gate structure 240. Furthermore, a fifth gate contact path VG5 extending in the z-direction can be disposed on the fourth gate contact GC4. The fifth gate contact path VG5 can be connected to a first-sixth metal line M1_6 extending in the first direction x. That is, the fifth gate structure 240 can be electrically connected to the first-sixth metal line M1_6, the fifth gate contact path VG5, and the fourth gate contact GC4 to receive a first clock signal En. Therefore, the third NMOS transistor N3 can be selected by the first clock signal En.

[0347] The locations of the fourth gate contact GC4 and the fifth gate contact path VG5 electrically connected to the fifth gate structure 240 are not limited to this.

[0348] A sixth gate contact GC6 extending in the z-direction can be disposed on the sixth gate structure 250. Furthermore, a sixth gate contact path VG6 extending in the z-direction can be disposed on the sixth gate contact GC6. The sixth gate contact path VG6 can be connected to a first-seventh metal line M1_7 extending in the first direction x. That is, the sixth gate structure 250 can be electrically connected to the first-seventh metal line M1_7, the sixth gate contact path VG6, and the sixth gate contact GC6 to receive signals at the second master latch node. Therefore, the fourth PMOS transistor P4 and the fourth NMOS transistor N4 can be selected by the signals at the second master latch node.

[0349] The sixth gate contact GC6 and the sixth gate contact path VG6, electrically connected to the sixth gate structure 250, are shown in this figure as being disposed on the second active region ACT2, but are not limited thereto, and can be as follows: Figure 41 The settings shown are on the first active region ACT1.

[0350] The fifth source / drain contact path VSD5 extending in the z-direction can be disposed on the fourth source / drain contact 130. Furthermore, the first and fourth metal lines M1_4 extending in the x-direction can be disposed on the fifth source / drain contact path VSD5 and can be connected to an external source.

[0351] The fifth source / drain contact path VSD5, electrically connected to the fourth source / drain contact 130, is shown in this figure as being disposed on the first active region ACT1, but is not limited thereto, and can be as follows: Figure 41 The settings shown are on the second active region ACT2.

[0352] A plurality of gate structures (e.g., first gate structures 200 to sixth gate structures 250) and a plurality of source / drain contacts (e.g., first source / drain contacts 100 to seventh source / drain contacts 160) that are adjacent to each other in the first direction x can be spaced apart from each other by 1 CPP. As an example, the first gate structure 200 and the first source / drain contact 100 that are adjacent to each other can be spaced apart from each other by 1 CPP.

[0353] For example, suppose the first gate structure 200 and the first source / drain contact 100 are adjacent to each other. When the distance between the center line of the first gate structure 200 extending in the second direction y and the center line of the first source / drain contact 100 extending in the second direction y is 1 CPP, this means that no other gate structure or source / drain contact is provided between the first gate structure 200 and the first source / drain contact 100.

[0354] Furthermore, metal lines that are adjacent to each other in the second direction y (e.g., first metal line M1_1 to first seventh metal line M1_7) can be spaced apart by 1 CPP. As an example, the first metal line M1_1 and the first third metal line M1_3 that are adjacent to each other can be spaced apart by 1 CPP (see reference). Figure 41 ).

[0355] For example, suppose the first metal wire M1_1 and the first third metal wire M1_3 are adjacent to each other. When the distance between the center line of the first metal wire M1_1 extending in the first direction x and the center line of the first third metal wire M1_3 extending in the first direction x is 1 CPP, this means that no other metal wire is set between the first metal wire M1_1 and the first third metal wire M1_3.

[0356] Figure 42 It is shown that it is used for Figure 8 The circuit diagram of the main latch M_L3 is shown.

[0357] When the main reference Figure 42 The main latch M_L3 in the middle is used to describe Figure 42 Master latch M_L3 and Figure 39 When there is a difference between the master latches M_L2, the first transmission unit TSU1 includes a third tri-state inverter TRI3.

[0358] The third tri-state inverter TRI3, comprising a first PMOS transistor P1, a first NMOS transistor N1, a second PMOS transistor P2, and a second NMOS transistor N2, can operate on the first clock signal En and the second clock signal... Under its control, the data signal D received from the signal node SN is inverted.

[0359] The first latch unit LU1 and Figure 40 The first latch unit shown is the same, so its description will be omitted.

[0360] Figure 43 and Figure 44 Based on some example implementations Figure 42 The layout diagram. In the following text, to avoid repetition, only the layout diagram will be used. Figure 43 describe Figure 43 and Figure 44 The common parts will be described, and the differences will be briefly described with reference to the corresponding figures. Furthermore, for simplicity, the layout diagram of region R4_3 of the main latch M_L3 will be described primarily.

[0361] When reference Figure 43 When describing region R4_3a of region R4_3, the first PMOS transistor P1 to the fourth PMOS transistor P4 can be disposed on the first active region ACT1 extending in the first direction x. Furthermore, the first NMOS transistor N1 to the fourth NMOS transistor N4 can be formed on the second active region ACT2 extending in the first direction x and disposed on the second active region ACT1 spaced apart from the first active region ACT1 in the second direction y.

[0362] The power rail 10 can be disposed above the first active region ACT1 in the second direction y. Furthermore, the ground rail 20 can be disposed below the second active region ACT2 in the second direction y.

[0363] Region R4_3a of the main latch M_L3 of an integrated circuit according to some example embodiments may include a plurality of gate structures and a plurality of source / drain contacts that extend in the second direction y and are spaced apart from each other in the first direction x.

[0364] For example, the first source / drain contact 100 and the second source / drain contact 110 can be respectively disposed on the first active region ACT1 and the second active region ACT2, spaced apart from each other in the second direction y. That is, the first source / drain contact 100 can be connected to the power rail 10 through the first source / drain contact path VSD1 to supply the power supply voltage to the second PMOS transistor P2. In addition, the second source / drain contact 110 can be connected to the ground rail 20 through the third source / drain contact path VSD3 to ground the second NMOS transistor N2.

[0365] The first gate structure 200 is configured to be spaced apart from the first source / drain contact 100 and the second source / drain contact 110 in the first direction x. The first gate structure 200 may be disposed on the first active region ACT1 and the second active region ACT2.

[0366] The third source / drain contact 120 and the fourth source / drain contact 130 can be respectively disposed on the first active region ACT1 and the second active region ACT2, spaced apart from each other in the second direction y and spaced apart from the first gate structure 200 in the first direction x.

[0367] The second gate structure 210 can be disposed on the first active region ACT1 and spaced apart from the third source / drain contact 120 and the fourth source / drain contact 130 in the first direction x. Furthermore, the third gate structure 220 can be disposed on the second active region ACT2 and spaced apart from the third source / drain contact 120 and the fourth source / drain contact 130 in the first direction x.

[0368] The fifth source / drain contact 140 can be configured to extend in the second direction y and be spaced apart from the second gate structure 210 and the third gate structure 220 in the first direction x. The drain of the first PMOS transistor P1 can be connected to the drain of the first NMOS transistor N1 through the fifth source / drain contact 140. Furthermore, the drain of the third PMOS transistor P3 can be connected to the source of the third NMOS transistor N3 through the fifth source / drain contact 140. That is, the drains of the first PMOS transistor P1, the drain of the first NMOS transistor N1, the drain of the third PMOS transistor P3, and the source of the third NMOS transistor N3 can be connected to each other through the fifth source / drain contact 140. By connecting multiple transistors via a single source / drain contact (e.g., the fifth source / drain contact 140), the height of the integrated circuit according to some example embodiments can be reduced.

[0369] Therefore, the stability of the process used to manufacture semiconductor integrated circuits, including those designed according to some example embodiments, can be improved. Furthermore, the degrees of freedom of metal lines can be increased, and pin congestion can be reduced.

[0370] The fourth gate structure 230 may be disposed on the first active region ACT1 and spaced apart from the fifth source / drain contact 140 in the first direction x. Furthermore, the fifth gate structure 240 may be disposed on the second active region ACT2 and spaced apart from the fifth source / drain contact 140 in the first direction x.

[0371] The sixth source / drain contact 150 can be configured to be spaced apart from the fourth gate structure 230 and the fifth gate structure 240 in the first direction x. The sixth source / drain contact 150 can extend in the second direction y and can be disposed on the first active region ACT1 and the second active region ACT2. That is, the source of the third PMOS transistor P3 and the drain of the third NMOS transistor N3 can be connected to each other through the sixth source / drain contact 150. In addition, the drain of the fourth PMOS transistor P4 can be connected to the drain of the fourth NMOS transistor N4 through the sixth source / drain contact 150. That is, the source of the third PMOS transistor P3, the drain of the third NMOS transistor N3, the drain of the fourth PMOS transistor P4, and the drain of the fourth NMOS transistor N4 can be connected to each other through the sixth source / drain contact 150. By connecting multiple transistors via a single source / drain contact (e.g., the sixth source / drain contact 150), the height of the integrated circuit according to some example embodiments can be reduced.

[0372] Therefore, the stability of the process used to manufacture semiconductor integrated circuits, including those designed according to some example embodiments, can be improved. Furthermore, the degrees of freedom of metal lines can be increased, and pin congestion can be reduced.

[0373] A sixth gate structure 250 can be disposed on the first active region ACT1 and the second active region ACT2, spaced apart from the sixth source / drain contact 150 in the first direction x. Furthermore, a seventh source / drain contact 160 can be disposed on the first active region ACT1, spaced apart from the sixth gate structure 250 in the first direction x. The seventh source / drain contact 160 can be connected to the power rail 10 via the second source / drain contact path VSD2 to supply power voltage to the fourth PMOS transistor P4. Furthermore, an eighth source / drain contact 170 can be disposed on the second active region ACT2, spaced apart from the sixth gate structure 250 in the first direction x. The eighth source / drain contact 170 can be connected to the ground rail 20 via the fourth source / drain contact path VSD4 to ground the fourth NMOS transistor N4.

[0374] Next, we will describe the structure and operation in which the signal is applied, as well as the structure extending to z from the third party.

[0375] A fifth gate contact GC5 extending in the z-direction can be disposed on the first gate structure 200. Furthermore, a first gate contact path VG1 extending in the z-direction can be disposed on the fifth gate contact GC5. The first gate contact path VG1 can be connected to a first metal line M1_1 extending in the x-direction. That is, the first gate structure 200 can be electrically connected to the first metal line M1_1, the first gate contact path VG1, and the fifth gate contact GC5 to receive the data signal D. Therefore, the second PMOS transistor P2 and the second NMOS transistor N2 can be selected by the data signal D.

[0376] The fifth gate contact GC5 and the first gate contact path VG1, which are electrically connected to the first gate structure 200, are shown in this figure as being disposed on the first active region ACT1, but are not limited thereto, and can be disposed as follows: Figure 44 The settings shown are on the second active region ACT2.

[0377] A first gate contact GC1 extending in the z-direction can be disposed on the second gate structure 210. Furthermore, a second gate contact path VG2 extending in the z-direction can be disposed on the first gate contact GC1. The second gate contact path VG2 can be connected to a first / second metal line M1_2 extending in the first direction x. That is, the second gate structure 210 can be electrically connected to the first / second metal line M1_2, the second gate contact path VG2, and the first gate contact GC1 to receive a first clock signal En. Therefore, the first PMOS transistor P1 can be selected by the first clock signal En.

[0378] The locations of the first gate contact GC1 and the second gate contact path VG2 electrically connected to the second gate structure 210 are not limited to this.

[0379] A third gate contact GC3 extending in the z-direction can be disposed on the third gate structure 220. Furthermore, a third gate contact path VG3 extending in the z-direction can be disposed on the third gate contact GC3. The third gate contact path VG3 can be connected to a first-third metal line M1_3 extending in the first direction x. That is, the third gate structure 220 can be electrically connected to the first-third metal line M1_3, the third gate contact path VG3, and the third gate contact GC3 to receive a second clock signal. Therefore, the first NMOS transistor N1 can be controlled by the second clock signal. Selected.

[0380] The locations of the third gate contact GC3 and the third gate contact path VG3 electrically connected to the third gate structure 220 are not limited to this.

[0381] A second gate contact GC2 extending in the z-direction can be disposed on the fourth gate structure 230. Furthermore, a fourth gate contact path VG4 extending in the z-direction can be disposed on the second gate contact GC2. The fourth gate contact path VG4 can be connected to a first-fifth metal line M1_5 extending in the first direction x. That is, the fourth gate structure 230 can be electrically connected to the first-fifth metal line M1_5, the fourth gate contact path VG4, and the second gate contact GC2 to receive a second clock signal. Therefore, the third PMOS transistor P3 can be controlled by the second clock signal. Selected.

[0382] The locations of the second gate contact GC2 and the fourth gate contact path VG4 electrically connected to the fourth gate structure 230 are not limited to this.

[0383] A fourth gate contact GC4 extending in the z-direction can be disposed on the fifth gate structure 240. Furthermore, a fifth gate contact path VG5 extending in the z-direction can be disposed on the fourth gate contact GC4. The fifth gate contact path VG5 can be connected to a first-sixth metal line M1_6 extending in the first direction x. That is, the fifth gate structure 240 is electrically connected to the first-sixth metal line M1_6, the fifth gate contact path VG5, and the fourth gate contact GC4 to receive a first clock signal En. Therefore, the third NMOS transistor N3 can be selected by the first clock signal En.

[0384] The locations of the fourth gate contact GC4 and the fifth gate contact path VG5 electrically connected to the fifth gate structure 240 are not limited to this.

[0385] A sixth gate contact GC6 extending in the z-direction can be disposed on the sixth gate structure 250. Furthermore, a sixth gate contact path VG6 extending in the z-direction can be disposed on the sixth gate contact GC6. The sixth gate contact path VG6 can be connected to a first-seventh metal line M1_7 extending in the first direction x. That is, the sixth gate structure 250 can be electrically connected to the first-seventh metal line M1_7, the sixth gate contact path VG6, and the sixth gate contact GC6 to receive a scan input signal Si. Therefore, the fourth PMOS transistor P4 and the fourth NMOS transistor N4 can be selected by the scan input signal Si.

[0386] The sixth gate contact GC6 and the sixth gate contact path VG6, electrically connected to the sixth gate structure 250, are shown in this figure as being disposed on the second active region ACT2, but are not limited thereto, and can be as follows: Figure 44 The settings shown are on the first active region ACT1.

[0387] A fifth source / drain contact path VSD5 extending in the z-direction can be disposed on the fifth source / drain contact 140. Furthermore, a first / fourth metal line M1_4 extending in the x-direction can be disposed on the fifth source / drain contact path VSD5 and can be connected to an external source.

[0388] The fifth source / drain contact path VSD5, electrically connected to the fifth source / drain contact 140, is shown in this figure as being disposed on the first active region ACT1, but is not limited thereto, and can be as follows: Figure 44 The settings shown are on the second active region ACT2.

[0389] A plurality of gate structures (e.g., first gate structures 200 to sixth gate structures 250) and a plurality of source / drain contacts (e.g., first source / drain contacts 100 to eighth source / drain contacts 170) that are adjacent to each other in the first direction x can be spaced apart from each other by 1 CPP. As an example, the first gate structure 200 and the first source / drain contact 100 that are adjacent to each other can be spaced apart from each other by 1 CPP.

[0390] For example, suppose the first gate structure 200 and the first source / drain contact 100 are adjacent to each other. When the distance between the center line of the first gate structure 200 extending in the second direction y and the center line of the first source / drain contact 100 extending in the second direction y is 1 CPP, this means that no other gate structure or source / drain contact is provided between the first gate structure 200 and the first source / drain contact 100.

[0391] Furthermore, metal lines that are adjacent to each other in the second direction y (e.g., first metal line M1_1 to first seventh metal line M1_7) can be spaced apart by 1 CPP. As an example, the first metal line M1_1 and the first third metal line M1_3 that are adjacent to each other can be spaced apart by 1 CPP (see reference). Figure 44 ).

[0392] For example, suppose the first metal wire M1_1 and the first third metal wire M1_3 are adjacent to each other. When the distance between the center line of the first metal wire M1_1 extending in the first direction x and the center line of the first third metal wire M1_3 extending in the first direction x is 1 CPP, this means that there are no other metal wires between the first metal wire M1_1 and the first third metal wire M1_3.

[0393] In concluding this detailed description, those skilled in the art will recognize that many variations and modifications can be made to the exemplary embodiments without substantially departing from the principles of the inventive concept. Therefore, the disclosed exemplary embodiments are used in a general and descriptive sense only and not for limiting purposes.

[0394] This application claims priority to Korean Patent Application No. 10-2019-0171535, filed on December 20, 2019, with the Korean Intellectual Property Office, and Korean Patent Application No. 10-2020-0069127, filed on June 8, 2020, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. An integrated circuit, comprising: The first active region and the second active region extend in a first direction and are spaced apart from each other in a second direction that intersects the first direction; A power rail extends in the first direction and is spaced apart from the first active region in the second direction; A grounding rail extends in the first direction and is spaced apart from the second active region and the power rail in the second direction; A first source / drain contact extends in the second direction over at least a portion of the first active region and is configured to receive power from the power rail through the first source / drain contact path; A second source / drain contact extends in the second direction, is spaced apart from the first source / drain contact in the second direction on at least a portion of the second active region, and is connected to the ground rail via a second source / drain contact path to be grounded; A first gate structure extends in the second direction and is spaced apart from the first source / drain contact and the second source / drain contact in the first direction on at least a portion of the first active region and at least a portion of the second active region; A third source / drain contact extends in the second direction and is located on at least a portion of the first active region and at least a portion of the second active region, so as to be spaced apart from the first gate structure in the first direction; A second gate structure extends in the second direction and is spaced apart from the third source / drain in the first direction at at least a portion of the first active region. A third gate structure extends in the second direction and is spaced apart from the third source / drain in the first direction and from the second gate structure in the second direction on at least a portion of the second active region; A fourth source / drain contact is spaced apart from the second gate structure and the third gate structure in the first direction on at least a portion of the first active region and at least a portion of the second active region. A fourth gate structure extends in the second direction and is spaced apart from the fourth source / drain in the first direction on at least a portion of the first active region; A fifth gate structure extends in the second direction and is spaced apart from the fourth source / drain in the first direction and from the fourth gate structure in the second direction on at least a portion of the second active region; A fifth source / drain contact is located on at least a portion of the first active region and at least a portion of the second active region, spaced apart from the fourth gate structure and the fifth gate structure in the first direction; A sixth gate structure extends in the second direction and is spaced apart from the fifth source / drain in the first direction at least a portion of the first active region and at least a portion of the second active region. A sixth source / drain contact extends in the second direction and is on at least a portion of the first active region, spaced apart from the sixth gate structure in the first direction; as well as A seventh source / drain contact extends in the second direction and is spaced apart from the sixth gate structure in the first direction and from the sixth source / drain contact in the second direction at least a portion of the second active region.

2. The integrated circuit according to claim 1, wherein The first active region includes a first active fin that protrudes from the first active region in a third direction and extends in the first direction. The second active region includes a second active fin, which protrudes from the second active region in the third direction, extends in the first direction, and is spaced apart from the first active fin in the second direction. The third direction intersects with the first direction and the second direction.

3. The integrated circuit according to claim 2, wherein The first active fin includes a first fin and a second fin, the second fin being spaced apart from the first fin in the second direction, and The second active fin includes a third fin and a fourth fin, wherein the fourth fin is spaced apart from the third fin in the second direction.

4. The integrated circuit according to claim 2, wherein The first gate structure and the sixth gate structure surround the first active fin and the second active fin. The second gate structure and the fourth gate structure surround the first active fin, and The third gate structure and the fifth gate structure surround the second active fin.

5. The integrated circuit according to claim 1, further comprising: A third source / drain contact path is connected to the sixth source / drain contact and configured to transfer the power from the power rail to the sixth source / drain contact; as well as A fourth source / drain contact path is connected to the seventh source / drain contact and configured to ground the seventh source / drain contact to the ground rail.

6. The integrated circuit according to claim 1, further comprising: A first metal line is configured to transmit a first signal via a first gate contact connected to the first gate structure; The second metal line is configured to transmit a second signal via a second gate contact connected to the second gate structure; A third metal line is configured to transmit a third signal via a third gate contact connected to the third gate structure; A fourth metal line is configured to transmit the third signal via a fourth gate contact connected to the fourth gate structure; The fifth metal line is configured to transmit the second signal via a fifth gate contact connected to the fifth gate structure; as well as The sixth metal line is configured to transmit a fourth signal via a sixth gate contact connected to the sixth gate structure.

7. The integrated circuit of claim 6, wherein the first gate contact is on the first active region or the second active region.

8. The integrated circuit of claim 6, wherein the sixth gate contact is on the first active region or the second active region.

9. The integrated circuit of claim 1, wherein each of the first source / drain contact and the sixth source / drain contact has a raised or recessed shape at its end in the second direction.

10. The integrated circuit of claim 1, wherein the mutually facing ends of the second gate structure and the third gate structure, and the mutually facing ends of the fourth gate structure and the fifth gate structure, have a raised shape or a recessed shape.

11. An integrated circuit, comprising: A first inverter includes a first p-channel metal-oxide-semiconductor (PMOS) transistor and a first n-channel metal-oxide-semiconductor (NMOS) transistor, the first PMOS transistor and the first NMOS transistor being selected via a first metal line, a first input voltage being configured to be applied to the first metal line, and the first inverter being configured to output a first inverted voltage by inverting the first input voltage, wherein the drain of the first NMOS transistor and the drain of the first PMOS transistor are connected via a first source / drain contact, the first metal line extends in a first direction, and the first source / drain contact extends in a second direction perpendicular to the first direction; A first transmission gate includes a second PMOS transistor and a second NMOS transistor. The second PMOS transistor is selected via a second metal line, and a first active voltage is configured to be applied to the second metal line. The second NMOS transistor is selected via a third metal line, and a second active voltage is configured to be applied to the third metal line. The source of the second PMOS transistor and the drain of the second NMOS transistor are connected via a first source / drain contact, and the drain of the second PMOS transistor and the source of the second NMOS transistor are connected via a second source / drain contact. as well as A first tri-state inverter includes a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor, and a fourth NMOS transistor. The third PMOS transistor is selected via a fourth metal line, and a second active voltage is configured to be applied to the fourth metal line. The third NMOS transistor is selected via a fifth metal line, and a first active voltage is configured to be applied to the fifth metal line. The fourth PMOS transistor and the fourth NMOS transistor are selected via a sixth metal line, and a second input voltage is configured to be applied to the sixth metal line. The first tri-state inverter is configured to invert the second input voltage, wherein the drain of the third PMOS transistor and the drain of the third NMOS transistor are connected via a second source / drain contact.

12. The integrated circuit according to claim 11, further comprising: A first active region extends in the first direction and includes the first PMOS transistor to the fourth PMOS transistor; The second active region extends in the first direction and includes the first NMOS transistor to the fourth NMOS transistor; A power rail extends in the first direction and is configured to supply power voltage to the first PMOS transistor and the fourth PMOS transistor; as well as A ground rail extends in the first direction and is configured to supply ground voltage to the first NMOS transistor and the fourth NMOS transistor. The first active region and the second active region are spaced apart by a first distance in a second direction that intersects with the first direction. The first active region and the power rail are spaced apart from each other by a second distance in the second direction, and The second active region and the grounding rail are spaced apart from each other by a third distance in the second direction.

13. The integrated circuit of claim 12, wherein the second distance is equal to the third distance.

14. The integrated circuit of claim 12, wherein the sum of the second distance and the third distance is greater than the first distance.

15. The integrated circuit of claim 12, wherein the sum of the second distance and the third distance is less than the first distance.

16. The integrated circuit according to claim 11, further comprising: The first gate contact, through which the first metal line applies the first input voltage; The second gate contact through which the first active voltage is applied by the second metal line; A third gate contact through which the second active voltage is applied; A fourth gate contact through which the second active voltage is applied; The fifth gate contact, through which the fifth metal line applies the first active voltage; and The sixth gate contact through which the second input voltage is applied by the sixth metal line.

17. The integrated circuit according to claim 11, further comprising: A first active region extends in the first direction and includes the first PMOS transistor to the fourth PMOS transistor, wherein the first metal line applies the first gate contact through which the first input voltage is applied, the second metal line applies the first gate contact through which the first active voltage is applied, and the fourth metal line applies the second active voltage through which the fourth gate contact is applied on the first active region. The second active region extends in the first direction and includes the first NMOS transistor to the fourth NMOS transistor, wherein the third metal line applies the second active voltage through a third gate contact, the fifth metal line applies the first active voltage through a fifth gate contact, and the sixth metal line applies the second input voltage through a sixth gate contact on the second active region. A power rail extends in the first direction and is configured to supply power voltage to the first PMOS transistor and the fourth PMOS transistor; as well as A ground rail extends in the first direction and is configured to supply ground voltage to the first NMOS transistor and the fourth NMOS transistor. The first active region and the power rail are spaced apart from each other by a first distance in the second direction, and The second active region and the grounding rail are spaced apart from each other by a second distance in the second direction.

18. An integrated circuit, comprising: The first inverter is configured to invert the first input voltage and output a first inverted voltage; The first transmission gate is configured to receive the first inverted voltage; The second inverter is configured to invert the second input voltage and output a second inverted voltage. as well as The second transmission gate is configured to receive the second inverted voltage. The first transmission gate includes a first n-channel metal-oxide-semiconductor (NMOS) transistor and a first p-channel metal-oxide-semiconductor (PMOS) transistor spaced apart from each other in a first direction. The drain of the first NMOS transistor and the source of the first PMOS transistor are connected by a first source / drain contact extending in the first direction, and the first transmission gate receives the first inverted voltage through the first source / drain contact. The second transmission gate includes a second NMOS transistor and a second PMOS transistor spaced apart from each other in the first direction, wherein the drain of the second NMOS transistor and the source of the second PMOS transistor are connected by a second source / drain contact extending in the first direction, and the second transmission gate receives the second inverted voltage through the second source / drain contact. The source of the first NMOS transistor, the drain of the first PMOS transistor, the source of the second NMOS transistor, and the drain of the second PMOS transistor are connected to each other through a third source / drain contact extending in the first direction. The first NMOS transistor and the second PMOS transistor are selected by a first active voltage, and The first PMOS transistor and the second NMOS transistor are selected by a second active voltage.

19. The integrated circuit according to claim 18, further comprising: The first gate contact is configured to apply the second active voltage to the first PMOS transistor; The second gate contact is configured to apply the first active voltage to the second PMOS transistor; The third gate contact is configured to apply the first active voltage to the first NMOS transistor; as well as The fourth gate contact is configured to apply the second active voltage to the second NMOS transistor. The first gate contact and the second gate contact are at the same height in the first direction.

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