switching device

Abstract

Provided is a switching device capable of preventing a current from flowing sharply and capable of quickly starting. The switching device includes a first P-type MOS transistor, a first control circuit, and a second control circuit. A gate of the first P-type MOS transistor and the first control circuit and the second control circuit are electrically connected to a first node. The first control circuit is configured to lower a voltage of the first node from a first time at which the first P-type MOS transistor is in an off state to a second time. The second control circuit is configured to lower the voltage of the first node from a third time to a fourth time at which the first P-type MOS transistor is in an on state. The second time is a time later than the first time. The fourth time is a time later than the second time and the third time. The first P-type MOS transistor is in the on state during the first time. The first control circuit lowers the voltage of the first node per unit time more than the second control circuit.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2022-25841 (filed on February 22, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The implementation methods generally involve switching devices. Background Technology

[0004] Switching devices are used in electrical control and other applications. Such switching devices are required to prevent sudden current outflow and to enable rapid start-up. Summary of the Invention

[0005] One embodiment provides a switching device that can prevent a sudden outflow of current and enable rapid start-up.

[0006] The switching device of this embodiment includes a first P-type MOS transistor, a first control circuit, and a second control circuit. The gate of the first P-type MOS transistor is connected to a first node. The first and second control circuits are electrically connected to the first node. The first control circuit is configured to reduce the voltage of the first node from a first moment when the first P-type MOS transistor is in the off state to a second moment. The second control circuit is configured to reduce the voltage of the first node during a first time period from a third moment to a fourth moment when the first P-type MOS transistor is in the on state. The second moment is a moment delayed from the first moment. The fourth moment is a moment delayed from both the second and third moments. The first P-type MOS transistor becomes in the on state during the first time period. The voltage of the first node reduced by the first control circuit per unit time is greater than the voltage of the first node reduced by the second control circuit per unit time. The first control circuit includes a second P-type MOS transistor, a third P-type MOS transistor, and a first N-type MOS transistor. One end of the second P-type MOS transistor is connected to a voltage source. The third P-type MOS transistor is connected between the other end of the second P-type MOS transistor and the first node, and the gate of the third P-type MOS transistor is connected to the first node. The first N-type MOS transistor is electrically connected between the first node and a first power supply with a voltage lower than that of the voltage source. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a configuration example of the system according to the first embodiment.

[0008] Figure 2 This is a block diagram illustrating a configuration example of the load switch IC according to the first embodiment.

[0009] Figure 3This is a circuit diagram illustrating an example of the circuit configuration of the load switch IC according to the first embodiment.

[0010] Figure 4 This is a timing diagram showing the state of the signal at the moment when the load switch IC of the first embodiment switches from off to on.

[0011] Figure 5 This is a circuit diagram illustrating an example of the connection state of the load switch IC in the first embodiment, representing the period from time t0 to time t1.

[0012] Figure 6 This is a circuit diagram illustrating an example of the connection state of the load switch IC in the first embodiment between time t1 and time t2.

[0013] Figure 7 This is a circuit diagram illustrating an example of the connection state of the load switch IC in the first embodiment during the period from time t3 to time t6.

[0014] Figure 8 This is a circuit diagram illustrating an example of the circuit configuration of the load switch IC in a comparative example of the first embodiment.

[0015] Figure 9 This is a timing diagram showing the state of the signal at the moment when the load switch IC of the comparative example of the first embodiment switches from off to on.

[0016] Figure 10 This is a timing diagram showing the state of the signal at the moment when the load switch IC of the modified example of the first embodiment switches from off to on, according to time.

[0017] Figure 11 This is a circuit diagram illustrating an example of the circuit configuration of the load switch IC in the second embodiment.

[0018] Figure 12 This is a timing diagram showing the state of the signal at the moment when the load switch IC of the second embodiment switches from off to on. Detailed Implementation

[0019] The following embodiments are described with reference to the accompanying drawings. Each embodiment illustrates an apparatus and method for embodying the technical concept of the invention. The drawings are schematic or conceptual, and the dimensions and proportions of each drawing may not be identical to reality. Unless explicitly or obviously excluded, the description of one embodiment applies to the description of other embodiments. The technical concept of the present invention is not limited by the shape, structure, or arrangement of its constituent elements.

[0020] Furthermore, in the following description, the same reference numerals are used to denote constituent elements that have substantially the same function and structure. The numbers following the text in the reference numerals are used to distinguish elements that are referred to using reference numerals containing the same text and have the same structure from one another. Where it is not necessary to distinguish elements indicated by reference numerals containing the same text from one another, these elements are referred to using reference numerals containing only text.

[0021] [1] First implementation method

[0022] [1-1] Structure (Construction)

[0023] The load switch IC104 of the first embodiment will be described below.

[0024] [1-1-1] Composition of System 300

[0025] Figure 1 This is a block diagram illustrating an example configuration of system 300 according to the first embodiment. System 300 can be implemented as a system for connecting various electrical appliances to an external power source. Figure 1 As shown, system 300 includes an external power supply 200 and an electrical appliance 100. The external power supply 200 supplies power to the electrical appliance 100 from the outside.

[0026] Appliance 100 includes various electrical appliances that are connected to an external power source, such as smartphones and tablets. Appliance 100 includes an AC-DC converter 101, a DC-DC converter 102, a microcontroller 103, a load switch IC 104, and an application module 105.

[0027] AC-DC converter 101 converts the AC voltage supplied from external power supply 200 into DC voltage. DC-DC converter 102 converts the DC voltage supplied from AC-DC converter 101 into a DC voltage suitable for operating application module 105. The DC voltage suitable for operating application module 105 is, for example, the input voltage VDD.

[0028] Microcontroller 103 controls electrical appliance 100. Microcontroller 103 operates based on code (program) stored in a storage medium. Microcontroller 103 generates a control signal EN based on the code. Microcontroller 103 outputs the generated control signal EN to load switch IC 104 (switching device). The control signal EN contains signals for causing electrical appliance 100 to operate. Electrical appliance 100, for example, switches between on and off states based on the control signal EN.

[0029] The load switch IC 104 is supplied with an input voltage VDD from the DC-DC converter 102. The load switch IC 104 receives a control signal EN from the microcontroller 103. Based on the control signal EN, the load switch IC 104 controls the power supply to the application module 105. That is, the load switch IC 104 is configured in system 300 between the external power supply 200 and the application module 105, and controls the power supply to the application module 105. Details of the load switch IC 104 will be described later.

[0030] [1-1-2] Composition of load switch IC104

[0031] Figure 2 This is a block diagram illustrating an example configuration of the load switch IC104 according to the first embodiment. For example... Figure 2 As shown, the load switch IC104 includes a switching PMOS transistor P1, a pre-discharge circuit 1, a slew rate control circuit 2, and a control circuit 3.

[0032] The switching PMOS transistor P1 functions as a switch to toggle whether a voltage is applied to the application module 105. One end of the switching PMOS transistor P1 is connected to the node of the power supply voltage VDD. The node of the power supply voltage VDD is, for example, supplied with a voltage of a certain magnitude of VDD by the DC-DC converter 102. The other end of the switching PMOS transistor P1 is connected to the application module 105. The gate of the switching PMOS transistor P1 is connected to node S1.

[0033] When the switching PMOS transistor P1 is off, no voltage is applied to the application module 105. When the switching PMOS transistor P1 is on, the application module 105 is supplied with an output voltage VOUT, and an output current IOUT flows into the application module 105.

[0034] The control circuit 3 controls the pre-discharge circuit 1 and the slew rate control circuit 2 based on the control signal EN received from the microcontroller 103.

[0035] The pre-discharge circuit 1 controls the voltage applied to the gate of the switching PMOS transistor P1, i.e., node S1. The pre-discharge circuit 1 lowers the potential of node S1 from the input voltage VDD to the startup voltage Von. The startup voltage Von is a voltage that is less than the supply voltage VDD by an amount less than the threshold voltage Vthp of the switching PMOS transistor P1. In other words, startup voltage Von = supply voltage VDD - threshold voltage Vthp. That is, the potential of node S1 is lowered by the pre-discharge circuit 1 to the potential at which the switching PMOS transistor P1 turns on (= startup voltage Von). At the point when the potential of node S1 reaches the startup voltage Von, the switching PMOS transistor P1 turns on. A detailed explanation of the pre-discharge circuit 1 is provided later.

[0036] The slew rate control circuit 2 controls the current flowing into the application module 105. The current flowing into the application module 105 is sometimes referred to as the output current IOUT. The slew rate control circuit 2 further lowers the potential of node S1, which has been reduced to the starting voltage Von by the pre-discharge circuit 1. At this time, the slew rate control circuit 2 applies a gradually changing voltage to node S1, gradually lowering the potential of node S1. By gradually lowering the potential of node S1, the current flowing into the application module 105 gradually increases.

[0037] If the output current IOUT increases sharply, it may cause malfunctions in the application module 105. Therefore, the slew rate control circuit 2 applies a gradually changing voltage to node S1 to prevent current from flowing sharply into the application module 105.

[0038] Figure 3 Indicates in Figure 2 The specific circuit configuration of the load switch IC104 in the first embodiment shown in the description is as follows. Figure 3 As shown, the slew rate control circuit 2 includes a resistor R1 and an NMOS transistor N1. One end of the resistor R1 is connected to node S1. The other end of the resistor R1 is connected to one end of the NMOS transistor N1. The other end of the NMOS transistor N1 is connected to a node with a ground voltage VSS (e.g., 0V). The gate of the NMOS transistor N1 is connected to node S0.

[0039] The pre-discharge circuit 1 includes a resistor R2, an NMOS transistor N2, and PMOS transistors P2 and P3. One end of PMOS transistor P2 is connected to the node of the power supply voltage VDD. The other end of PMOS transistor P2 is connected to one end of PMOS transistor P3. The gate of PMOS transistor P2 is connected to node S2.

[0040] The other end of PMOS transistor P3 is connected to one end of resistor R2. The gate of PMOS transistor P3 is connected to node S1. That is, PMOS transistor P3 is diode-connected. PMOS transistor P3 and the switching PMOS transistor P1 form a current mirror.

[0041] The threshold voltage of PMOS transistor P3 is, for example, the same threshold voltage Vthp as that of switching PMOS transistor P1. The threshold voltage of PMOS transistor P3 is sometimes set to a value lower than the threshold voltage Vthp, as will be shown in a variation.

[0042] The other end of resistor R2 is connected to one end of NMOS transistor N2. The other end of NMOS transistor N2 is connected to the node with ground voltage VSS. The gate of NMOS transistor N2 is connected to node S3.

[0043] Control circuit 3 includes PMOS transistor P4, delay circuit 31, and one-shot pulse circuit 32. Details regarding each signal will be provided in [reference needed]. Figure 5 To be discussed later.

[0044] Node S4 receives the control signal EN from microcontroller 103. One end of PMOS transistor P4 is connected to the node with power supply voltage VDD. The other end of PMOS transistor P4 is connected to node S1. The gate of PMOS transistor P4 receives the control signal EN from node S4. PMOS transistor P4 is turned on when the control signal EN is low and turned off when the control signal EN is high.

[0045] Delay circuit 31 controls slew rate control circuit 2. The input of delay circuit 31 receives the control signal EN from node S4. Delay circuit 31 generates a delay signal ENa based on the received control signal EN. The delay signal ENa is a signal that delays the switching time of the control signal EN from low to high by a certain time, i.e., a delay time Δt. When the control signal EN switches from high to low, it is output without this delay. The output of delay circuit 31 sends the delay signal ENa to node S0. Delay circuit 31 controls the conduction time of NMOS transistor N1 in slew rate control circuit 2 by setting the delay time Δt. NMOS transistor N1 becomes on when the delay signal ENa is high and becomes off when the delay signal ENa is low.

[0046] A single-trigger pulse circuit 32 controls the pre-discharge circuit 1. The input of the single-trigger pulse circuit 32 receives the control signal EN from node S4. The single-trigger pulse circuit 32 generates a pulse signal ENP based on the received control signal EN. The pulse signal ENP is a single-trigger pulse signal that becomes active at the moment the control signal EN switches from low to high. The pulse width of the single-trigger pulse signal is, for example, a delay time Δt. The single-trigger pulse circuit 32 can arbitrarily set the pulse width of the pulse signal ENP.

[0047] The first output terminal of the single-trigger pulse circuit 32 outputs a pulse signal ENP_n to node S2. The second output terminal of the single-trigger pulse circuit 32 outputs a pulse signal ENP to node S3. The pulse signal ENP_n is the inverted signal of the pulse signal ENP.

[0048] The single-trigger pulse circuit 32 controls the conduction time of the NMOS transistor N2 and PMOS transistor P2 in the pre-discharge circuit 1 by setting the pulse width of the pulse signals ENP and ENP_n. The NMOS transistor N2 and PMOS transistor P2 are only turned on during the period of the output pulse.

[0049] [1-2] Actions

[0050] Figure 4 This is a timing diagram showing the states of several signals at the moments when the load switch IC104 of the first embodiment switches from off to on, according to time. Figure 4 The timing diagram shows the control signal EN, the delay signal Ena, the pulse signal ENP, the pulse signal ENP_n, the potential of node S1, and the output voltage VOUT.

[0051] At time t0, microcontroller 103 initiates control to turn on application module 105. At time t0, control signal EN is set to low. Because control signal EN is low, delay circuit 31 maintains delay signal Ena at low level at time t0. Because control signal EN is low, single-trigger pulse circuit 32 maintains pulse signal ENP at low level and pulse signal ENP_n at high level. At time t0, the potential of node S1 is the power supply voltage VDD. At time t0, output voltage VOUT is the ground voltage VSS.

[0052] An example of the connection of the load switch IC104 at this time is shown as follows: Figure 5 . Figure 5 This is a circuit diagram illustrating an example of the connection state of the load switch IC104 in the first embodiment during the period from time t0 to time t1. The operation at time t1 is described later. Figure 5As shown, during the period from time t0 to time t1, the PMOS transistor P4 is in the on state because the control signal EN is low.

[0053] During the period from time t0 to time t1, since the delay signal Ena is low, the NMOS transistor N1 is in the off state.

[0054] During the period from time t0 to time t1, the NMOS transistor N2 is in the off state because the pulse signal ENP is low. Similarly, the PMOS transistor P2 is in the off state because the pulse signal ENP_n is high.

[0055] Based on the states of PMOS transistors P2, P3, and P4 and NMOS transistors N1 and N2 as described above, the potential of node S1 is the power supply voltage VDD during the period from time t0 to time t1. Since the potential of node S1 is the power supply voltage VDD, PMOS transistors P1 and P3 are in the off state during the period from time t0 to time t1.

[0056] Since the switching PMOS transistor P1 is in the off state, no voltage from the DC-DC converter 102 is applied to the application module 105 during the period from time t0 to time t1. At this time, the output voltage VOUT is, for example, the ground voltage VSS.

[0057] like Figure 4 As shown, at time t1, the microcontroller 103 begins to shift the control signal EN to a high level. As previously mentioned, the delay signal Ena is a signal that delays the control signal EN from a low level to a high level by a time delay Δt. At time t1, the time delay Δt has not yet elapsed since time t1; therefore, at time t1, the delay signal Ena is at a low level.

[0058] Based on the fact that the control signal EN has been moved to a high level, the single-trigger pulse circuit 32 sets the pulse signal ENP to a high level. After the pulse signal ENP becomes high, the single-trigger pulse circuit 32 maintains the pulse signal ENP at a high level for a delay time Δt. The delay time Δt is equal to the period from time t1 to time t2. That is, from time t1 to time t2 after the delay time Δt, the pulse signal ENP remains at a high level.

[0059] On the other hand, the single-trigger pulse circuit 32 sets the pulse signal ENP_n to a low level based on the fact that the control signal EN has become high. After the pulse signal ENP_n becomes low, the single-trigger pulse circuit 32 maintains the pulse signal ENP_n at a low level for a delay time Δt. That is, from time t1 to time t2, the pulse signal ENP_n remains at a low level.

[0060] At time t1, the pulse signal ENP begins to move to a high level. Based on this high level, NMOS transistor N2 becomes active. Therefore, from time t1, the pre-discharge circuit 1 begins to operate, and the potential of node S1 begins to decrease from the supply voltage VDD. In other words, the potential of node S1 begins to decrease at time t1. At this time, the potential of node S1 decreases by a certain amount per unit time, for example. The degree of decrease in the potential of node S1 depends on the value of resistor R2 and the driving capability of NMOS transistor N2. The potential of node S1 does not reach the starting voltage Von until time t2.

[0061] Although the potential of node S1 begins to decrease from time t1, it does not reach the startup voltage Von during the period from time t1 to time t2. Therefore, during the period from time t1 to time t2, the switching PMOS transistor P1 is in the off state, and the output voltage VOUT is the ground voltage VSS.

[0062] An example of the connection of the load switch IC104 at this time is shown as follows: Figure 6 . Figure 6 This is a circuit diagram illustrating an example of the connection state of the load switch IC104 in the first embodiment between time t1 and time t2. (Example) Figure 6 As shown, during the period from time t1 to time t2, since the control signal EN is high, the PMOS transistor P4 is in the off state.

[0063] During the period from time t1 to time t2, since the delay signal ENa is at a low level, the NMOS transistor N1 is in the off state.

[0064] During the period from time t1 to time t2, since the pulse signal ENP is high, the NMOS transistor N2 is in the on state. Similarly, since the pulse signal ENP_n is low, the PMOS transistor P2 is in the on state.

[0065] Specifically, at time t1, NMOS transistor N2 begins to switch to the on state. As NMOS transistor N2 becomes on, the charge accumulated at node S1 begins to be released. NMOS transistor N2 releases the accumulated charge at node S1 via resistor R2. As the charge is released, the potential of node S1 gradually decreases. However, until time t2, the potential of node S1 does not reach the startup voltage Von.

[0066] During the period from time t1 to time t2, since the potential of node S1 does not reach the starting voltage Von, PMOS transistors P1 and P3 are in the off state. Because PMOS transistor P1 is in the off state, the output voltage VOUT is the ground voltage VSS during the period from time t1 to time t2.

[0067] like Figure 4 As shown, at time t3, the delay circuit 31 sets the delay signal ENa to a high level. Therefore, the NMOS transistor N1 turns on, and the slew rate control circuit 2 begins to operate. Here, time t3 is a time delayed by Δt from time t1. Time t3 is also a time slightly delayed from time t2.

[0068] At time t3, the single-trigger pulse circuit 32 sets the pulse signal ENP to a low level. On the other hand, the single-trigger pulse circuit 32 sets the pulse signal ENP_n to a high level. Therefore, NMOS transistor N2 is turned off, and the control of the potential of node S1 by NMOS transistor N2 ceases. The time at which NMOS transistor N2 is turned off is sometimes set to a time later than time t3; a variation of this example will be shown.

[0069] At time t3, the potential of node S1 reaches the starting voltage Von. As a result, the switching PMOS transistor P1 turns on.

[0070] Starting from time t3, the potential of node S1 continuously decreases under the control of slew rate control circuit 2. At this time, the potential of node S1 decreases by a certain amount per unit time, for example. The degree of decrease in the potential of node S1 depends on the value of resistor R1 and the driving capability of NMOS transistor N1. For example, the decrease in the potential of node S1 per unit time during the period from time t3 to time t5 is smaller than the decrease during the period from time t1 to time t2. That is, the decrease in the potential of node S1 per unit time when the pre-discharge circuit 1 is driven is larger than the decrease when the slew rate control circuit 2 is driven. This is to prevent a rapid influx of current into the application module 105 caused by a sudden application of a voltage below the starting voltage Von to node S1. Details will be described later.

[0071] Given that the switching PMOS transistor P1 is already turned on, starting from time t3, the output voltage VOUT begins to rise from the ground voltage VSS.

[0072] The output voltage VOUT rises from time t3 to time t4. At time t4, the output voltage VOUT rises to voltage Vm. In other words, the output voltage VOUT begins to rise at time t3 and reaches voltage Vm at time t4. Voltage Vm depends on the load value of the application module 105. During this time, the output voltage VOUT rises by a certain amount per unit time, for example. The output voltage VOUT reaches voltage Vm at time t4 and then maintains voltage Vm.

[0073] The potential of node S1 decreases continuously from time t3, reaching the ground voltage VSS at time t5.

[0074] An example of the connection of the load switch IC104 at this time is shown as follows: Figure 7 . Figure 7 This is a circuit diagram illustrating an example of the connection state of the load switch IC104 in the first embodiment, representing the period from time t3 to time t6, which follows time t5. (Example) Figure 7 As shown, during the period from time t3 to time t6, the PMOS transistor P4 is in the off state because the control signal EN is high.

[0075] During the period from time t3 to time t6, since the delay signal Ena is at a high level, the NMOS transistor N1 is in the on state.

[0076] At time t3, NMOS transistor N1 becomes on and begins to release the charge accumulated at node S1. NMOS transistor N1 releases the accumulated charge at node S1 via resistor R1. As the charge is released, the potential of node S1 gradually decreases, reaching ground voltage VSS at time t5.

[0077] Thus, the load switch IC104 in the first embodiment lowers the potential of node S1 to the starting voltage Von through the pre-discharge circuit 1, and then causes the slew rate control circuit 2 to operate.

[0078] During the period from time t3 to time t6, NMOS transistor N2 is off because the pulse signal ENP is low. Similarly, PMOS transistor P2 is off because the pulse signal ENP_n is high. Assuming that PMOS transistor P3 becomes on when NMOS transistor N2 and PMOS transistor P2 are on, this can sometimes cause a through-current to flow between node VDD and node VSS. The load switch IC104 of the first embodiment keeps NMOS transistor N2 and PMOS transistor P2 off during the period from time t3 to time t6, thereby suppressing the through-current.

[0079] At time t3, the potential of node S1 changes to the starting voltage Von, causing switching PMOS transistors P1 and P3 to turn on. Subsequently, from time t3 to time t6, the potential of node S1 continuously decreases, thus keeping switching PMOS transistors P1 and P3 in the on state.

[0080] like Figure 4 As shown, at time t6, the microcontroller 103 begins to shift the control signal EN to a low level. Based on the fact that the control signal EN has been shifted to a low level, the PMOS transistor P4 becomes turned on.

[0081] As mentioned earlier, the delay signal Ena is not delayed from the delay signal En when the control signal EN switches from high to low. Therefore, based on the fact that the control signal EN has already moved to low, the delay circuit 31 makes the delay signal Ena low. Based on the fact that the delay signal Ena has become low, the NMOS transistor N1 becomes off.

[0082] If a delay time is assumed, the NMOS transistor N1 will turn off more slowly than the PMOS transistor P4 will turn on, potentially causing a through current between nodes VDD and VSS. The load switch IC104 in the first embodiment does not set a delay time when the control signal EN switches from high to low, thereby suppressing the through current.

[0083] Since NMOS transistor N1 has become off, the potential of node S1 rises to the power supply voltage VDD.

[0084] Given that the voltage rises to the power supply voltage VDD, the switching PMOS transistor P1 is turned off, and the output voltage VOUT drops to the ground voltage VSS.

[0085] [1-3] Advantages (Effects) of the First Embodiment

[0086] According to the first embodiment described above, the load switch IC104 can prevent a rapid influx of current into the application module 105 when the load switch IC104 is in the ON state, and can quickly start the load switch IC104. The detailed effects of the load switch IC104 of the first embodiment will be explained below.

[0087] The time elapsed until the load switch IC104 starts is sometimes referred to as the output turn-on time ton1. "Load switch IC104 starts" means that the PMOS transistor P1 turns on. The output turn-on time ton1 is the time elapsed from the change of the control signal EN to turn-on until the PMOS transistor P1 turns on. That is, the output turn-on time ton1 of the load switch IC104 is the time from time t1 to time t3. A rapid influx of current into the application module 105 means that the output current IOUT increases rapidly.

[0088] Figure 8 This illustrates an example of the circuit configuration of the load switch IC111 in a comparative example of the first embodiment. The load switch IC111 in the comparative example differs from the load switch IC104 in that it lacks the pre-discharge circuit 1, the delay circuit 31, and the single-trigger pulse circuit 32. Figure 3 The differences are as follows. Regarding other construction aspects, load switch IC111 is largely the same as load switch IC104. The following explanation focuses on the differences between load switch IC111 and load switch IC104. For detailed information on each signal, please refer to [link to relevant documentation]. Figure 9 To be discussed later.

[0089] like Figure 8 As shown, the gate of the switching PMOS transistor P1 is connected to node S1. When the switching PMOS transistor P1 is turned on, the application module 105 is supplied with an output voltage VOUT and an output current IOUT flows in.

[0090] Similar to the slew rate control circuit 2 of the load switch IC104, the slew rate control circuit 2 of the comparative example load switch IC111 has a resistor R1 and an NMOS transistor N1. The gate of the NMOS transistor N1 receives a control signal EN from node S4. The NMOS transistor N1 becomes on when the control signal EN is high and becomes off when the control signal EN is low.

[0091] Figure 9 This is a timing diagram showing the states of several signals at the moments when the load switch IC111 of the comparative example of the first embodiment switches from off to on, according to time. Figure 9 The timing diagram shows the control signal EN of the load switch IC111, the potential of node S1, and the output voltage VOUT. Figure 9 For comparison, it is shown in the middle. Figure 4 The potential of node S1 of the load switch IC104 and the state of the output voltage VOUT are shown. The following mainly describes the differences in waveforms between the load switch IC104 and the first embodiment.

[0092] During the period from time t0 to time t1, the PMOS transistor P4 is in the on state because the control signal EN is low. Meanwhile, the NMOS transistor N1 is in the off state. Therefore, similar to the first embodiment, the switching PMOS transistor P1 is in the off state, and the output voltage VOUT is, for example, the ground voltage VSS.

[0093] At time t1, microcontroller 103 begins to shift the control signal EN to a high level. Based on this high level, NMOS transistor N1 becomes on. Therefore, starting from time t1, the potential of node S1 begins to decrease from the power supply voltage VDD under the control of the slew rate control circuit 2. At this time, the potential of node S1 decreases by a certain amount per unit time, for example. The degree of decrease in the potential of node S1 depends on the value of resistor R1 and the driving capability of NMOS transistor N2.

[0094] Although the potential of node S1 begins to decrease from time t1, during the period from time t1 to time t2', the potential of node S1 does not reach the starting voltage Von. Therefore, during the period from time t1 to time t2', the switching PMOS transistor P1 is in the off state, and the output voltage VOUT is the ground voltage VSS.

[0095] During the period from time t1 to time t2', NMOS transistor N1 is in the on state because the control signal EN is high. Specifically, at time t1, NMOS transistor N1 begins to switch to the on state. As NMOS transistor N1 becomes on, the charge accumulated at node S1 begins to be released. Because the charge is released, the potential of node S1 gradually decreases. However, during the period up to time t2', the potential of node S1 does not reach the startup voltage Von.

[0096] At time t3', the potential of node S1 reaches the start-up voltage Von. Therefore, the switching PMOS transistor P1 turns on. Here, time t3' is slightly later than time t2'.

[0097] As previously stated, the decrease in potential of node S1 per unit time when the pre-discharge circuit 1 is driven is greater than the decrease when the slew rate control circuit 2 is driven. Load switch IC111 lowers the potential of node S1 via slew rate control circuit 2. Load switch IC104 lowers the potential of node S1 to the starting voltage Von via pre-discharge circuit 1. Therefore, the time t3' when the potential of node S1 of load switch IC111 reaches the starting voltage Von is delayed compared to the time t3' when the potential of node S1 of load switch IC104 reaches the starting voltage Von. Therefore, time t2' is delayed compared to t2.

[0098] At time t3', because the control signal EN is high, NMOS transistor N1 remains on. The potential of node S1 continuously decreases under the control of slew rate control circuit 2. During the period from time t1 to time t5', the potential of node S1 decreases by a certain amount per unit time. The potential of node S1 reaches the ground voltage VSS at time t5'. Since time t3' is a time later than time t3, time t5' is a time later than time t5.

[0099] Thus, in the comparative example of the first embodiment, the load switch IC111 lowers the potential of node S1 to the starting voltage Von through the slew rate control circuit 2, and then also activates the slew rate control circuit 2.

[0100] Load switch IC111 is controlled by slew rate control circuit 2 during the period from time t1 to time t5', and load switch IC104 is controlled by slew rate control circuit 2 during the period from time t3 to time t5. Therefore, during the period from time t1 to time t5' for load switch IC111 and the period from time t3 to time t5 for load switch IC104, the decrease in potential per unit time of node S1 is, for example, the same.

[0101] Given that the PMOS transistor P1 is already turned on, starting from time t3', the output voltage VOUT begins to rise from the ground voltage VSS. This rise in output voltage VOUT continues from time t3' to time t4'. The output voltage VOUT rises by the same amount per unit time as the load switch IC104 during the period from time t3 to time t4.

[0102] Thus, the potential of node S1 of load switch IC111 is controlled by the slew rate control circuit 2 to decrease from the power supply voltage VDD to the starting voltage Von. Therefore, the moment when node S1 of load switch IC111 reaches the starting voltage Von is time t3', which is delayed from time t3. Time t3 is the moment when node S1 of load switch IC104 in the first embodiment reaches the starting voltage Von. That is, the time it takes for the potential of node S1 of load switch IC111 to reach the starting voltage Von may be longer than that of node S1 of load switch IC104. In other words, the time it takes for load switch IC111 to turn on may be longer than that of load switch IC104. In other words, the output turn-on time ton1 of load switch IC111 may be longer than that of load switch IC104.

[0103] As mentioned earlier, the slew rate control circuit 2 applies a gradually changing voltage to node S1 to prevent the output current IOUT from increasing abruptly. Therefore, if the slew rate control circuit 2 is removed from the load switch IC in order to shorten the output on-time ton1, the output current IOUT will increase abruptly, which may cause malfunctions in the application module 105, etc.

[0104] In contrast, the load switch IC 104 of the first embodiment includes a pre-discharge circuit 1 and a slew rate control circuit 2 within the load switch IC. Compared to the slew rate control circuit 2, the pre-discharge circuit 1 lowers the potential of node S1 more quickly. Therefore, the load switch IC 104 of the first embodiment can use the pre-discharge circuit 1, and compared to the case where only the slew rate control circuit 2 is used, as in the comparative example, the output turn-on time ton1 can be shortened accordingly.

[0105] As described above, in the first embodiment, the load switch IC104 lowers the potential of node S1 to the startup voltage Von through the pre-discharge circuit 1, and then activates the slew rate control circuit 2. The pre-discharge circuit 1 continues to lower the potential of node S1 until the potential of node S1 reaches the startup voltage Von, i.e., until the switching PMOS transistor P1 is turned on. Therefore, even if the potential of node S1 is rapidly lowered through the pre-discharge circuit 1, the output current IOUT will not flow sharply into the application module 105.

[0106] The load switch IC104 lowers the potential of node S1 only after the potential of node S1 reaches the starting voltage Von. Therefore, the potential of node S1 can be lowered slowly, preventing a sharp increase in the output current IOUT.

[0107] That is, compared with the load switch IC111, the load switch IC104 can shorten the output conduction time ton1 and prevent the output current IOUT from increasing sharply.

[0108] This is because the load switch IC104 has a pre-discharge circuit 1 and a slew rate control circuit 2, which can control the output on-time ton1 and the output current IOUT respectively. Specifically, the load switch IC104 mainly controls the output on-time ton1 through the pre-discharge circuit 1, and mainly controls the output current IOUT through the slew rate control circuit 2. In this way, the load switch IC104 can control the output current IOUT independently of the output on-time ton1.

[0109] Furthermore, in the first embodiment, the load switch IC104 keeps both NMOS transistor N2 and PMOS transistor P2 in the off state during the period from time t3 to time t6, thereby suppressing through current. By suppressing through current, the load switch IC104 in the first embodiment can perform energy-efficient startup.

[0110] [2] Variations of the first embodiment

[0111] <First example>

[0112] In the first embodiment described above, the case where the NMOS transistor N2 and PMOS transistor P2 turn off at the same time as the NMOS transistor N1 turns on (time t3) is illustrated. However, the operation of NMOS transistor N2, PMOS transistor P2, and NMOS transistor N1 is not limited to this. For example, NMOS transistor N2 and PMOS transistor P2 may turn off after NMOS transistor N1 turns on and a certain amount of time has elapsed.

[0113] Figure 10 This is a timing diagram showing the states of several signals at the moments when the load switch IC104 of the modified first embodiment switches from off to on, according to time. The control signal EN, delay signal Ena, pulse signal ENP, pulse signal ENP_n, the potential of node S1, and the output voltage VOUT are referenced. Figure 4 The descriptions are the same, therefore the descriptions are omitted.

[0114] In the load switch IC 104 of the first embodiment described above, an example is shown where the pulse of the pulse signal ENP is set to a low level and the pulse of the pulse signal ENP_n is set to a high level at time t3. In a modified example of the load switch IC 104 of the first embodiment, at time tx, the pulse of the pulse signal ENP is set to a low level and the pulse of the pulse signal ENP_n is set to a high level. Time tx is a time later than time t3 and earlier than time t4.

[0115] In other words, in the modified load switch IC104, the pulse widths of the pulse signals ENP and ENP_n are equal to the pulse width Δtx. The pulse width Δtx is longer than the delay time Δt. That is, in the modified load switch IC104 of the first embodiment, the pulse widths of the pulse signals ENP and ENP_n are longer than the pulse widths of the pulse signals ENP and ENP_n in the load switch IC104 of the first embodiment.

[0116] As previously described, the single-trigger pulse circuit 32 controls the turn-on time of the NMOS transistor N2 and PMOS transistor P2 in the pre-discharge circuit 1 by setting the pulse widths of the pulse signals ENP and ENP_n. Furthermore, as previously described, the delay circuit 31 controls the turn-on time of the NMOS transistor N1 in the slew rate control circuit 2 by setting the delay time Δt.

[0117] That is, in a variation of the first embodiment, the time when NMOS transistor N2 and PMOS transistor P2 become off (time tx) is a time later than the time when NMOS transistor N1 becomes on (time t3).

[0118] In the load switch IC104 of the first embodiment, for example, undesirable delays sometimes occur during the period from when NMOS transistor N2 and PMOS transistor P2 turn off at time t3 until NMOS transistor N1 turns on. Reasons for this undesirability include delays caused by the time required for signal transmission, and deviations in transistor performance. In this case, the switching PMOS transistor P1 may sometimes fail to turn on due to the pre-discharge circuit 1.

[0119] In the modified load switch IC104, the time when NMOS transistor N2 and PMOS transistor P2 are turned off is delayed from time t3 to time tx, thereby ensuring a certain margin for undesirable delays. That is, even if undesirable delays occur, the switching PMOS transistor P1 can be turned on by the pre-discharge circuit 1.

[0120] However, during the period from time t3 to time tx, both the pre-discharge circuit 1 and the slew rate control circuit 2 lower the potential of node S1. Furthermore, during this period, while NMOS transistor N2 and PMOS transistor P2 are conducting, PMOS transistor P3 is also conducting. Therefore, a through-current may occur between node VDD and node VSS. In contrast, by setting time tx as close as possible to time t3, the through-current can be suppressed.

[0121] <Second Example>

[0122] In the first embodiment, an example is shown where the threshold voltage of the PMOS transistor P3 is the same as the threshold voltage Vthp of the switching PMOS transistor P1. However, the threshold voltage of the PMOS transistor P3 is sometimes set to a value lower than the threshold voltage Vthp.

[0123] As mentioned earlier, PMOS transistor P3 and switching PMOS transistor P1 form a current mirror. Therefore, if PMOS transistor P3 is turned on and current flows through it, current also flows through switching PMOS transistor P1. Sometimes, control is implemented to prevent the current from increasing abruptly, i.e., to prevent the output current IOUT from increasing abruptly.

[0124] In the modified load switch IC 104 of the first embodiment, the threshold voltage of PMOS transistor P3 is set to a value lower than the threshold voltage Vthp. In this way, the modified load switch IC 104 can turn on the switching PMOS transistor P1 before PMOS transistor P3. After the switching PMOS transistor P1 turns on (after time t3), the slew rate control circuit 2 operates, thus controlling the output current IOUT in a manner that prevents a sharp increase. That is, the modified load switch IC 104 has a structure in which PMOS transistor P3 is not turned on before the slew rate control circuit 2 operates. Therefore, the modified load switch IC 104 can reduce the risk of a sharp increase in the output current IOUT.

[0125] Furthermore, the modified load switch IC104 can reduce the risk of a sharp increase in output current IOUT caused by the current mirror structure by adjusting the gate length and / or gate width of PMOS transistor P3 and / or switching PMOS transistor P1.

[0126] [3] Second implementation method

[0127] The load switch IC104 of the second embodiment will be described below. The load switch IC104 of the second embodiment is different from the load switch IC104 of the first embodiment. Hereinafter, the load switch IC104 of the second embodiment will sometimes be referred to as load switch IC104b in order to distinguish it from the load switch IC104 of the first embodiment.

[0128] [3-1] Construction of load switch IC104b

[0129] The load switch IC104b in the second embodiment differs from the load switch IC104b in the construction of the delay circuit 31. Hereinafter, the delay circuit 31 of the second embodiment will sometimes be referred to as delay circuit 31b to distinguish it from the delay circuit 31 of the first embodiment. The delay circuit 31b of the load switch IC104b is synchronized with the single trigger pulse circuit 32. Regarding other construction aspects, the second embodiment is largely the same as the first embodiment. Hereinafter, the differences between the load switch IC104b of the second embodiment and the first embodiment will be explained.

[0130] use Figure 11 The construction of the delay circuit 31b will be explained. Figure 11 This is a circuit diagram illustrating a configuration example of the load switch IC104b according to the second embodiment. In the first embodiment, the delay circuit 31 operates asynchronously with the single-trigger pulse circuit 32. Therefore, the delay circuit 31 operates based on a preset delay time Δt, generating a delayed signal ENa. In contrast, the delay circuit 31b in the second embodiment operates triggered by a pulse signal ENP_n sent from the single-trigger pulse circuit 32. That is, the delay circuit 31b is synchronized with the single-trigger pulse circuit 32.

[0131] like Figure 11 As shown, the delay circuit 31b includes a flip-flop circuit 311 and an AND gate 312. Details regarding each signal will be provided in [reference needed]. Figure 12 To be discussed later.

[0132] The trigger circuit 311 outputs a signal generated from its output terminal Q based on the signal supplied to the data input terminal D and the pulse signal ENP_n. Hereinafter, the signal output from the output terminal Q is sometimes referred to as the output signal Q. The data input terminal D of the trigger circuit 311 is connected to the node of the power supply voltage VDD. The clock input terminal CK of the trigger circuit 311 is connected to node S2. The clock input terminal CK of the trigger circuit 311 receives the pulse signal ENP_n sent from the single trigger pulse circuit 32. The pulse signal ENP_n is used as a clock signal within the trigger circuit 311. The trigger circuit 311 maintains the level supplied to the data input terminal D at the moment the pulse signal ENP_n switches from low to high, and outputs the maintained level from the output terminal Q, that is, switches the output signal Q to high. The output signal Q, switched to high, remains high until the data held within the trigger circuit 311 is reset by the conditions described later.

[0133] The reset signal input terminal CLR of the trigger circuit 311 receives the control signal EN from node S4. If the control signal EN received from the reset signal input terminal CLR goes low, the trigger circuit 311 resets the data held in the trigger circuit 311 and continuously outputs a low-level signal.

[0134] The first input of AND gate 312 receives the control signal EN from node S4. The second input of AND gate 312 receives the output signal Q from flip-flop circuit 311. The output of AND gate 312 is connected to node S0. AND gate 312 sends the logic product of the signal received from the first input and the signal received from the second input, i.e., the delayed signal ENb, from its output to node S0. The gate of NMOS transistor N1 receives the delayed signal ENb from node S0.

[0135] [3-2] Action

[0136] Figure 12 This is a timing diagram showing the states of several signals as the load switch IC104b of the second embodiment switches from off to on, arranged chronologically. The control signal EN, pulse signal ENP, pulse signal ENP_n, the potential of node S1, and the output voltage VOUT are referenced. Figure 4 The descriptions are the same, so they are omitted. The following mainly describes the delayed signal ENb and the output signal Q.

[0137] At time t0, the trigger circuit 311 is in a reset state, maintaining the output signal Q at a low level. At time t0, the control signal EN is low, and the output signal Q is low, therefore the AND gate 312 maintains the delayed signal ENb at a low level.

[0138] At time t1, microcontroller 103 begins to shift the control signal EN to a high level. At time t1, trigger circuit 311 is in a reset state, maintaining the output signal Q at a low level. During the period after time t1 and before time t2, the control signal EN is high and the output signal Q is low, therefore AND gate 312 maintains the delayed signal ENb at a low level.

[0139] At time t2, the pulse signal ENP_n is low. Therefore, the output signal Q is low. At time t2, the control signal EN is high, and the output signal Q is low, so AND gate 312 keeps the delayed signal ENb low.

[0140] At time t3, the pulse signal ENP_n switches from low to high. As mentioned earlier, the trigger circuit 311 switches the output signal Q to high when the pulse signal ENP_n switches from low to high. Therefore, at time t3, the output signal Q shifts from low to high.

[0141] At time t3, the control signal EN is high and the output signal Q is high, so AND gate 312 shifts the delayed signal ENb to high.

[0142] At time t6, microcontroller 103 begins to shift the control signal EN to a low level. As previously mentioned, if the received control signal EN is shifted low, the trigger circuit 311 maintains the output signal Q at a low level. Based on the fact that the control signal EN has been shifted low, the trigger circuit 311 shifts the output signal Q from a high level to a low level. At this time, the control signal EN is low, and the output signal Q is low, therefore AND gate 312 maintains the delayed signal ENb at a low level.

[0143] As shown above, the timing diagram for the delayed signal ENb is the same as that for the delayed signal ENA. Therefore, the timing diagrams for the potential of node S1 and the output voltage VOUT, as well as the operation and reference of each transistor, are also included. Figure 4 The descriptions are the same, so the descriptions are omitted.

[0144] [3-3] Advantages (Effects) of the Second Embodiment

[0145] The load switch IC104b according to the second embodiment described above, like the first embodiment, can shorten the output on-time ton1 of the load switch IC104b and prevent the output current IOUT from increasing sharply. Furthermore, the load switch IC104b according to the second embodiment can synchronize the operation of the pre-discharge circuit 1 with the timing of driving the slew rate control circuit 2.

[0146] First, according to the second embodiment of the load switch IC104b, similar to the first embodiment, the output current IOUT can be controlled independently of the output on-time ton1 by having a pre-discharge circuit 1 and a slew rate control circuit 2. Therefore, similar to the first embodiment, compared to the load switch IC111, the load switch IC104b can shorten the output on-time ton1 and prevent the output current IOUT from increasing sharply.

[0147] Furthermore, according to the second embodiment of the load switch IC104b, similar to the first embodiment, the NMOS transistor N2 and the PMOS transistor P2 are turned off during the period from time t3 to time t6, thereby suppressing through current. The load switch IC104 of the first embodiment can perform energy-efficient startup by suppressing through current.

[0148] Furthermore, the delay circuit 31 and the single-trigger pulse circuit 32 in the first embodiment operate asynchronously. Therefore, when the delay circuit 31 is given a margin as in the modified example, there is a possibility that both the slew rate control circuit 2 and the pre-discharge circuit 1 lower the potential of node S1.

[0149] In contrast, the load switch IC104b of the second embodiment can synchronize the operation of the pre-discharge circuit 1 with the timing of driving the slew rate control circuit 2. As mentioned above, the delay circuit 31b of the second embodiment is triggered by the pulse signal ENP_n sent from the single-trigger pulse circuit 32. By using the pulse signal ENP_n as the trigger, the delay circuit 31b can synchronize the action of turning off the NMOS transistor N2 and the PMOS transistor P2 at time t3 with the action of turning on the NMOS transistor N1.

[0150] Therefore, the load switch IC104b in the second embodiment does not need to adjust the pulse width Δtx of the pulse signal ENP_n and the delay time Δt of the delay signal Ena as in the variation of the first embodiment.

[0151] As a result, the load switch IC104b of the second embodiment can prevent both the slew rate control circuit 2 and the pre-discharge circuit 1 from lowering the potential of node S1. That is, according to the load switch IC104b, compared with the load switch IC104 of the first embodiment, it can more effectively prevent the output current IOUT from increasing sharply.

[0152] Furthermore, according to the load switch IC104b, there will be no situation where NMOS transistor N2 and PMOS transistor P2 are turned on simultaneously, and PMOS transistor P3 is also turned on at the same time. Therefore, it is possible to prevent through current from flowing between node VDD and node VSS.

[0153] [4] Other variations, etc.

[0154] In the first and second embodiments, the load switches IC104 and 104b may also be constructed in other ways.

[0155] In this specification, "connection" means electrical connection, and does not exclude situations where there are other components in between, for example. "Electrical connection" can also be via an insulator, as long as it can operate in the same way as the electrically connected component.

[0156] "Approximately the same" refers to a moment that includes, for example, an error that introduces unwanted delays, such as the time required to transmit signals.

[0157] The first and second embodiments of the present invention are provided as examples and are not intended to limit the scope of the invention. The first and second embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. The first and second embodiments and their variations are included in the scope and spirit of the invention, and are also included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A switching device, characterized in that, have: The first P-type MOS transistor has its gate connected to the first node; A first control circuit is electrically connected to the first node; as well as The second control circuit is electrically connected to the first node; The first control circuit is configured to reduce the voltage of the first node from a first moment when the first P-type MOS transistor is in the off state to a second moment. The second control circuit is configured to reduce the voltage of the first node during a first time period from the third time point to the fourth time point when the first P-type MOS transistor is in the on state. The second moment is a moment that is delayed compared to the first moment. The fourth time point is a time point that is delayed compared to the second time point and the third time point. The first P-type MOS transistor becomes in the on state during the first time period. In the first control circuit, compared to the second control circuit, the voltage of the first node decreases more per unit time. The first control circuit includes: The second P-type MOS transistor has one end connected to a voltage source; A third P-type MOS transistor is connected between the other end of the second P-type MOS transistor and the first node, and its gate is connected to the first node; as well as A first N-type MOS transistor is electrically connected between the first node and a first power supply with a voltage lower than that of the voltage source.

2. The switching device according to claim 1, characterized in that, Also includes: A pulse circuit that controls the first control circuit; and A delay circuit that controls the second control circuit; One end of the first P-type MOS transistor is connected to the voltage source. The first control circuit further includes a first resistor, which is electrically connected between the first node and one end of the first N-type MOS transistor. The pulse circuit is connected to the gate of the second P-type MOS transistor and the gate of the first N-type MOS transistor, respectively.

3. The switching device according to claim 2, characterized in that, The delay circuit receives the first signal and sends the second signal to the second control circuit. The delay circuit shifts the second signal from low to high by a second time interval after the first signal shifts from low to high. The pulse circuit receives the first signal and sends the third and fourth signals to the gates of the second P-type MOS transistor and the first N-type MOS transistor, respectively. The second control circuit begins to reduce the voltage of the first node based on the fact that the second signal shifts from a low level to a high level. The first signal shifts from a low level to a high level during the period when the first P-type MOS transistor is in the off state. The third signal has a single-triggered pulse that shifts from high to low based on the first signal shifting from low to high. The fourth signal has a single-triggered pulse that shifts from low to high based on the first signal shifting from low to high.

4. The switching device according to claim 3, characterized in that, The first control circuit begins to reduce the voltage of the first node based on the fact that the fourth signal shifts from a low level to a high level.

5. The switching device according to claim 3, characterized in that, The delay circuit has a trigger circuit and receives the third signal from the pulse circuit, and shifts the second signal from low level to high level based on the pulse of the third signal shifting from low level to high level.

6. The switching device according to claim 1, characterized in that, The third time point is the same as the second time point.

7. The switching device according to claim 1, characterized in that, The third moment is a moment that is delayed compared to the second moment.

8. The switching device according to claim 3, characterized in that, The pulse circuit shifts the third signal from a high level to a low level and the fourth signal from a low level to a high level.

9. The switching device according to claim 8, characterized in that, The pulse width of the third signal and the fourth signal is a time greater than or equal to the second time.

10. A switching device, characterized in that, have: The first P-type MOS transistor has its gate connected to the first node; A first control circuit is electrically connected to the first node; The second control circuit is electrically connected to the first node; A pulse circuit that controls the first control circuit; as well as A delay circuit that controls the second control circuit; The pulse circuit outputs a second signal with a first level that spans a first time period, based on a first signal. The delay circuit outputs a third signal that delays the first signal by a certain time. The first control circuit is configured to reduce the voltage of the first node during the period when the second signal of the first level is received. The second control circuit is configured to reduce the voltage of the first node based on the third signal. In the first control circuit, the voltage of the first node decreases more per unit time compared to the second control circuit.

11. The switching device according to claim 10, characterized in that, The second control circuit reduces the voltage of the first node based on the fact that the third signal changes from the second level to the third level.

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