Pixel and display device comprising pixels

Abstract

This invention relates to pixels and display devices including the pixels. The pixel includes: a light-emitting diode (LED); a first PMOS transistor including a first electrode connected to a node and a second electrode connected to the LED, and transmitting a drive current to the LED; a second transistor connected between a data line and a node, and turned on by a first scan signal; a third NMOS transistor connected between the gate electrode and the second electrode of the first PMOS transistor, and turned on by a first transmit control signal; a fourth NMOS transistor connected between the gate electrode of the first PMOS transistor and a first initialization voltage line, and turned on by a second transmit control signal; a fifth transistor connected between the drive voltage line and a node, and turned on by the first transmit control signal; and a sixth transistor connected between the second electrode of the first PMOS transistor and the LED, and turned on by the first transmit control signal.

Description

Technical Field

[0001] The embodiments relate to pixels and display devices including the pixels. Background Technology

[0002] Generally, a display device may include a display element and a driving circuit for controlling the electrical signals applied to the display element. The driving circuit may include a thin-film transistor (TFT), a storage capacitor, and multiple wirings.

[0003] To precisely control the emission (e.g., emittance) of display elements, the number of thin-film transistors electrically connected to a single display element has been increased. Accordingly, research to address the issues of high integration complexity and power consumption in display devices has been actively conducted. Summary of the Invention

[0004] One or more embodiments provide a display device driven by thin-film transistors including silicon semiconductors and thin-film transistors including oxide semiconductors, and provide reduced power consumption and high integration. However, the aspects and features described above in the embodiments are merely examples, and the scope of this disclosure is not limited thereto.

[0005] Additional features and aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of the exemplary embodiments described in this disclosure.

[0006] According to an embodiment, the pixel includes: a light-emitting diode (LED); a first transistor including a gate electrode, a first electrode connected to a node, and a second electrode connected to the LED, and transmitting a drive current to the LED; a second transistor connected between a data line and a node, and turned on by a first scan signal; a third transistor connected between the gate electrode and the second electrode of the first transistor, and turned on by a first transmit control signal; a fourth transistor connected between the gate electrode of the first transistor and a first initialization voltage line, and turned on by a second transmit control signal; a fifth transistor connected between the drive voltage line and the node, and turned on by the first transmit control signal; and a sixth transistor connected between the second electrode of the first transistor and the LED, and turned on by the first transmit control signal. The first transistor includes a PMOS transistor, and the third and fourth transistors each include an NMOS transistor.

[0007] PMOS transistors may include silicon semiconductors, and NMOS transistors may include oxide semiconductors.

[0008] The pixel may further include: a first capacitor connected between the driving voltage line and the gate electrode of the first transistor; and a second capacitor connected between the gate electrode of the first transistor and the gate electrode of the second transistor.

[0009] The second transmit control signal can be output before the first transmit control signal.

[0010] The pixel may further include: a first scan line connected to the gate electrode of a second transistor; a second scan line connected to the gate electrode of a fourth transistor; and an emission control line connected to the gate electrodes of a third transistor, a fifth transistor, and a sixth transistor.

[0011] The pixel may further include: a first scan line connected to the gate electrode of a second transistor; a second scan line connected to the gate electrode of a fourth transistor; a third scan line connected to the gate electrode of a third transistor; and an emission control line connected to the gate electrodes of a fifth transistor and a sixth transistor. The third scan line may be a branch of the emission control line.

[0012] The pixel may further include: a seventh transistor connected between the light-emitting diode and the second initialization voltage line, and turned on by the second scan signal.

[0013] The second scan signal can be output before the first scan signal, or after the first scan signal.

[0014] The second transistor, the fifth transistor, the sixth transistor, and the seventh transistor may each include a PMOS transistor containing silicon semiconductor.

[0015] According to an embodiment, the display device includes: a plurality of pixels; a scan driving circuit configured to supply scan signals to the plurality of pixels; an emission control driving circuit configured to supply emission control signals to the plurality of pixels; and a data driving circuit configured to supply data signals to the plurality of pixels. Each of the plurality of pixels includes: a light-emitting diode (LED); a first transistor including a gate electrode, a first electrode connected to a node, and a second electrode connected to the LED, and transmitting a drive current to the LED; a second transistor connected between a data line and a node, and turned on by a first scan signal; a third transistor connected between the gate electrode and the second electrode of the first transistor, and turned on by a first emission control signal; a fourth transistor connected between the gate electrode of the first transistor and a first initialization voltage line, and turned on by a second emission control signal; a fifth transistor connected between a drive voltage line and a node, and turned on by the first emission control signal; and a sixth transistor connected between the second electrode of the first transistor and the LED, and turned on by the first emission control signal. The first transistor includes a PMOS transistor, and the third and fourth transistors each include an NMOS transistor.

[0016] PMOS transistors may include silicon semiconductors, and NMOS transistors may include oxide semiconductors.

[0017] Each of the plurality of pixels may include: a first capacitor connected between a driving voltage line and the gate electrode of a first transistor; and a second capacitor connected between the gate electrode of the first transistor and the gate electrode of the second transistor.

[0018] The transmit control drive circuit can sequentially output transmit control signals that have been shifted by an interval, and the second transmit control signal can be output before the first transmit control signal.

[0019] Each of the plurality of pixels may further include: a first scan line connected to the gate electrode of a second transistor; a second scan line connected to the gate electrode of a fourth transistor; and an emission control line connected to the gate electrodes of a third transistor, a fifth transistor, and a sixth transistor. Scan driving circuitry may be connected to the first scan line, and emission control driving circuitry may be connected to the second scan line and the emission control line.

[0020] Each of the plurality of pixels may further include: a first scan line connected to the gate electrode of a second transistor; a second scan line connected to the gate electrode of a fourth transistor; a third scan line connected to the gate electrode of a third transistor; and an emission control line connected to the gate electrodes of a fifth transistor and a sixth transistor. The third scan line may be a branch of the emission control line, a scan drive circuit may be connected to the first scan line, and an emission control drive circuit may be connected to the second scan line and the emission control line.

[0021] Each of the plurality of pixels may further include: a seventh transistor connected between the light-emitting diode and the second initialization voltage line, and turned on by a second scan signal supplied via a fourth scan line connected to the gate electrode of the seventh transistor.

[0022] The scan drive circuit can sequentially output scan signals that have been shifted by an interval, and the second scan signal can be output before or after the first scan signal.

[0023] The second transistor, the fifth transistor, the sixth transistor, and the seventh transistor may each include a PMOS transistor containing silicon semiconductor.

[0024] Each of the third and fourth transistors may include a lower gate electrode and an upper gate electrode.

[0025] The lower gate electrode of the third transistor and the lower gate electrode of the fourth transistor can be on different layers. Attached Figure Description

[0026] The above and other aspects and features of the embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 This is a schematic perspective view of a display device according to an embodiment.

[0028] Figure 2 It is along Figure 1 A schematic cross-sectional view taken from line I-I'.

[0029] Figure 3 This is a schematic plan view of the display panel according to an embodiment.

[0030] Figure 4 schematically illustrated Figure 3 The scan drive circuit (SDRV) and transmit control drive circuit (EDRV) are shown.

[0031] Figure 5 They are respectively by Figure 4 The timing diagram shown is of the scan signal and transmit control signal output by SDRV and EDRV.

[0032] Figure 6 This is an equivalent pixel circuit diagram according to an embodiment.

[0033] Figure 7 yes Figure 6 The timing diagram for driving the pixel circuit shown is shown.

[0034] Figure 8A and Figure 8B This is a schematic diagram of a plurality of thin-film transistors and capacitors arranged on a pair of pixel circuits of a display device according to an embodiment.

[0035] Figure 9 It is along Figure 8A A schematic cross-sectional view taken from line II-II'.

[0036] Figure 10 It is along Figure 8A Schematic cross-sectional view taken from lines III-III' and IV-IV'.

[0037] Figure 11 and Figure 12 Each is illustrated in the diagram. Figure 8A The layout shown is only for some of the components.

[0038] Figure 13 This is an equivalent pixel circuit diagram according to another embodiment.

[0039] Figure 14 This is a schematic diagram showing the positions of a plurality of thin-film transistors and capacitors arranged on a pair of pixel circuits of a display device according to another embodiment.

[0040] Figure 15 It is along Figure 14 A schematic cross-sectional view of the line V-V'.

[0041] Figure 16 and Figure 17 Each is illustrated in the diagram. Figure 14 The layout shown is only for some of the components. Detailed Implementation

[0042] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, in which the same reference numerals always refer to the same elements. In this respect, the illustrated embodiments may take different forms and should not be construed as limited to the description set forth herein. Accordingly, only exemplary embodiments are described below with reference to the accompanying drawings to explain aspects of this description. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, and variations thereof.

[0043] It will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0044] As used in this article, the singular form of “one” is intended to include the plural form as well, unless the context explicitly indicates otherwise.

[0045] It will be further understood that the terms “comprising,” “having,” and / or “including” are used herein to specify the presence of the stated features or elements, but do not exclude the presence or addition of one or more other features or elements.

[0046] It will be understood that when a layer, area, or element is referred to as being "on" or "formed" on another layer, area, or element, that layer, area, or element may be directly or indirectly on, or directly or indirectly formed on, another layer, area, or element. For example, intermediate layers, areas, or elements may also exist.

[0047] For ease of explanation, the dimensions of the elements in the accompanying drawings may be enlarged. In other words, for ease of explanation, the dimensions and thicknesses of the elements shown in the accompanying drawings may be arbitrarily illustrated, and the embodiments described below are not limited thereto.

[0048] Furthermore, in describing embodiments of the invention, the use of the word "may" refers to "one or more embodiments of the invention." Additionally, the term "exemplary" is intended to indicate or illustrate. As used herein, the terms "use," "in use," and "being used" may be considered synonymous with the terms "utilizing," "being utilized," and "being exploited," respectively. As used herein, the terms "substantially," "approximately," and similar terms are used as approximate terms and not as terms of degree, and are intended to take into account the inherent biases in measured or calculated values ​​that will be recognized by those skilled in the art.

[0049] In the following embodiments, the expression “extending in a first direction or a second direction” may include extending not only in a linear direction (e.g., not only having a linear shape), but also extending in a zigzag or curved direction (e.g., having a zigzag or curved shape) in the first or second direction.

[0050] In the following embodiments, the expression "in a plane" can refer to the plane of the object when viewed from above, and the expression "in a cross-section" can refer to the plane of the object when viewed from the side of the object when it is cut vertically. In the following embodiments, when the first element and the second element "overlap," the first element can be located above or below the second element.

[0051] In the following embodiments, the term "ON" used in association with the state of the device can refer to the active state of the device, and the term "OFF" can refer to the inactive state of the device. The term "ON" used in association with signals received by the device can refer to a signal that activates the device, and the term "OFF" can refer to a signal that disables the device. The device can be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor can be activated by a low-level voltage, and an N-channel transistor can be activated by a high-level voltage. Accordingly, the "ON" voltage of a P-channel transistor can be understood as a voltage level opposite to the "ON" voltage of an N-channel transistor (e.g., from low to high).

[0052] Figure 1 This is a schematic perspective view of the display device 1 according to an embodiment, and Figure 2 yes Figure 1 The schematic cross-sectional view of the display device 1 shown can be compared with that along the line Figure 1 The section cut by line I-I' corresponds to the section cut by line I-I'.

[0053] The display device according to the embodiments can be implemented by electronic devices such as smartphones, cellular phones, smartwatches, navigation devices, game consoles, televisions, vehicle heads, laptop computers, tablet computers, personal media players (PMPs), personal digital assistants (PDAs), etc. (e.g., it can be included in an electronic device). Furthermore, the electronic device can be a flexible device.

[0054] Display device 1 may have a display area DA for displaying an image and a peripheral area PA disposed around the display area DA. Display device 1 can provide an image by using light emitted from a plurality of pixels disposed in the display area DA.

[0055] Display device 1 can have various shapes, for example, a rectangular plate shape with two parallel sides. When display device 1 has a rectangular plate shape, either pair of sides can be longer than the other pair. In an embodiment, for ease of explanation, display device 1 has a rectangular shape having a pair of long sides and a pair of short sides, wherein the extension direction of the short sides is a first direction (e.g., the x-direction), the extension direction of the long sides is a second direction (e.g., the y-direction), and the direction perpendicular to the extension directions of the long and short sides is a third direction (e.g., the z-direction). In another embodiment, display device 1 can have a non-rectangular shape. Non-rectangular shapes can include, for example, circles, ellipses, polygons with partially circular shapes, and polygons other than rectangles.

[0056] When the display area DA is considered to be a planar shape, the display area DA can be as follows: Figure 1 The rectangular shape is illustrated in the figure. In another embodiment, the display area DA can be a polygonal shape such as a triangle, pentagon, hexagon, circle, ellipse, irregular shape, etc.

[0057] The peripheral region PA, which is set around the display area DA, can be a non-display area in which no pixels are set. The display area DA can be completely surrounded by the peripheral region PA (e.g., it can be completely surrounded by the peripheral region PA along the periphery of the display area DA). Various wiring for transmitting electrical signals to be applied to the display area DA, as well as pads on which printed circuit boards or driver IC chips are attached, can be located in the peripheral region PA.

[0058] In the following description, an organic light-emitting display device is described as an example of display device 1, but display device 1 according to this disclosure is not limited thereto. In other embodiments, display device 1 may be an inorganic light-emitting display device (or an inorganic EL display device) or a quantum dot light-emitting display device.

[0059] refer to Figure 2 The display device 1 may include a display panel 10, an input sensing layer 40 disposed on the display panel 10, and an optical functional layer 50 that may be covered by a window 60.

[0060] Display panel 10 can display images. Display panel 10 may include pixels disposed in display area DA. Pixels may include display elements. Display elements may be connected to pixel circuitry. Display elements may include organic light-emitting diodes, quantum dot organic light-emitting diodes, etc.

[0061] The input sensing layer 40 acquires coordinate information based on external input, such as a touch event. The input sensing layer 40 may include sensing electrodes (e.g., touch electrodes) and traces connected to the sensing electrodes. The input sensing layer 40 may be disposed on the display panel 10. The input sensing layer 40 may detect external input using mutual capacitance and / or self-capacitance methods.

[0062] The input sensing layer 40 can be formed directly on the display panel 10, or it can be formed separately and then coupled to the display panel 10 via an adhesive layer such as an optically clear adhesive. For example, the input sensing layer 40 can be formed after the process of forming the display panel 10 (e.g., formed continuously). In this embodiment, the input sensing layer 40 can be part of the display panel 10, and the adhesive layer may not be provided between the input sensing layer 40 and the display panel 10. Figure 2 An input sensing layer 40 is illustrated between the display panel 10 and the optical functional layer 50. However, in another embodiment, the input sensing layer 40 may be disposed on (e.g., above) the optical functional layer 50.

[0063] The optical functional layer 50 may include an anti-reflective layer. The anti-reflective layer reduces the reflectivity of light (e.g., external light) incident on the display panel 10 from the outside through the window 60. The anti-reflective layer may include a retarder and / or a polarizer. The retarder may be a film-type or a liquid crystal coating-type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may be a film-type or a liquid crystal coating-type. The film-type may include a stretched synthetic resin film, and the liquid crystal coating-type may include an array of liquid crystals (e.g., liquid crystals arranged in an array). The retarder and polarizer may further include a protective film. The retarder and polarizer themselves or the protective film may be defined as the base layer of the anti-reflective layer.

[0064] In another embodiment, the anti-reflective layer may include a black matrix and color filters. The color filters can be arranged considering the color of light emitted from each pixel of the display panel 10. In another embodiment, the anti-reflective layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers from each other. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, can interfere destructively with each other, and accordingly, the reflectivity of external light can be reduced.

[0065] The optical functional layer 50 may include a lens layer. The lens layer may improve the output efficiency of light emitted from the display panel 10 (e.g., improve the luminous efficiency or extraction efficiency of the display panel 10) or reduce color deviation. The lens layer may include layers having a concave lens shape or a convex lens shape and / or multiple layers with different refractive indices. The optical functional layer 50 may include all or any one of the anti-reflective layers and lens layers described above.

[0066] In this embodiment, the optical functional layer 50 may be formed sequentially after the processes for forming the display panel 10 and / or the input sensing layer 40. In this embodiment, an adhesive layer may not be provided between the optical functional layer 50 and the display panel 10 and / or the input sensing layer 40.

[0067] Figure 3 This is a schematic plan view of the display panel according to an embodiment. Figure 4 schematically illustrated Figure 3 The scan drive circuit (SDRV) and transmit control drive circuit (EDRV) shown are, and Figure 5 They are respectively by Figure 4 The timing diagram shown is of the scan signal and transmit control signal output by SDRV and EDRV.

[0068] refer to Figure 3 The display panel 10 may have a display area DA and a peripheral area PA. The display panel 10 may include a substrate 100, and for example, the substrate 100 may have a display area DA and a peripheral area PA.

[0069] Substrate 100 may comprise a variety of suitable materials such as glass, metal, or plastic. According to embodiments, substrate 100 may comprise a flexible material (or may be formed from a flexible material). Substrate 100 comprising a flexible material may refer to a substrate that is easily bent, folded, or rolled. As some examples, substrate 100 comprising a flexible material may comprise ultrathin glass, metal, or plastic.

[0070] Multiple pixels P can be set in the display area DA of the display panel 10. Pixels P can be arranged in a pattern such as a stripe matrix, (A registered trademark of Samsung Display Co., Ltd.) Various forms (e.g., arrangements) of matrices, mosaic matrices, etc., are arranged and can realize (e.g., display) images. According to one embodiment, such as Figure 6 As illustrated, each pixel P may include an organic light-emitting diode (OLED) as a display element, and the OLED may be connected to a pixel circuit (PC). Each pixel P may emit light, such as red, green, blue, or white, via the OLED.

[0071] The peripheral area PA of the display panel 10 is located outside the display area DA and can be an area where no image is displayed. From the pixel circuit connected to each pixel P, the SDRV for supplying the scan signal SS, the EDRV for supplying the transmit control signal ES, the data drive circuit DDRV for supplying the data signal DATA, and the main power wiring for supplying the drive voltage and common voltage can be located in the peripheral area PA. Figure 3 The illustration shows the data driver circuit DDRV positioned close to (e.g., adjacent to) the substrate 100. However, according to another embodiment, the data driver circuit DDRV can be positioned on a flexible printed circuit board (FPCB) electrically connected to pads disposed on one side of the display panel 10.

[0072] refer to Figure 4 SDRV and EDRV can each be implemented by including multiple stages of shift registers (e.g., each can include its own).

[0073] An SDRV may include multiple stages (..., SSTn-1, SSTn, SSTn+1, ...) connected independently (e.g., sequentially). Each stage (..., SSTn-1, SSTn, SSTn+1, ...) may output a scan signal (..., SSn-1, SSn, SSn+1, ...). The first stage (..., SSTn-1, SSTn, SSTn+1, ...) may output a scan signal in response to a start signal, and the other stages may receive a carry signal from the previous stage as a start signal. The carry signal may be a scan signal output from the previous stage. Each stage (..., SSTn-1, SSTn, SSTn+1, ...) may output a scan signal according to the driving timing.

[0074] In an embodiment, such as Figure 5 As illustrated, the scan signals (..., SSn-1, SSn, SSn+1, ...) can each have a low-level signal with a width of one horizontal period 1H, and can be output to be sequentially shifted by one horizontal period 1H relative to the previous scan signal.

[0075] The EDRV may include multiple stages (..., ESTn-1, ESTn, ESTn+1, ...) connected independently (e.g., sequentially). Each of the stages (..., ESTn-1, ESTn, ESTn+1, ...) may output a transmit control signal (..., ESn-1, ESn, ESn+1, ...). The first stage of the stages (..., ESTn-1, ESTn, ESTn+1, ...) may output a transmit control signal in response to a start signal, and the other stages may receive a carry signal from the previous stage as a start signal. The carry signal may be a transmit control signal output from the previous stage. Each of the stages (..., ESTn-1, ESTn, ESTn+1, ...) may output a transmit control signal according to the drive timing. In an embodiment, as... Figure 5 As illustrated, the transmit control signals (..., ESn-1, ESn, ESn+1, ...) can each have a high-level signal with a width of 2 horizontal periods 2H, and can be output to be sequentially shifted by 1 horizontal period 1H relative to the previous transmit control signal.

[0076] although Figure 4 The illustration shows SDRV levels and EDRV levels provided in a one-to-one correspondence (e.g., SDRV and EDRV include the same number of levels), but this is exemplary, and various modifications are possible such that one EDRV level corresponds to two SDRV levels. Furthermore, Figure 5 The width and shift degree of the scan signals (..., SSn-1, SSn, SSn+1, ...) and transmit control signals (..., ESn-1, ESn, ESn+1, ...) illustrated in the figure are exemplary, and various modifications are possible so that the transmit control signals (..., ESn-1, ESn, ESn+1, ...) are output in the form of being sequentially shifted by 1 / 2 horizontal period 1 / 2H.

[0077] Figure 6 This is an equivalent circuit diagram of the pixels according to the embodiment, and Figure 7 yes Figure 6 Timing diagram of the pixel circuit driving.

[0078] refer to Figure 6Pixel P may include an OLED as a display element, and the OLED may be connected to pixel circuitry PC. Pixel circuitry PC may include multiple transistors (e.g., first to seventh transistors T1, T2, T3, T4, T5, T6, and T7), a first capacitor Cst, a second capacitor Cbt, and signal lines connected to them, a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a drive voltage line PL. Signal lines may include a data line DL, a first scan line SL1, a second scan line SL2, a third scan line SL3, and an emitt control line EL. In another embodiment, at least one of the signal lines, the first initialization voltage line VIL1, the second initialization voltage line VIL2, and / or the drive voltage line PL may be shared by adjacent (e.g., neighboring) pixels.

[0079] The driving voltage ELVDD can be transmitted to the first transistor T1 via the driving voltage line PL. The initialization voltage Vint used to initialize the first transistor T1 and the OLED can be transmitted to the pixel P via the first initialization voltage line VIL1 and the second initialization voltage line VIL2.

[0080] The first scan line SL1, the second scan line SL2, the third scan line SL3, the transmit control line EL, the first initialization voltage line VIL1, and the second initialization voltage line VIL2 can be in the first direction (e.g., Figure 1 The data lines DL and drive voltage lines PL can extend in a second direction (e.g., the x-direction) to be arranged separately from each other in each row. Figure 1 Extending in the y-direction, so that they are arranged separately from each other in each column.

[0081] exist Figure 6 In the diagram, from the first transistor T1 to the seventh transistor T7, the third transistor T3 and the fourth transistor T4 can be implemented as n-channel MOSFETs (NMOS), and the other transistors can be implemented as p-channel MOSFETs (PMOS). Figure 6 In the first transistor T1 to the seventh transistor T7, the first electrode can be the source electrode or the drain electrode, and the second electrode of the first transistor T1 to the seventh transistor T7 can be the drain electrode or the source electrode.

[0082] The first transistor T1 may include a gate electrode connected to node N2, a first electrode connected to node N1, and a second electrode. The first electrode of the first transistor T1 is connected to the drive voltage line PL via a fifth transistor T5, and the second electrode of the first transistor T1 is electrically connected to the OLED via a sixth transistor T6. The first transistor T1 acts as a drive transistor and receives the data signal DATA through the switching operation of the second transistor T2, and drives the drive current I. OLED Supply to OLED.

[0083] The gate electrode of the second transistor T2 is connected to the first scan line SL1, the first electrode of the second transistor T2 is connected to the data line DL, and the second electrode of the second transistor T2 is connected to node N1 and via the fifth transistor T5 to the drive voltage line PL. The second transistor T2 is turned on by the first scan signal SSn received via the first scan line SL1 and performs a switching operation to transmit the data signal DATA received via the data line DL to node N1.

[0084] The gate electrode of the third transistor T3 is connected to the emitter control line EL, the first electrode of the third transistor T3 is connected to the gate electrode of the first transistor T1, and the second electrode of the third transistor T3 is connected to the second electrode of the first transistor T1 and connected to the OLED via the sixth transistor T6. The third transistor T3 is turned on by the first emitter control signal ESN received via the emitter control line EL and connects the diode of the first transistor T1.

[0085] The gate electrode of the fourth transistor T4 is connected to the third scan line SL3, the first electrode of the fourth transistor T4 is connected to the first initialization voltage line VIL1, and the second electrode of the fourth transistor T4 is connected to the gate electrode of the first transistor T1. The fourth transistor T4 is turned on by the second transmit control signal ESN-k (where k≥1) received via the third scan line SL3, and transmits the initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1, thereby initializing the voltage of the gate electrode of the first transistor T1.

[0086] The second transmit control signal ESn-k can be a previous transmit control signal output before the first transmit control signal ESn (e.g., the current transmit control signal). The previous transmit control signal can be a transmit control signal that immediately precedes the first transmit control signal ESn (e.g., output immediately before the first transmit control signal ESn) (e.g., ESn-1), or one of a transmit control signal that has already been output (or even earlier) before the first transmit control signal ESn (e.g., ESn-2, ESn-3, etc.).

[0087] The gate electrode of the fifth transistor T5 is connected to the emitter control line EL, the first electrode of the fifth transistor T5 is connected to the drive voltage line PL, and the second electrode of the fifth transistor T5 is connected to node N1. The gate electrode of the sixth transistor T6 is connected to the emitter control line EL, the first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1, and the second electrode of the sixth transistor T6 is connected to the OLED. The fifth transistor T5 and the sixth transistor T6 are concurrently (e.g., simultaneously) turned on by a first emitter control signal ESN received via the emitter control line EL, and form a current path such that the drive current I... OLED It can flow in the direction from the driving voltage line PL to the OLED.

[0088] The gate electrode of the seventh transistor T7 is connected to the second scan line SL2, the first electrode of the seventh transistor T7 is connected to the second initialization voltage line VIL2, and the second electrode of the seventh transistor T7 is connected to the OLED. The seventh transistor T7 is turned on by the second scan signal SSn-1 or SSn+1 received via the second scan line SL2, and transmits the initialization voltage Vint from the second initialization voltage line VIL2 to the OLED, thereby initializing the OLED.

[0089] The second scan signal SSn-1 can be a previous scan signal output before the first scan signal SSn (the current scan signal). In other embodiments, the second scan signal SSn+1 can be a next scan signal output after the first scan signal SSn. In some embodiments, the seventh transistor T7 can be omitted.

[0090] The first capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 is connected to the gate electrode of the first transistor T1, and the second electrode CE2 is connected to the drive voltage line PL. The first capacitor Cst can maintain the voltage applied to the gate electrode of the first transistor T1 by storing and maintaining a voltage corresponding to the difference between the voltage at the opposite ends of the drive voltage line PL and the gate electrode of the first transistor T1.

[0091] The second capacitor Cbt may include a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 is connected to the gate electrode of the first scan line SL1 and the second transistor T2. The fourth electrode CE4 is connected to the gate electrode of the first transistor T1 and the first electrode CE1 of the first capacitor Cst. When the first scan signal SSn received via the first scan line SL1 is the voltage used to turn off the second transistor T2, the second capacitor Cbt, which is a boost capacitor, can reduce the voltage (e.g., the black voltage) by increasing the voltage at node N2 to display black.

[0092] An OLED may include pixel electrodes and counter electrodes, and the counter electrodes may receive a common voltage ELVSS. The OLED may receive a drive current I from a first transistor T1. OLED It emits light, thus displaying the image.

[0093] In this embodiment, at least one of transistors T1 to T7 may include a semiconductor layer comprising oxide, and the other transistors may include a semiconductor layer comprising silicon. For example, the first transistor T1, which affects (e.g., directly affects) the brightness of the display device, may include a semiconductor layer comprising polycrystalline silicon with high reliability, thereby enabling a high-resolution display device.

[0094] Oxide semiconductors have high carrier mobility and low leakage current, resulting in a small voltage drop (e.g., not huge) even with long drive times. For example, low-frequency driving is possible when the color change in the image based on the voltage drop is small during low-frequency driving. Thus, since oxide semiconductors provide relatively low leakage current, by employing at least one of the third transistor T3 and the fourth transistor T4, which are connected to the gate electrode of the first transistor T1, as oxide semiconductors, leakage current flowing to the gate electrode of the first transistor T1 can be prevented or substantially prevented, and power consumption can be reduced.

[0095] refer to Figure 7 The following describes the detailed operation of pixel P according to an embodiment.

[0096] During the first time period t1, when the second transmit control signal ESN-2 with a high level is supplied via the third scan line SL3, the fourth transistor T4 is turned on, and the first transistor T1 is initialized by the initialization voltage Vint supplied from the first initialization voltage line VIL1.

[0097] During the second time period t2, the third transistor T3 is turned on by a high-level first emitt control signal ESN supplied via the emitt control line EL. In this state, the first transistor T1 is connected to the turned-on third transistor T3 by a diode and is forward biased. During the 2-1 time period t21 (i.e., the first half of the second time period t2), which is part of the second time period t2, the seventh transistor T7 is turned on when a low-level second scan signal SSn-1 is supplied via the second scan line SL2, and the OLED is initialized by an initialization voltage Vint supplied via the second initialization voltage line VIL2. During the 2-2 time period t22 (i.e., the second half of the second time period t2), which is part of the second time period t2, the second transistor T2 is turned on when a low-level first scan signal SSn is supplied via the first scan line SL1. A compensation voltage obtained by compensating the threshold voltage (Vth) of the first transistor T1 in the data signal DATA supplied via the data line DL is applied to the gate electrode of the first transistor T1. A driving voltage ELVDD and a compensation voltage are applied to opposite terminals of the first capacitor Cst, and a charge corresponding to the voltage difference between the opposite terminals of the first capacitor Cst is stored.

[0098] During the third time period t3, the first transmit control signal ESn, supplied via the transmit control line EL, transitions from a high level to a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on by the low-level first transmit control signal ESn. Correspondingly, the drive current I is determined based on the voltage difference between the gate electrode voltage of the first transistor T1 and the drive voltage ELVDD. OLED It is generated and drives current I. OLED It is supplied to the OLED via the sixth transistor T6.

[0099] Figure 7 The illustration shows an example in which the emitter control signal applied to the gate electrode of the fourth transistor T4 is the second emitter control signal ESn-2 and the scan signal applied to the gate electrode of the seventh transistor T7 is the second scan signal SSn-1. In another embodiment, as described above, the emitter control signal ESn-1 and the scan signal SSn+1 can be used as the second emitter control signal and the second scan signal, respectively.

[0100] Figure 8A and Figure 8B This is a schematic diagram of a plurality of thin-film transistors and capacitors arranged in a pair of pixel circuits of a display device according to an embodiment. Figure 9 It is along Figure 8A The cross-sectional view taken from line II-II', and Figure 10 It is along Figure 8ASchematic cross-sectional view taken from lines III-III' and IV-IV'. Figure 11 and Figure 12 Each is illustrated in the diagram. Figure 8A The layout of only some of the constituent elements shown.

[0101] Figure 8A The illustration shows a pair of pixels arranged in the same row but in adjacent columns. Figure 8A In the image, the pixel circuits of the pixels arranged in the left pixel region CA1 and the pixel circuits of the pixels arranged in the right pixel region CA2 have left and right symmetrical structures.

[0102] refer to Figure 8A According to the embodiment, the pixel circuit of the display device can be connected to a first scan line 133, a second scan line 133', a third scan line SL3, an emission control line 135, a first initialization voltage line 147 and a second initialization voltage line 147' extending in a first direction (e.g., the x direction), and a data line 181, a first driving voltage line 172 and a second driving voltage line 183 extending in a second direction (e.g., the y direction) intersecting (e.g., crossing) the first direction.

[0103] In addition, the pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor Cst, and a second capacitor Cbt.

[0104] In this embodiment, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may each be provided as thin-film transistors comprising silicon semiconductors. The third transistor T3 and the fourth transistor T4 may each be provided as thin-film transistors comprising oxide semiconductors.

[0105] The second scan line 133' can be the first scan line SL1 in the previous or next row. Figure 8A An example of a pixel circuit is illustrated, which includes a first scan line SL1 in the next row as a second scan line 133'.

[0106] The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be disposed on the same layer and can comprise the same material. For example, the semiconductor layer can comprise polycrystalline silicon. The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be connected to each other (e.g., they can be continuous or integral with each other) and can be bent into various shapes.

[0107] Each of the semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a channel region and source and drain regions on either side (e.g., opposite sides) of the channel region. In embodiments, the source and drain regions may be doped with impurities, and the impurities may include N-type or P-type impurities. The source and drain regions may correspond to source and drain electrodes, respectively. The source and drain regions may switch with each other depending on the characteristics of the transistor. In the following description, terms such as source and drain regions are used instead of source and drain electrodes.

[0108] The first transistor T1 may include a first semiconductor layer AS1 and a first gate electrode G1. The first semiconductor layer AS1 (see example...) Figure 9 The first semiconductor layer AS1 may include a first channel region A1 and a first source region S1 and a first drain region D1 on both sides of the first channel region A1. The first semiconductor layer AS1 has a curved shape, for example, such as... The multiple bends of shapes such as “S”, “M”, and “W” create a long channel length within a small space. Because the first channel region A1 is formed relatively long, the driving range of the gate voltage applied to the first gate electrode G1 is increased, allowing for more precise control of the grayscale of the light emitted from the OLED, thereby improving display quality. In some embodiments, the first semiconductor layer AS1 may be provided in a linear shape rather than a curved shape. The first gate electrode G1 is island-shaped and is provided to overlap with the first channel region A1, while the first gate insulating layer 112 is provided between the first gate electrode G1 and the first channel region A1 (see example...). Figure 9 ).

[0109] The first capacitor Cst can be configured to overlap with the first transistor T1. The first capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first gate electrode G1 can serve not only as the control electrode of the first transistor T1, but also as the first electrode CE1 of the first capacitor Cst. For example, the first gate electrode G1 and the first electrode CE1 can be formed integrally (e.g., they can be a single unit). The second electrode CE2 of the first capacitor Cst is provided to overlap with the first electrode CE1, and a second gate insulating layer 113 is provided between the first electrode CE1 and the second electrode CE2 (see example). Figure 9 The second gate insulating layer 113 can be used as the dielectric layer of the first capacitor Cst.

[0110] Node connection line 171 can be electrically connected to the first electrode CE1 and the third semiconductor layer AO3 of the third transistor T3 (see example). Figure 10The second electrode CE2 can be electrically connected to the first driving voltage line 172, and the first driving voltage line 172 can be electrically connected to the second driving voltage line 183. The first driving voltage line 172 and the second driving voltage line 183 can extend in a second direction. The second electrode CE2 can extend in a first direction and can transmit the driving voltage ELVDD in the first direction. Accordingly, in the display area DA, a plurality of first driving voltage lines 172 and second driving voltage lines 183 and a plurality of second electrodes CE2 can form a grid structure.

[0111] The second transistor T2 may include a second semiconductor layer AS2 (see example...) Figure 9 The second semiconductor layer AS2 may include a second channel region A2 and a second source region S2 and a second drain region D2 on both sides of the second channel region A2. The second source region S2 may be electrically connected to the data line 181, and the second drain region D2 may be connected to the first source region S1. The second gate electrode G2 may be part of the first scan line 133.

[0112] The fifth transistor T5 may include a fifth semiconductor layer AS5 (see example...) Figure 10 The fifth semiconductor layer AS5 may include a fifth channel region A5 and a fifth source region S5 and a fifth drain region D5 on either side of the fifth channel region A5. The fifth source region S5 may be electrically connected to the first drive voltage line 172, and the fifth drain region D5 may be connected to the first source region S1. The fifth gate electrode G5 may be part of the emitter control line 135.

[0113] The sixth transistor T6 may include a sixth semiconductor layer AS6 (see example...) Figure 10 The sixth semiconductor layer AS6 may include a sixth channel region A6 and a sixth source region S6 and a sixth drain region D6 on either side of the sixth channel region A6. The sixth source region S6 may be connected to the first drain region D1, and the sixth drain region D6 may be electrically connected to the pixel electrode 310 of the OLED (see example). Figure 10 The sixth gate electrode G6 may be part of the emitter control line 135.

[0114] The seventh transistor T7 may include a seventh semiconductor layer and a seventh gate electrode G7. The seventh semiconductor layer may include a seventh channel region A7 and a seventh source region S7 and a seventh drain region D7 on both sides of the seventh channel region A7. The seventh source region S7 may be electrically connected to the second initialization voltage line 147', and the seventh drain region D7 may be connected to the sixth drain region D6. The seventh gate electrode G7 may be part of the second scan line 133'.

[0115] First interlayer insulation layer 114 (see example) Figure 9 and Figure 10The transistors T1, T2, T5 to T7, T6 and T7, which include silicon semiconductors, can be disposed on the first interlayer insulating layer 114. The transistors T3 and T4, which include oxide semiconductors, can be disposed on the first interlayer insulating layer 114.

[0116] The semiconductor layers of the third transistor T3 and the fourth transistor T4 can be disposed on the same layer and can comprise the same material. For example, the semiconductor layers can each comprise an oxide semiconductor.

[0117] The semiconductor layers of the third transistor T3 and the fourth transistor T4 may each include a channel region and source and drain regions on either side of the channel region. In embodiments, the source and drain regions may have high carrier concentrations due to plasma processing. The source and drain regions may correspond to source and drain electrodes, respectively. In the following description, terms such as source and drain regions are used instead of source and drain electrodes.

[0118] The third transistor T3 may include a third semiconductor layer AO3 comprising an oxide semiconductor (see example...). Figure 10 The third semiconductor layer AO3 may include a third channel region A3 and a third source region S3 and a third drain region D3 on both sides of the third channel region A3. The third source region S3 may be bridged to the first gate electrode G1 via node connection line 171. The third drain region D3 may be electrically connected to the first semiconductor layer AS1 of the first transistor T1 and the sixth semiconductor layer AS6 of the sixth transistor T6. The third gate electrode G3 may be part of the emitter control line 135.

[0119] The fourth transistor T4 may include a fourth semiconductor layer AO4 comprising an oxide semiconductor (see example...). Figure 9 The fourth semiconductor layer AO4 may include a fourth channel region A4 and a fourth source region S4 and a fourth drain region D4 on either side of the fourth channel region A4. The fourth source region S4 may be electrically connected to the first initialization voltage line 147, and the fourth drain region D4 may be bridged to the first gate electrode G1 via node connection line 171. The fourth gate electrode G4 may be part of the third scan line SL3.

[0120] A third gate insulating layer 115 is disposed between the third semiconductor layer AO3 and the third gate electrode G3, and between the fourth semiconductor layer AO4 and the fourth gate electrode G4, corresponding to each channel region (see example). Figure 9 and Figure 10 ).

[0121] The third electrode CE3 of the second capacitor Cbt may be part of the first scan line 133 and connected to the second gate electrode G2. The fourth electrode CE4 of the second capacitor Cbt is configured to overlap with the third electrode CE3 and may be provided as an oxide semiconductor. The fourth electrode CE4 may be provided on the same layer as the fourth semiconductor layer AO4 of the fourth transistor T4 and may extend from the fourth semiconductor layer AO4.

[0122] Second interlayer insulation layer 116 (see example) Figure 9 and Figure 10 The first drive voltage line 172 and the node connection line 171 can be disposed on the second interlayer insulating layer 116, which includes an oxide semiconductor third transistor T3 and a fourth transistor T4.

[0123] First planarization layer 118 (see example) Figure 9 and Figure 10 The data line 181 and the second driving voltage line 183 are set on the first driving voltage line 172, and the data line 181 and the second driving voltage line 183 can extend in the second direction on the first planarization layer 118.

[0124] In an embodiment, the first scan line 133, the second scan line 133', and the emission control line 135 may be provided on the same layer and may include the same material as the first gate electrode G1.

[0125] The third scan line SL3 may include a lower scan line 137 and an upper scan line 163 disposed on different layers. The lower scan line 137 may be provided on the same layer as the first electrode CE1 of the first capacitor Cst, and may include the same material as the first electrode CE1 of the first capacitor Cst. The upper scan line 163 may be disposed on the third gate insulating layer 115. The lower scan line 137 may be configured to overlap at least a portion of the upper scan line 163. The lower scan line 137 and the upper scan line 163 may correspond to a portion of the fourth gate electrode G4 of the fourth transistor T4, and the fourth transistor T4 may have a dual-gate structure in which control electrodes are provided above and below the semiconductor layer, respectively.

[0126] In another embodiment, such as Figure 8B As illustrated, the third scan line SL3 may consist only of the upper scan line 163. The upper scan line 163 may correspond to a portion of the fourth gate electrode G4 of the fourth transistor T4, and the fourth transistor T4 may have a single-gate structure in which the control electrode is provided above the semiconductor layer.

[0127] The first initialization voltage line 147 and the second initialization voltage line 147' can be disposed on the same layer and can include the same material as the second electrode CE2 of the first capacitor Cst.

[0128] The following will be referenced Figure 9 and Figure 10 The structure of the display device according to the embodiment is described in detail in stacking order.

[0129] Figure 9 and Figure 10 Is with Figure 8A The diagram shows a cross-sectional view of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the first capacitor Cst, the second capacitor Cbt, and a portion of the corresponding OLED display device. For ease of explanation, Figure 8A Some of the components shown can be obtained from Figure 9 and Figure 10 omitted.

[0130] The substrate 100 may include glass, ceramic, metallic, or materials with flexible or bendable properties (e.g., flexible or bendable materials). When the substrate 100 has flexible or bendable properties, it may include polymer resins such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP).

[0131] The substrate 100 may have a single-layer or multi-layer structure of material, and the multi-layer structure may further include an inorganic layer. For example, the substrate 100 may include a first base layer 101, a first barrier layer 103, a second base layer 105, and a second barrier layer 107. The first base layer 101 and the second base layer 105 may each comprise a polymer resin. The first base layer 101 and the second base layer 105 may each comprise a transparent polymer resin. As barrier layers for preventing (or substantially preventing) the intrusion of external foreign matter, the first barrier layer 103 and the second barrier layer 107 may have a composition such as silicon nitride (SiN). x ) or silicon dioxide (SiO) x ( ) Inorganic materials with single-layer or multi-layer structures.

[0132] A buffer layer 111 may be disposed on the substrate 100. The buffer layer 111 can increase the smoothness of the upper surface of the substrate 100, and the buffer layer 111 may include materials such as silicon oxide (SiO2). x Oxide films such as silicon nitride (SiN) and / or oxide films such as silicon nitride (SiN) x ) or silicon oxynitride (SiON) nitride film.

[0133] A barrier layer may be further provided between the substrate 100 and the buffer layer 111. The barrier layer can prevent or reduce the intrusion of impurities from the substrate 100 into the silicon semiconductor layer. The barrier layer may include inorganic and / or organic materials such as oxides or nitrides, and may have a single-layer or multi-layer structure of inorganic and organic materials.

[0134] A silicon semiconductor layer, namely the semiconductor layer of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, can be disposed on the buffer layer 111.

[0135] The silicon semiconductor layer may include: a first semiconductor layer AS1 of the first transistor T1, comprising a first channel region A1, a first source region S1, and a first drain region D1; a second semiconductor layer AS2 of the second transistor T2, comprising a second channel region A2, a second source region S2, and a second drain region D2; a fifth semiconductor layer AS5 of the fifth transistor T5, comprising a fifth channel region A5, a fifth source region S5, and a fifth drain region D5; a sixth semiconductor layer AS6 of the sixth transistor T6, comprising a sixth channel region A6, a sixth source region S6, and a sixth drain region D6; and a seventh semiconductor layer AS7 of the seventh transistor T7, comprising a seventh channel region A7, a seventh source region S7, and a seventh drain region D7. For example, the channel region, source region, and drain region of each of the first transistor T1, the second transistor T2, and the fifth to seventh transistors T5, T6, and T7 may be a portion of the silicon semiconductor layer.

[0136] The first gate insulating layer 112 may be located on a silicon semiconductor layer. The first gate insulating layer 112 may comprise an inorganic material comprising an oxide or a nitride. For example, the first gate insulating layer 112 may comprise silicon oxide (SiO2). x ), silicon nitride (SiN) x It is at least one of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0137] The first gate electrode G1 of the first transistor T1, the second gate electrode G2 of the second transistor T2, the fifth gate electrode G5 of the fifth transistor T5, the sixth gate electrode G6 of the sixth transistor T6, and the seventh gate electrode G7 of the seventh transistor T7 can be disposed on the first gate insulating layer 112. Furthermore, the first scan line 133, the second scan line 133', the emission control line 135, and the lower scan line 137 of the third scan line SL3 can be disposed on the first gate insulating layer 112 in a first direction (e.g., Figure 8A Extending in the x-direction. A portion of the first scan line 133 may be the third electrode CE3 of the second capacitor Cbt. For example, as... Figure 11As illustrated, the protruding portion 135P of the emitter control line 135 can be the lower gate electrode G3a of the third transistor T3. A portion of the lower scan line 137 of the third scan line SL3 can be the lower gate electrode G4a of the fourth transistor T4.

[0138] The first gate electrode G1 of the first transistor T1 can be an island (e.g., it can be an island-shaped structure). The second gate electrode G2 of the second transistor T2 can be a portion of the first scan line 133 that intersects with the semiconductor layer. The seventh gate electrode G7 of the seventh transistor T7 can be a portion of the second scan line 133' that intersects with the semiconductor layer. The fifth gate electrode G5 of the fifth transistor T5 and the sixth gate electrode G6 of the sixth transistor T6 can be a portion of the emitter control line 135 that intersects with the semiconductor layer.

[0139] The first gate electrode G1 of the first transistor T1 can be used not only as the control electrode of the first transistor T1, but also as the first electrode CE1 of the first capacitor Cst.

[0140] The gate electrodes of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), etc., and may include one or more materials, and may be formed in a single-layer structure or a multi-layer structure.

[0141] The second gate insulating layer 113 can be disposed on the gate electrode. The second gate insulating layer 113 may comprise an inorganic material containing oxides or nitrides. For example, the second gate insulating layer 113 may comprise SiO2. x SiN x At least one of SiON, Al2O3, TiO2, Ta2O5, HfO2 and ZnO2.

[0142] The second electrode CE2 can be configured to overlap with the first electrode CE1 on the second gate insulating layer 113. The second electrode CE2 may include an opening SOP. The opening SOP is formed by removing a portion of the second electrode CE2 and may have a closed shape.

[0143] The second gate insulating layer 113 can be used as the dielectric layer of the first capacitor Cst. The second electrodes CE2 of adjacent pixels can be connected to each other. The second electrodes CE2 of adjacent pixels can be formed integrally (e.g., they can be a single unit).

[0144] The second electrode CE2 of the first capacitor Cst may include one or more materials selected from Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, Cu, etc., and may be formed as a single layer or formed as a multilayer structure.

[0145] The first initialization voltage line 147 and the second initialization voltage line 147' may include the same material as the second electrode CE2 of the first capacitor Cst, and may extend in the first direction on the second gate insulating layer 113.

[0146] The first interlayer insulating layer 114 can be disposed on the second electrode CE2 of the first capacitor Cst. The first interlayer insulating layer 114 may comprise an inorganic material containing oxides or nitrides. For example, the first interlayer insulating layer 114 may comprise SiO2. x SiN x At least one of SiON, Al2O3, TiO2, Ta2O5, HfO2 and ZnO2.

[0147] An oxide semiconductor layer, including an oxide semiconductor, may be disposed on the first interlayer insulating layer 114. The oxide semiconductor layer may be, for example, a zinc oxide-based material, and may include zinc oxide, In-Zn oxide, Ga-In-Zn oxide, etc. In some embodiments, the oxide semiconductor layer may include an IGZO (In-Ga-Zn-O) semiconductor, an ITZO (In-Sn-Zn-O) semiconductor, or an IGTZO (In-Ga-Sn-Zn-O) semiconductor, in which a metal such as In, Ga, or Sn is contained in ZnO.

[0148] The semiconductor layer of each of the third transistor T3 and the fourth transistor T4 may include a channel region and source and drain regions on either side of the channel region. The source and drain regions of each of the third transistor T3 and the fourth transistor T4 can be formed by making the oxide semiconductor conductive through adjusting the carrier concentration of the oxide semiconductor. For example, the source and drain regions of each of the third transistor T3 and the fourth transistor T4 can be formed by increasing the carrier concentration of the oxide semiconductor through a plasma process on the oxide semiconductor by using a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof.

[0149] The oxide semiconductor layer may include: a third semiconductor layer AO3 of the third transistor T3 comprising a third channel region A3, a third source region S3, and a third drain region D3, and a fourth semiconductor layer AO4 of the fourth transistor T4 comprising a fourth channel region A4, a fourth source region S4, and a fourth drain region D4. For example, the channel region, source region, and drain region of each of the third transistor T3 and the fourth transistor T4 may be part of the oxide semiconductor layer. The fourth source region S4 of the fourth transistor T4 may overlap with the first initialization voltage line 147.

[0150] The fourth semiconductor layer AO4 may include the fourth electrode CE4 of the second capacitor Cbt. The fourth electrode CE4 of the second capacitor Cbt may extend from the fourth semiconductor layer AO4 of the fourth transistor T4. For example, the fourth electrode CE4 may include an oxide semiconductor and may be disposed on the first interlayer insulating layer 114. The second gate insulating layer 113 and the first interlayer insulating layer 114 are disposed between the third electrode CE3 and the fourth electrode CE4 of the second capacitor Cbt, and the second gate insulating layer 113 and the first interlayer insulating layer 114 may serve as the dielectric layer of the second capacitor Cbt.

[0151] The upper scan line 163 of the third scan line SL3 may extend in the first direction on the oxide semiconductor layer. For example, the third scan line SL3 may be provided as two conductive layers disposed on different layers. The upper scan line 163 of the third scan line SL3 may be configured to at least partially overlap with the lower scan line 137. Figure 11 As illustrated, the portion of the upper scan line 163 of the third scan line SL3 that overlaps with the fourth semiconductor layer AO4 can be the upper gate electrode G4b of the fourth transistor T4. Figure 11 As illustrated, the upper gate electrode G3b of the third transistor T3, which at least partially overlaps with the protrusion 135P of the emitter control line 135, can be disposed on the third semiconductor layer AO3 of the third transistor T3. For example, the third transistor T3 and the fourth transistor T4 can have a dual-gate structure in which control electrodes are provided above and below the semiconductor layer, respectively. The upper gate electrode G3b of the third transistor T3 can be connected to the connection electrode 174 via a contact opening (e.g., a contact hole) 45 in the second interlayer insulating layer 116, and the connection electrode 174 can be connected to the emitter control line 135 via a contact opening (e.g., a contact hole) 47 in the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116.

[0152] The third gate insulating layer 115 can be disposed between the fourth semiconductor layer AO4 and the upper scan line 163 of the third scan line SL3, and between the third semiconductor layer AO3 and the upper gate electrode G3b. The third gate insulating layer 115 can be patterned in a shape corresponding to the upper scan line 163 and the emission control line 135 of the third scan line SL3.

[0153] The third gate insulating layer 115 may include an inorganic material comprising oxides or nitrides. For example, the third gate insulating layer 115 may include SiO2. x SiN x At least one of SiON, Al2O3, TiO2, Ta2O5, HfO2, and ZnO2. The upper gate electrode G3b of the third transistor T3 and the upper gate electrode G4b of the fourth transistor T4 can be disposed on the third gate insulating layer 115, which may include at least one of Mo, Cu, and Ti, and can be formed as a single layer structure or formed as a multilayer structure.

[0154] The second interlayer insulating layer 116 can be configured to cover the third transistor T3 and the fourth transistor T4. The second interlayer insulating layer 116 can be disposed on the upper gate electrode G3b of the third transistor T3 and the upper gate electrode G4b of the fourth transistor T4. The first drive voltage line 172, the node connection line 171, and the connection electrodes 173, 174, 175, 176, and 177 can be disposed on the second interlayer insulating layer 116.

[0155] The second interlayer insulating layer 116 may include an inorganic material comprising oxides or nitrides. For example, the second interlayer insulating layer 116 may include SiO2. x SiN x At least one of SiON, Al2O3, TiO2, Ta2O5, HfO2 and ZnO2.

[0156] The first driving voltage line 172, the node connection line 171, and the connecting electrodes 173, 174, 175, 176, and 177 may comprise highly conductive materials such as metals or conductive oxides. For example, the first driving voltage line 172, the node connection line 171, and the connecting electrodes 173, 174, 175, 176, and 177 may comprise at least one of Al, Cu, and Ti, and may be formed as a single-layer structure or formed as a multilayer structure. In some embodiments, the first driving voltage line 172, the node connection line 171, and the connecting electrodes 173, 174, 175, 176, and 177 may be provided as a three-layer structure of titanium, aluminum, and titanium (Ti / Al / Ti) arranged (or stacked) in sequence.

[0157] The first driving voltage line 172 can be connected to the second electrode CE2 of the first capacitor Cst via a contact opening (e.g., a contact hole) 41 formed in the first interlayer insulating layer 114 and the second interlayer insulating layer 116. The first driving voltage line 172 can be connected to the fifth source region S5 of the fifth transistor T5 via a contact opening (e.g., a contact hole) 42 formed in the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116.

[0158] A portion of the node connection line 171 may be connected to the first gate electrode G1 via a contact opening (e.g., a contact hole) 31. The contact opening 31 may penetrate the second interlayer insulating layer 116, the first interlayer insulating layer 114, and the second gate insulating layer 113, and may expose the first gate electrode G1. A portion of the node connection line 171 is inserted into the contact opening 31 such that the node connection line 171 can be electrically connected to the first gate electrode G1.

[0159] The contact opening 31 is configured to be separated from the edge of the opening SOP within the opening SOP of the second electrode CE2 (e.g., spaced apart), and the node connection line 171 inserted into the contact opening 31 can be electrically connected to the first electrode CE1 (e.g., the contact opening 31 does not contact the second electrode CE2 or the contact opening 31 is not open to the second electrode CE2).

[0160] One end of the node connection line 171 can be connected to the third semiconductor layer AO3 via a contact opening (e.g., a contact hole) 46. The contact opening 46 can penetrate the second interlayer insulating layer 116 and expose the third semiconductor layer AO3.

[0161] The other end of the node connection line 171 can be connected to the fourth electrode CE4 or the fourth semiconductor layer AO4 of the second capacitor Cbt via a contact opening (e.g., a contact hole) 32. The contact opening 32 can penetrate the second interlayer insulating layer 116 and expose the fourth semiconductor layer AO4.

[0162] The fourth electrode CE4 of the second capacitor Cbt can be connected to the node connection line 171 and can be electrically connected to the first gate electrode G1. Accordingly, when the first scan signal SSn supplied via the first scan line SL1 is turned off (e.g., set to high), the second capacitor Cbt can clearly express the black grayscale by increasing the voltage at node N2 (see, for example...). Figure 6 ).

[0163] One end of the connecting electrode 173 can be connected to the sixth source region S6 of the sixth transistor T6 and the first drain region D1 of the first transistor T1 via a contact opening (e.g., a contact hole) 34. The contact opening 34 can penetrate the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116, and expose the silicon semiconductor layer. The other end of the connecting electrode 173 can be connected to the third drain region D3 of the third transistor T3 via a contact opening (e.g., a contact hole) 33. The contact opening 33 can penetrate the second interlayer insulating layer 116 and expose the oxide semiconductor layer.

[0164] The connecting electrode 175 can be connected to the second source region S2 of the second transistor T2 via a contact opening (e.g., a contact hole) 35 formed in the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116.

[0165] A portion of the connecting electrode 176 can be connected to the fourth source region S4 of the fourth transistor T4 via a contact opening (e.g., a contact hole) 36 formed in the second interlayer insulating layer 116, and connected to the first initialization voltage line 147 via a contact opening (e.g., a contact hole) 37 formed in the first interlayer insulating layer 114 and the second interlayer insulating layer 116.

[0166] The connecting electrode 177 can be connected to the drain region D6 of the sixth transistor T6 via a contact opening (e.g., a contact hole) 38 formed in the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116.

[0167] The first planarization layer 118 can be disposed on the first drive voltage line 172, the node connection line 171, and the connection electrodes 173, 174, 175, 176, and 177.

[0168] Data line 181, second drive voltage line 183 and connection electrode 185 can be disposed on the first planarization layer 118.

[0169] Data line 181 can be connected to connection electrode 175 via contact opening (e.g., contact hole) 61 formed in the first planarization layer 118, and thus connected to the second source region S2 of the second transistor T2. Figure 9 As illustrated, data line 181 can be configured to partially overlap with first drive voltage line 172. In terms of cross-section, first drive voltage line 172 can be disposed on a layer between the first gate electrode G1 of first transistor T1 and data line DL. Accordingly, first drive voltage line 172 can reduce the coupling between first gate electrode G1 and data line 181.

[0170] The second driving voltage line 183 can be connected to the first driving voltage line 172 via a contact opening (e.g., a contact hole) 62 formed in the first planarization layer 118. Figure 12 As illustrated, the second driving voltage line 183 may cover the fourth semiconductor layer AO4 of the fourth transistor T4. Accordingly, the second driving voltage line 183 may block light that can be applied from above the substrate 100 (e.g., it may block light that can be incident on the substrate 100 from above). Furthermore, a portion of the second driving voltage line 183 may overlap with the node connection line 171.

[0171] The connection electrode 185 can be connected to the connection electrode 177 via a contact opening (e.g., a contact hole) 63 formed in the first planarization layer 118, and thus connected to the drain region D6 of the sixth transistor T6. The connection electrode 185 can be connected to the pixel electrode 310 via a contact opening (e.g., a contact hole) 64 formed in the second planarization layer 119, and can transmit signals applied through the sixth transistor T6 to the pixel electrode 310.

[0172] The first planarization layer 118 and the second planarization layer 119 may comprise organic materials such as acrylic acid, benzocyclobutene (BCB), polyimide, or hexamethyldisilane (HMDSO). In other embodiments, the first planarization layer 118 and the second planarization layer 119 may each comprise an inorganic material. The first planarization layer 118 and the second planarization layer 119 may serve as protective layers covering the first transistor T1 through the seventh transistor T7, and the upper surfaces of the first planarization layer 118 and the second planarization layer 119 may be flat (e.g., planar). The first planarization layer 118 and the second planarization layer 119 may be provided as a single layer or as a multilayer structure.

[0173] A pixel defining layer 120 may be disposed on the second planarization layer 119. The pixel defining layer 120 may have an opening corresponding to each pixel, i.e., an opening exposing at least the central (or center) portion of the pixel electrode 310, thereby defining the pixel. Furthermore, the pixel defining layer 120 may increase the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310, thereby preventing, for example, the generation of electric arcs at the edges of the pixel electrode 310. The pixel defining layer 120 may comprise an organic material such as polyimide or HMDSO.

[0174] The intermediate layer 320 of the OLED may comprise a low molecular weight material or a polymer material. When comprising a low molecular weight material, the intermediate layer 320 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emitter layer (EML), an electron transport layer (ETL), and / or an electron injection layer (EIL) are stacked, and the intermediate layer 320 may comprise various suitable organic materials such as copper phthalocyanine (CuPc), N,N'-bis(naphthyl-1-yl)-N,N'-diphenyl-benzidine (NPB), or aluminum tri-8-hydroxyquinoline (Alq3). The above layers may be formed using a vacuum deposition method.

[0175] When polymer materials are included, the intermediate layer 320 may include a structure comprising an HTL and an EML. In this embodiment, the HTL may include poly(3,4-ethylenedioxythiophene) (PEDOT), and the EML may include polymer materials of the polyphenylene vinylidene (PPV) type and polyfluorene type. The intermediate layer 320 may be formed using screen printing, inkjet printing, or laser-induced thermal imaging (LITI) methods.

[0176] The intermediate layer 320 is not limited to the structure and configuration described above, and can have various suitable structures. The intermediate layer 320 may include an integrated layer over the plurality of pixel electrodes 310 (e.g., extending continuously over the plurality of pixel electrodes 310), or may include a layer patterned corresponding to each of the pixel electrodes 310.

[0177] The counter electrode 330 can be integrally formed relative to multiple OLEDs corresponding to the pixel electrode 310.

[0178] Because OLEDs are easily damaged by external moisture or oxygen, a thin-film encapsulation layer or sealing substrate can be disposed on the OLED to cover and protect it. The thin-film encapsulation layer can cover the display area DA and extend beyond the display area DA. The thin-film encapsulation layer can include an inorganic encapsulation layer having at least one inorganic material and an organic encapsulation layer having at least one organic material. In some embodiments, the thin-film encapsulation layer can be provided as a structure in which a first inorganic encapsulation layer / organic encapsulation layer / second inorganic encapsulation layer is stacked (or sequentially stacked). The sealing substrate can be positioned facing the substrate 100 and can be bonded to the substrate 100 in the peripheral area PA using a sealing member such as a sealant or frit.

[0179] Furthermore, spacers for preventing mask scratches may be provided on the pixel defining layer 120, and various functional layers such as polarizing layers for reducing external light reflection, black matrices, color filters, and / or touchscreen layers with touch electrodes may be provided on the thin-film encapsulation layer.

[0180] Figure 13 This is an equivalent circuit diagram of a pixel according to another embodiment. Figure 14 A schematic diagram showing the positions of a plurality of thin-film transistors and capacitors arranged on a pair of pixel circuits of a display device according to another embodiment is illustrated. Figure 15 It is along Figure 14 A schematic cross-sectional view of the line V-V', and Figure 16 and Figure 17 Each is illustrated in the diagram. Figure 14 The diagram shows only the layout of some of the components. For clarity, details relating to the above references are omitted. Figures 6 to 12 Descriptions of elements that are the same as or substantially similar to the described elements.

[0181] Figure 13 The pixel circuit shown is Figure 6 The pixel circuit shown differs in that the gate electrode of the third transistor T3 is connected to the emitter control line EL, except that the gate electrode of the third transistor T3 is connected to the fourth scan line SL4. Figure 13 In the pixel circuit shown, the fourth scan line SL4 can receive the first transmit control signal ESn together with the transmit control line EL. In an embodiment, the fourth scan line SL4 can be a branch line of the transmit control line EL. Figure 7 The timing diagram shown can be applied to Figure 13 The driving timing of the pixel circuit shown is shown.

[0182] refer to Figure 14 and Figure 15 The fourth scan line SL4 may extend in a first direction (e.g., the x direction) between the first scan line 133 and the emission control line 135.

[0183] The semiconductor layers of the third transistor T3 and the fourth transistor T4 can be disposed on the same layer and can comprise the same material. For example, the semiconductor layer can comprise an oxide semiconductor.

[0184] The third semiconductor layer AO3 of the third transistor T3 may include a third channel region A3 and a third source region S3 and a third drain region D3 on both sides of the third channel region A3. The third source region S3 may be bridged to the first gate electrode G1 via node connection line 171. In addition, the third source region S3 may be connected to a fourth drain region D4 disposed on the same layer. The third drain region D3 may be electrically connected to the first semiconductor layer AS1 of the first transistor T1 and the sixth semiconductor layer AS6 of the sixth transistor T6. The third gate electrode G3 may be part of the fourth scan line SL4.

[0185] The gate electrode of the third transistor T3 can be connected to the fourth scan line SL4. The first electrode of the third transistor T3 is connected to the gate electrode of the first transistor T1, and the second electrode of the third transistor T3 is connected to the second electrode of the first transistor T1 and connected to the OLED via the sixth transistor T6. The third transistor T3 can be turned on by the first transmit control signal ESn received via the fourth scan line SL4 to connect the diode of the first transistor T1.

[0186] The fourth scan line SL4 may include a lower scan line 145 and an upper scan line 165 disposed on different layers. The lower scan line 145 may be provided on the same layer as the second electrode CE2 of the first capacitor Cst and the first initialization voltage line 147, and may comprise the same material as the second electrode CE2 of the first capacitor Cst and the first initialization voltage line 147. The upper scan line 165 may be disposed on the third gate insulating layer 115. The lower scan line 145 may be configured to at least partially overlap with the upper scan line 165. The lower scan line 145 and the upper scan line 165 may correspond to the third gate electrode of the third transistor T3, and the third transistor T3 may have a dual-gate structure having control electrodes provided above and below the semiconductor layer, respectively. In another embodiment, the fourth scan line SL4 may include only the upper scan line 165 while the lower scan line 145 is omitted, and therefore the third transistor T3 may have a single-gate structure.

[0187] The fourth electrode CE4 of the second capacitor Cbt can be provided on the same layer as the third semiconductor layer AO3 of the third transistor T3 and the fourth semiconductor layer AO4 of the fourth transistor T4, and can be the region between the third semiconductor layer AO3 and the fourth semiconductor layer AO4. In another embodiment, the fourth electrode CE4 can extend from the fourth semiconductor layer AO4. In another embodiment, the fourth electrode CE4 can extend from the third semiconductor layer AO3.

[0188] One end of the node connection line 171 can be connected to the first gate electrode G1 via the contact opening 31. The other end of the node connection line 171 can be connected to the fourth electrode CE4 of the second capacitor Cbt, or connected to the fourth semiconductor layer AO4 or the third semiconductor layer AO3 via the contact opening 32 (see example). Figure 9 ).

[0189] According to an embodiment, because the driving circuit for driving the display element includes a first thin-film transistor comprising a silicon semiconductor and a second thin-film transistor comprising an oxide semiconductor, a display device with low power consumption and high resolution can be provided. According to an embodiment, because the second thin-film transistor is driven using an emission control driving circuit without including a separate scan driving circuit for driving the second thin-film transistor, the peripheral region PA can be reduced.

[0190] Furthermore, in a direction parallel to the surface of the substrate (in a plan view), as the gate electrode of the first thin-film transistor and the node connection lines and data lines connected thereto are vertically separated (e.g., vertically separated or spaced apart) by the insulating layer in the multilayer structure, and another voltage layer is provided between the gate electrode of the first thin-film transistor and the node connection lines and data lines connected to the gate electrode of the first thin-film transistor, the effect of the coupling capacitance between the gate electrode and the data lines of the first thin-film transistor can be reduced.

[0191] Furthermore, because the pixel circuitry includes a boost capacitor, black and grayscale can be clearly achieved.

[0192] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and are not intended for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A pixel, comprising: Light-emitting diode; The first transistor includes a gate electrode, a first electrode connected to a node, and a second electrode connected to the light-emitting diode, and transmits drive current to the light-emitting diode; A second transistor is connected between the data line and the node; A third transistor is connected between the gate electrode of the first transistor and the second electrode; A fourth transistor is connected between the gate electrode of the first transistor and the first initialization voltage line; The fifth transistor is connected between the drive voltage line and the node; and The sixth transistor is connected between the second electrode of the first transistor and the light-emitting diode. Wherein, the first transistor includes a PMOS transistor, and the third transistor and the fourth transistor each include an NMOS transistor, and The length of the conduction voltage of the first transmit control signal that turns on the third transistor is the same as the length of the conduction voltage of the second transmit control signal that turns on the fourth transistor. in: The second transistor is turned on by the first scan signal output from the scan drive circuit. The third transistor, the fifth transistor, and the sixth transistor are turned on by a first transmit control signal output from the transmit control drive circuit, and The fourth transistor is turned on by a second transmit control signal output from the transmit control drive circuit before the first transmit control signal.

2. The pixel according to claim 1, wherein, The PMOS transistor comprises silicon semiconductor, and The NMOS transistor comprises an oxide semiconductor.

3. The pixel according to claim 1, further comprising: A first capacitor is connected between the driving voltage line and the gate electrode of the first transistor; and A second capacitor is connected between the gate electrode of the first transistor and the gate electrode of the second transistor.

4. The pixel according to claim 1, further comprising: The first scan line is connected to the gate electrode of the second transistor; The second scan line is connected to the gate electrode of the fourth transistor; and The transmit control line is connected to the gate electrode of the third transistor, the gate electrode of the fifth transistor, and the gate electrode of the sixth transistor.

5. The pixel according to claim 1, further comprising: The first scan line is connected to the gate electrode of the second transistor; The second scan line is connected to the gate electrode of the fourth transistor; The third scan line is connected to the gate electrode of the third transistor; and The transmit control line is connected to the gate electrode of the fifth transistor and the gate electrode of the sixth transistor. The third scan line is a branch line of the emission control line.

6. The pixel according to claim 1, further comprising: The seventh transistor is connected between the light-emitting diode and the second initialization voltage line, and is turned on by the second scan signal.

7. The pixel according to claim 6, wherein, The second scan signal is output before the first scan signal, or after the first scan signal.

8. The pixel according to claim 6, wherein, The second transistor, the fifth transistor, the sixth transistor, and the seventh transistor each comprise a PMOS transistor containing silicon semiconductor.

9. A display device, comprising: Multiple pixels; A scan drive circuit is configured to supply scan signals to the plurality of pixels; An emission control drive circuit is configured to supply an emission control signal to the plurality of pixels; and A data driving circuit is configured to supply data signals to the plurality of pixels. Each of the plurality of pixels includes: Light-emitting diode; The first transistor includes a gate electrode, a first electrode connected to a node, and a second electrode connected to the light-emitting diode, and transmits drive current to the light-emitting diode; A second transistor is connected between the data line and the node; A third transistor is connected between the gate electrode of the first transistor and the second electrode; A fourth transistor is connected between the gate electrode of the first transistor and the first initialization voltage line; The fifth transistor is connected between the drive voltage line and the node; and A sixth transistor is connected between the second electrode of the first transistor and the light-emitting diode, wherein the first transistor includes a PMOS transistor, and the third and fourth transistors each include an NMOS transistor. The length of the conduction voltage of the first transmit control signal that turns on the third transistor is the same as the length of the conduction voltage of the second transmit control signal that turns on the fourth transistor. in: The second transistor is turned on by the first scan signal in the scan signal output from the scan drive circuit. The third transistor, the fifth transistor, and the sixth transistor are turned on by the first transmission control signal in the transmission control signal output from the transmission control drive circuit, and The fourth transistor is turned on by a second transmit control signal output from the transmit control drive circuit before the first transmit control signal.

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