Display device

Abstract

A display device includes a substrate having a display area and a non-display area. Multiple pixels are arranged in the display area. A chip mounting area is arranged in the non-display area. The chip mounting area includes data output pad units, light-emitting test transistor units, and multiple lines connecting the data output pad units and the light-emitting test transistor units. The light-emitting test transistor units are configured to transmit at least one light-emitting test signal to the multiple pixels through the data output pad units. Each of the multiple lines has the same resistance.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0017182, filed on February 12, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a display device. Background Technology

[0004] A display device is a device for displaying images. Display devices include display panels such as organic light-emitting display panels or liquid crystal display panels.

[0005] Organic light-emitting diode (OLED) display devices are a type of self-emitting display device. An OLED display device includes an organic light-emitting layer inserted between a pixel electrode and a counter electrode. When the pixel electrode and counter electrode inject electrons and holes into the organic light-emitting layer, respectively, excitons are generated by the recombination of electrons and holes. Light is generated when the excitons transition from the excited state to the ground state.

[0006] Display devices using chip-on-plastic (COP) or chip-on-glass (COG) methods for directly attaching driver integrated circuits to a transistor array substrate include a chip mounting region to which the driver integrated circuit is bonded. The chip mounting region may include a plurality of output pads electrically connected to output bumps of the driver integrated circuit, and a plurality of input pads electrically connected to input bumps of the driver integrated circuit to supply signals from the outside to the driver integrated circuit.

[0007] Light emission testing can be performed during the manufacturing process of the display panel of a display device. Light emission testing detects whether the display panel is driven by applying a test signal to the display panel in a state where the driving integrated circuit is not mounted in the chip mounting area.

[0008] In such display devices, static electricity may be generated during the manufacturing process. When static electricity is generated and transferred to the light-emitting thin-film transistor (TFT) for testing, it may damage the TFT and prevent normal light-emitting tests from being performed. Summary of the Invention

[0009] The technical objective of this invention is to provide a display device that protects light-emitting thin-film transistors from the effects of static electricity generated during the manufacturing process.

[0010] The purpose of this disclosure is not limited to the above-described technical objectives, and other technical objectives not described will be clearly understood by those skilled in the art from the following description.

[0011] According to an exemplary embodiment of the present invention, a display device includes a substrate having a display area and a non-display area. A plurality of pixels are arranged in the display area. A chip mounting area is arranged in the non-display area. The chip mounting area includes a data output pad unit, a light-emitting test transistor unit, and multiple lines connecting the data output pad unit and the light-emitting test transistor unit. The light-emitting test transistor unit is configured to transmit at least one light-emitting test signal to the plurality of pixels through the data output pad unit.

[0012] The resistance of the multiple lines connected between the data output pad unit and the light-emitting test transistor unit is the same.

[0013] The data output pad unit may include a first data output pad, a second data output pad, and a third data output pad configured in multiple rows. The light-emitting test transistor unit may include a first light-emitting test transistor, a second light-emitting test transistor, and a third light-emitting test transistor configured in multiple rows. The length of the first line connecting one end of the first data output pad and one end of the first light-emitting test transistor to each other, the length of the second line connecting one end of the second data output pad and one end of the second light-emitting test transistor to each other, and the length of the third line connecting one end of the third data output pad and one end of the third light-emitting test transistor to each other may be the same.

[0014] The first data output pad, the second data output pad, and the third data output pad can have a quadrilateral shape, such as a parallelogram.

[0015] The chip mounting area may further include data input pad units connected to the light-emitting test transistor unit, and the data input pad units may be connected to multiple ground lines.

[0016] Each of the resistors in the multiple grounding wires can be between 500KΩ and 1MΩ.

[0017] The gate electrode of the first light-emitting test transistor, the gate electrode of the second light-emitting test transistor, and the gate electrode of the third light-emitting test transistor can be respectively connected to the lines supplying the first light-emitting test control signal, the second light-emitting test control signal, and the third light-emitting test control signal, and the other terminals of the first light-emitting test transistor, the second light-emitting test transistor, and the third light-emitting test transistor can be respectively connected to the first test signal line, the second test signal line, and the third test signal line.

[0018] The first test signal applied through the first test signal line can be a red test signal, the second test signal applied through the second test signal line can be a green test signal, and the third test signal applied through the third test signal line can be a blue test signal.

[0019] The chip mounting area may further include a dummy output pad unit arranged on at least one side of the data output pad unit; and a dummy transistor unit connected to the dummy output pad unit.

[0020] The dummy output pad unit may include a first dummy output pad, a second dummy output pad, and a third dummy output pad configured in multiple rows. The dummy transistor unit may include a first dummy transistor, a second dummy transistor, and a third dummy transistor configured in multiple rows. The length of the fourth line connecting one end of the first dummy output pad and one end of the first dummy transistor to each other, the length of the fifth line connecting one end of the second dummy output pad and one end of the second dummy transistor to each other, and the length of the sixth line connecting one end of the third dummy output pad and one end of the third dummy transistor to each other may be the same.

[0021] The first dummy output pad, the second dummy output pad, and the third dummy output pad can have any shape, either parallelogram or triangle.

[0022] The lengths of the first, second, and third lines can be longer than the lengths of the fourth, fifth, and sixth lines, respectively.

[0023] The chip mounting area may include dummy input pad units connected to dummy transistor units, and the dummy input pad units may be connected to multiple ground lines.

[0024] Each of the resistors in the multiple grounding wires can be between 500KΩ and 1MΩ.

[0025] The gate electrode of the first dummy transistor, the gate electrode of the second dummy transistor, and the gate electrode of the third dummy transistor, as well as the other terminals of the first dummy transistor, the second dummy transistor, and the third dummy transistor, can be in a floating state.

[0026] The data output pad unit may include a first data output pad, a second data output pad, and a third data output pad configured in multiple rows. The light-emitting test transistor unit may include a first light-emitting test transistor, a second light-emitting test transistor, and a third light-emitting test transistor configured in multiple rows. Some of the following may include a first line connecting one end of the first data output pad and one end of the first light-emitting test transistor, a second line connecting one end of the second data output pad and one end of the second light-emitting test transistor, and a third line connecting one end of the third data output pad and one end of the third light-emitting test transistor: a first line connecting one end of the first data output pad and one end of the second light-emitting test transistor, and a third line connecting one end of the third data output pad and one end of the third light-emitting test transistor: a third line connecting one end of the third light-emitting test transistor, a second line connecting one end of the third data output pad and one end of the third light-emitting test transistor, a third line connecting one end of the third data output pad and one end of the third light-emitting test transistor, a third line connecting one end of the first ...

[0027] The chip mounting area may include data input pad units that are connected to the light-emitting test transistor unit, and the data input pad units may be connected to multiple ground lines.

[0028] The chip mounting area may include a dummy output pad unit arranged on at least one side of the data output pad unit; and a dummy transistor unit connected to the dummy output pad unit.

[0029] The dummy output pad unit may include a first dummy output pad, a second dummy output pad, and a third dummy output pad configured in multiple rows. The dummy transistor unit may include a first dummy transistor, a second dummy transistor, and a third dummy transistor configured in multiple rows. The length of the fourth line connecting one end of the first dummy output pad and one end of the first dummy transistor to each other, the length of the fifth line connecting one end of the second dummy output pad and one end of the second dummy transistor to each other, and the length of the sixth line connecting one end of the third dummy output pad and one end of the third dummy transistor to each other may be the same.

[0030] The chip mounting area may include dummy input pad units connected to dummy transistor units, and the dummy input pad units may be connected to multiple ground lines.

[0031] Each of the resistors in the multiple grounding wires can be between 500KΩ and 1MΩ.

[0032] The display device according to embodiments of the present disclosure can protect the light-emitting test thin-film transistors from electrostatic effects through the pad wiring of the display panel.

[0033] The effects of this disclosure are not limited to those illustrated above, and many more effects are included in this specification. Attached Figure Description

[0034] The above and other features of this disclosure will become more apparent from the further detailed description of exemplary embodiments of this disclosure with reference to the accompanying drawings, in which:

[0035] Figure 1 This is a diagram illustrating an exemplary embodiment of the present invention, including a shorting bar on a mother substrate.

[0036] Figure 2 This is a plan view illustrating an exemplary display device according to a concept of the present invention;

[0037] Figure 3 This is a cross-sectional view of a display device according to an exemplary embodiment of the present invention;

[0038] Figure 4 This is a circuit diagram of pixels included in a display device according to an exemplary embodiment of the present invention.

[0039] Figure 5 This is an exemplary embodiment of the concept of the present invention. Figure 2 A block diagram of the chip mounting area shown;

[0040] Figure 6 This is a diagram illustrating the wiring of a light-emitting test pad and a light-emitting test thin-film transistor according to an exemplary embodiment of the present invention;

[0041] Figure 7 This is a diagram illustrating the wiring of a dummy pad and a dummy thin-film transistor according to an exemplary embodiment of the present invention.

[0042] Figure 8 This is a diagram illustrating the wiring of a light-emitting test pad and a light-emitting test thin-film transistor according to an exemplary embodiment of the present invention;

[0043] Figure 9 This is an exemplary embodiment of the concept of the present invention. Figure 8 An enlarged view of region A; and

[0044] Figure 10 This is a diagram illustrating the wiring of a dummy pad and a dummy thin-film transistor according to an exemplary embodiment of the present invention. Detailed Implementation

[0045] The same reference numerals refer to the same components. Furthermore, in the drawings, the thickness, proportions, and dimensions of the components are exaggerated for the purpose of effectively describing the technical content. "And / or" includes all of one or more combinations that can be defined by associated configurations.

[0046] Terms such as “first,” “second,” etc., can be used to describe various components. However, components are not limited by these terms. Terms are used only to distinguish one component from another. For example, without departing from the scope of the inventive concept, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0047] Furthermore, the terms "below," "below," "above," and "over" are used to describe the relationships between the configurations shown in the accompanying drawings. These terms are described as relative concepts based on the directions indicated in the drawings.

[0048] It should be understood that terms such as "comprising," "having," etc., are used to specify the presence of features, quantities, steps, operations, components, parts, or combinations thereof described in the specification. However, these terms do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof.

[0049] Figure 1 This is a diagram used to describe the mother substrate including the shorting bar.

[0050] Reference Figure 1 In an exemplary embodiment, the mother substrate 1 includes a plurality of unit regions CA. Each unit region CA may correspond to an array substrate of a unit display panel completed in a subsequent process.

[0051] The size of each of the multiple unit areas CA can be changed according to the size of the display device. Figure 1 In an exemplary embodiment, 28 cell regions CA are formed in a mother substrate 1. However, the exemplary embodiments of the present invention are not limited thereto, and in other exemplary embodiments, the number and arrangement of the plurality of cell regions CA may be changed.

[0052] According to an exemplary embodiment of the present invention, a shorting strip SB can be formed in the mother substrate 1. For example, the shorting strip SB can be formed from a plurality of horizontal portions SB_H formed for each horizontal row of a plurality of cell regions CA and an edge portion SB_E connecting the plurality of horizontal portions SB_H and surrounding the entire edge of the plurality of cell regions CA.

[0053] Each of the multiple cell regions CA includes a non-display region NDA and a display region DA. The non-display region NDA may include a chip mounting region ICA to which a driver integrated circuit is bonded, and the display region DA may include panel load cells. The panel load cells may include electrical components such as multiple gate lines, multiple data lines, and multiple thin-film transistors formed in the display region DA.

[0054] The chip mounting area ICA can be electrically connected to the shorting bar SB via multiple connection lines, such as multiple ground lines GRL. The chip mounting area ICA may be part of a driver integrated circuit (IC) attached in a subsequent process. In an exemplary embodiment, a display device including the chip mounting area ICA may be a chip-on-plastic (COP) or chip-on-glass (COG) type display device in which the driver IC is directly connected to the array substrate. However, exemplary embodiments of the inventive concept are not limited thereto.

[0055] Because the shorting bar SB is formed to be much larger than the other lines, it can be used as a charge storage device. Since the stage on which the mother substrate 1 is placed is mostly grounded during the thin-film transistor process, the charge accumulated in the shorting bar SB can be discharged through the stage.

[0056] The deposition process of the mother substrate 1 can be performed under vacuum using a deposition equipment. A mask can be placed on the mother substrate 1 for the deposition process. When the mother substrate 1 and the mask come into contact with each other, charges accumulated in the mother substrate 1 through induction, friction, and stripping charges are simultaneously discharged to the point of contact with the mask, potentially damaging previously formed thin-film transistors. The mother substrate 1 and the mask are typically in contact with each other at the central region C of the mother substrate 1 by their own gravity. Therefore, it is necessary to protect the cell region CA located in the center of the mother substrate 1 from electrostatic discharge.

[0057] Figure 2 This is a diagram illustrating a display device according to an exemplary embodiment of the concept of the present invention.

[0058] Reference Figure 2 In an exemplary embodiment, the display device 10 may include a display area DA and a non-display area NDA in a plan view. The display device 10 may include a plurality of pixels PX. The area in which the plurality of pixels PX are arranged is defined as the display area DA. Figure 2 In the exemplary embodiment shown, the non-display area NDA may be defined along the edge of the display area DA. For example, the non-display area NDA may surround at least one side of the display area DA. In the exemplary embodiment, a plurality of pixels PX may be formed by repeatedly arranged red pixels, green pixels, and blue pixels, and the red pixels, green pixels, and blue pixels may include a unit pixel.

[0059] The display device 10 may include a scan line SL, a data line DL, an emission line EL, an initialization voltage line VINT, a first power supply voltage line ELVDD, a pad unit PD, an anti-static diode unit EPD, a driver integrated circuit DRC, and a chip mounting area ICA.

[0060] Scan lines SL are connected to corresponding pixels PX among multiple pixels PX, and data lines DL are also connected to corresponding pixels PX among multiple pixels PX. Each emitter line EL can be arranged parallel to its corresponding scan line SL. For example... Figure 2 In the exemplary embodiment shown, scan line SL and emitter line EL may extend in a first direction DR1. An initialization voltage line VINT may provide an initialization voltage to multiple pixels PX. A voltage line PL may be connected to the multiple pixels PX and may provide a first voltage to the multiple pixels PX. The voltage line PL may extend in the first direction DR1 and includes multiple lines disposed in a second direction DR2 perpendicular to the first direction DR1.

[0061] The scan drive circuit SDR, connected to the scan line SL and the emission line EL, can be positioned on one side of the non-display area NDA. For example, as... Figure 2 In the exemplary embodiment shown, the scan drive circuit SDR can be arranged to the left of the non-display area NDA. However, the exemplary embodiments of the inventive concept are not limited thereto. Some of the scan lines SL, data lines DL, transmit lines EL, initialization voltage lines VINT, and voltage lines PL can be arranged on the same layer, and other lines can be arranged on different layers.

[0062] The antistatic diode unit EPD can be located (for example, on the second direction DR2) in the non-display area NDA between the display area DA and the chip mounting area ICA.

[0063] The pad unit PD can be connected to the ends of the initialization voltage line VINT and the first power supply voltage line ELVDD.

[0064] The chip mounting area (ICA) can be arranged in the non-display area (NDA) of the substrate (SUB). The driver integrated circuit (DRC) for driving multiple scan lines (SL) and multiple data lines (DL) to display images on multiple pixels (PX) is mounted on the chip mounting area (ICA).

[0065] The driver integrated circuit (DRC) can be mounted on the chip mounting area (ICA) after the light emission testing process for multiple pixel PXs. The DRC supplies gate signals to multiple scan lines (SLs) based on power, timing control signals, and timing clock signals input from the flexible circuit board attached to the substrate (SUB). Furthermore, the DRC converts digital input data from the flexible circuit board into analog data signals and supplies the converted data signals to multiple data lines (DLs). The input pad unit (IPD) and output pad unit (OPD) on which the DRC is mounted can be configured as follows: Figure 5 The exemplary embodiment shown is formed in the chip mounting area ICA, which will be described later.

[0066] The chip mounting area ICA can be connected to the shorting bar SB via the ground wire GRL. A portion of the multiple ground wires GRL can be exposed to the outside along the cut lines CTL that divide the mother substrate 1 into each cell area CA. See below for further details. Figure 6 and Figure 7 The exemplary embodiment of the grounding wire GRL is described in detail.

[0067] Figure 3 This is a cross-sectional view of a display device according to an exemplary embodiment of the present invention.

[0068] Reference Figure 3In an exemplary embodiment, the display device 10 may include a substrate SUB and a circuit layer DP-CL disposed on the substrate SUB on a third direction DR3 perpendicular to the upper surface of the substrate SUB and perpendicular to the first direction DR1 and the second direction DR2. A light-emitting element layer DP-OLED (e.g., on the third direction DR3) is disposed on the circuit layer DP-CL. An encapsulation layer TFE surrounds the light-emitting element layer DP-OLED. For example, as... Figure 3 In the exemplary embodiment shown, the encapsulation layer TFE can directly contact the upper surface and side surface of the light-emitting element layer DP-OLED.

[0069] In exemplary embodiments, the substrate SUB may include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite substrate, etc. For example, the plastic substrate may include at least one material selected from acrylic resins, methacrylic resins, polyisoprene, ethylene resins, epoxy resins, polyurethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins. In exemplary embodiments, the substrate SUB may be a flexible substrate. However, the exemplary embodiments of the present invention are not limited thereto, and in other exemplary embodiments, the substrate SUB may be a rigid substrate.

[0070] The substrate SUB can be divided into a display area DA and a non-display area NDA adjacent to the display area DA. For example, the non-display area NDA can be arranged at the edge of the display area DA. However, exemplary embodiments of the present invention are not limited thereto. For example, in an exemplary embodiment, the non-display area NDA can be defined on only one side of the display area DA.

[0071] The DP-CL circuit layer can be disposed on the substrate SUB. The DP-CL circuit layer can be disposed within the display area DA and the non-display area NDA of the substrate SUB. The DP-CL circuit layer may include at least one pixel insulating layer, multiple conductive layers, and a semiconductor layer. The multiple conductive layers of the DP-CL circuit layer can be configured with signal lines or pixel driving circuitry.

[0072] The DP-OLED light-emitting element layer can include organic light-emitting diodes. The DP-OLED light-emitting element layer can be arranged in the display area DA.

[0073] An encapsulation layer TFE can be disposed on the DP-OLED light-emitting element layer. The TFE can be arranged to surround the DP-OLED light-emitting element layer. The TFE can cover and seal the DP-OLED light-emitting element layer. In an exemplary embodiment, the TFE can include at least one inorganic layer and at least one organic layer. For example, the TFE can include at least two inorganic layers and an organic layer disposed between the at least two inorganic layers. The inorganic layer protects the DP-OLED light-emitting element layer from moisture / oxygen, and the organic layer protects the DP-OLED light-emitting element layer from foreign matter such as dust particles. In an exemplary embodiment, the inorganic layer can include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, etc. The organic layer can include an acrylic organic material. However, exemplary embodiments of the present invention are not limited thereto. In an exemplary embodiment, the inorganic layer can be provided by a deposition method, and the organic layer can be provided by a coating process. However, exemplary embodiments of the present invention are not limited thereto.

[0074] The touch sensing unit TS is disposed on the encapsulation layer TFE. For example, as Figure 3 In the exemplary embodiments shown, the touch sensing unit TS can be (e.g., on the third-party DR3) directly disposed on the encapsulation layer TFE. However, the exemplary embodiments of the inventive concept are not limited thereto, and in other exemplary embodiments, an inorganic layer can be disposed between the encapsulation layer TFE and the touch sensing unit TS. The inorganic layer can be a buffer layer. In the exemplary embodiments, the inorganic layer can be at least one selected from a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. However, this is merely an example, and the exemplary embodiments of the inventive concept are not limited thereto. Furthermore, the buffer layer can be an organic layer. Although the buffer layer has been described as a separate configuration, the encapsulation layer TFE can be configured to include a buffer layer.

[0075] The touch sensing unit TS includes a touch sensor and touch signal lines. The touch sensor and touch signal lines can have a single-layer or multi-layer structure.

[0076] In an exemplary embodiment, the touch sensor and touch signal line may include at least one compound selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The touch sensor and touch signal line may include a metal layer (e.g., molybdenum, silver, titanium, copper, aluminum, or alloys thereof). The touch sensor and touch signal line may have the same layer structure or different layer structures. Details of the touch sensing unit TS will be described later.

[0077] Figure 4 This is a circuit diagram of pixels included in a display device according to an exemplary embodiment of the present invention. Figure 4The diagram shows connections to multiple data lines (DL) (see reference). Figure 2 Let PXij be the i-th pixel of the j-th data line Dj. Each of i and j can be a positive integer.

[0078] Reference Figure 4 In an exemplary embodiment, pixel PXij may include a first transistor to a seventh transistor T1, T2, T3, T4, T5, T6 and T7, a storage capacitor Cst and an organic light-emitting diode OLED.

[0079] Although the transistors in the exemplary embodiments of the present invention are shown as P-type transistors, in other exemplary embodiments, the pixel circuits may be configured to perform the same functions as N-type transistors.

[0080] The first electrode of the storage capacitor Cst can be connected to the first power supply voltage line ELVDD, and the second electrode of the storage capacitor Cst can be connected to the gate electrode of the first transistor T1.

[0081] In the first transistor T1, the first electrode can be connected to the second electrode of the fifth transistor T5, the second electrode of the first transistor T1 can be connected to the first electrode of the sixth transistor T6, and the gate electrode of the first transistor T1 can be connected to the second electrode of the storage capacitor Cst. The first transistor T1 can be referred to as the driving transistor. The first transistor T1 determines the amount of driving current flowing between the first power supply voltage line ELVDD and the second power supply voltage line ELVSS based on the potential difference between the gate electrode and the source electrode.

[0082] In the second transistor T2, the first electrode can be connected to the data line Dj, and the second electrode of the second transistor T2 can be connected to the first electrode of the first transistor T1. The gate electrode of the second transistor T2 can be connected to the current scan line Si. The second transistor T2 can be referred to as a switching transistor, a scan transistor, a gate transistor, etc. When a scan signal with a conduction level is applied to the current scan line Si, the second transistor T2 introduces the data voltage of the data line Dj into the pixel PXij.

[0083] In the third transistor T3, the first electrode is connected to the second electrode of the first transistor T1, the second electrode of the third transistor T3 is connected to the gate electrode of the first transistor T1, and the gate electrode of the third transistor T3 is connected to the current scan line Si. When a scan signal with a conduction level is applied to the current scan line Si, the third transistor T3 is connected to the first transistor T1 in a diode configuration.

[0084] In the fourth transistor T4, the first electrode is connected to the gate electrode of the first transistor T1, the second electrode of the fourth transistor T4 is connected to the initialization voltage line VINT, and the gate electrode of the fourth transistor T4 is connected to the previous scan line S(i-1). In another exemplary embodiment, the gate electrode of the fourth transistor T4 may be connected to another scan line. When a scan signal with an on-level is applied to the previous scan line S(i-1), the fourth transistor T4 transmits an initialization voltage to the gate electrode of the first transistor T1 to initialize the charge on the gate electrode of the first transistor T1.

[0085] In the fifth transistor T5, the first electrode is connected to the first power supply voltage line ELVDD, the second electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1, and the gate electrode of the fifth transistor T5 is connected to the emitter line Ei. In the sixth transistor T6, the first electrode is connected to the second electrode of the first transistor T1, the second electrode of the sixth transistor T6 is connected to the anode of the organic light-emitting diode (OLED), and the gate electrode of the sixth transistor T6 is connected to the emitter line Ei. The fifth transistor T5 and the sixth transistor T6 can be referred to as emitter transistors. When a conduction-level emitter signal is applied to the emitter line Ei, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power supply voltage line ELVDD and the second power supply voltage line ELVSS, causing the organic light-emitting diode (OLED) to emit light.

[0086] In the seventh transistor T7, the first electrode is connected to the anode of the organic light-emitting diode (OLED), the second electrode of the seventh transistor T7 is connected to the initialization voltage line VINT, and the gate electrode of the seventh transistor T7 is connected to the current scan line Si. In another exemplary embodiment, the gate electrode of the seventh transistor T7 may be connected to another scan line. For example, the gate electrode of the seventh transistor T7 may be connected to the previous scan line S(i-1), the scan line preceding scan line S(i-1), the next scan line (the (i+1)th scan line), or the scan line following the (i+1)th scan line. When a scan signal with an on-level is applied to the current scan line Si, the seventh transistor T7 transmits the initialization voltage to the anode of the organic light-emitting diode (OLED) to initialize the amount of charge accumulated in the organic light-emitting diode (OLED).

[0087] In an organic light-emitting diode (OLED), the anode can be connected to the second electrode of the sixth transistor T6, and the cathode can be connected to the second power supply voltage line ELVSS.

[0088] Figure 5 yes Figure 2 A block diagram of the chip mounting area shown in an exemplary embodiment.

[0089] Reference Figure 5 In an exemplary embodiment, the chip mounting area ICA may include an output pad unit OPD, an input pad unit IPD, a first dummy transistor unit DM_TR1, a second dummy transistor unit DM_TR2, and a light emission test transistor unit DT_TR. Probe pads PP may be arranged outside the chip mounting area ICA. A driver integrated circuit DRC may be mounted on the chip mounting area ICA after the light emission test process. (See the driver integrated circuit DRC for reference.) Figure 2 It can include multiple input bumps and multiple output bumps.

[0090] An input pad unit (IPD) may include multiple input pads electrically connected to multiple input bumps formed in a driver integrated circuit (DRC). The input pad unit (IPD) may include a data input pad unit (DTP12), a first dummy input pad unit (DMP12), and a second dummy input pad unit (DMP22). Each of the multiple input pad units (IPDs) may be electrically connected to a flexible circuit board.

[0091] Output pad units (OPDs) can be electrically connected to multiple output bumps formed in the driver integrated circuit (DRC). An output pad unit (OPD) may include a data output pad unit (DTP11), a first dummy output pad unit (DMP11), and a second dummy output pad unit (DMP21). Each of the multiple output pad units (OPDs) can be electrically connected to multiple data lines (DLs) formed in the display area (DA) via data connection lines (DCLs).

[0092] In the chip mounting area (ICA), a first dummy transistor unit DM_TR1, a second dummy transistor unit DM_TR2, and a light-emitting test transistor unit DT_TR can be arranged between the input pad unit IPD and the output pad unit OPD. The light-emitting test transistor unit DT_TR can be electrically connected to the output pad unit OPD to supply test signals to the output pad unit OPD. The first dummy transistor unit DM_TR1 and the second dummy transistor unit DM_TR2 can be connected to the first dummy output pad unit DMP11 and the second dummy output pad unit DMP21, respectively. However, the first dummy transistor unit DM_TR1 and the second dummy transistor unit DM_TR2 do not supply test signals to the output pad unit OPD.

[0093] The probe pad PP can supply various test signals from the test fixture to the light-emitting test transistor unit DT_TR via the test signal line during the light-emitting test process, and can also supply various enable signals to the light-emitting test transistor unit DT_TR via the enable signal line.

[0094] In the display device 10, the output pad unit OPD formed in the chip mounting area ICA may not be covered by an insulating layer and may be exposed to the outside during the manufacturing process. Therefore, the thin-film transistor may be damaged due to static electricity. In related fields, when comparing the resistance of the conductor connected to the display area DA based on the data output pad unit DTP11 with the conductor connected to the light-emitting test transistor unit DT_TR through the anti-static diode unit EPD, because the resistance of the conductor connected to the light-emitting test transistor unit DT_TR is relatively small, electrostatic current flows towards the light-emitting test transistor unit DT_TR. Therefore, there have been cases where the light-emitting test transistor unit DT_TR is damaged. Hereinafter, reference will be made to… Figures 6 to 10 The exemplary embodiments are described in detail with a wiring method for preventing damage to the light-emitting test transistor unit DT_TR.

[0095] Figure 6 This is a diagram illustrating the wiring of a light-emitting test pad and a light-emitting test thin-film transistor according to an exemplary embodiment of the present invention.

[0096] Reference Figure 2 , Figure 5 and Figure 6 In an exemplary embodiment, the display area DA may include a first pixel, a second pixel, and a third pixel that emit different colors of light. For example, the first pixel, the second pixel, and the third pixel may have a structure that is respectively disposed on lines in the first column line, the second column line, and the third column line. Each pixel may include, for example, Figure 4 The pixel circuit PC shown in the exemplary embodiment.

[0097] In an exemplary embodiment, the first pixel may be a red pixel that emits red light, the second pixel may be a blue pixel that emits blue light, and the third pixel may be a green pixel that emits green light.

[0098] However, exemplary embodiments of the present invention are not limited thereto. For example, in other exemplary embodiments, the display area DA may further include different color pixels (e.g., white pixels, etc.) for displaying colors other than red, green, and blue.

[0099] The light-emitting test transistor unit DT_TR can include multiple transistors. For example, such as Figure 6In the exemplary embodiment shown, the light-emitting test transistor unit DT_TR may include a first light-emitting test transistor M1 to a third light-emitting test transistor M3. However, the exemplary embodiment of the inventive concept is not limited thereto, and the number of transistors may be varied in other exemplary embodiments. The first terminals of the first light-emitting test transistors M1 to M3 may be connected to each of the plurality of data output pads DT_OP of the data output pad unit DTP11, and the opposite second terminals of the first light-emitting test transistors M1 to M3 may be connected to each of the plurality of data input pads DT_IP of the data input pad unit DTP12. Each of the data output pads DT_OP may be connected to a plurality of data lines DL formed in the display area DA via a data connection line DCL through an antistatic diode unit EPD. The light-emitting test transistor unit DT_TR transmits the light-emitting test signal to the pixels in the display area DA through the data output pad unit DTP11.

[0100] For example, such as Figure 6 In the exemplary embodiment shown, the red test signal DC_R, the blue test signal DC_B, and the green test signal DC_G can be supplied to the data line DL respectively through the light-emitting test transistor unit DT_TR. However, in the exemplary embodiment that includes pixels of different colors, the supplied test signals can correspond to pixels of different colors. Figure 6 In the exemplary embodiment shown, the gate of the first light-emitting test transistor M1 can be commonly connected to the line supplying the first light-emitting test control signal Gate_C1, the gate of the second light-emitting test transistor M2 can be commonly connected to the line supplying the second light-emitting test control signal Gate_C2, and the gate of the third light-emitting test transistor M3 can be commonly connected to the line supplying the third light-emitting test control signal Gate_C3.

[0101] The first light emission test control signal Gate_C1, the second light emission test control signal Gate_C2, and the third light emission test control signal Gate_C3 can be in DC form used to maintain the conduction state of the first light emission test transistor, the second light emission test transistor, and the third light emission test transistors M1 to M3. During light emission testing, the first light emission test control signal Gate_C1, the second light emission test control signal Gate_C2, and the third light emission test control signal Gate_C3 can be supplied to the gates of the first light emission test transistor, the second light emission test transistor, and the third light emission test transistors M1 to M3. Therefore, while maintaining the conduction state, the first light emission test transistor, the second light emission test transistor, and the third light emission test transistors M1 to M3 can supply the red test signal DC_R, the blue test signal DC_B, and the green test signal DC_G supplied from the light emission test signal lines to multiple data lines DL, respectively.

[0102] The scan drive circuit (SDR) can sequentially generate scan signals and supply them to the display area (DA). Therefore, pixels receiving the scan signals and the light emission test signals can emit light to display an image, and thus, light emission tests can be performed.

[0103] Although all of the first light-emitting test transistors M1 to the third light-emitting test transistors M3 are shown as PMOS type transistors, the exemplary embodiments of the present invention are not limited thereto. For example, in another exemplary embodiment, all of the first light-emitting test transistors M1 to the third light-emitting test transistors M3 may be NMOS type transistors or transistors of different conductivity types.

[0104] According to an exemplary embodiment of the present invention, a plurality of corresponding data output pads DT_OP can be spaced apart from each other at predetermined intervals and can be formed in parallel in a plurality of rows. For example, the plurality of data output pads DT_OP may include a first data output pad DT_OP1, a second data output pad DT_OP2, and a third data output pad DT_OP3. However, the exemplary embodiments of the present invention are not limited thereto, and in other exemplary embodiments, the number of the plurality of data output pads DT_OP can be varied. Figure 6 In the exemplary embodiment shown, the first data output pad DT_OP1, the second data output pad DT_OP2, and the third data output pad DT_OP3 may have a quadrilateral shape, such as a parallelogram. However, the exemplary embodiment of the inventive concept is not limited thereto. The first data output pad DT_OP1, the second data output pad DT_OP2, and the third data output pad DT_OP3 may be arranged in three rows.

[0105] The corresponding first light-emitting test transistor, second light-emitting test transistor, and third light-emitting test transistors M1 to M3 can be spaced apart from each other at a predetermined interval and can be formed in parallel in multiple rows. For example, as Figure 6 In the exemplary embodiment shown, the first light-emitting test transistor, the second light-emitting test transistor, and the third light-emitting test transistors M1 to M3 can be arranged in three rows. The corresponding first light-emitting test transistor, second light-emitting test transistor, and third light-emitting test transistors M1 to M3 can be spaced apart from the first data output pad DT_OP1, the second data output pad DT_OP2, and the third data output pad DT_OP3 at the same interval.

[0106] For example, the resistance of the first line L1 corresponding to the line from the first data output pad DT_OP1 to the first light-emitting test transistor M1, the resistance of the second line L2 corresponding to the line from the second data output pad DT_OP2 to the second light-emitting test transistor M2, and the resistance of the third line L3 corresponding to the line from the third data output pad DT_OP3 to the third light-emitting test transistor M3 can all be substantially the same.

[0107] Typically, electrostatic current is more likely to flow towards the data output pad DT_OP connected to the line with lower resistance among the multiple data output pads DT_OP. According to an exemplary embodiment of the present invention, when the resistance of each of the first line L1, second line L2, and third line L3 corresponding to the lines between the first light-emitting test transistor, the second light-emitting test transistor, and the third light-emitting test transistors M1 to M3 and the first data output pad DT_OP1, the second data output pad DT_OP2, and the third data output pad DT_OP3 is balanced, the electrostatic current may not flow towards any of the multiple data output pads DT_OP, and the electrostatic current may more likely flow towards areas other than the multiple data output pads DT_OP.

[0108] Multiple corresponding data input pads DT_IP can be spaced apart from each other at predetermined intervals and can be formed in parallel in multiple rows. For example, the multiple data input pads DT_IP may include a first data input pad DT_IP1, a second data input pad DT_IP2, and a third data input pad DT_IP3. However, exemplary embodiments of the inventive concept are not limited thereto, and in other exemplary embodiments, the number of multiple data input pads DT_IP can be varied. Figure 6In the exemplary embodiment shown, the first data input pad DT_IP1, the second data input pad DT_IP2, and the third data input pad DT_IP3 may have a parallelogram shape. However, the exemplary embodiment of the inventive concept is not limited thereto. The first data input pad DT_IP1, the second data input pad DT_IP2, and the third data input pad DT_IP3 may be arranged in three rows.

[0109] The first terminal of the first data input pad DT_IP1, the first terminal of the second data input pad DT_IP2, and the first terminal of the third data input pad DT_IP3 can be connected to the first light-emitting test transistor, the second light-emitting test transistor, and the third light-emitting test transistor M1 to M3, respectively. Furthermore, the relative second terminals of the first data input pad DT_IP1, the second data input pad DT_IP2, and the third data input pad DT_IP3 can be connected to the first terminals of multiple ground lines GRL. Figure 1 and Figure 6 The short-circuit bar SB is shown in the exemplary embodiment. Multiple grounding wires GRL can be formed with bends to maximize their length in a relatively narrow space. Therefore, the multiple grounding wires GRL can have high resistance values. For example, in the exemplary embodiment, the resistance of the grounding wires GRL can be in the range of approximately 500 kΩ to approximately 1 MΩ.

[0110] Therefore, even if electrostatic current flows to any of the multiple data output pads DT_OP during the manufacturing process of the display device 10, the instantaneous discharge of electrostatic current can be prevented because the ground wire GRL with a high resistance value is located on the path through which the electrostatic current is emitted. Thus, damage to the first light-emitting test transistor, the second light-emitting test transistor, and the third light-emitting test transistors M1 to M3, which are located on the emission path of the electrostatic current, can be prevented.

[0111] A portion of the multiple grounding wires GRL, spaced apart from the first end of the multiple grounding wires GRL, can be exposed to the outside along the cutting lines CTL used to cut the mother substrate 1 into each cell region CA. Therefore, the grounding wires GRL can be used to prevent static electricity from flowing into the display device 10 from the outside after the driver integrated circuit DRC is mounted on the chip mounting region ICA.

[0112] Figure 7 This is a diagram illustrating the wiring of dummy pads and dummy thin-film transistors according to an exemplary embodiment of the present invention.

[0113] Reference Figure 2 , Figure 5 and Figure 6In an exemplary embodiment, a first dummy output pad unit DMP11 may be arranged to the left of a data output pad unit DTP11, and a second dummy output pad unit DMP21 may be arranged to the right of a data output pad unit DTP11. Each of the plurality of first dummy output pads DMP11 and the plurality of second dummy output pads DMP21 is not electrically connected to a display area DA. Although the positions of the first dummy output pad units DMP11 and the second dummy output pad units DMP21 differ from each other, the first dummy output pad units DMP11 and the second dummy output pad units DMP21 are configured to be substantially identical. Therefore, a description of the dummy output pad units will be given based on the first dummy output pad unit DMP11.

[0114] According to an exemplary embodiment of the present invention, a plurality of corresponding dummy output pads DM_OP in the first dummy output pad unit DMP11 can be spaced apart from each other at a predetermined interval and can be formed in parallel in multiple rows. For example, as Figure 7 In the exemplary embodiment shown, the plurality of dummy output pads DM_OP may include a first dummy output pad DM_OP1, a second dummy output pad DM_OP2, and a third dummy output pad DM_OP3. However, the exemplary embodiments of the present invention are not limited thereto, and in other exemplary embodiments, the number of the plurality of dummy output pads DM_OP may be varied. For example... Figure 7 In the exemplary embodiment shown, the first dummy output pad DM_OP1, the second dummy output pad DM_OP2, and the third dummy output pad DM_OP3 may have a parallelogram shape. However, the exemplary embodiments of the inventive concept are not limited thereto. Figure 7 In the exemplary embodiment shown, the first dummy output pad DM_OP1, the second dummy output pad DM_OP2, and the third dummy output pad DM_OP3 can be arranged in three rows.

[0115] Similarly, the corresponding first dummy transistor, second dummy transistor, and third dummy transistors M4 to M6 in the first dummy transistor unit DM_TR1 can be spaced apart from each other at predetermined intervals and can be formed in parallel in multiple rows. For example, as Figure 7 In the exemplary embodiment shown, the first dummy transistor, the second dummy transistor, and the third dummy transistors M4 to M6 can be arranged in three rows. The corresponding first dummy transistor, second dummy transistor, and third dummy transistors M4 to M6 can be spaced apart from the first dummy output pad, the second dummy output pad, and the third dummy output pad DM_OP1, DM_OP2, and DM_OP3 at the same distance.

[0116] However, with Figure 6In contrast to the first, second, and third light-emitting test transistors M1 to M3 shown in the exemplary embodiment, the first, second, and third dummy transistors M4 to M6 may not supply the first light-emitting test control signal Gate_C1, the second light-emitting test control signal Gate_C2, the third light-emitting test control signal Gate_C3, the red test signal DC_R, the blue test signal DC_B, and the green test signal DC_G to multiple data lines DL respectively. For example, the first, second, and third dummy transistors M4 to M6 may be in a floating state. For example, the gate electrode and the second terminal of the first to third dummy transistors M4 to M6 may be in a floating state.

[0117] According to an exemplary embodiment of the present invention, the distance between the first dummy output pad unit DMP11 and the first dummy transistor unit DM_TR1 can be shorter than the distance between the data output pad unit DTP11 and the light-emitting test transistor unit DT_TR. For example, Figure 7 The length of the fourth line L4, which corresponds to the line from the first dummy output pad DM_OP1 to the first dummy transistor M4, shown in the exemplary embodiment, can be greater than... Figure 6 The first line L1 shown in the exemplary embodiment is short in length, corresponding to the line from the first data output pad DT_OP1 to the first light-emitting test transistor M1. Figure 7 The length of the fifth line L5, corresponding to the line from the second dummy output pad DM_OP2 to the second dummy transistor M5, shown in the exemplary embodiment, can be greater than... Figure 6 In the exemplary embodiment shown, the length of the second line L2 corresponding to the line from the second data output pad DT_OP2 to the second light-emitting test transistor M2 is short. Similarly, Figure 7 The length of the sixth line L6, corresponding to the line from the third dummy output pad DM_OP3 to the third dummy transistor M6 shown in the exemplary embodiment, can be greater than... Figure 6 The third line L3 shown in the exemplary embodiment is shorter than the line from the third data output pad DT_OP3 to the third light-emitting test transistor M3.

[0118] Among the first dummy output pad unit DMP11, the second dummy output pad unit DMP21, and the data output pad unit DTP11, electrostatic current is more likely to flow towards the side connected to the line with lower resistance. Therefore, when the distance between the first dummy output pad unit DMP11 and the first dummy transistor unit DM_TR1 is shorter than the distance between the data output pad unit DTP11 and the light-emitting test transistor unit DT_TR, electrostatic current is more likely to flow towards the first dummy transistor unit DM_TR1 rather than the light-emitting test transistor unit DT_TR.

[0119] Multiple corresponding dummy input pads DM_IP in the first dummy input pad unit DMP12 can be spaced apart from each other at predetermined intervals and can be formed in parallel in multiple rows. For example, the multiple dummy input pads DM_IP may include a first dummy input pad DM_IP1, a second dummy input pad DM_IP2, and a third dummy input pad DM_IP3. However, exemplary embodiments of the present invention are not limited thereto, and in other exemplary embodiments, the number of multiple dummy input pads DM_IP can be varied. Figure 7 In the exemplary embodiment shown, the first dummy input pad DM_IP1, the second dummy input pad DM_IP2, and the third dummy input pad DM_IP3 may have a parallelogram shape. However, the exemplary embodiments of the inventive concept are not limited thereto. Figure 7 In the exemplary embodiment shown, the first dummy input pad DM_IP1, the second dummy input pad DM_IP2, and the third dummy input pad DM_IP3 can be arranged in three rows.

[0120] The first terminals of the first dummy input pad DM_IP1, the second dummy input pad DM_IP2, and the third dummy input pad DM_IP3 can be connected to the first dummy transistor, the second dummy transistor, and the third dummy transistor M4 to M6, respectively, and their respective second terminals can be connected to multiple ground lines GRL. The second terminals of the multiple ground lines GRL can be connected to... Figure 1 , Figure 6 and Figure 7 The short-circuit bar SB is shown in an exemplary embodiment. Multiple grounding wires GRL can be formed with bends to maximize their length in confined spaces. Therefore, the multiple grounding wires GRL can have high resistance values. For example, the resistance of the grounding wires GRL can be in the range of approximately 500 kΩ to approximately 1 MΩ.

[0121] A portion of the multiple grounding wires GRL, spaced apart from the first end of the multiple grounding wires GRL, can be exposed to the outside along the cutting lines CTL used to cut the mother substrate 1 into each cell region CA. Therefore, the grounding wires GRL can be used to prevent static electricity from flowing into the display device 10 from the outside after the driver integrated circuit DRC is mounted on the chip mounting region ICA.

[0122] Other exemplary embodiments of the inventive concept will be described below. In the following exemplary embodiments, configurations identical to those already described will be omitted or simplified, and the differences will be described primarily.

[0123] Figure 8 This is a diagram illustrating the wiring of a light-emitting test pad and a light-emitting test thin-film transistor according to another exemplary embodiment of the present invention. Figure 9 This is an exemplary embodiment of the concept of the present invention. Figure 8 A magnified view of region A.

[0124] Reference Figure 2 , Figure 5 , Figure 8 and Figure 9 An exemplary embodiment, Figure 8 The exemplary embodiments shown are in conjunction with Figure 6 The difference in the exemplary embodiment shown is that the shortest distance from the first data output pad DT_OP1 to the first light-emitting test transistor M1', the shortest distance from the second data output pad DT_OP2 to the second light-emitting test transistor M2', and the shortest distance from the third data output pad DT_OP3 to the third light-emitting test transistor M3' are different from each other.

[0125] The light-emitting test transistor unit DT_TR' can include multiple transistors. For example, such as Figure 8 In the exemplary embodiment shown, the plurality of transistors in the light-emitting test transistor unit DT_TR' may include a first light-emitting test transistor M1' to a third light-emitting test transistor M3'. However, the exemplary embodiments of the present invention are not limited thereto, and in other exemplary embodiments, the number of transistors in the light-emitting test transistor unit DT_TR' may be varied. Figure 6In contrast to the first light-emitting test transistors M1' to M3' shown in the exemplary embodiment, the first light-emitting test transistors M1' to M3' are arranged in the same row. The first terminals of the first light-emitting test transistors M1' to M3' can be respectively connected to a plurality of data output pads DT_OP, and the opposite second terminals of the first light-emitting test transistors M1' to M3' can be respectively connected to a plurality of data input pads DT_IP. Each of the data output pads DT_OP can be connected to a plurality of data lines DL formed in the display area DA via an anti-static diode unit EPD (e.g., via a data connection line DCL).

[0126] The red test signal DC_R, the blue test signal DC_B, and the green test signal DC_G can be supplied to the data line DL through the first light-emitting test transistor M1', the second light-emitting test transistor M2', and the third light-emitting test transistor M3', respectively. The gates of the first light-emitting test transistor M1', the second light-emitting test transistor M2', and the third light-emitting test transistor M3' can be jointly connected to the line supplying the fourth light-emitting test control signal Gate_C4.

[0127] During the light emission test, a fourth light emission test control signal, Gate_C4, in DC form, used to maintain the on-state of the first, second, and third light emission test transistors M1' to M3', can be supplied to the gates of these transistors. Therefore, while maintaining the on-state, the first, second, and third light emission test transistors M1' to M3' can supply the red test signal DC_R, the blue test signal DC_B, and the green test signal DC_G, respectively, from the light emission test signal lines to multiple data lines DL.

[0128] The scan drive circuit (SDR) can sequentially generate scan signals and supply them to the display area (DA). Therefore, pixels receiving the scan signals and the light emission test signals can emit light to display an image, and thus, light emission tests can be performed.

[0129] Although all of the first light-emitting test transistors M1' to the third light-emitting test transistors M3' are shown as PMOS type transistors, the exemplary embodiments of the present invention are not limited thereto. For example, in other exemplary embodiments, all of the first light-emitting test transistors M1' to the third light-emitting test transistors M3' may be NMOS type transistors or transistors of different conductivity types.

[0130] According to an exemplary embodiment of the present invention, a plurality of corresponding data output pads DT_OP can be spaced apart from each other at predetermined intervals and can be formed in parallel in a plurality of rows. For example, the plurality of data output pads DT_OP may include a first data output pad DT_OP1, a second data output pad DT_OP2, and a third data output pad DT_OP3. However, the exemplary embodiment of the present invention is not limited thereto, and in other exemplary embodiments, the number of the plurality of data output pads DT_OP can be varied. In an exemplary embodiment, the first data output pad DT_OP1, the second data output pad DT_OP2, and the third data output pad DT_OP3 may have a parallelogram shape. However, the exemplary embodiment of the present invention is not limited thereto. Figure 8 In the exemplary embodiment shown, the first data output pad DT_OP1, the second data output pad DT_OP2, and the third data output pad DT_OP3 can be set in three rows.

[0131] The corresponding first light-emitting test transistor, second light-emitting test transistor, and third light-emitting test transistors M1' to M3' can be spaced apart from each other at a predetermined interval and can be formed in parallel in a single row. However, exemplary embodiments of the inventive concept are not limited thereto. The shortest distance from the first data output pad DT_OP1 to the first light-emitting test transistor M1', the shortest distance from the second data output pad DT_OP2 to the second light-emitting test transistor M2', and the shortest distance from the third data output pad DT_OP3 to the third light-emitting test transistor M3' can be different from each other. For example, as Figure 8 As shown in the exemplary embodiment, the shortest distance from the third data output pad DT_OP3 to the third light-emitting test transistor M3' can be greater than the shortest distance from the first data output pad DT_OP1 to the first light-emitting test transistor M1' and the shortest distance from the second data output pad DT_OP2 to the second light-emitting test transistor M2'. The shortest distance from the second data output pad DT_OP2 to the second light-emitting test transistor M2' can also be greater than the shortest distance from the first data output pad DT_OP1 to the first light-emitting test transistor M1'. However, the exemplary embodiments of the present invention are not limited thereto.

[0132] However, as Figure 9In the exemplary embodiment shown, the lengths of the first line L1' corresponding to the length from the first data output pad DT_OP1 to the first light-emitting test transistor M1', the second line L2' corresponding to the length from the second data output pad DT_OP2 to the second light-emitting test transistor M2', and the third line L3' corresponding to the length from the third data output pad DT_OP3 to the third light-emitting test transistor M3' can be made substantially the same by adjusting the bending period. For example, as Figure 9 In the exemplary embodiment shown, the bending period from the first data output pad DT_OP1 to the first light-emitting test transistor M1' can be greater than the bending period from the second data output pad DT_OP2 to the second light-emitting test transistor M2'. The bending period from the second data output pad DT_OP2 to the second light-emitting test transistor M2' can be greater than the bending period from the third data output pad DT_OP3 to the third light-emitting test transistor M3'.

[0133] For example, all of the following can be substantially the same: the resistance corresponding to the length of the first line L1' from the first data output pad DT_OP1 to the first light-emitting test transistor M1', the resistance corresponding to the length of the second line L2' from the second data output pad DT_OP2 to the second light-emitting test transistor M2', and the resistance corresponding to the length of the third line L3' from the third data output pad DT_OP3 to the third light-emitting test transistor M3'.

[0134] therefore, Figures 8 to 9 The wiring of the light-emitting test pads and light-emitting test thin-film transistors of the display device shown in the exemplary embodiment will have the same characteristics as... Figure 6 The exemplary embodiments shown have the same or similar effects.

[0135] Figure 10 This is a diagram illustrating the wiring of a dummy pad and a dummy thin-film transistor according to another exemplary embodiment of the present invention.

[0136] Reference Figure 2 , Figure 5 , Figure 7 and Figure 10 An exemplary embodiment of the present exemplary embodiment and Figure 7 The difference in the exemplary embodiment shown is that the first dummy output pad DM_OP1', the second dummy output pad DM_OP2', and the third dummy output pad DM_OP3' have a triangular shape with sharp ends.

[0137] Specifically, multiple corresponding dummy output pads DM_OP' can be spaced apart from each other at predetermined intervals and can be formed in parallel in multiple rows. For example, the multiple dummy output pads DM_OP' may include a first dummy output pad DM_OP1', a second dummy output pad DM_OP2', and a third dummy output pad DM_OP3'. However, exemplary embodiments of the inventive concept are not limited thereto, and in other exemplary embodiments, the number of multiple dummy output pads DM_OP' can be varied. At least some of the first dummy output pad DM_OP1', the second dummy output pad DM_OP2', and the third dummy output pad DM_OP3' may have a triangular shape with sharp ends. Figure 10 In the exemplary embodiment shown, the first dummy output pad DM_OP1', the second dummy output pad DM_OP2', and the third dummy output pad DM_OP3' can be arranged in three rows.

[0138] Typically, charge can be distributed relatively widely on a conductor surface with a small radius of curvature (e.g., a sharp portion). When static electricity is generated, current can easily flow through the areas where charge accumulates. Therefore, when the first dummy output pad DM_OP1', the second dummy output pad DM_OP2', and the third dummy output pad DM_OP3' have a triangular shape with sharp ends, the electrostatic current generated during the manufacturing process of the display device 10 is more likely to flow to the first dummy output pad to the third dummy output pad DM_OP1', DM_OP2', and DM_OP3' compared to multiple data output pads DT_OP with a parallelogram shape.

[0139] The scope of this invention is not limited to the details described in the exemplary embodiments. All changes, modifications, and equivalent concepts are included within the scope of this invention.

Claims

1. A display device, comprising: The substrate includes both the display area and the non-display area; Multiple pixels arranged in the display area; as well as A chip mounting area is arranged in the non-display area. The chip mounting area includes a data output pad unit, a light-emitting test transistor unit, and multiple lines connecting the data output pad unit and the light-emitting test transistor unit. The light-emitting test transistor unit is configured to transmit at least one light-emitting test signal to the plurality of pixels through the data output pad unit. The resistance of each of the multiple lines is the same.

2. The display device according to claim 1, wherein: The data output pad unit includes a first data output pad, a second data output pad, and a third data output pad arranged in multiple rows; The light-emitting test transistor unit includes a first light-emitting test transistor, a second light-emitting test transistor, and a third light-emitting test transistor arranged in multiple rows, and The lengths of the first line connecting the first data output pad to the first terminal of the first light-emitting test transistor, the second line connecting the second data output pad to the first terminal of the second light-emitting test transistor, and the third line connecting the third data output pad to the first terminal of the third light-emitting test transistor are the same.

3. The display device according to claim 2, wherein: The chip mounting area further includes a data input pad unit connected to the light-emitting test transistor unit; and The data input pad unit is connected to multiple grounding lines.

4. The display device according to claim 3, wherein: The gate electrode of the first light-emitting test transistor, the gate electrode of the second light-emitting test transistor, and the gate electrode of the third light-emitting test transistor are respectively connected to the lines supplying the first light-emitting test control signal, the second light-emitting test control signal, and the third light-emitting test control signal; and The second terminals of the first light-emitting test transistor, the second light-emitting test transistor, and the third light-emitting test transistor are respectively connected to the first test signal line, the second test signal line, and the third test signal line.

5. The display device according to claim 2, wherein, The chip mounting area further includes: A dummy output pad unit disposed on at least one side of the data output pad unit; and The dummy transistor unit is connected to the dummy output pad unit.

6. The display device according to claim 5, wherein: The dummy output pad unit includes a first dummy output pad, a second dummy output pad, and a third dummy output pad, which are set in multiple rows; The dummy transistor unit includes a first dummy transistor, a second dummy transistor, and a third dummy transistor disposed in multiple rows; and The length of the fourth line connecting the first dummy output pad to the first terminal of the first dummy transistor, the length of the fifth line connecting the second dummy output pad to the first terminal of the second dummy transistor, and the length of the sixth line connecting the third dummy output pad to the first terminal of the third dummy transistor are the same.

7. The display device according to claim 6, wherein, The lengths of the first line, the second line, and the third line are respectively longer than the lengths of the fourth line, the fifth line, and the sixth line.

8. The display device according to claim 6, wherein: The chip mounting area includes dummy input pad units connected to the dummy transistor unit; and The dummy input pad unit is connected to multiple grounding lines.

9. The display device according to claim 6, wherein, The gate electrode of the first dummy transistor, the gate electrode of the second dummy transistor, and the gate electrode of the third dummy transistor, as well as the second terminal of the first dummy transistor, the second terminal of the second dummy transistor, and the second terminal of the third dummy transistor, are in a floating state.

10. The display device according to claim 1, wherein: The data output pad unit includes a first data output pad, a second data output pad, and a third data output pad arranged in multiple rows; The light-emitting test transistor unit includes a first light-emitting test transistor, a second light-emitting test transistor, and a third light-emitting test transistor arranged in multiple rows. At least one of the following lines includes a bent portion: a first line connecting the first data output pad to the first terminal of the first light-emitting test transistor, a second line connecting the second data output pad to the first terminal of the second light-emitting test transistor, and a third line connecting the third data output pad to the first terminal of the third light-emitting test transistor. The lengths of the first line, the second line, and the third line are the same; and At least two of the following shortest distances—from the first data output pad to the first end of the first light-emitting test transistor, from the second data output pad to the first end of the second light-emitting test transistor, and from the third data output pad to the first end of the third light-emitting test transistor—are different from each other.

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