Pixel circuit and display panel

Abstract

This invention provides a pixel circuit and a display panel. The pixel circuit includes a driving transistor and a first capacitor. The control terminal of the driving transistor is connected to a first terminal of the first capacitor at a first node, and the second terminal of the first capacitor is connected to a third node. A first initialization unit initializes the potential of the first node in response to a first scan signal. A data writing unit writes a data signal to the first node in response to a third scan signal. A compensation unit writes the threshold voltage of the driving transistor to the third node in response to either the first or fourth scan signal. A light-emitting control unit outputs the output current of the driving transistor to a light-emitting element in response to a light-emitting control signal. This invention adds a compensation unit, enabling the light-emitting control unit to respond to the same light-emitting control signal. Therefore, it eliminates the need for custom-developed driving chips, reducing the cost of the display panel and increasing its market penetration.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a pixel circuit and a display panel. Background Technology

[0002] Organic light-emitting display (OLED) devices have many advantages, such as being all-solid-state, self-emissive, having a wide viewing angle, a wide color gamut, fast response speed, high luminous efficiency, high brightness, high contrast, being ultra-thin and ultra-light, having low power consumption, a wide operating temperature range, the ability to manufacture large-size and flexible panels, and simple manufacturing processes. They can realize truly flexible displays and are becoming increasingly popular in the market.

[0003] An OLED display panel contains multiple pixel circuits and light-emitting elements that are electrically connected to each pixel circuit. Each pixel circuit contains a driving transistor, and the driving current generated by the driving transistor drives the organic light-emitting element to emit light and display. The magnitude of the driving current is used to control the brightness of the organic light-emitting element.

[0004] When the pixel circuit is working, the driver chip provides the necessary transmission signals to each unit of the pixel circuit, such as scan signals, light emission control signals, and data signals. The more transmission signals involved in the pixel circuit, the more pins are required on the driver chip, which will increase the cost of the driver chip accordingly. Summary of the Invention

[0005] To address the problems in the prior art, the present invention aims to provide a pixel circuit and a display panel. The pixel circuit requires fewer transmission signals, eliminates the need for custom-developed driver chips, reduces the cost of the display panel, and increases the market penetration rate of the display panel.

[0006] This invention provides a pixel circuit, comprising:

[0007] A driving transistor and a first capacitor, wherein the control terminal of the driving transistor is connected to a first node via a first terminal of the first capacitor, and the second terminal of the first capacitor is connected to a third node;

[0008] The first initialization unit, in response to the first scan signal, initializes the potential of the first node;

[0009] The data writing unit responds to the third scan signal to write the data signal to the first node;

[0010] The compensation unit, in response to the first scan signal or the fourth scan signal, writes the threshold voltage of the driving transistor to the third node;

[0011] The light-emitting control unit, in response to the light-emitting control signal, outputs the output current of the driving transistor to the light-emitting element, thereby controlling the light-emitting element to emit light.

[0012] In some embodiments, the first terminal of the driving transistor is electrically connected to the second node, and the second terminal of the driving transistor is electrically connected to the third node.

[0013] In some embodiments, the first initialization unit includes a second transistor, the control terminal of the second transistor is electrically connected to the first scan line, the first terminal of the second transistor is electrically connected to the first initialization line, and the second terminal of the second transistor is electrically connected to the first node.

[0014] In some embodiments, the data writing unit includes a third transistor, the control terminal of the third transistor being electrically connected to a third scan line, the first terminal of the third transistor being electrically connected to a data line, and the second terminal of the third transistor being electrically connected to the first node.

[0015] In some embodiments, the light-emitting control unit includes a fourth transistor and a fifth transistor, the control terminals of the fourth transistor and the fifth transistor are electrically connected to the light-emitting control line, the first terminal of the fourth transistor is electrically connected to the first power line, and the second terminal of the fourth transistor is electrically connected to the second node.

[0016] The first terminal of the fifth transistor is electrically connected to the third node, and the second terminal of the fifth transistor is electrically connected to the first terminal of the light-emitting element.

[0017] In some embodiments, the system further includes a second initialization unit and a third initialization unit, wherein the second initialization unit is used to initialize the potential of the first terminal of the light-emitting element; and the third initialization unit is used to initialize the potential of the third node.

[0018] The second initialization unit includes a sixth transistor, the control terminal of which is electrically connected to the second scan line, the first terminal of which is electrically connected to the second initialization line, and the second terminal of which is electrically connected to the first terminal of the light-emitting element; the second terminal of the light-emitting element is electrically connected to the second power line.

[0019] The third initialization unit includes a seventh transistor, the control terminal of which is electrically connected to the second scan line, the first terminal of which is electrically connected to the second initialization line, and the second terminal of which is electrically connected to the third node.

[0020] In some embodiments, the compensation unit includes an eighth transistor, the control terminal of which is electrically connected to the first scan line or the fourth scan line, the first terminal of which is electrically connected to the first power line or the first initialization line, and the second terminal of which is electrically connected to the second node.

[0021] In some embodiments, a second capacitor is further included, wherein the two substrates of the second capacitor are electrically connected to the potential stabilization line and the third node, respectively.

[0022] In some embodiments, at least one transistor in the pixel circuit includes a back gate, which is electrically connected to any one of the first power line, the first initialization line, the second initialization line, the second power line, the setting signal line, the control terminal of the transistor, the first terminal of the transistor, and the second terminal of the transistor.

[0023] This invention also provides a display panel, including the pixel circuit described above.

[0024] The pixel circuit and display panel provided by this invention have the following advantages:

[0025] This invention adds a compensation unit, enabling the light-emitting control unit to respond to the same light-emitting control signal, eliminating the need for custom-developed driver chips, reducing the cost of display panels, and increasing the market penetration rate of display panels. Attached Figure Description

[0026] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0027] Figure 1 This is a schematic diagram of a pixel circuit in the prior art;

[0028] Figure 2 yes Figure 1 The driving timing diagram of the pixel circuit;

[0029] Figure 3 This is a schematic diagram of a pixel circuit according to an embodiment of the present invention;

[0030] Figure 4 This is a driving timing diagram of a pixel circuit according to an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of the operation of a pixel circuit in the first time period according to an embodiment of the present invention;

[0032] Figure 6 This is a schematic diagram of the operation of a pixel circuit in the second time period according to an embodiment of the present invention;

[0033] Figure 7 This is a schematic diagram of the operation of a pixel circuit in the third time period according to an embodiment of the present invention;

[0034] Figure 8 This is a schematic diagram of the operation of a pixel circuit in the fourth time period according to an embodiment of the present invention;

[0035] Figure 9 This is a schematic diagram of a pixel circuit according to another embodiment of the present invention;

[0036] Figure 10 This is a schematic diagram of a pixel circuit according to another embodiment of the present invention;

[0037] Figure 11 This is a schematic diagram of a pixel circuit according to another embodiment of the present invention;

[0038] Figure 12 yes Figure 11 The driving timing diagram of the pixel circuit is shown.

[0039] Figure 13 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0040] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted.

[0041] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate different embodiments or examples represented in this application, as well as features of different embodiments or examples.

[0042] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0043] It should be further understood that the terms "comprising" or "including" indicate the presence of a feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C." Exceptions to this definition only arise when a combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0044] like Figure 1 and Figure 2 As shown, the fourth transistor T4' and the fifth transistor T5' in the pixel circuit control the emission time of the OLED element. When En1' and En2' are both high, the fourth transistor T4' and the fifth transistor T5' are turned on, driving transistor T1' to generate a driving current to drive the OLED element to emit light. When the pixel circuit performs PWM (Pulse Width Modulation) dimming, the high-level duty cycle of the first emission control signal En1' and the second emission control signal En2' needs to be adjusted to control the emission time of the OLED element. Figure 2 As shown, since the waveforms of the first light-emitting control signal En1' and the second light-emitting control signal En2' are different within a single frame display cycle, the driver chip (IC) needs to provide these two sets of light-emitting control signals separately to adjust their high and low duty cycles respectively. However, most current driver chips only support one set of light-emitting control signals. Therefore, developing a new driver chip is necessary to meet the requirements of the current pixel circuit during PWM dimming, which increases the cost of the driver chip and consequently the cost of the display panel, thus affecting the market penetration rate of the display panel.

[0045] To address the problems in the prior art, embodiments of the present invention provide a pixel circuit. Figure 3 A schematic diagram of a pixel circuit provided in an embodiment of the present invention is shown. For example... Figure 3 As shown, the pixel circuit includes:

[0046] A driving transistor T1 and a first capacitor C1 are connected. The control terminal of the driving transistor T1 is connected to the first terminal of the first capacitor C1 and the first node N1 is connected to the second terminal of the first capacitor C1 and the third node N3.

[0047] The first initialization unit 10 initializes the potential of the first node N1 in response to the first scan signal Sn1;

[0048] The data writing unit 20 responds to the third scan signal Sn3 to write the data signal Data to the first node N1;

[0049] The compensation unit 30, in response to the fourth scan signal Sn4, writes the threshold voltage of the driving transistor T1 to the third node N3;

[0050] The light-emitting control unit 40, in response to the light-emitting control signal En, outputs the output current of the driving transistor T1 to the light-emitting element 50, thereby controlling the light-emitting element 50 to emit light.

[0051] In this embodiment of the invention, by adding a compensation unit 30, the light-emitting control unit 40 responds to the same light-emitting control signal En. The existing driver chip can provide the required transmission signal for this pixel circuit, eliminating the need to develop a new driver chip, reducing the cost of the display panel, and increasing the market penetration rate of the display panel.

[0052] For further information, please refer to [link / reference]. Figure 3 The pixel circuit in this embodiment of the invention further includes a second initialization unit 60 and a third initialization unit 70. The second initialization unit 60 is used to initialize the potential of the first terminal of the light-emitting element 50; the third initialization unit 70 is used to initialize the potential of the second node N2 and the third node N3.

[0053] Furthermore, the control terminal of the driving transistor T1 is electrically connected to the first node N1, the first terminal of the driving transistor T1 is electrically connected to the second node N2, and the second terminal of the driving transistor T1 is electrically connected to the third node N3.

[0054] Furthermore, the first initialization unit 10 includes a second transistor T2. The control terminal of the second transistor T2 is electrically connected to the first scan line, the first terminal of the second transistor T2 is electrically connected to the first initialization line, and the second terminal of the second transistor T2 is electrically connected to the first node N1. The first scan line is used to transmit the first scan signal Sn1, and the first initialization line is used to transmit the first initialization signal Vref.

[0055] Furthermore, the data writing unit 20 includes a third transistor T3, the control terminal of the third transistor T3 is electrically connected to the third scan line, the first terminal of the third transistor T3 is electrically connected to the data line, and the second terminal of the third transistor T3 is electrically connected to the first node N1.

[0056] Furthermore, the light-emitting control unit 40 includes a fourth transistor T4 and a fifth transistor T5. The control terminals of the fourth transistor T4 and the fifth transistor T5 are electrically connected to the light-emitting control line. The first terminal of the fourth transistor T4 is electrically connected to the first power supply line, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2. The light-emitting control line is used to transmit the light-emitting control signal En, and the first power supply line is used to transmit the first power supply signal ELVDD.

[0057] The first terminal of the fifth transistor T5 is electrically connected to the third node N3, and the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the light-emitting element 50.

[0058] The second initialization unit 60 includes a sixth transistor T6. The control terminal of the sixth transistor T6 is electrically connected to the second scan line, the first terminal of the sixth transistor T6 is electrically connected to the second initialization line, and the second terminal of the sixth transistor T6 is electrically connected to the first terminal of the light-emitting element 50. The second terminal of the light-emitting element 50 is electrically connected to the second power supply line.

[0059] The third initialization unit 70 includes a seventh transistor T7. The control terminal of the seventh transistor T7 is electrically connected to the second scan line, the first terminal of the seventh transistor T7 is electrically connected to the second initialization line, and the second terminal of the seventh transistor T7 is electrically connected to the third node N3. The second scan line is used to transmit the second scan signal Sn2, and the second initialization line is used to transmit the second initialization signal Vint.

[0060] Furthermore, the compensation unit 30 includes an eighth transistor T8, the control terminal of the eighth transistor T8 is electrically connected to the fourth scan line, the first terminal of the eighth transistor T8 is electrically connected to the first power line or the first initialization line, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2.

[0061] Furthermore, the pixel circuit also includes a second capacitor C2. The two substrates of the second capacitor C2 are electrically connected to the potential stabilization line and the third node N3, respectively. The second capacitor C2 is used to stabilize the potential of the third node N3. Here, the potential stabilization line is the first power supply line.

[0062] It should be noted that all the transistors mentioned above are thin-film transistors (TFTs). A TFT has a first terminal, a second terminal, and a control terminal. The first terminal is either the source or the drain, the second terminal is either the source or the drain, and the control terminal is the gate. When a working level is provided to the gate, the transistor is turned on; when a non-working level is provided to the gate, the transistor is turned off. Transistors can be classified into P-type transistors and N-type transistors according to their conductivity characteristics. A P-type transistor is turned on when the control terminal is low and turned off when the control terminal is high; that is, the working level of a P-type transistor is low, and the non-working level is high. An N-type transistor is turned on when the control terminal is high and turned off when the control terminal is low; that is, the working level of an N-type transistor is high, and the non-working level is low. In this embodiment of the invention, the driving transistors T1 to the eighth transistor T8 are all N-type transistors.

[0063] The light-emitting elements in this embodiment of the invention include, but are not limited to, organic light-emitting diodes (OLEDs). The following description uses an OLED as an example. An OLED includes an anode and a cathode. Here, the first end of the light-emitting element 50 is the anode of the OLED, and the second end of the light-emitting element 50 is the cathode of the OLED.

[0064] Figure 4 The following is a driving timing diagram of the pixel circuit according to an embodiment of the present invention. Figures 5 to 8 The operation of the pixel circuit during each working time period is shown below. Figures 4 to 8 Therefore, when displaying one frame of image, the driving method of the pixel circuit includes the following steps:

[0065] like Figure 4 and Figure 5 As shown, during the first time period t1, the first scan signal Sn1 and the second scan signal Sn2 are high-level signals, while the third scan signal Sn3, the fourth scan signal Sn4, and the light emission control signal En are low-level signals. Correspondingly, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are turned on, while the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off. The first initialization signal Vref is transmitted to the first node N1 through the second transistor T2 to initialize the potential of the first node N1. The second initialization signal Vint is transmitted to the anode of the OLED through the sixth transistor T6 to reset the anode of the OLED, causing the internal electric field formed by the directional movement of impurity ions within the OLED organic layer to gradually disappear, thereby restoring the characteristics of the OLED. The second initialization signal Vint is transmitted to the third node N3 through the seventh transistor T7 to initialize the potential of the third node N3.

[0066] At this time, the potential of the first node N1 is Vref, denoted as N1 = Vref;

[0067] The potential of the third node N3 is: N3 = Vint.

[0068] The gate voltage (Vg) of driving transistor T1 is the same as the potential of node N1, the source voltage (Vs) of driving transistor T1 is the same as the potential of the third node N3, and the drain voltage (Vd) of driving transistor T1 is the same as the potential of the second node N2. At this time, the gate-source voltage of driving transistor T1 is Vgs = Vg - Vs = Vref - Vint > Vth, driving transistor T1 is turned on, then N2 = N3 = Vint, and the second node N2 is initialized.

[0069] like Figure 4 and Figure 6 As shown, during the second time period t2, the first scan signal Sn1 is still at a high level, so the second transistor T2 remains on; the fourth scan signal Sn4 is at a high level, so the eighth transistor T8 is on; the second scan signal Sn2 is at a low level, so the sixth transistor T6 and the seventh transistor T7 are off. It should be noted that the states of scan signals not explicitly mentioned do not change, and the states of the corresponding controlled transistors remain unchanged. The same applies to the following steps, and will not be explained further.

[0070] At this time, the potential of the first node N1 is Vref, denoted as: N1 = Vref;

[0071] The first power signal ELVDD or the first initialization signal Vref is transmitted to the third node N3 through the eighth transistor T8 to charge the first capacitor C1. For example, when the first initialization signal Vref is transmitted to the third node N3 through the eighth transistor T8 and the driving transistor T1, and when the potential of the third node N3 is: N3 = N1 - Vth_T1 = Vref - Vth_T1, the driving transistor T1 is turned off, and the threshold voltage Vth_T1 of the driving transistor T1 is stored in the first capacitor C1.

[0072] like Figure 4 and Figure 7 As shown, during the third time period t3, when the first scan signal Sn1 is low, the second transistor T2 is off; when the third scan signal Sn3 is high, the third transistor T3 is on; and when the fourth scan signal Sn4 is low, the fourth transistor T4 is off. The data signal Data is transmitted to the first node N1 through the third transistor T3 and stored in the first capacitor C1.

[0073] At this moment, the potential of the first node N1 is: N1 = Data;

[0074] The potential change of the first node N1 is ΔV(N1) = Data - Vref;

[0075] The potentials of the second node N2 and the third node N3 are: N2 = N3 = Vref - Vth_T1 + (Data - Vref) * C1 / (C1 + C2);

[0076] The potential of the OLED anode is: Anode = Vint;

[0077] At this time, the gate-source voltage of the driving transistor T1 is Vgs = [1-C1 / (C1+C2)]*(Data-Vref)+Vth_T1.

[0078] like Figures 4 to 8 As shown, during the fourth time period t4, the third scan signal Sn3 is at a low level, and the third transistor T3 is cut off; the light emission control signal En is at a high level, and the fourth transistor T4 and the fifth transistor T5 are turned on, driving transistor T1 to generate a driving current that is transmitted to the OLED, causing the OLED to emit light.

[0079] At this time, the potential of the third node N3 is N3 = ELVSS + Voled;

[0080] The potential change of the third node N3 is ΔV(N3) = ELSS + Voled - Vref + Vth_T1 - (Data - Vref) * C1 / (C1 + C2);

[0081] The potential of the first node N1 is: N1=Data+△V(N3)=ELVSS+Voled+[1-C1 / (C1+C2)]*(Data-Vref)+Vth_T1;

[0082] The gate-source voltage driving transistor T1 is: Vgs = [1 - C1 / (C1 + C2)] * (Data - Vref) + Vth - T1;

[0083] Luminous current during the luminescence stage: I oled =1 / 2Cox*W / L*μ[1-C1 / (C1+C2)] 2 *(Data-Vref) 2 .

[0084] At this point, the pixel circuit has completed the display of one frame of image. Subsequent image frame displays can refer to the driving method steps of the pixel circuit described above.

[0085] Figure 9 A schematic diagram of a pixel circuit according to another embodiment of the present invention is shown. (As shown) Figure 9 As shown, with Figure 3Compared to the pixel circuit shown, the difference lies in that one end of the second capacitor C2 in this embodiment is connected to the second initialization line, achieving the same technical effect as the pixel circuit described above. Please refer to the above description of the technical effects; they will not be repeated here. The specific driving method for the pixel circuit in this embodiment can be found in the above description of the pixel driving method; it will not be repeated here.

[0086] Figure 10 A schematic diagram of a pixel circuit according to another embodiment of the present invention is shown. (As shown) Figure 10 As shown, with Figure 3 Compared to the pixel circuit shown, the difference lies in that all transistors in this embodiment of the pixel circuit also have a back gate, which is connected to a fixed voltage signal line, such as any one of the following: a first power line transmitting the first power signal ELVDD, a second power line transmitting the second power voltage signal ELVSS, a first initialization line transmitting the first initialization signal Vref, and a second initialization line transmitting the second initialization signal Vint. In another embodiment, a setting signal line can also be set according to actual needs. The setting signal line is used to transmit a fixed signal and is electrically connected to the back gate of the transistor. In other embodiments, the back gate of the transistor can also be electrically connected to any one of the control terminal, the first terminal, or the second terminal of the transistor, which can also achieve the technical effects of the pixel circuit described above. Please refer to the above description of the technical effects, which will not be repeated here. The number of transistors with back gates is not limited to the above settings and can be set according to actual needs. The setting of back gates in transistors is beneficial to improving the threshold drift problem of transistors. The specific driving method of the pixel circuit in this embodiment can be referred to the above description of the pixel driving method, which will not be repeated here.

[0087] Figure 11 A schematic diagram of a pixel circuit according to another embodiment of the present invention is shown. (As shown) Figure 11 As shown, with Figure 3 Compared to the pixel circuit shown, the difference lies in that the control terminal of the eighth transistor T8 in the pixel circuit provided in this embodiment is electrically connected to the first scan line. The reduction of the fourth scan line can correspondingly reduce one set of gate drive circuits used to output the fourth scan signal, thereby reducing the bezel size of the display panel.

[0088] Figure 12 It shows Figure 11 The timing diagram of the pixel circuit is shown. Figure 4Compared to the timing diagram shown, the difference lies in that the second scan signal Sn2 is high earlier than the first scan signal, meaning that initializing the OLED anode and the third node N3 occurs earlier than writing the threshold voltage Vth_T1 of the driving transistor T1 to the third node N3. Specifically, within one image frame display cycle, the sixth transistor T6 and the seventh transistor T7 are first turned on to initialize the OLED anode and the third node N3, respectively. Then, when the first scan signal Sn1 is high, the driving transistor T1 and the eighth transistor T8 are turned on, transmitting the first initialization signal Vref or ELVDD to the third node N3 to charge the first capacitor C1 and write the threshold voltage Vth_T1 of the driving transistor T1 to the third node N3. Other steps of the specific driving method of the pixel circuit in this embodiment can be found in the above description of the pixel driving method, and will not be repeated here.

[0089] This invention also provides a display panel, including the pixel circuit described above. Figure 13 A display panel provided in an embodiment of the present invention is shown. For example... Figure 13 As shown, the display panel 200 includes a display area 210 and a non-display area 220. The display area 210 has a plurality of pixel circuits 100 arranged in an array as described above. Each pixel circuit 100 drives a corresponding light-emitting element to emit light. The display panel 200 can achieve all the technical effects of the pixel circuits 100 described above; for details, please refer to the description of the technical effects of the pixel circuits, which will not be repeated here.

[0090] The pixel circuit and display panel provided by this invention have the following advantages:

[0091] In this embodiment of the invention, by adding a compensation unit, the light-emitting control unit responds to the same light-emitting control signal. The existing driver chip can provide the required transmission signal for this pixel circuit, eliminating the need to develop a new driver chip, thus reducing the cost of the display panel and increasing the market penetration rate of the display panel.

[0092] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that, include: A driving transistor and a first capacitor, wherein the control terminal of the driving transistor is connected to a first node via a first terminal of the first capacitor, and the second terminal of the first capacitor is connected to a third node; The first initialization unit, in response to the first scan signal, initializes the potential of the first node; The data writing unit responds to the third scan signal to write the data signal to the first node; The compensation unit, in response to the first scan signal or the fourth scan signal, writes the threshold voltage of the driving transistor to the third node; The light-emitting control unit, in response to the light-emitting control signal, outputs the output current of the driving transistor to the light-emitting element, thereby controlling the light-emitting element to emit light.

2. The pixel circuit according to claim 1, characterized in that, The first terminal of the driving transistor is electrically connected to the second node, and the second terminal of the driving transistor is electrically connected to the third node.

3. The pixel circuit according to claim 2, characterized in that, The first initialization unit includes a second transistor, the control terminal of the second transistor is electrically connected to the first scan line, the first terminal of the second transistor is electrically connected to the first initialization line, and the second terminal of the second transistor is electrically connected to the first node.

4. The pixel circuit according to claim 3, characterized in that, The data writing unit includes a third transistor, the control terminal of which is electrically connected to a third scan line, the first terminal of which is electrically connected to a data line, and the second terminal of which is electrically connected to the first node.

5. The pixel circuit according to claim 4, characterized in that, The light-emitting control unit includes a fourth transistor and a fifth transistor. The control terminals of the fourth transistor and the fifth transistor are electrically connected to the light-emitting control line. The first terminal of the fourth transistor is electrically connected to the first power line, and the second terminal of the fourth transistor is electrically connected to the second node. The first terminal of the fifth transistor is electrically connected to the third node, and the second terminal of the fifth transistor is electrically connected to the first terminal of the light-emitting element.

6. The pixel circuit according to claim 5, characterized in that, It also includes a second initialization unit and a third initialization unit, wherein the second initialization unit is used to initialize the potential of the first terminal of the light-emitting element; and the third initialization unit is used to initialize the potential of the third node. The second initialization unit includes a sixth transistor, the control terminal of which is electrically connected to the second scan line, the first terminal of which is electrically connected to the second initialization line, and the second terminal of which is electrically connected to the first terminal of the light-emitting element; the second terminal of the light-emitting element is electrically connected to the second power line. The third initialization unit includes a seventh transistor, the control terminal of which is electrically connected to the second scan line, the first terminal of which is electrically connected to the second initialization line, and the second terminal of which is electrically connected to the third node.

7. The pixel circuit according to claim 6, characterized in that, The compensation unit includes an eighth transistor, the control terminal of which is electrically connected to the first scan line or the fourth scan line, the first terminal of which is electrically connected to the first power line or the first initialization line, and the second terminal of which is electrically connected to the second node.

8. The pixel circuit according to claim 7, characterized in that, It also includes a second capacitor, the two substrates of which are electrically connected to the potential stabilization line and the third node, respectively.

9. The pixel circuit according to claim 8, characterized in that, At least one transistor in the pixel circuit includes a back gate, which is electrically connected to any one of the first power line, the first initialization line, the second initialization line, the second power line, the setting signal line, the control terminal of the transistor, the first terminal of the transistor, and the second terminal of the transistor.

10. A display panel, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 8.

Images