Display device and display panel

Abstract

The invention provides a display device and a display panel. A display device includes a first scan stage to which a first scan signal is applied, where the first scan stage includes: a first control transistor and a second control transistor connected in parallel with each other, configured to receive a carry signal, and connected to a Q2 node; and third and fourth control transistors connected in series with each other with a QB node therebetween, and having respective gate electrodes connected to a Q2 node, in which, in a first scan stage configured to output a first scan signal of an n-th horizontal line, the pull-up transistor is configured to receive a second B scan clock, and in a second scan stage configured to output a second scan signal of an n-th horizontal line, the pull-up transistor is configured to receive a third B scan clock. A gate electrode of the first control transistor is configured to receive a first B-scan clock, and a gate electrode of the second control transistor is configured to receive the first scan clock or the second B-scan clock.

Description

Technical Field

[0001] This disclosure relates to display devices and display panels. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images has increased in various forms. In recent years, various flat panel display devices, such as organic light-emitting diode (OLED) displays and liquid crystal displays (LCDs), have been applied.

[0003] In the example, the gate drive circuit of the organic light-emitting display device includes a separate inverter circuit configured using CMOS to generate a scan signal. This inverter circuit inverts the input signal to output the scan signal.

[0004] The descriptions provided in the Background section should not be assumed to be prior art simply because they are mentioned or related to it. The Background section may contain information describing one or more aspects of the subject matter. Summary of the Invention

[0005] The addition of an inverter circuit increases the size of the gate drive circuit, which in turn increases the bezel of the display device, making it difficult to achieve a narrow bezel.

[0006] The advantage of this disclosure is that it provides a display device that can reduce the size of the gate drive circuit and achieve a narrow bezel in the display device.

[0007] Additional features and advantages of this disclosure will be set forth in the following description, will be apparent in part from the description, or may be learned by practice of the disclosure. These and other advantages of this disclosure will be realized and obtained by means of the structures particularly pointed out in the written description and its claims and the accompanying drawings.

[0008] To achieve these and other advantages, in accordance with the purposes of this disclosure, as embodied and broadly described herein, a display device includes a first scan stage for applying a first scan signal, wherein the first scan stage includes: a first control transistor and a second control transistor connected in parallel to each other, configured to receive a carry signal and connected to a Q2 node; and a third control transistor and a fourth control transistor connected in series to each other, having a QB node therebetween, and having respective gate electrodes connected to the Q2 node, wherein in the first scan stage configured to output a first scan signal for an nth horizontal line, a pull-up transistor is configured to receive a second B scan clock, the gate electrode of the first control transistor is configured to receive a first B scan clock, and the gate electrode of the second control transistor is configured to receive either the first scan clock or the second B scan clock.

[0009] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed contents of this disclosure. Attached Figure Description

[0010] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated in and form a part of this specification, illustrate exemplary embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0011] Figure 1 This is a view that schematically illustrates a display device according to a first exemplary embodiment of the present disclosure;

[0012] Figure 2 This is a circuit diagram that schematically illustrates an example of a pixel according to a first exemplary embodiment of the present disclosure;

[0013] Figure 3 This is a view illustrating the configuration of the gate driving portion of a display device according to a first exemplary embodiment of the present disclosure;

[0014] Figure 4 and Figure 5 This is a timing diagram that schematically illustrates an example of a drive signal output from a gate drive section according to a first exemplary embodiment of the present disclosure;

[0015] Figure 6 This is a cross-sectional view schematically illustrating an example of the cross-sectional structure of a display panel according to a first exemplary embodiment of the present disclosure;

[0016] Figure 7 This is a view that schematically illustrates an example of the structure of a scan drive circuit according to a first exemplary embodiment of the present disclosure;

[0017] Figure 8 This is a schematic example of a driver. Figure 7 The timing waveform of the signal of the scan drive circuit;

[0018] Figure 9 This is a view that schematically illustrates an example of the structure of a scan drive circuit according to a second exemplary embodiment of the present disclosure;

[0019] Figure 10 This is a view schematically illustrating an example of the structure of a scan drive circuit according to a third exemplary embodiment of the present disclosure; and

[0020] Figure 11 This is a schematic example of a driver. Figure 10 The timing waveform of the signal of the scanning drive circuit.

[0021] In all accompanying drawings and detailed descriptions, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, the relative dimensions and descriptions of these elements may be exaggerated. Detailed Implementation

[0022] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. The process of the described steps and / or operations is illustrative; however, the order of the steps and / or operations is not limited to the order described herein and can be modified in accordance with manners known in the art, except where the steps and / or operations must occur in a specific order. The names of the various elements used in the following description may have been chosen solely for convenience in writing the specification and may therefore differ from the names used in actual products.

[0023] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only these embodiments complete this disclosure. This disclosure is intended to fully inform those skilled in the art of this disclosure of its scope, and the content of this disclosure may be defined by the scope of the claims.

[0024] The shapes (e.g., dimensions, lengths, widths, heights, thicknesses, positions, radii, diameters, and areas), scales, angles, numbers, etc., disclosed in the accompanying drawings to illustrate embodiments of the present disclosure are merely illustrative, and the present disclosure is not limited to the contents shown. Throughout the specification, the same reference numerals refer to the same components.

[0025] Furthermore, in describing this disclosure, if it is determined that a detailed description of the relevant known technology unnecessarily obscures the subject matter of this disclosure, its detailed description may be omitted. When words such as "comprising," "including," "having," and "consisting of" are used in this disclosure, other components may be added unless the word "only" is used. When components are expressed in a singular form, the inclusion of plural forms is included unless otherwise expressly stated.

[0026] The term “exemplary” is used to indicate that something is used as an example or illustration. An aspect is an example aspect. “Implementation,” “example,” “aspect,” etc., should not be construed as superior to or better than other implementations. Unless otherwise stated, an embodiment, example, exemplary implementation, aspect, etc., may refer to one or more implementations, one or more examples, one or more exemplary implementations, one or more aspects, etc. Furthermore, the term “may” encompasses all the meanings of the term “can.”

[0027] When explaining components, even without a separate explicit description, it is interpreted as including a margin range. Any implementation described as an "example" in this article is not necessarily to be interpreted as superior to or better than other implementations.

[0028] When describing positional relationships, for example, when the positional relationship between two components is described as "above", "above", "higher", "lower", "side", "below", etc., one or more other components may be positioned between the two components unless "exactly" or "directly" is used.

[0029] When describing time relationships, such as when time priority is described as "after", "next", "before", etc., discontinuous cases may be included unless "direct" or "immediate" is used.

[0030] In this document, terms such as “below,” “lower,” “above,” and “upper” may be used to describe the relationships between the elements shown in the accompanying drawings. It should be understood that these terms are spatially relative and based on the orientation shown in the accompanying drawings.

[0031] In describing the components of this disclosure, terms such as first, second, A, B, (a), (b) may be used. These terms are used only to distinguish a component from other components, and the nature, order, sequence, or number of components is not limited by these terms.

[0032] The corresponding features of the various embodiments of this disclosure may be partially or wholly connected or combined with each other, and may be technically interlocked and driven in various ways. The corresponding embodiments may be implemented independently of each other or may be implemented together in an associated relationship.

[0033] The term “at least one” should be understood to include any and all combinations of one or more related listed items. For example, “at least one of the first element, the second element, and the third element” means all combinations of the three listed elements, any two of the three elements, and each individual element (the first element, the second element, or the third element).

[0034] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It should also be understood that terms (e.g., those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the relevant artistic context, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, the terms “part” or “unit” may be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the functions described herein, as would be understood by one of skill in the art.

[0035] In the following description, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, in the following embodiments, the same and similar reference numerals are assigned to the same and similar components, and their detailed descriptions may be omitted or given only briefly.

[0036] <First Exemplary Implementation>

[0037] Figure 1 A view illustrating a display device according to a first exemplary embodiment of the present disclosure. Figure 2 A circuit view illustrating an example of a pixel according to a first exemplary embodiment of the present disclosure. Figure 3 This is a view illustrating the configuration of the gate driving portion of a display device according to a first exemplary embodiment of the present disclosure. Figure 4 and Figure 5 A timing diagram illustrating an example of a drive signal output from a gate drive section according to a first exemplary embodiment of the present disclosure. Figure 4 The illustration shows the drive signal output during the refresh frame in the VRR (variable refresh rate) method of the first exemplary embodiment of this disclosure. Figure 5 The illustration shows a drive signal output during a skip frame in a VRR method according to a first exemplary embodiment of this disclosure.

[0038] Before going into detail, the display device 10 according to this exemplary embodiment may include a light-emitting display device equipped with light-emitting diodes. Furthermore, the display device 10 of this exemplary embodiment may include all types of display devices that apply the VRR method.

[0039] In addition, for ease of explanation, in this exemplary embodiment, an organic light-emitting display device is used as an example of the display device 10 for description.

[0040] Reference Figures 1 to 5 The display device 10 of this exemplary embodiment may include a display panel 100 and a driving circuit portion for driving the display panel 100.

[0041] Here, the driving circuit section may include, for example, a gate driving section (or gate driving circuit) 210, a data driving section (or data driving circuit) 220, and a timing control section (or timing control circuit) 240. Additionally, the driving circuit section may include a power supply section (or power supply circuit) 280, which supplies the power required to drive the display panel 100, the gate driving section 210, the data driving section 220, and the timing control section 240.

[0042] The display panel 100 may include a display area AA for displaying images and a non-display area NA disposed outside (or completely or partially surrounding) the display area AA. For example, the non-display area NA may be partially or completely invisible from the front of the display panel 100, for example, by bending towards the back of the display panel 100, but is not limited thereto. For example, the entire non-display area NA may be flat.

[0043] In the display area AA, multiple pixels P can be set in a matrix along multiple horizontal lines (or row lines) and multiple vertical lines (or column lines).

[0044] Here, the multiple pixels P can include pixels displaying different colors, such as red pixels, green pixels, and blue pixels displaying red, green, and blue respectively, but are not limited to these. For example, it can also include white pixels displaying white. In addition, it can also include pixels displaying colors other than red, green, blue, and white, such as cyan, magenta, or yellow, but are not limited to these.

[0045] In the display panel 100, various signal lines for transmitting drive signals for driving pixels P can be formed on the substrate.

[0046] In this regard, for example, multiple data lines DL that transmit data signals (or data voltages) as image signals can extend in the vertical direction and be connected to the pixels P of the corresponding vertical lines.

[0047] Additionally, the gate line GL that sends the gating signal (or gating voltage) can extend horizontally and connect to the corresponding pixel P on the horizontal line.

[0048] In this exemplary embodiment, multiple gating signals can be used to drive each pixel P. For example, a first scan signal SC1 to a fourth scan signal SC4 and a light emission control signal EM can be used. Accordingly, multiple gate lines GL that transmit multiple gating signals can be used, for example, a first scan line SCL1 to a fourth scan line SCL4 and a light emission control line EML can be used. The implementation is not limited thereto. For example, each pixel P can be driven by one or more gating signals. For example, depending on the design, at least one of the first scan signal SC1 to a fourth scan signal SC4 and the light emission control signal EM can be omitted.

[0049] In this way, multiple pixels P can be defined by multiple data lines DL and gate lines GL that intersect each other.

[0050] Each pixel P may include a light-emitting diode OD as a light-emitting element, as well as a plurality of transistors and at least one capacitor for driving the light-emitting diode OD.

[0051] In addition, in this exemplary embodiment, for ease of explanation, ... Figure 2 Taking the 8T1C structure shown as an example, pixel P is equipped with eight transistors T1 to T7 and DT, as well as a capacitor Cst. The implementation is not limited to this. For example, each pixel P may include one or more transistors and one or more capacitors. For example, each pixel P may have a 2T1C structure, a 3T2C structure, a 5T2C structure, etc., but is not limited to this.

[0052] Reference Figure 2 Pixel P may include multiple switching transistors, such as first transistor T1 to seventh transistor T7, driving transistor DT, storage capacitor Cst and light-emitting diode OD.

[0053] Each of the first transistor T1 through the seventh transistor T7 and the driving transistor DT may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0054] Each of the first transistor T1 through the seventh transistor T7 and the driving transistor DT can be a P-type or N-type transistor. Additionally, in Figure 2 In this configuration, for example, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are configured as P-type transistors, the first transistor T1 and the seventh transistor T7 are configured as N-type transistors, and the driving transistor DT is configured as a P-type transistor, but is not limited thereto. Alternatively, the driving transistor DT may be configured as an N-type transistor.

[0055] The first transistor T1 through the seventh transistor T7 and the driving transistor DT may contain semiconductors of the same material or semiconductors of different materials. For example, some of the first transistors T1 through the seventh transistor T7 and the driving transistor DT may have a semiconductor layer selected from polycrystalline silicon, oxide semiconductor, amorphous silicon, compound semiconductor, and oxide semiconductor, while other transistors may have another semiconductor layer selected from polycrystalline silicon, oxide semiconductor, amorphous silicon, compound semiconductor, and oxide semiconductor.

[0056] Furthermore, since oxide semiconductors possess excellent cutoff current characteristics and properties suitable for switching transistors, at least one of the first transistors T1 to the seventh transistor T7 can have an oxide semiconductor layer. Additionally, since polysilicon has excellent mobility, the driving transistor DT can have a polysilicon layer. Of course, the first transistors T1 to the seventh transistor T7 and the driving transistor DT can be configured in other ways. For example, the driving transistor DT can have an oxide semiconductor layer.

[0057] In addition, in this exemplary embodiment, the case in which the first transistor T1 and the seventh transistor T7 include an oxide semiconductor layer and the remaining transistors T2 to T6 and DT include a polysilicon layer is taken as an example.

[0058] Provided Figure 2 The gating signal for the nth horizontal line (more specifically, at least one of the odd and even horizontal lines constituting the nth horizontal line) can be provided from the corresponding nth stage of the gate driving section 210. For example, four scan signals can be provided: first to fourth scan signals (SC1 to SC4: SC1(n) to SC4(n)) and two light emission control signals: first and second light emission control signals (EM: EM1(n) and EM2(n)). In this case, in the display area AA, the first scan line SCL1 to the fourth scan line SCL4 and the first light emission control line EML1 and the second light emission control line EML2 can be provided, which are connected to the nth stage and send the first scan signal SC1(n) to the fourth scan signal SC4(n) and the first light emission control signal EM1(n) and the second light emission control signal EM2(n) to the pixel P. Alternatively, the gate driving section 210 can be configured to provide one light emission control signal instead of two light emission control signals EM1(n) and EM2(n).

[0059] The first transistor T1 can be used as a sampling transistor, the second transistor T2 can be used as a data supply transistor, the third transistor T3 and the fourth transistor T4 can be used as light-emitting control transistors, the fifth transistor T5 can be used as a bias transistor, the sixth transistor T6 can be used as a reset transistor (or the first initialization transistor), and the seventh transistor T7 can be used as an initialization transistor (or the second initialization transistor).

[0060] A light-emitting diode (LED) OD can include an anode electrode and a cathode electrode. The anode electrode of the LED OD can be connected to the fifth node N5, and the cathode electrode of the LED OD can be applied with a low-potential drive voltage EVSS.

[0061] The driving transistor DT may include a first electrode connected to a second node N2, a second electrode connected to a third node N3, and a gate electrode connected to a first node N1. The driving transistor DT can provide a driving current to the light-emitting diode OD based on the voltage of the first node N1 (i.e., the data voltage Vdata stored in the storage capacitor Cst).

[0062] The first transistor T1 may include a first electrode connected to a first node N1, a second electrode connected to a third node N3, and a gate electrode for receiving a first scan signal SC1(n). The first transistor T1 may be turned on in response to the first scan signal SC1(n), and a data voltage Vdata may be applied (or written or sampled) to the gate electrode of the driving transistor DT.

[0063] The storage capacitor Cst can be connected between the first node N1 and the fourth node N4. The storage capacitor Cst can store or maintain the high-potential drive voltage EVDD.

[0064] The second transistor T2 may include a first electrode connected to the data line DL (or receiving the data voltage Vdata), a second electrode connected to the second node N2, and a gate electrode for receiving the second scan signal SC2(n). The second transistor T2 may be turned on in response to the second scan signal SC2(n) and send the data voltage Vdata to the second node N2.

[0065] The third transistor T3 and the fourth transistor T4 (or the first and second light-emitting control transistors) can be connected between the power line of the high-potential drive voltage EVDD and the light-emitting diode OD, and can form a current path along which the drive current generated by the drive transistor DT moves.

[0066] The third transistor T3 may include a first electrode connected to the fourth node N4 and receiving a high-potential drive voltage EVDD, a second electrode connected to the second node N2, and a gate electrode receiving a first light-emitting control signal EM1(n).

[0067] The fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the anode of the light-emitting diode OD), and a gate electrode that receives the second light-emitting control signal EM2(n).

[0068] The third transistor T3 and the fourth transistor T4 can be turned on in response to the first light emission control signal EM1(n) and the second light emission control signal EM2(n), and the driving current can be supplied to the light emission diode OD, and the light emission diode OD can emit light with a brightness corresponding to the driving current.

[0069] The fifth transistor T5 may include a first electrode connected to the bias voltage line VobsL that transmits the bias voltage Vobs, a second electrode connected to the second node N2, and a gate electrode that receives the third scan signal SC3(n).

[0070] The sixth transistor T6 may include a first electrode connected to a reset voltage line (or first initialization voltage line) VarL that transmits the anode reset voltage (or first initialization voltage) Var, a second electrode connected to the fifth node N5, and a gate electrode that receives the third scan signal SC3(n).

[0071] The fifth transistor T5 and the sixth transistor T6 can be turned on in response to the third scan signal SC3(n), the bias voltage Vobs can be applied to the second node N2, and the anode reset voltage Var can be applied to the fifth node N5 (i.e., the anode electrode of the light-emitting diode OD).

[0072] The seventh transistor T7 may include a first electrode connected to the initialization voltage line ViniL that transmits the initialization voltage Vini, a second electrode connected to the first node N1, and a gate electrode that receives the fourth scan signal SC4(n).

[0073] The seventh transistor T7 can be turned on in response to the fourth scan signal SC4(n), and an initialization voltage Vini can be applied to initialize the gate electrode of the driving transistor DT. Due to the high-potential driving voltage EVDD applied to the storage capacitor Cst, unnecessary charge may remain in the gate electrode of the driving transistor DT. Therefore, the remaining charge can be initialized by applying the initialization voltage Vini to the gate electrode of the driving transistor DT through the seventh transistor T7.

[0074] The 8T1C structure of pixel P described above is an example, and pixel P in this exemplary embodiment can be configured with different structures.

[0075] Reference Figure 1 The timing control section 240 processes the image data Do input from the host system, adapts it to the size and resolution of the display panel 100, and supplies it to the data driving section 220. The timing control section 240 can generate a gate control signal GCS and a data control signal DCS using synchronization signals input from the host system (e.g., a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal HSY, and a vertical synchronization signal VSY). By supplying the gate control signal GCS and the data control signal DCS thus generated to the gate driving section 210 and the data driving section 220, respectively, the gate driving section 210 and the data driving section 220 can be controlled.

[0076] The timing control unit 240 can be configured to be combined with various processors (such as microprocessors, mobile processors, application processors, etc.) depending on the device to which it is to be installed.

[0077] Additionally, the host system may be, for example, the drive system for the electronic device to which the display device 10 is applied. The electronic device may be, for example, a television (TV), a navigation system, a monitor, a mobile device or wearable device, a home appliance, a building, a vehicle, a set-top box, a game console, etc., but is not limited to these.

[0078] The gate driving section 210 can receive the gate control signal GCS from the timing control section 240, generate a gating signal, and apply the gating signal to the gate line GL in sequence. For example, the gating signal can be output sequentially from top to bottom in the vertical direction, sequentially from bottom to top in the vertical direction, or in a different order than the sequential order, but is not limited to these.

[0079] The gate driving portion 210 may be disposed on at least one side of, for example, the display area AA. In this exemplary embodiment, the gate driving portion 210 is configured to include a first gate driving portion 211 and a second gate driving portion 212 disposed on both sides of the display area AA (e.g., the left and right sides of the display area AA).

[0080] For example, the gate driving portion 210 can be directly formed in the non-display area NA on the substrate of the display panel 100, for example, using a GIP (gate in panel) structure. In this case, the gate driving portion 210 can be formed during the process of forming the elements of the display panel 100, or it can be formed in a process different from the process of forming the elements of the display panel 100. The implementation is not limited to this. For example, the gate driving portion 210 can be disposed on a separate panel or a separate film and connected to the display panel 100 using a tape-on-board (TAB) method, a chip-on-glass (COG) method, a chip-on-panel (COP) method, or a chip-on-film (COF) method, but is not limited to this.

[0081] The gate driving section 210 configured with a GIP structure may include, for example, a first scan driving circuit that sequentially outputs a first scan signal SC1, a second scan driving circuit that sequentially outputs a second scan signal SC2, a third scan driving circuit that sequentially outputs a third scan signal SC3, a fourth scan driving circuit that sequentially outputs a fourth scan signal SC4, a first light-emitting driving circuit that sequentially outputs a first light-emitting control signal EM1, and a second light-emitting driving circuit that sequentially outputs a second light-emitting control signal EM2, but is not limited thereto.

[0082] Each of the first to fourth scan driving circuits, the first light-emitting driving circuit, and the second light-emitting driving circuit may be configured with a shift register, which includes, but is not limited to, multiple stages for outputting corresponding signals.

[0083] Further reference Figure 3 Describe the gate drive section 210. Figure 3 A portion of the gate driving section 210 is illustrated. For ease of explanation, a configuration of a portion of the nth horizontal line of the driving display area AA of the gate driving section 210 is illustrated, wherein the nth horizontal line is configured with an nth odd horizontal line (or a 2n-1th horizontal line) and an nth even horizontal line (or a 2nth horizontal line).

[0084] For example, in the first gate driving section 211 of the gate driving section 210, for example, a first scan level SSC1(n), a third scan level SSC3(n) and a fourth scan level SSC4(n) that constitute the first, third and fourth scan driving circuits respectively, a first light-emitting level SEM1(n) and a second light-emitting level SEM2(n) that constitute the first and second light-emitting driving circuits respectively, and an odd-numbered second scan level SSC2_O(n) and an even-numbered second scan level SSC2_E(n) that constitute the second scan driving circuit can be provided.

[0085] Additionally, in the second gate driving section 212 of the gate driving section 210, for example, a first scan level SSC1(n), a third scan level SSC3(n), and a fourth scan level SSC4(n) that constitute the first, third, and fourth scan driving circuits, a first light-emitting level SEM1(n), a second light-emitting level SEM2(n) that constitute the first and second light-emitting driving circuits, and an odd-numbered second scan level SSC2_O(n) and an even-numbered second scan level SSC2_E(n) that constitute the second scan driving circuit can be provided.

[0086] In the gate driving section 210, the odd-numbered second scan levels SSC2_O(n) and even-numbered second scan levels SSC2_E(n) constituting the second scan driving circuit can be positioned closest to the display area AA, while the second light-emitting level SEM2(n) can be positioned at the outermost part furthest from the display area AA. Furthermore, the first light-emitting level SEM1(n) can be positioned between the first scan level SSC1(n) and the fourth scan level SSC4(n).

[0087] Figure 3 The first scan level SSC1(n) to the fourth scan level SSC4(n) and the first light-emitting level SEM1(n) and the second light-emitting level SEM2(n) shown are examples, and they can be set in various combinations in the first gate driving section 211 and the second gate driving section 212.

[0088] The first scan level SSC1(n) can generate a first scan signal SC1(n) and output it to the corresponding first scan line SCL1. Therefore, the pixel P_O(n) of the nth odd-numbered horizontal line and the pixel P_E(n) of the nth even-numbered horizontal line can be jointly subjected to the first scan signal SC1(n).

[0089] The odd-numbered second scan level SSC2_O(n) can generate an odd-numbered second scan signal SC2_O(n) and output it to the corresponding odd-numbered second scan line SCL2, and the even-numbered second scan level SSC2_E(n) can generate an even-numbered second scan signal SC2_E(n) and output it to the corresponding even-numbered second scan line SCL2. Therefore, the pixel P_O(n) of the nth odd-numbered horizontal line can be given an odd-numbered second scan signal SC2_O(n), and the pixel P_E(n) of the nth even-numbered horizontal line can be given an even-numbered second scan signal SC2_E(n). Here, the odd-numbered second scan signals SC2_O(n) and SC2_E(n) can have different timings. For example, the odd-numbered second scan signals SC2_O(n) and SC2_E(n) can be applied to the data writing period of the nth odd-numbered horizontal line and the immediately following data writing period of the nth even-numbered horizontal line, respectively.

[0090] The third scan level SSC3(n) can generate a third scan signal SC3(n) and output it to the corresponding third scan line SCL3. Therefore, the pixel P_O(n) of the nth odd-numbered horizontal line and the pixel P_E(n) of the nth even-numbered horizontal line can be jointly subjected to the third scan signal SC3(n).

[0091] The fourth scan level SSC4(n) can generate the fourth scan signal SC4(n) and output it to the corresponding fourth scan line SCL4. Therefore, the pixel P_O(n) of the nth odd-numbered horizontal line and the pixel P_E(n) of the nth even-numbered horizontal line can be jointly subjected to the fourth scan signal SC4(n).

[0092] The first luminous level SEM1(n) can generate a first luminous control signal EM1(n) and output it to the corresponding first luminous control line EML1. Therefore, the pixel P_O(n) of the nth odd-numbered horizontal line and the pixel P_E(n) of the nth even-numbered horizontal line can be jointly subjected to the first luminous control signal EM1(n).

[0093] The second luminous level SEM2(n) can generate a second luminous control signal EM2(n) and output it to the corresponding second luminous control line EML2. Therefore, the pixel P_O(n) of the nth odd-numbered horizontal line and the pixel P_E(n) of the nth even-numbered horizontal line can be jointly subjected to the second luminous control signal EM2(n).

[0094] Additionally, refer to Figure 3 The bias voltage line VobsL, reset voltage line VarL, and initialization voltage line ViniL can be disposed between the gate driving section 210 and the display area AA. For example, the bias voltage line VobsL and the initialization voltage line ViniL can be disposed between the first gate driving section 211 and the display area AA, and the reset voltage line VarL can be disposed between the second gate driving section 212 and the display area AA, but are not limited thereto.

[0095] The bias voltage line VobsL, the reset voltage line VarL, and the initialization voltage line ViniL can supply the bias voltage Vobs, the anode reset voltage Var, and the initialization voltage Vini from the power supply section 280 to the pixel P in the display area AA, respectively.

[0096] Figure 3 In this context, each of the bias voltage line VobsL, the reset voltage line VarL, and the initialization voltage line ViniL is illustrated as being located only on the left or right side of the display area AA, but is not limited thereto. Each of the bias voltage line VobsL, the reset voltage line VarL, and the initialization voltage line ViniL can be located on both sides, and even if located on one side, its position on the left or right is not restricted.

[0097] In addition, refer to Figure 3 For example, one or more optical regions OA1 and OA2 may be provided in the display area AA, but the implementation is not limited thereto. For example, depending on the design, at least one or all of the optical regions OA1 and OA2 may be omitted. Although one or more optical regions OA1 and OA2 are illustrated as being located in the upper part of the display area AA, the implementation is not limited thereto. For example, one or more optical regions OA1 and OA2 may be located in various positions on the display area AA. For example, one or more optical regions OA1 and OA2 may be located in the same position or in separate positions.

[0098] One or more optical regions OA1 and OA2 may be configured to overlap with one or more optoelectronic devices, such as imaging devices like cameras (or image sensors) and / or detection sensors like proximity sensors and illuminance sensors, but are not limited thereto. For operation of the optoelectronic devices, light-transmitting structures may be formed in one or more optical regions OA1 and OA2, and these structures may have a certain level or higher transmittance. In other words, the number of pixels P per unit area in one or more optical regions OA1 and OA2 may be less than the number of pixels P per unit area in the conventional areas of the display area AA excluding optical regions OA1 and OA2, but are not limited thereto. For example, the resolution of one or more optical regions OA1 and OA2 may be lower than the resolution of the conventional areas within the display area AA, but is not limited thereto. For example, one or more optical regions OA1 and OA2 may have light-transmitting structures formed therein, and may have a higher transmittance than the conventional areas within the display area AA, regardless of their resolution, but are not limited thereto.

[0099] Refer again Figure 1 The data driving section 220 can receive image data Do and data control signal DCS from the timing control section 240, and in response to the data control signal DCS, the data driving section 220 can convert the image data Do into analog image data, i.e., data voltage Vdata, and output it to the corresponding data line DL.

[0100] The power supply section 280 can use, for example, a DC-DC converter to generate the DC power required to drive the pixel array and drive circuitry of the display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc.

[0101] The power supply section 280 can receive a power supply voltage Vcc from the host system, for example, as a driving voltage for driving the display device 10, and generate DC voltages such as low-gating voltages VGL and VEL, high-gating voltages VGH and VEH, high-level driving voltage EVDD, and low-level driving voltage EVSS. The low-gating voltages VGL and VEL, and the high-gating voltages VGH and VEH, can be supplied to the gate driving section 210. The high-level driving voltage EVDD and the low-level driving voltage EVSS can be jointly supplied to the pixels P in the display panel 100.

[0102] For example, the display device 10 of this exemplary embodiment configured as described above can employ a VRR method that adjusts the refresh cycle (or refresh rate) to drive at low power and reduce power consumption.

[0103] In this regard, in normal driving mode (i.e., high-speed driving mode), display device 10 can operate to refresh (or update) the image of display panel 100 (or the data voltage Vdata applied to each pixel P) on a frame FR basis. For example, in high-speed driving mode, display device 10 can be driven at a refresh rate of 120Hz, thereby performing a refresh operation on each of the 120 frames FR per second. Thus, in high-speed driving mode, all frames FR can be assigned as refresh frames FRr written with the data voltage Vdata. The implementation is not limited to this. For example, in high-speed driving mode, display device 10 can be driven at a refresh rate higher or lower than 120Hz. For example, in high-speed driving mode, display device 10 can be driven at refresh rates such as 60Hz, 90Hz, 165Hz, 180Hz, etc., but is not limited to this.

[0104] When displaying static images, the display device 10 can be driven in a low-speed drive mode. In low-speed drive mode, the refresh rate is reduced, resulting in a longer refresh cycle for the display panel 100. For example, in low-speed drive mode with a refresh rate of 10Hz, one refresh frame FRr and 11 consecutive skip frames FRs can be alternately repeated. Therefore, in low-speed drive mode, the frame FR can be divided into a refresh frame FRr in which data voltage Vdata is written and skip frames FRs in which data voltage Vdata is not written and is skipped.

[0105] Thus, in low-speed drive mode, as the drive frequency decreases, the period of refresh frame FRr (or the interval between refresh frames FRr) becomes longer, and there are one or more skip frames FRs between refresh frames FRr.

[0106] During skip frame refreshes (FRs), image refresh operations are stopped, which reduces power consumption.

[0107] When the data voltage Vdata is written in the refresh frame FRr, the first scan signal SC1 to the fourth scan signal SC4 (more specifically, their scan pulses) can be applied during the non-light-emitting period to write the data voltage Vdata to the corresponding pixel P.

[0108] Additionally, in skip frames FRs where no data voltage Vdata is written and maintained, the following operations can be performed: a bias voltage Vobs can be applied to alleviate the hysteresis of the driving transistor DT, and an anode reset voltage Var can be applied to reset the anode electrode of the light-emitting diode OD. For this purpose, a third scan signal SC3 (more specifically, its scan pulse) can be applied to provide the bias voltage Vobs and the anode reset voltage Var to the pixel P.

[0109] Further references are available. Figure 4 and Figure 5Describe the drivers in the refresh frame FRr and skip frame FRs of the VRR method.

[0110] In addition, Figure 4 and Figure 5 For ease of explanation, the first light emission control signal EM1(n) and the second light emission control signal EM2(n) are not illustrated separately, but rather an example of a light emission control signal EM(n) representing them is shown.

[0111] First, refer to Figure 4 This describes the driving mechanism in the refresh frame FRr. The refresh frame FRr can be divided into a non-emitting period Tne and an emitting period Te. The non-emitting period Tne of the refresh frame FRr can be referred to as the first non-emitting period Tne1, and the emitting period Te of the refresh frame FRr can be referred to as the first emitting period Te1.

[0112] The first non-emitting period Tne1 and the first emitting period Te1 can be defined by the emitting control signal EM(n) of the refresh frame FRr. In this regard, the high-level (as off level) scan pulse segment of the emitting control signal EM(n) can correspond to the first non-emitting period Tne1, and the low-level (as on level) segment of the emitting control signal EM(n) can correspond to the first emitting period Te1.

[0113] During the first non-light-emitting period Tne1 of the refresh frame FRr, the operation of applying and writing the data voltage Vdata can be performed.

[0114] In this regard, for example, during the data writing period (or sampling period) Tw, when each of the odd-numbered second scan signals SC2_O(n) and even-numbered second scan signals SC2_E(n) is applied, more specifically, when a low-level (as an on-state) scan pulse is applied to each of the odd-numbered second scan signals SC2_O(n) and even-numbered second scan signals SC2_E(n), the data voltage Vdata of each of the odd-numbered pixels P_O(n) and even-numbered pixels P_E(n) can be applied and written to the gate electrode of the driving transistor DT. Additionally, during the data writing period Tw, the threshold voltage of the driving transistor DT can be sampled and reflected in the gate electrode of the driving transistor DT.

[0115] During the data writing period Tw, the first scan signal SC1(n) can have a high-level (on-state) scan pulse, which enables the first transistor T1 to be in the on state.

[0116] Additionally, during the first non-light-emitting period Tne, at least one bias period (or anode reset period) Tobs can be set, during which a bias voltage Vobs and an anode reset voltage Var are applied. In this exemplary embodiment, the case where the bias periods Tobs are set before and after the data writing period Tw is taken as an example. In this case, for ease of explanation, the bias periods Tobs set before data writing can be referred to as the first bias period Tobs1, and the bias periods Tobs set after data writing can be referred to as the second bias period Tobs2.

[0117] In each of the first bias period Tobs1 and the second bias period Tobs2, the third scan signal SC3(n) may have a low-level (on-level) scan pulse.

[0118] In this configuration, the fifth transistor T5 can be turned on, allowing a bias voltage Vobs to be applied to the second node N2 and the third node N3. This enables the conduction bias stress operation of the drive transistor DT.

[0119] Additionally, the sixth transistor T6 can be turned on, allowing the anode reset voltage Var to be applied to the fifth node N5. This enables an anode reset operation to be performed on the anode electrode of the light-emitting diode OD.

[0120] Additionally, the application of the initialization voltage Vini can be performed between the data writing period Tw and the first bias period Tobs1. During this initialization period Ti, the fourth scan signal SC4(n) can have a high-level (on-state) scan pulse. Therefore, the seventh transistor T7 can be turned on, allowing the initialization voltage Vini to be applied to the first node N1, i.e., the gate electrode of the driving transistor DT. This enables the initialization operation for the driving transistor DT.

[0121] Next, refer to Figure 5 This describes the driving force in skipped frames (FRs). Skipped frames (FRs) can be divided into a non-emitting period (Tne) and an emitting period (Te). Here, the non-emitting period (Tne) of the skipped frames (FRs) can be referred to as the second non-emitting period (Tne2), and the emitting period (Te) of the skipped frames (FRs) can be referred to as the second emitting period (Te2).

[0122] The second non-emitting period Tne2 and the second emitting period Te2 can be defined by the emitting control signal EM(n) of the skipped frames FRs. In this regard, the high-level (as off level) scan pulse segment of the emitting control signal EM(n) can correspond to the second non-emitting period Tne2, and the low-level (as on level) segment of the emitting control signal EM(n) can correspond to the second emitting period Te2.

[0123] During the second non-light-emitting period Tne2 of the skip frame FRs, the operation of writing data voltage Vdata is not performed, therefore the data writing period Tw within the first non-light-emitting period Tne1 of the refresh frame FRr is not set.

[0124] Therefore, during the second non-light-emitting period Tne2 of the skip frame FRs, the first scan signal SC1(n) associated with the data write operation can be maintained at a low level of the off level, and the second scan signals SC2_O(n) and SC2_E(n) can be maintained at a high level of the off level.

[0125] In addition, during the second non-light-emitting period Tne2 of the skip frame FRs, the initialization operation of applying the initialization voltage Vini is not performed, so the initialization period Ti in the first non-light-emitting period Tne1 of the refresh frame FRr is not set.

[0126] Therefore, during the second non-light-emitting period Tne2 of the skip frame FRs, the fourth scan signal SC4(n) associated with the initialization operation can be maintained at a low level of the off level.

[0127] Additionally, during the second non-emitting period Tne2 of the skipped frame FRs, a bias period Tobs can be set, during which a bias voltage Vobs and an anode reset voltage Var are applied. For ease of explanation, the bias period Tobs set within the second non-emitting period Tne2 can be referred to as the third bias period Tobs3.

[0128] During the third bias period Tobs3, the third scan signal SC3(n) can have a low-level (on-state) scan pulse. Therefore, a conduction bias stress operation can be performed on the driving transistor DT, and an anode reset operation can be performed on the anode electrode of the light-emitting diode OD.

[0129] Further references will be made below. Figure 6 An example describing the cross-sectional structure of the display panel 100 of this exemplary embodiment. Figure 6 This is a cross-sectional view schematically illustrating an example of the cross-sectional structure of a display panel according to a first exemplary embodiment of the present disclosure.

[0130] exist Figure 6 For ease of explanation, two thin-film transistors (TFTs) TFT1 and TFT2 are illustrated in pixel P within the display area AA. Here, TFT1, which is positioned relatively low and closer to the substrate 101, is referred to as the first thin-film transistor TFT1, and it can be a polysilicon thin-film transistor. TFT2, which is positioned relatively high and farther from the substrate 101, is referred to as the second thin-film transistor TFT2, and it can be an oxide thin-film transistor.

[0131] In addition, the first thin-film transistor TFT1 can be a driving transistor ( Figure 2 (DT in the text), but not limited to this, and in Figure 6 For ease of explanation, the example shown illustrates the case where the first thin-film transistor TFT1 is connected to the light-emitting diode OD. Furthermore, the second thin-film transistor TFT2 can be any of the first to seventh transistors serving as switching thin-film transistors. Figure 2 One of T1 to T7 in the transistor, more specifically, the first transistor T1 connected to the storage capacitor Cst, or the seventh transistor T7 connected to the gate electrode of the driving transistor DT, but not limited thereto.

[0132] The substrate 101 can be configured as, for example, a thin glass substrate (or glass film) or a plastic substrate (or plastic film) to achieve the flexible characteristics of the display panel 100. The embodiments are not limited thereto. For example, the substrate 101 can be configured as a rigid substrate or a flexible substrate. For example, the substrate 101 can be configured as a transparent substrate or an opaque substrate.

[0133] Here, when the substrate 101 is configured as a glass substrate, for example, the substrate 101 may have a thickness of about 0.2 mm.

[0134] Additionally, when the substrate 101 is configured as a plastic substrate, for example, the substrate 101 may include at least one polyimide layer, but is not limited thereto. In this exemplary embodiment, a substrate 101 configured with two polyimide layers, namely a first polyimide layer 101a and a second polyimide layer 101b, is taken as an example.

[0135] The first thin-film transistor (TFT) 1 may include a first semiconductor layer 105 disposed on a substrate 101, a first gate electrode 115 overlapping the semiconductor layer 105 and interposed therebetween with a first insulating layer 110, and a first source electrode 151 and a first drain electrode 152 located on a fourth insulating layer 145 above the first gate electrode 115. Here, the first semiconductor layer 105 may be formed of polysilicon, but is not limited thereto.

[0136] The first semiconductor layer 105 may include a central channel region and source and drain regions on both sides thereof. The first source electrode 151 and the first drain electrode 152 may be connected to the source and drain regions of the first semiconductor layer 105 through a first contact hole 156 and a second contact hole 157 formed in the insulating layers 110, 120, 125, 135 and 145 located below the first source electrode 151 and the first drain electrode 152.

[0137] A second insulating layer 120 can be formed on the first gate electrode 115 of the first thin-film transistor TFT1.

[0138] The first interlayer insulating layer 125 can be formed on the second insulating layer 120. The second thin-film transistor TFT2 can be formed on the first interlayer insulating layer 125.

[0139] The second thin-film transistor (TFT2) may include a second semiconductor layer 130 located on a first interlayer insulating layer 125, a second gate electrode 140 overlapping the second semiconductor layer 130 and interposed therebetween with a third insulating layer 135, and a second source electrode 153 and a second drain electrode 154 located on a fourth insulating layer 145 above the second gate electrode 140. Here, the second semiconductor layer 130 may be formed of an oxide semiconductor, but is not limited thereto.

[0140] The second semiconductor layer 130 may include a central channel region and source and drain regions on both sides thereof. The second source electrode 153 and the second drain electrode 154 may be connected to the source and drain regions of the second semiconductor layer 130 through a third contact hole 158 and a fourth contact hole 159 formed in the insulating layers 135 and 145 located below the second source electrode 153 and the second drain electrode 154.

[0141] A second interlayer insulating layer (or a first planarization layer) 160 can be formed on the second thin-film transistor TFT2.

[0142] Here, the first insulating layer 110, the second insulating layer 120, the third insulating layer 135, and the fourth insulating layer 145 may be formed of inorganic insulating materials such as silicon nitride or silicon oxide, but are not limited thereto. For example, the first insulating layer 110, the second insulating layer 120, the third insulating layer 135, and the fourth insulating layer 145 may be formed of the same material or different materials, but are not limited thereto.

[0143] In addition, the first interlayer insulation layer 125 and the second interlayer insulation layer 160 may be formed of organic insulating materials such as photoacrylic acid or benzocyclobutene, but are not limited thereto.

[0144] The connecting electrode 162 can be formed on the second interlayer insulating layer 160. The connecting electrode 162 can be connected to the first drain electrode 152 through a contact hole 161 formed in the second interlayer insulating layer 160.

[0145] A third interlayer insulating layer (or a second planarization layer) 163 may be formed on the connecting electrode 162. The third interlayer insulating layer 163 may be formed of an organic insulating material such as photoacrylic acid or benzocyclobutene, but is not limited thereto. For example, depending on the design, the connecting electrode 162 may be omitted. In this case, for example, one of the second interlayer insulating layer 160 and the third interlayer insulating layer 163 may be omitted, but is not limited thereto.

[0146] The light-emitting diode OD and the dam 165 can be formed on the third interlayer insulating layer 163.

[0147] A light-emitting diode (OD) may include an anode electrode (or a first electrode) 171, a light-emitting layer 172, and a cathode electrode (or a second electrode) 173.

[0148] The anode electrode 171 can be connected to the connection electrode 162 through a contact hole 164 formed in the third interlayer insulating layer 163. Alternatively, for example, the anode electrode 171 can be connected to the first drain electrode 152 through contact holes formed in the second interlayer insulating layer 160 and the third interlayer insulating layer 163 without the connection electrode 162. However, this disclosure is not limited thereto.

[0149] The embankment 165 may be disposed along the boundary of pixel P and may be formed to cover the edge of anode electrode 171, but is not limited thereto. The light-emitting layer 172 may be formed on the anode electrode 171 exposed through the opening of the embankment 165.

[0150] Cathode electrode 173 can be formed on light-emitting layer 172 and can be driven by a low potential voltage (e.g., Figure 2 (EVSS).

[0151] An encapsulation layer 180 may be formed on the cathode electrode 173. The encapsulation layer 180 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. In this disclosure, a structure of the encapsulation layer 180 in which a first encapsulation layer 181, a second encapsulation layer 182, and a third encapsulation layer 183 are stacked sequentially is described as an example.

[0152] The first encapsulation layer 181 can be formed on the substrate 101 on which the cathode electrode 173 is formed. The third encapsulation layer 183 can be formed on the substrate 101 on which the second encapsulation layer 182 is formed, and can be formed together with the first encapsulation layer 181 to surround the upper surface, lower surface and side surface of the second encapsulation layer 182, but is not limited thereto. The first encapsulation layer 181 and the third encapsulation layer 183 can reduce, minimize or prevent the penetration of external moisture or oxygen into the light-emitting diode OD. The first encapsulation layer 181 and the third encapsulation layer 183 can be formed of an inorganic insulating material that can be deposited at low temperatures, such as silicon nitride, silicon oxide, silicon oxynitride or aluminum oxide, but is not limited thereto.

[0153] The second encapsulation layer 182 can act as a buffer to alleviate interlayer stress caused, for example, by bending of the display device 10, and can flatten the interlayer steps. The second encapsulation layer 182 can be formed on the substrate 101 on which the first encapsulation layer 181 is formed using a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon carbide (SiOC), or a photosensitive organic insulating material such as photoacrylic acid (but not limited thereto). When the second encapsulation layer 182 is formed by inkjet printing, a dam DAM can be provided in the non-display area NA to reduce or prevent the liquid second encapsulation layer 182 from diffusing to the edge of the substrate 101. The dam DAM can be positioned closer to the edge of the substrate 101 than the second encapsulation layer 182. The dam DAM reduces or prevents the second encapsulation layer 182 from diffusing to the pad area with conductive pads on the outermost edge of the substrate 101.

[0154] The dam DAM can be designed to reduce or prevent the diffusion of the second encapsulation layer 182. However, if the second encapsulation layer 182 is formed beyond the height of the dam DAM during the process, the second encapsulation layer 182, as an organic layer, may be exposed to the outside, allowing moisture and the like to easily penetrate into the light-emitting element. To reduce or prevent this, 10 or more dam DAMs can be formed consecutively, but this is not a limitation. For example, one or more dam DAMs can be formed.

[0155] For example, the dam DAM can be formed simultaneously with the first interlayer insulation layer 125, the second interlayer insulation layer 160, and / or the third interlayer insulation layer 163, but is not limited thereto. For example, when the first interlayer insulation layer 125 is formed, the lower layer of the dam DAM can be formed together; and when the second interlayer insulation layer 160 and the third interlayer insulation layer 163 are formed, the upper layer of the dam DAM can be formed together, so that the dam DAM can be formed in a three-layer laminated structure. As another example, the dam DAM can be formed together with one or both of the first interlayer insulation layer 125, the second interlayer insulation layer 160, and the third interlayer insulation layer 163. As another example, the dam DAM can be formed separately from the first interlayer insulation layer 125, the second interlayer insulation layer 160, and the third interlayer insulation layer 163, but is not limited thereto.

[0156] Therefore, the dam DAM can be formed of the same material as the first interlayer insulation layer 125, the second interlayer insulation layer 160 and the third interlayer insulation layer 163, but is not limited thereto.

[0157] For example, the dam DAM can be formed to overlap with the low-potential drive voltage line VSSL, but is not limited thereto. For example, the low-potential drive voltage line VSSL can be formed in the layer below the area where the dam DAM is located in the non-display area NA.

[0158] The low-potential driving voltage line VSSL and the gate driving portion 210 configured with a GIP structure can be formed along the periphery of the display panel 100, and the low-potential driving voltage line VSSL can be located outside the gate driving portion 210, but is not limited thereto. Additionally, the low-potential driving voltage line VSSL can be connected to the cathode electrode 173 to apply a low-potential driving voltage EVSS. The gate driving portion 210 is shown in the figures only in planar and cross-sectional form, but it can be configured with the same structure as the first thin-film transistor TFT1 and / or the second thin-film transistor TFT2 in the display area AA, but is not limited thereto.

[0159] A touch layer (or touch element layer) 190 may be disposed on the encapsulation layer 180. In the touch layer 190, a touch buffer layer 191 may be positioned between the touch sensor metal, including touch electrode connection lines 192 and 194, and touch electrodes 195 and 196, and the cathode electrode 173 of the light-emitting diode OD. For example, depending on the design, the touch layer 190 may be omitted.

[0160] The touch buffer layer 191 can prevent chemical solutions (developers, etchants, etc.) used in the manufacturing process of the touch sensor metal disposed on the touch buffer layer 191 or external moisture from penetrating into the light-emitting layer 172 containing organic materials. Therefore, the touch buffer layer 191 can reduce or prevent damage to the light-emitting layer 172, which is susceptible to chemical solutions or moisture.

[0161] According to the mutual capacitance-based touch sensor structure, touch electrodes 195 and 196 can be disposed on the touch buffer layer 191, and touch electrodes 195 and 196 can be disposed crosswise with each other.

[0162] Touch electrode connecting wires 192 and 194 can electrically connect touch electrodes 195 and 196. One of the touch electrode connecting wires 192 and 194 can be located on a different layer from touch electrodes 195 and 196, with a touch insulating layer 193 inserted between them. Alternatively, one of the touch electrode connecting wires 192 and 194 can also be located on a different layer from the other touch electrode connecting wire, with a touch insulating layer 193 inserted between them.

[0163] The touch electrode connection lines 192 and 194 can be configured to overlap with the embankment 165, thereby reducing or preventing a decrease in aperture ratio, but are not limited thereto.

[0164] Additionally, a portion of touch electrodes 195 and 196 and a portion of touch electrode connection line 192 may extend along the top and side surfaces of the package layer 180 and the top and side surfaces of the dam DAM, and be electrically connected to the touch driver circuit via touch pads 198 and 199.

[0165] A portion of touch electrodes 195 and 196 and a portion of touch electrode connection line 192 can receive touch drive signals from touch drive circuit and send them to touch electrodes 195 and 196, and can send touch sensing signals detected by touch electrodes 195 and 196 to touch drive circuit.

[0166] In this regard, for example, the driver IC (e.g., a data IC, etc.) including the data driver section 220 of the touch driver circuit can be configured in a COF type and connected to the non-display area NA of the substrate 101 of the display panel 100. In this case, the ends of the touch pads 198 and 199 can be connected to the flexible circuit film on which the driver IC is mounted, thereby enabling signal transmission. However, this disclosure is not limited thereto.

[0167] A touch protection layer 197 may be provided on touch electrodes 195 and 196. In the accompanying drawings, the touch protection layer 197 is shown as being provided only on touch electrodes 195 and 196, but is not limited thereto, and the touch protection layer 197 may extend before or after the dam DAM to be provided on the touch electrode connection line 192.

[0168] Alternatively, for example, a color filter may be disposed on the encapsulation layer 180. This color filter may be positioned on the touch layer 190, or between the encapsulation layer 180 and the touch layer 190. For example, depending on the design, the color filter may be omitted.

[0169] In addition, in this exemplary embodiment, the scan drive circuit of the gate drive section 210 can be configured to generate a scan signal without a separate inverter circuit using a clock and a transistor configured with oxide semiconductor. The scan drive circuit generates a scan signal applied to the transistor configured with oxide semiconductor within the pixel P.

[0170] In this way, the scan drive circuit can generate the corresponding scan signal without using an inverter circuit, thereby reducing the number of transistors in the scan drive circuit. Therefore, the scan drive circuit can be designed to be simple and have a small size (or small area). This can reduce the size of the gate drive portion 210, thereby reducing the bezel width of the display device 10 and thus achieving a narrow bezel.

[0171] In this exemplary embodiment, the scan drive circuit that does not include the inverter circuit may be, for example, a first scan drive circuit that generates a first scan signal SC1 applied to the first transistor T1 of pixel P and / or a fourth scan drive circuit that generates a fourth scan signal SC4 applied to the seventh transistor T7 of pixel P.

[0172] The structure and operation of the scan drive circuit, excluding the inverter circuit, can be described in more detail below.

[0173] Figure 7 A view illustrating an example of the structure of a scan drive circuit according to a first exemplary embodiment of the present disclosure. Figure 8 To illustrate the driver Figure 7 The timing waveform of the signal of the scanning drive circuit.

[0174] exist Figure 7 For ease of explanation, an example is given of a first scan level SSC1(n) located in the nth horizontal line within the first scan level SSC1 that forms the first scan drive circuit that generates the first scan signal SC1. Figure 8 In the example, from Figure 7 The first scan signal SC1(n) (more specifically, its scan pulse) output by the first scan level SSC1(n) of the nth horizontal line is used as an example.

[0175] In addition, the fourth scan drive circuit that generates the fourth scan signal SC4 can be configured and driven in a similar manner to the first scan drive circuit.

[0176] Reference Figure 7 and Figure 8 as well as Figures 1 to 6 The first scan driving circuit may include a plurality of first scan levels SSC1 that output first scan signals SC1 to a plurality of first scan lines SCL1 disposed in the display area AA.

[0177] Regarding the configuration of the first scan level SSC1, taking the nth first scan level SCC1(n) as an example, it can include an output section OC and a control section CCP that controls the output operation of the output section OC.

[0178] In this regard, the output section OC may include, for example, a pull-up transistor (or Q transistor) Ts1, a pull-down transistor (or QB transistor) Ts2, a Q capacitor CQ, and a QB capacitor CQB.

[0179] The control section CCP may include, for example, a transfer transistor TA and multiple control transistors Ts3, Ts4, Ts5 and Ts6. The multiple control transistors Ts3, Ts4, Ts5 and Ts6 may include, for example, a first control transistor Ts3, a second control transistor Ts4, a third control transistor Ts5 and a fourth control transistor Ts6 (or an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor).

[0180] Each of the transistors Ts1 to Ts6 and TA constituting the first scan stage SSC1(n) can be a P-type transistor or an N-type transistor. Each of the transistors Ts1 to Ts6 and TA constituting the first scan stage SSC1(n) can be a transistor using an oxide semiconductor, a transistor using polysilicon, or a transistor using other semiconductors (e.g., compound semiconductors, oxide semiconductors, amorphous silicon semiconductors, etc.). For example, the transistors Ts1 to Ts6 and TA constituting the first scan stage SSC1(n) can be transistors of the same type or transistors of different types. For example, the transistors Ts1 to Ts6 and TA constituting the first scan stage SSC1(n) can be transistors using the same semiconductor or transistors using different semiconductors.

[0181] In this exemplary embodiment, the following example is given: among the plurality of transistors Ts1 to Ts6 and TA constituting the first scan level SSC1(n), pull-up transistor Ts1, pull-down transistor Ts2, transfer transistor TA, and first control transistor Ts3 and fourth control transistor Ts6 are configured as N-type transistors including an oxide semiconductor layer, and second control transistor Ts4 and third control transistor Ts5 are configured as P-type transistors including a polysilicon layer.

[0182] Here, the N-type oxide transistors Ts1, Ts2, Ts3, Ts6, and TA can be formed, for example, with the same structure as the N-type oxide transistors T1 and T7 in pixel P. The P-type polysilicon transistors Ts5 and Ts6 can be formed, for example, with the same structure as the P-type polysilicon transistors T2 to T6 and DT in pixel P. However, the implementation is not limited to this. As an example, at least one or each of the N-type oxide transistors Ts1, Ts2, Ts3, Ts6, and TA can be formed with a structure different from that of the N-type oxide transistors T1 and T7 in pixel P, or at least one or each of the P-type polysilicon transistors Ts5 and Ts6 can be formed with a structure different from that of the P-type polysilicon transistors T2 to T6 and DT in pixel P.

[0183] The pull-up transistor Ts1 of the output section OC can pull up the output terminal NO of the first scan stage SSC1(n) in response to the Q node signal applied to its gate electrode. Conversely, the pull-down transistor Ts2 can pull down the output terminal NO in response to the QB node signal applied to its gate electrode.

[0184] The N-type pull-up transistor Ts1 can have, for example, a second electrode (or drain electrode) that receives the corresponding scan clock SCLKB2 and a first electrode (or source electrode) connected to the output terminal NO of the first scan stage SSC1(n). Here, the scan clock SCLKB2 input to the pull-up transistor Ts1 can be referred to as the second B scan clock SCLKB2. In this case, the second B scan clock SCLKB2 can be a clock signal with a waveform that is out of phase with the second scan clock SCLKB2.

[0185] Additionally, the N-type pull-down transistor Ts2 may have, for example, a second electrode (or drain electrode) connected to the output terminal NO and a first electrode (or source electrode) provided with a gating low voltage VGL output from the power supply section 280.

[0186] Additionally, the transfer transistor TA in the control section CCP can transfer charge from node Q2 to node Q in response to a high gate voltage VGH. The N-type transfer transistor TA may have, for example, a gate electrode to which a high gate voltage VGH is applied, a first electrode (or source electrode) connected to node Q, and a second electrode (or drain electrode) connected to node Q2.

[0187] The first control transistor Ts3 can provide the previous first scan signal SC1(n-1) to the Q2 node in response to the corresponding scan clock SCLKB1. This signal is the output signal of the previous first scan stage SSC1. The N-type first control transistor Ts3 may have, for example, a gate electrode to which the scan clock SCLKB1 is applied, a first electrode (or source electrode) connected to the Q2 node, and a second electrode (or drain electrode) to which the previous stage's first scan signal SC1(n-1) is applied. Here, the scan clock SCLKB1 input to the first control transistor Ts3 may be referred to as the first B scan clock SCLKB1.

[0188] The second control transistor Ts4 can be connected in parallel with the first control transistor Ts3, and can provide the previous first scan signal SC1(n-1) to the Q2 node in response to the corresponding scan clock SCLK1. This signal is the output signal of the previous first scan stage SSC1. The P-type second control transistor Ts4 can have, for example, a gate electrode to which the scan clock SCLK1 is applied, a second electrode (or drain electrode) connected to the Q2 node, and a first electrode (or source electrode) to which the previous first scan signal SC1(n-1) is applied. Here, the scan clock SCLK1 input to the second control transistor Ts4 can be referred to as the first scan clock SCLK1.

[0189] Here, the previous first scan signal SC1(n-1) applied to the first control transistor Ts3 and the second control transistor Ts4 can be used as a start signal (or carry signal). In addition, when the first scan level SSC1(n) is the scan level of the first horizontal line, the start signal provided from the timing control section 240 can be input to the first control transistor Ts3 and the second control transistor Ts4 to start their output operation.

[0190] Furthermore, the first scan clock SCLK1 and the first B scan clock SCLKB1 can be clock signals with opposite phase waveforms. Additionally, the first scan clock SCLK1 can have a different phase than the second scan clock SCLK2.

[0191] The third control transistor Ts5 can send a gating high voltage VGH to the QB node in response to the voltage of the Q2 node. The P-type third control transistor Ts5 may have, for example, a gate electrode connected to the Q2 node, a second electrode (or drain electrode) connected to the QB node, and a first electrode (or source electrode) to which the gating high voltage VGH is applied.

[0192] The fourth control transistor Ts6 can be connected in series with the third control transistor Ts5, with a QB node interposed between them, and can send a low-gating voltage VGL to the QB node in response to the voltage of the Q2 node. The N-type fourth control transistor Ts6 may have, for example, a gate electrode connected to the Q2 node, a second electrode (or drain electrode) connected to the QB node, and a first electrode (or source electrode) to which the low-gating voltage VGL is applied.

[0193] Additionally, the Q capacitor CQ can be connected between the Q node and the output terminal NO, and the QB capacitor CQB can be connected between the QB node and the line transmitting the strobe low voltage VGL. Here, the capacitance of the Q capacitor CQ and the capacitance of the QB capacitor CQB can be set to be greater than the capacitance of the storage capacitor Cst in pixel P.

[0194] The first scan level SSC1(n) configured as described above can shift the previous first scan signal SC1(n-1) according to the three input scan clocks SCLK1, SCLKB1, and SCLKB2, and can output its first scan signal SC1(n) to the first scan line SCL1 of the nth horizontal line.

[0195] Thus, the first scan level SSC1(n) of the nth horizontal line can be operated by receiving the first scan clock SCLK1, the first B scan clock SCLKB1, and the second B scan clock SCLKB2.

[0196] Additionally, the first scan level SSC1 located on the (n-1)th and (n+1)th horizontal lines before and after the nth horizontal line can operate by receiving its corresponding three scan clocks (e.g., the second scan clock SCLK2, the second B scan clock SCLKB2, and the first B scan clock SCLKB1). For example, in each of the first scan levels SSC1 located on the (n-1)th and (n+1)th horizontal lines, the pull-up transistor Ts1 can be configured to receive the first B scan clock SCLKB1, and the first control transistor Ts3 and the second control transistor Ts4 can be configured to receive the second B scan clock SCLKB2 and the second scan clock SCLK2, respectively.

[0197] Further references are available. Figure 8 This describes the output operation of the first scan signal SC1(n) from the nth first scan level SSC1(n).

[0198] As described above, the nth first scan level SSC1(n) can receive three corresponding scan clocks, namely, the first scan clock SCLK1, the first B scan clock SCLKB1, and the second scan clock SCLKB2, to output the corresponding first scan signal SC1(n).

[0199] For example, during the first time period t1, the previous first scan signal SC1(n-1) can be in a low state. During the first time period t1, the first scan clock SCLK1 can transition from a low state to a high state, and conversely, the first B scan clock SCLKB1 can transition from a high state to a low state.

[0200] Here, during the period when the first scan clock SCLK1 is low and the first B scan clock SCLKB1 is high, the first control transistor Ts3 and the second control transistor Ts4 can be turned on, so that the low voltage of the previous first scan signal SC1(n-1) (i.e., the gating low voltage VGL) can be applied to node Q2. Therefore, the voltage of node Q2 becomes low.

[0201] Subsequently, during the period when the first scan clock SCLK1 is high and the first B scan clock SCLKB1 is low, the first control transistor Ts3 and the second control transistor Ts4 can be turned off, and the voltage of the Q2 node can be maintained at a low level.

[0202] Thus, during the first time period t1, the low voltage of the previous first scan signal SC1(n-1) can be sent to the Q2 node, thereby setting the Q2 node to a low state.

[0203] In this case, the voltage at node Q2 can be transferred to node Q through the conducting transfer transistor TA, causing node Q to go low.

[0204] In response to the low voltage at node Q2, the third control transistor Ts5 can be turned on, and the fourth control transistor Ts6 can be turned off. Therefore, the high gate voltage VGH can be transferred to node QB through the turned-on third control transistor Ts5, making node QB high.

[0205] Thus, during the first time period t1, node Q can go low and node QB can go high. Correspondingly, pull-up transistor Ts1 can be turned off and pull-down transistor Ts2 can be turned on, allowing the low voltage VGL to be output to output terminal NO through pull-down transistor Ts2. In this way, the low-level first scan signal SC1(n) can be applied to the first scan line SCL1 of the nth horizontal line.

[0206] Next, in the second time period t2, the previous first scan signal SC1(n-1) can be switched to a high state. During the second time period t2, the first scan clock SCLK1 can be in a low state, and conversely, the first B scan clock SCLKB1 can be in a high state.

[0207] In this configuration, the first control transistor Ts3 and the second control transistor Ts4 can be turned on, allowing the high voltage of the previous first scan signal SC1(n-1) (i.e., the gating high voltage VGH) to be applied to node Q2. Therefore, during the second time period t2, the voltage of node Q2 can be at a high level.

[0208] In this situation, the voltage of node Q2 can be transferred to node Q through the conducting transfer transistor TA, allowing node Q to be in a high state.

[0209] Additionally, in response to the high voltage at node Q2, the third control transistor Ts5 can be turned off, and the fourth control transistor Ts6 can be turned on. Therefore, the low gate voltage VGL can be transferred to node QB through the turned-on fourth control transistor Ts6, allowing node QB to be in a low state.

[0210] Thus, during the second time period t2, node Q can be in a high state and node QB can be in a low state. Therefore, pull-up transistor Ts1 can be turned on and pull-down transistor Ts2 can be turned off, so that the second B scan clock SCLKB2 can be output to the output terminal NO through pull-up transistor Ts1.

[0211] Here, during the second time period t2, the second B scan clock SCLKB2 can have a low-level voltage (i.e., a low-gated voltage VGL), so that a low-level first scan signal SC1(n) can be applied to the first scan line SCL1 of the nth horizontal line.

[0212] As described above, corresponding to the high segment of the previous first scan signal SC1(n-1), the low segment of the first scan clock SCLK1 controlling the second control transistor Ts4 and the high segment of the first B scan clock SCLKB1 controlling the first control transistor Ts3 can be set. For example, the high segment of the previous first scan signal SC1(n-1) can be set to substantially coincide with (or have substantially the same timing) the low segment of the first scan clock SCLK1 and the high segment of the first B scan clock SCLKB1.

[0213] Next, in the third time period t3, the previous first scan signal SC1(n-1) can be switched to a low state. During the third time period t3, the first scan clock SCLK1 can be in a high state, and conversely, the first B scan clock SCLKB1 can be in a low state.

[0214] In this situation, the first control transistor Ts3 and the second control transistor Ts4 can be turned off. Therefore, during the third time period t3, node Q2 can remain high, node Q can remain high, and node QB can remain low.

[0215] Thus, during the third time period t3, node Q can be in a high state, and node QB can be in a low state. Accordingly, pull-up transistor Ts1 can remain in the on state, and pull-down transistor Ts2 can remain in the off state, thereby enabling the second B scan clock SCLKB2 to be continuously output to the output terminal NO through pull-up transistor Ts1.

[0216] Here, during the third time period t3, the second B scan clock SCLKB2 can continue to have a low level voltage (i.e., a low gate voltage VGL), so that the first scan signal SC1(n) which is at a low level can be continuously applied to the first scan line SCL1 of the nth horizontal line.

[0217] Here, the low segment of the second B-scan clock SCLKB2 input to the pull-up transistor Ts1 can be set to be wider than the high segment of the previous first scan signal SC1(n-1). Conversely, the high segment of the second B-scan clock SCLKB2 input to the pull-up transistor Ts1 can be set to be narrower than the low segment of the first B-scan clock SCLKB1. Furthermore, the high segments of the second B-scan clock SCLKB2 and the first B-scan clock SCLKB1 can be set to be separated by a certain time interval, for example, a third time interval t3.

[0218] Next, during the fourth time period t4, the previous first scan signal SC1(n-1) can be kept low. During the fourth time period t4, the first scan clock SCLK1 can be kept high, and conversely, the first B scan clock SCLKB1 can be kept low.

[0219] In this situation, the first control transistor Ts3 and the second control transistor Ts4 can be turned off. Therefore, during the fourth time period t4, node Q2 can remain high, node Q can remain high, and node QB can remain low.

[0220] Thus, during the fourth time period t4, the Q node can be in a high state and the QB node can be in a low state. Accordingly, the pull-up transistor Ts1 can remain in the on state and the pull-down transistor Ts2 can remain in the off state, so that the second B scan clock SCLKB2 can be output to the output terminal NO through the pull-up transistor Ts1.

[0221] Here, the second B scan clock SCLKB2 can have a high-voltage (i.e., high-voltage VGH gate) pulse during the fourth time period t4, so that the high-level first scan signal SC1(n) can be applied to the first scan line SCL1 of the nth horizontal line. For example, during the fourth time period t4, a scan pulse with a high-voltage VGH gate can be generated for the first scan signal SC1(n), and it can be applied to the first scan line SCL1 of the nth horizontal line.

[0222] When the first scan signal SC1(n) of the selected high voltage VGH is output from the output terminal NO, the Q node can bootstrap through the Q capacitor CQ, thereby increasing the voltage of the Q node to a level higher than the selected high voltage VGH. Because the Q node voltage is increased through bootstrap, the second B scan clock SCLKB2 can be stably output to the output terminal NO.

[0223] Additionally, during the fourth time period t4, when the second B scan clock SCLKB2 switches to a low voltage, the voltage at the output terminal NO can also switch to a low voltage, thereby enabling the output of the first scan signal SC1(n) at a low level. Furthermore, the voltage at the Q node can be reduced to a gate high voltage by the Q capacitor CQ.

[0224] Next, in the fifth time period t5, the previous first scan signal SC1(n-1) can remain low. During the fifth time period t5, the first scan clock SCLK1 can have a low segment and then switch to a high segment; and conversely, the first B scan clock SCLKB1 can have a high segment and then switch to a low segment.

[0225] Here, during the period when the first scan clock SCLK1 is low and the first B scan clock SCLKB1 is high, the first control transistor Ts3 and the second control transistor Ts4 can be turned on, thereby applying the low voltage of the previous first scan signal SC1(n-1) to node Q2. Therefore, the voltage of node Q2 can become low.

[0226] Subsequently, during the segment where the first scan clock SCLK1 is high and the first B scan clock SCLKB1 is low, the first control transistor Ts3 and the second control transistor Ts4 can be turned off, and the voltage of the Q2 node can be maintained at a low level.

[0227] Thus, during the fifth time period t5, similar to the first time period t1, the low voltage of the previous first scan signal SC1(n-1) can be sent to the Q2 node, thereby setting the Q2 node to a low state.

[0228] In this case, the voltage at node Q2 can be sent to node Q through the conducting transfer transistor TA, thereby setting node Q to a low state.

[0229] In response to the low voltage at node Q2, the third control transistor Ts5 can be turned on and the fourth control transistor Ts6 can be turned off. Therefore, the high gate voltage VGH can be sent to node QB through the turned-on third control transistor Ts5, thereby setting node QB to a high state.

[0230] Thus, during the fifth time period t5, node Q can be in a low state and node QB can be in a high state. Accordingly, pull-up transistor Ts1 can be turned off and pull-down transistor Ts2 can be turned on, allowing the low gate voltage VGL to be output through output terminal NO. Therefore, the low-level first scan signal SC1(n) can be applied to the first scan line SCL1 of the nth horizontal line.

[0231] Through the above operations, the first scan signal SC1(n) can be stably output from the nth first scan level SSC1(n) to the corresponding first scan line SCL1.

[0232] The first scan signal SC1(n) generated in this way can be provided to the pixel P of the corresponding horizontal line through the first scan line SCL1.

[0233] Furthermore, when the display device 10 is driven in low-speed mode using the VRR method, the pixel P refresh operation is not performed during the skip frame FRs period, so the first scan signal SC1 can be maintained in a low state, such as Figure 5 As shown. In addition, the first scan signal SC1 can remain low even during the blank period between adjacent frames FR.

[0234] For the output of the first scan signal SC1(n) at a low level during the skip frames FRs and blank periods, for example, the first scan clock SCLK1 and the second scan clock SCLK2 can be maintained at a high state, and the first B scan clock SCLKB1 and the second B scan clock SCLKB2 can be maintained at a high state (or a low state).

[0235] In this case, the first control transistor Ts3 of the first scan stage SSC1 can be kept in the on state, and the Q2 node and the Q node can be kept in the low state.

[0236] Furthermore, the third control transistor Ts5 can remain in the on state and the fourth control transistor Ts6 can remain in the off state, thereby enabling the high voltage VGH to be continuously applied to the QB node through the third control transistor Ts5. As a result, the QB node can be maintained in the high state.

[0237] Therefore, during the skip frames FRs and blank periods, the first scan signal SC1 can be maintained in a continuously low state.

[0238] As described above, according to this exemplary embodiment, the scan drive circuit of the gate drive portion that generates the scan signal applied to the transistor configured with oxide semiconductor in the pixel may include the transistor configured with oxide semiconductor, and may receive multiple clock signals and output the scan signal.

[0239] In this way, the scan drive circuit can generate a scan signal using a scan clock and transistors configured with oxide semiconductors without requiring a separate inverter circuit configured by CMOS.

[0240] Therefore, the number of transistors in the scan drive circuit can be reduced, thus allowing the scan drive circuit to be designed to be simple and have a small size (or small area).

[0241] For example, a scan drive circuit using an inverter circuit has ten transistors, including two transistors constituting the inverter circuit, while this exemplary embodiment can reduce the number of transistors by three.

[0242] Therefore, the size of the gate drive section can be reduced, thereby reducing the width of the bezel and achieving a narrow bezel.

[0243] Furthermore, since the number of transistors can be reduced, the power required to drive the reduced number of transistors can be reduced, thereby reducing power consumption and enabling low-power operation.

[0244] <Second Exemplary Implementation>

[0245] Figure 9This is a view that schematically illustrates a structural example of a scan drive circuit according to a second exemplary embodiment of the present disclosure.

[0246] In the following description, detailed explanations of components that are the same as or similar to those in the first exemplary embodiment described above may be omitted or given only briefly.

[0247] Similar to the first exemplary embodiment, in the gate driving section of this exemplary embodiment, the scan driving circuit of the gate driving section that generates the scan signal applied to the transistor formed of oxide semiconductor in the pixel may include the transistor formed of oxide semiconductor, and may receive multiple clock signals and output the scan signal.

[0248] However, unlike the first exemplary embodiment, the QB capacitor can be removed from the scan stage constituting the scan drive circuit. Figure 7 (CQB in the text). (Refer to...) Figure 9 This was described.

[0249] exist Figure 9 For ease of explanation, an example is given of a first scan level SSC1(n) set on the nth horizontal line in the first scan level SSC1 that forms the first scan drive circuit that generates the first scan signal SC1.

[0250] In addition, the fourth scan drive circuit that generates the fourth scan signal can be configured and driven in a similar manner to the first scan drive circuit.

[0251] The first scan drive circuit may include a plurality of first scan levels SSC1 that output first scan signals SC1 to a plurality of first scan lines disposed in the display area.

[0252] Similar to the first exemplary embodiment, in the first scan level SSC1, the output section OC may include a pull-up transistor (or Q transistor) Ts1, a pull-down transistor (or QB transistor) Ts2, and a Q capacitor CQ. Thus, in this exemplary embodiment, the output section OC does not include a QB capacitor ( Figure 7 (CQB in the middle).

[0253] Similar to the first exemplary embodiment, the control section CCP may include a transfer transistor TA and multiple control transistors Ts3, Ts4, Ts5, and Ts6. The multiple control transistors Ts3, Ts4, Ts5, and Ts6 may include, for example, a first control transistor Ts3, a second control transistor Ts4, a third control transistor Ts5, and a fourth control transistor Ts6 (or an eighth, ninth, tenth, and eleventh transistor).

[0254] Similar to the first exemplary embodiment, the first scan level SSC1(n) configured as described above can shift the previous first scan signal SC1(n-1) according to the three input scan clocks SCLK1, SCLKB1, and SCLKB2, and output the corresponding first scan signal SC1(n) to the corresponding first scan line.

[0255] As described above, the first scan stage SSC1 of this exemplary embodiment may omit the QB capacitor used to maintain the voltage of the QB node.

[0256] Even without the QB capacitor, the first scan stage SSC1 can still operate normally.

[0257] In this regard, QB capacitors are components used to maintain the voltage of the QB node, and are particularly needed for keeping the QB node in a low state for extended periods.

[0258] For example, when driven in low-speed mode using the VRR method, the first scan signal SC1 skips multiple frames ( Figure 5 The FRs in the QB node must remain high to keep the pull-down transistor Ts2 conducting. Therefore, a QB capacitor is connected to the QB node to maintain its voltage.

[0259] However, according to this exemplary embodiment, as mentioned above in the first exemplary embodiment, during the skip frame (and blank period), the first scan clock SCLK1 and the second scan clock SCLK2 can be maintained in a high state, and the first B scan clock SCLKB1 and the second B scan clock SCLKB2 can be maintained in a high state (or a low state).

[0260] In this case, the first control transistor Ts3 of the first scan stage SSC1 can be kept in the on state, and the Q2 node and the Q node can be kept in the low state.

[0261] Furthermore, the third control transistor Ts5 can remain in the on state and the fourth control transistor Ts6 can remain in the off state, thereby enabling the high voltage VGH to be continuously applied to the QB node through the third control transistor Ts5.

[0262] In this way, the high voltage VGH can be continuously transferred to the QB node, thereby allowing the QB node to remain in a high state.

[0263] In this way, based on the configuration and operation of the first scan level SSC1, the QB node can continuously maintain a high state.

[0264] Therefore, even if the QB capacitor, which is used to maintain the high state of the QB node during long-term operation, is omitted, the QB node can still maintain the high state due to the continuous input of the gating high voltage VGH to the QB node.

[0265] Therefore, in this exemplary embodiment, the QB capacitor can be removed from the first scan stage, thereby simplifying the design of the first scan drive circuit and making it smaller in size.

[0266] Therefore, the size of the gate drive can be further reduced, thereby further reducing the width of the bezel and achieving a narrow bezel.

[0267] <Third Exemplary Implementation>

[0268] Figure 10 A view illustrating an example of the structure of a scan drive circuit according to a third exemplary embodiment of the present disclosure. Figure 11 To illustrate the driver Figure 10 The timing waveform of the signal of the scanning drive circuit.

[0269] In the following description, detailed explanations of components that are the same as or similar to the first and second exemplary embodiments described above may be omitted or briefly given.

[0270] Similar to the first and second exemplary embodiments, in the gate driving section of this exemplary embodiment, the scan driving circuit of the gate driving section that generates a scan signal applied to a transistor formed of oxide semiconductor disposed in a pixel may include a transistor formed of oxide semiconductor, and may receive multiple clock signals and output a scan signal.

[0271] However, unlike the first and second exemplary embodiments, the scan stage constituting the scan drive circuit can receive two scan clocks, SCLKB1 and SCLKB2, and output a scan signal. (Refer to...) Figure 10 and Figure 11 This was described.

[0272] exist Figure 10 For ease of explanation, an example is given of a first scan level SSC1(n) in the nth horizontal line of the first scan level SSC1 that forms the first scan drive circuit that generates the first scan signal SC1.

[0273] In addition, the fourth scan drive circuit that generates the fourth scan signal can be configured and driven in a similar manner to the first scan drive circuit.

[0274] The first scan drive circuit may include a plurality of first scan levels SSC1 that output first scan signals SC1 to a plurality of first scan lines disposed in the display area.

[0275] Similar to the first exemplary embodiment, in the first scan level SSC1, the output section OC may include a pull-up transistor (or Q transistor) Ts1, a pull-down transistor (or QB transistor) Ts2, a Q capacitor CQ, and a QB capacitor CQB.

[0276] Alternatively, as another example, similar to the second exemplary implementation, the QB capacitor CQB can be removed from the first scan level SSC1.

[0277] Similar to the first and second exemplary embodiments, the control section CCP may include a transfer transistor TA and a plurality of control transistors Ts3, Ts4, Ts5, and Ts6. The plurality of control transistors Ts3, Ts4, Ts5, and Ts6 may include, for example, a first control transistor Ts3, a second control transistor Ts4, a third control transistor Ts5, and a fourth control transistor Ts6 (or an eighth, ninth, tenth, and eleventh transistor).

[0278] The N-type pull-up transistor Ts1 may have, for example, a second electrode (or drain electrode) that receives the corresponding scan clock SCLKB2 and a first electrode (or source electrode) connected to the output terminal NO of the first scan stage SSC1(n). Here, the scan clock SCLKB2 input to the pull-up transistor Ts1 may be referred to as the second B scan clock SCLKB2.

[0279] At this time, the second B scan clock SCLKB2 can be a clock signal with a waveform that is opposite in phase to the first B scan clock SCLKB1.

[0280] The first control transistor Ts3 can provide the previous first scan signal SC1(n-1) to the Q2 node in response to the corresponding scan clock SCLKB1. This signal is the output signal of the previous first scan stage SSC1. Here, the scan clock SCLKB1 input to the first control transistor Ts3 can be referred to as the first B scan clock SCLKB1.

[0281] The second control transistor Ts4 can be connected in parallel with the first control transistor Ts3, and can provide the previous first scan signal SC1(n-1) to the Q2 node in response to its corresponding scan clock SCLKB2 (i.e., the second B scan clock SCLKB2) as the output signal of the previous first scan stage SSC1.

[0282] At this time, the first B-scan clock SCLKB1 and the second B-scan clock SCLKB2, which have opposite phases, can have the same pulse width in their high and low segments. Therefore, unlike the first and second exemplary embodiments, the high segments (or low segments) of the first B-scan clock SCLKB1 and the second B-scan clock SCLKB2 can be generated alternately and continuously with essentially no time interval. For example, the low segment (or high segment) of the second B-scan clock SCLKB2 can be positioned correspondingly (or matched) to the high segment (or low segment) of the first B-scan clock SCLKB1.

[0283] Unlike the first and second exemplary embodiments, the first scan level SSC1(n) configured as above can shift the first scan signal SC1(n-1) according to the two input scan clocks SCLKB1 and SCLKB2, and output its first scan signal SC1(n) to the corresponding first scan line.

[0284] Thus, the first scan level SSC1(n) of the nth horizontal line can be operated by receiving the first B scan clock SCLKB1 and the second B scan clock SCLKB2.

[0285] Furthermore, the positions of the first B-scan clock SCLKB1 and the second B-scan clock SCLKB2 input to the first scan level SSC1 located on the (n-1)th and (n+1)th horizontal lines (before and after the nth horizontal line) can be reversed compared to the positions of the scan clocks SCLKB1 and SCLKB2 input to the first scan level SSC1(n) on the nth horizontal line. For example, in each of the first scan levels SSC1 located on the (n-1)th and (n+1)th horizontal lines, the pull-up transistor Ts1 can be configured to receive the first B-scan clock SCLKB1, and the first control transistor Ts3 and the second control transistor Ts4 can be configured to receive the second B-scan clock SCLKB2 and the first B-scan clock SCLKB1, respectively.

[0286] Further references are available. Figure 11 This describes the output operation of the first scan signal SC1(n) in the nth first scan level SSC1(n).

[0287] As described above, the nth first scan level SSC1(n) can receive the corresponding two scan clocks, namely the first B scan clock SCLKB1 and the second B scan clock SCLKB2, and output the corresponding first scan signal SC1(n).

[0288] For example, during the first time period t1, the previous first scan signal SC1(n-1) can be in a low state. During the first time period t1, the second B scan clock SCLKB2 can transition from a low state to a high state, and conversely, the first B scan clock SCLKB1 can transition from a high state to a low state.

[0289] In this case, during the first time period t1, the low voltage of the previous first scan signal SC1(n-1) can be sent to the Q2 node, thereby setting the Q2 node to a low state.

[0290] Therefore, during the first time period t1, the Q node can be in a low state, and the QB node can be in a high state. Thus, a low-level first scan signal SC1(n) can be applied to the first scan line of the nth horizontal line.

[0291] Next, in the second time period t2, the previous first scan signal SC1(n-1) can transition to a high state. During the second time period t2, the second B scan clock SCLKB2 can be in a low state, and conversely, the first B scan clock SCLKB1 can be in a high state.

[0292] In this configuration, the first control transistor Ts3 and the second control transistor Ts4 can be turned on, allowing the high voltage of the previous first scan signal SC1(n-1) (i.e., the gating high voltage VGH) to be applied to node Q2. Therefore, during the second time period t2, the voltage of node Q2 can be at a high level.

[0293] In this scenario, during the second time period t2, node Q can be in a high state and node QB can be in a low state.

[0294] Here, the second B scan clock SCLKB2 can have a low-level voltage (i.e., a low-level gate voltage VGL) during the second time period t2, so that the low-level first scan signal SC1(n) can be applied to the first scan line of the nth horizontal line.

[0295] As described above, corresponding to the high segment of the previous first scan signal SC1(n-1), the low segment of the second B scan clock SCLKB2, which controls the second control transistor Ts4, and the high segment of the first B scan clock SCLKB1, which controls the first control transistor Ts3, can be set. For example, the high segment of the previous first scan signal SC1(n-1) can be set to substantially coincide with (or have substantially the same timing) the low segment of the second B scan clock SCLKB2 and the high segment of the first B scan clock SCLKB1.

[0296] Next, in the third time period t3, the previous first scan signal SC1(n-1) can be switched to a low state. During the third time period t3, the second B scan clock SCLKB2 can be in a high state, and conversely, the first B scan clock SCLKB1 can be in a low state.

[0297] In this situation, the first control transistor Ts3 and the second control transistor Ts4 can be turned off. Therefore, during the third time period t3, node Q2 can remain high, node Q can remain high, and node QB can remain low.

[0298] Here, during the third time period t3, the second B scan clock SCLKB2 has a high voltage (i.e., a high gate voltage VGH) pulse, and the high-level first scan signal SC1(n) can be applied to the first scan line of the nth horizontal line.

[0299] Next, in the fourth time period t4, the previous first scan signal SC1(n-1) can remain low. During the fourth time period t4, the second B scan clock SCLKB2 can transition from a low segment to a high segment, and conversely, the first B scan clock SCLKB1 can transition from a high segment to a low segment.

[0300] In this case, similar to the first time period t1, in the fourth time period t4, the low voltage of the previous first scan signal SC1(n-1) can be sent to the Q2 node, thereby setting the Q2 node to a low state.

[0301] Therefore, in the fourth time period t4, node Q can be in a low state and node QB can be in a high state. Therefore, a low-level first scan signal SC1(n) can be applied to the first scan line of the nth horizontal line.

[0302] Through the above operations, the nth first scan level SSC1(n) can stably output the first scan signal SC1(n) to the corresponding first scan line.

[0303] As described above, the first scan level SSC1 of this exemplary embodiment can operate by receiving two scan clocks SCLKB1 and SCLKB2.

[0304] Therefore, compared to the first and second exemplary embodiments, the number of scan clocks in this exemplary embodiment can be reduced, and the first scan drive circuit can be designed to be simpler and smaller in size.

[0305] Therefore, the size of the gate drive circuit can be further reduced, thereby further reducing the width of the bezel and achieving a narrow bezel.

[0306] As described above, in embodiments of this disclosure, the scan drive circuit of the gate drive portion that generates a scan signal applied to a transistor configured with an oxide semiconductor disposed in a pixel may include a transistor configured with an oxide semiconductor and may receive multiple clock signals and output a scan signal.

[0307] In this way, the scan drive circuit can generate a scan signal using a scan clock and transistors configured with oxide semiconductors without a separate inverter circuit configured with CMOS. Although the exemplary embodiments described above are based on N-type transistors configured with oxide semiconductors and P-type transistors configured with polysilicon layers, the embodiments are not limited thereto. For example, N-type transistors can be configured with polysilicon layers or other semiconductors, and P-type transistors can be configured with oxide semiconductors or other semiconductors, but are not limited thereto.

[0308] Therefore, the number of transistors in the scan drive circuit can be reduced, allowing the scan drive circuit to be designed to be simple and have a small size (or area). Consequently, the size of the gate drive portion can be reduced, thereby reducing the bezel width of the display device and achieving a narrow bezel.

[0309] Furthermore, since the number of transistors can be reduced, the power required to drive the reduced number of transistors can be reduced, thereby reducing power consumption and enabling low-power operation.

[0310] Furthermore, the QB capacitor can be omitted from the scan drive circuit, allowing for a simpler and smaller scan drive circuit design. This enables further reduction in the size of the gate drive portion, thereby further reducing the bezel width and achieving a narrow bezel.

[0311] Furthermore, the number of scan clock cycles input to the scan drive circuit can be reduced, allowing the scan drive circuit to be designed to be simpler and smaller. Therefore, the size of the gate drive section can be further reduced, thereby further reducing the bezel width and achieving a narrow bezel.

[0312] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover various modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

[0313] Cross-references to related applications

[0314] This application claims priority to Korean Patent Application No. 10-2024-0165095, filed in Korea on November 19, 2024, the entire contents of which are incorporated herein by reference for all purposes, as if fully set forth herein.

Claims

1. A display device, the display device comprising: A display panel, the display panel including pixels, wherein each pixel includes a light-emitting diode and a plurality of transistors, the plurality of transistors being configured to be electrically connected to the light-emitting diode; and A first scan driving circuit, for each of a plurality of horizontal lines on the display panel, includes a first scan stage configured to output a first scan signal for that horizontal line. The first scan level includes: A pull-up transistor and a pull-down transistor, wherein the gate electrode of the pull-up transistor is connected to a first node, and the gate electrode of the pull-down transistor is connected to a second node; A transfer transistor, the transfer transistor being connected between the first node and the third node; A first control transistor and a second control transistor connected in parallel to each other, the first control transistor and the second control transistor having a first electrode configured to receive a carry signal and a second electrode connected to the third node; and A third control transistor and a fourth control transistor are connected in series with each other, the second node is located between the third control transistor and the fourth control transistor, and the third control transistor and the fourth control transistor have corresponding gate electrodes connected to the second node. Wherein, the first scan level configured to output the first scan signal of the nth horizontal line is configured to apply the first scan signal of the nth horizontal line to the first transistor among the plurality of transistors, and In the first scan stage configured to output the first scan signal of the nth horizontal line, the gate electrode of the first control transistor is configured to receive a first scan clock, the drain electrode of the pull-up transistor is configured to receive a second scan clock, and the gate electrode of the second control transistor is configured to receive a third scan clock or the second scan clock.

2. The display device according to claim 1, wherein, The pull-up transistor and the pull-down transistor, the first control transistor and the fourth control transistor, and the transfer transistor comprise oxide semiconductors.

3. The display device according to claim 2, wherein, The first transistor of the plurality of transistors includes the oxide semiconductor.

4. The display device according to claim 1, wherein, The pull-up transistor and the pull-down transistor, the first control transistor and the fourth control transistor, the transfer transistor, and the first transistor among the plurality of transistors are N-type transistors.

5. The display device according to claim 4, wherein, The gate electrode of the transfer transistor is configured to receive a high gate voltage, the first electrode of the third control transistor is configured to receive the high gate voltage, and the first electrode of the fourth control transistor and the source electrode of the pull-down transistor are configured to receive a low gate voltage.

6. The display device according to claim 1, further comprising a first capacitor connected between the first node and the source electrode of the pull-up transistor.

7. The display device according to claim 1, further comprising a second capacitor connected between the second node and the source electrode of the pull-down transistor.

8. The display device according to claim 1, wherein, In the first scan stage configured to output the first scan signal of the nth horizontal line, the gate electrode of the second control transistor is configured to receive the third scan clock, which has an opposite phase to the first scan clock, and the high portion of the first scan clock is separated from the high portion of the second scan clock by a predetermined time.

9. The display device according to claim 8, wherein, In each of the first scan stage configured to output the first scan signal of the (n-1)th horizontal line and the first scan stage configured to output the first scan signal of the (n+1)th horizontal line, the drain electrode of the pull-up transistor is configured to receive the first scan clock, the gate electrode of the first control transistor is configured to receive the second scan clock, and the gate electrode of the second control transistor is configured to receive the fourth scan clock. The fourth scan clock and the second scan clock have opposite phases.

10. The display device according to claim 8, wherein, The width of the lower portion of the second scan clock is set to be greater than the width of the higher portion of the carry signal, and The width of the high portion of the second scan clock is set to be smaller than the width of the low portion of the first scan clock.

11. The display device according to claim 8, wherein, The high portion of the carry signal is configured to coincide with the low portion of the third scan clock and the high portion of the first scan clock.

12. The display device according to claim 1, wherein, In the first scan stage configured to output the first scan signal of the nth horizontal line, the gate electrode of the second control transistor is configured to receive the second scan clock, the first scan clock and the second scan clock having opposite phases, and the first scan clock and the second scan clock having the same width of the high portion.

13. The display device according to claim 12, wherein, In each of the first scan stage configured to output the first scan signal of the (n-1)th horizontal line and the first scan stage configured to output the first scan signal of the (n+1)th horizontal line, the drain electrode of the pull-up transistor is configured to receive the first scan clock, the gate electrode of the first control transistor is configured to receive the second scan clock, and the gate electrode of the second control transistor is configured to receive the first scan clock.

14. The display device according to claim 12, wherein, The high portion of the carry signal is configured to coincide with the low portion of the second scan clock and the high portion of the first scan clock.

15. The display device according to claim 2, wherein, The second control transistor and the third control transistor comprise polysilicon.

16. The display device according to claim 15, wherein, The plurality of transistors in the pixel include transistors containing the polycrystalline silicon.

17. The display device according to claim 16, wherein, The second control transistor, the third control transistor, and the transistor containing the polysilicon in the pixel are P-type transistors.

18. The display device according to claim 1, wherein, The first transistor is configured to connect the gate electrode of the driving transistor among the plurality of transistors to the second electrode of the driving transistor in response to the first scan signal, or The first transistor is configured to send an initialization voltage to the gate electrode of the driving transistor in response to the first scan signal.

19. The display device according to any one of claims 1 to 18, wherein, The plurality of transistors in the pixel include a second transistor comprising the oxide semiconductor, and The display device further includes a second scan stage configured to apply a second scan signal to the second transistor, wherein the second scan stage is configured with the same structure as the first scan stage configured to output a first scan signal of the nth horizontal line.

20. A display panel, the display panel comprising: A pixel, the pixel comprising a light-emitting diode and a plurality of transistors configured to be electrically connected to the light-emitting diode; as well as A first scan driving circuit, comprising a scan stage configured to output a scan signal for the horizontal line of the display panel and to apply the scan signal to a first transistor among the plurality of transistors. The scan levels include: A pull-up transistor and a pull-down transistor, wherein the gate electrode of the pull-up transistor is connected to a first node, and the gate electrode of the pull-down transistor is connected to a second node; A transfer transistor, the transfer transistor being connected between the first node and the third node; A first control transistor and a second control transistor connected in parallel to each other, the first control transistor and the second control transistor having a first electrode configured to receive a carry signal and a second electrode connected to the third node; and A third control transistor and a fourth control transistor are connected in series with each other, the second node is located between the third control transistor and the fourth control transistor, and the third control transistor and the fourth control transistor have corresponding gate electrodes connected to the third node. Wherein, the gate electrode of the first control transistor is configured to receive a first scan clock, the drain electrode of the pull-up transistor is configured to receive a second scan clock, and the gate electrode of the second control transistor is configured to receive a third scan clock or the second scan clock.

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