Pixel circuit and display panel

Abstract

This invention discloses a pixel circuit and a display panel. The pixel circuit's light-emitting control module controls the light-emitting module to emit light according to a driving signal output by a driving module, based on signals on the light-emitting control signal line. A first initialization module writes an initialization voltage to the control terminal of the driving module based on signals on a first scan line. A compensation module's first terminal is connected to the first terminal of the driving module, and its second terminal is connected to the control terminal of the driving module via a leakage current suppression module. The compensation module performs threshold compensation on the driving module based on signals on a second scan line. The leakage current suppression module suppresses leakage current in the storage module. In this embodiment, the storage module leaks only through the leakage current suppression module, meaning there is only one leakage path. This reduces the number of leakage paths and the magnitude of the leakage current, which helps maintain the voltage stability of the driving module's control terminal and improves the flickering phenomenon caused by changes in the driving module's current.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit and a display panel. Background Technology

[0002] With the increasing demand for longer standby times in display products, low-frequency displays are becoming the trend. Existing display panels typically include pixel circuits, which contain driving transistors. These driving transistors are used to drive light-emitting devices to emit light, thereby enabling the display of the image.

[0003] Low-temperature polysilicon transistors (LTPS) have advantages such as high mobility, strong driving capability, and low manufacturing cost, making them widely used as driving transistors. However, LTPS have relatively large leakage current. In low-frequency displays, the time period for light emission within a frame becomes longer, which increases the leakage time of transistors in the pixel circuit. This can easily cause unstable gate voltage of the driving transistors in the pixel circuit, leading to screen flickering under low refresh rate operating conditions. Summary of the Invention

[0004] This invention provides a pixel circuit and a display panel to improve the voltage retention rate of the storage module and reduce the flickering phenomenon of the light-emitting module.

[0005] In a first aspect, embodiments of the present invention provide a pixel circuit, which includes: a driving module, a storage module, a compensation module, a first initialization module, a light-emitting module, a light-emitting control module, and a leakage current suppression module;

[0006] The storage module is connected to the control terminal of the drive module and is used to store the voltage of the control terminal of the drive module;

[0007] The light-emitting control module, the driving module, and the light-emitting module are connected between the first power line and the second power line. The light-emitting control module is used to control the light-emitting module to emit light according to the driving signal output by the driving module based on the signal on the light-emitting control signal line.

[0008] The first terminal of the first initialization module is connected to the initialization signal line, and the second terminal of the first initialization module is connected to the control terminal of the drive module through the leakage current suppression module. The first initialization module is used to write the initialization voltage provided by the initialization signal line to the control terminal of the drive module according to the signal on the first scan line.

[0009] The first end of the compensation module is connected to the first end of the drive module, and the second end of the compensation module is connected to the control end of the drive module through the leakage current suppression module. The compensation module is used to perform threshold compensation on the drive module according to the signal on the second scan line.

[0010] The leakage current suppression module is used to suppress leakage current in the storage module.

[0011] Optionally, at least one of the nodes of the internal devices of the first initialization module, the nodes of the internal devices of the leakage current suppression module, the nodes connected to the first initialization module, the nodes connected to the control terminal of the drive module, and the nodes connected to the compensation module is connected to a voltage stabilizing capacitor.

[0012] Optionally, the storage module includes a storage capacitor, and the capacitance value of the voltage regulator capacitor is smaller than the capacitance value of the storage capacitor.

[0013] Optionally, the leakage current suppression module includes a first transistor and a second transistor;

[0014] The first terminal of the first transistor is connected to the control terminal of the driving module, and the second terminal of the first transistor is connected to the second terminal of the first initialization module.

[0015] The first terminal of the second transistor is connected to the second terminal of the first transistor, and the second terminal of the second transistor is connected to the second terminal of the compensation module;

[0016] The gates of the first transistor and the second transistor are connected to a leakage control signal line.

[0017] Optionally, the light emission control module includes a first light emission control module and a second light emission control module;

[0018] The first light-emitting control module is connected between the first power line and the second end of the driving module, the second light-emitting control module is connected between the first end of the driving module and the first end of the light-emitting module, the second end of the light-emitting module is connected to the second power line, and the control terminals of the first light-emitting control module and the second light-emitting module are connected to the light-emitting control signal line.

[0019] Optionally, within a frame, the time interval of the pulses on the leakage control signal line is located within the time interval of the pulses on the light emission control signal line.

[0020] Optionally, the signal on the leakage control signal line and the signal on the light emission control signal line are opposite signals to each other.

[0021] Optionally, the pixel circuit further includes a data writing module and a second initialization module; the data writing module includes a third transistor, the driving module includes a fourth transistor; the compensation module includes a fifth transistor, the first initialization module includes a sixth transistor; the second initialization module includes a seventh transistor; the first light emission control module includes an eighth transistor, and the second light emission control module includes a ninth transistor.

[0022] The first terminal of the third transistor is connected to the data signal line, the second terminal of the third transistor is connected to the second terminal of the driving module, and the gate of the third transistor is connected to the second scan line.

[0023] The first terminal of the fourth transistor serves as the second terminal of the driving module, the second terminal of the fourth transistor serves as the first terminal of the driving module, and the gate of the fourth transistor serves as the control terminal of the driving module.

[0024] The first terminal of the fifth transistor serves as the first terminal of the compensation module, the second terminal of the fifth transistor serves as the second terminal of the compensation module, and the gate of the fifth transistor is connected to the second scan line;

[0025] The first terminal of the sixth transistor serves as the first terminal of the first initialization module, the second terminal of the sixth transistor serves as the second terminal of the first initialization module, and the gate of the sixth transistor is connected to the first scan line.

[0026] The first terminal of the seventh transistor is connected to the initialization signal line, the second terminal of the seventh transistor is connected to the first terminal of the light-emitting module, and the gate of the seventh transistor is connected to the third scan line;

[0027] The first terminal of the eighth transistor is connected to the first power supply line, the second terminal of the eighth transistor is connected to the first terminal of the fourth transistor, and the gate of the eighth transistor is connected to the light emission control signal line.

[0028] The first terminal of the ninth transistor is connected to the second terminal of the fourth transistor, the second terminal of the ninth transistor is connected to the first terminal of the light-emitting module, and the gate of the ninth transistor is connected to the light-emitting control signal line.

[0029] The first transistor and the sixth transistor are dual-gate transistors.

[0030] Optionally, the pixel circuit includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor;

[0031] The first terminal of the first capacitor is connected to the gate of the fourth transistor, the second terminal of the first capacitor is connected to the leakage control signal line, the first terminal of the second capacitor is connected to the second terminal of the sixth transistor, the second terminal of the second capacitor is connected to the initialization signal line, the first terminal of the third capacitor is connected to the second terminal of the second transistor, the second terminal of the third capacitor is connected to the initialization signal line, the first terminal of the fourth capacitor is connected to the dual-gate node of the sixth transistor, the second terminal of the fourth capacitor is connected to the initialization signal line, the first terminal of the fifth capacitor is connected to the initialization signal line, and the second terminal of the fifth capacitor is connected to the dual-gate node of the first transistor.

[0032] Secondly, embodiments of the present invention also provide a display panel, the display panel including the pixel circuit described in any of the first aspects.

[0033] This invention provides a pixel circuit and a display panel. The pixel circuit's storage module is connected to the control terminal of a driving module to store the voltage at the driving module's control terminal. A light-emitting control module, a driving module, and a light-emitting module are connected between a first power line and a second power line. The light-emitting control module controls the light-emitting module to emit light according to the driving signal output by the driving module, based on the signal on the light-emitting control signal line. A first initialization module is connected to the control terminal of the driving module via a leakage current suppression module, and is used to write an initialization voltage to the driving module's control terminal based on the signal on the first scan line. A compensation module's first terminal is connected to the first terminal of the driving module, and its second terminal is connected to the driving module's control terminal via the leakage current suppression module. The compensation module performs threshold compensation on the driving module based on the signal on the second scan line. The leakage current suppression module suppresses leakage current in the storage module. This invention suppresses leakage current in the storage module by setting a leakage current suppression module between the control terminal of the driving module and the common terminal of the compensation module and the first initialization module. Compared to existing technologies, where the storage module can leak through two paths—the compensation module and the first initialization module—the storage module in this embodiment of the invention only leaks through the leakage suppression module, meaning there is only one leakage path. This reduces the number of leakage paths and the magnitude of the leakage current, which helps maintain the stability of the voltage at the control terminal of the drive module, improves the voltage holding rate at the control terminal of the drive module, and alleviates the flickering phenomenon of the light-emitting module when emitting light caused by changes in the current of the drive module. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of an existing pixel circuit structure;

[0035] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0036] Figure 3This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0039] Figure 6 This is a timing diagram of a leakage current control signal line and a light emission control signal line provided in an embodiment of the present invention;

[0040] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0041] Figure 8 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0042] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0043] Figure 10 This is a simulation signal waveform diagram provided in an embodiment of the present invention;

[0044] Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0045] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0046] Figure 1 This is a schematic diagram of an existing pixel circuit. Figure 1As shown, the pixel driving circuit includes a driving transistor Mdr, a first switch M1, a second switch M2, a third switch M3, a fourth switch M4, a fifth switch M5, a sixth switch M6, a capacitor C0, and a light-emitting device D1. The driving transistors Mdr, M1, M2, M3, M4, M5, and M6 are exemplarily shown as P-type transistors. The first terminal of the fifth switch is connected to the reference voltage signal line Vref1, and the first terminal of the first switch M1 is connected to the data signal line Vdata. During the operation of the pixel driving circuit, in the light-emitting stage, the first scan signal provided by the first scan signal input terminal Scan1 is at a high level, the second scan signal provided by the second scan signal input terminal Scan2 is at a high level, and the light-emitting control signal provided by the light-emitting control signal input terminal E1 is at a low level. At this time, the third switch M3 and the fourth switch M4 are turned on, and the third switch M3 outputs the first power supply voltage provided by the first power supply line Vdd to the source of the driving transistor Mdr. The cathode of the light-emitting device D1 is electrically connected to the second power line Vss. At this time, the driving transistor Mdr provides driving current to the light-emitting device D1, causing it to emit light. During the light-emitting phase, the second switch M2 and the fifth switch M5 are turned off. However, leakage current still exists in the second switch M2 and the fifth switch M5. The two leakage paths cause the voltage at the gate of the driving transistor Mdr to decrease, which in turn causes a change in the driving current output by the driving transistor Mdr, resulting in the problem of flickering of the light-emitting device D1 when it emits light.

[0047] For the reasons stated above, embodiments of the present invention provide a pixel circuit. Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, with reference to... Figure 2 The pixel circuit includes: a driving module 100, a storage module 200, a compensation module 300, a first initialization module 400, a light-emitting module 500, a light-emitting control module 600, a leakage current suppression module 700, and a data writing module 800.

[0048] The storage module 200 is connected to the control terminal G of the drive module 100 and is used to store the voltage of the control terminal G of the drive module 100.

[0049] The light-emitting control module 600, the driving module 100, and the light-emitting module 500 are connected between the first power line Vdd and the second power line Vss. The light-emitting control module 600 is used to control the light-emitting module 500 to emit light according to the driving signal output by the driving module 100 based on the signal on the light-emitting control signal line EM.

[0050] The first terminal of the first initialization module 400 is connected to the initialization signal line Vref, and the second terminal of the first initialization module 400 is connected to the control terminal G of the drive module 100 through the leakage current suppression module 700. The first initialization module 400 is used to write the initialization voltage provided by the initialization signal line Vref to the control terminal G of the drive module 100 according to the signal on the first scan line S1.

[0051] The first end of the compensation module 300 is connected to the first end of the drive module 100, and the second end of the compensation module 300 is connected to the control terminal G of the drive module 100 through the leakage current suppression module 700. The compensation module 300 is used to perform threshold compensation on the drive module 100 according to the signal on the second scan line S2.

[0052] The leakage current suppression module 700 is used to suppress leakage current in the storage module 200.

[0053] The pixel circuit also includes a second initialization module 900. The first end of the data writing module 800 is connected to the data signal line Vdata, and the second end is connected to the second end of the driving module 100. The control end of the data writing module 800 is connected to the second scan line S2. The data writing module 800 is used to write the data voltage provided by the data signal line Vdata to the driving module 100 according to the signal on the second scan line S2. That is, the data writing module 800 can be turned on or off according to the signal on the second scan line S2. When on, the data voltage provided by the data signal line Vdata is transmitted to the driving module 100 through the on-state data writing module 800, and then written to the control end of the driving module via the transmission path of the driving module, compensation module, and leakage suppression module. The first end of the second initialization module 900 is connected to the initialization signal line Vref, and the second end is connected to the first end of the light-emitting module 500. The second initialization module 900 is used to write the initialization voltage provided by the initialization signal line Vref to the first end of the light-emitting module 500 according to the signal on the third scan line S3.

[0054] For example, the light-emitting module 500 can be an organic light-emitting diode (OLED), with the anode of the OLED serving as the first terminal of the light-emitting module 500 and the cathode of the OLED serving as the second terminal of the light-emitting module 500. The light-emitting module 500 emits light according to the driving signal output by the driving module 100, wherein the driving signal can be a driving current output by the driving module 100 based on the voltage of its control terminal G and second terminal.

[0055] Specifically, the pixel circuit operation can include three stages. In the first stage (initialization stage), the signal on the first scan line S1 controls the first initialization module 400 to be turned on. The initialization voltage provided by the initialization signal line Vref is written to the control terminal of the driving module 100 through the first initialization module 400 and the leakage suppression module 700, thus initializing the control terminal G of the driving module 100 in the first stage. In the second stage (data voltage writing and threshold compensation stage), the signal transmitted by the first scan line S1 controls the first initialization module 400 to be turned off, and the signal on the second scan line S2 controls the data writing module 800 and the compensation module 300 to be turned on. The data voltage provided by the data signal line Vdata is written to the control terminal G of the driving module 100 through the data writing module 800, the driving module 100, the compensation module 300, and the leakage suppression module 700. Since the compensation module 300 can compensate for the threshold of the driving module 100, the voltage at the control terminal of the driving module 100 can include the voltage associated with the data voltage and the threshold voltage, thus realizing the writing of the data voltage and threshold compensation of the driving module 100. Optionally, the signal of the third scan line S3 can be the same as the signal of the second scan line S2. In the second stage, the signal on the third scan line S3 controls the second initialization module 900 to be turned on. The initialization voltage provided by the initialization signal line Vref is written to the first terminal of the light-emitting module 500 through the second initialization module 900. The first terminal of the light-emitting module 500 is initialized in the second stage to avoid the influence of residual charge on the display effect. In the third stage (light-emitting stage), the signal on the first scan line S1 controls the first initialization module 400 to be turned off, the signal on the second scan line S2 controls the data writing module 800 and the compensation module 300 to be turned off, the signal on the third scan line S3 controls the second initialization module 900 to be turned off, and the signal on the light-emitting control signal line EM controls the light-emitting control module 600 to be turned on. The light-emitting control module 600 transmits the first power supply voltage on the first power supply line Vdd to the second terminal of the driving module 100. The driving module 100 outputs a driving signal to drive the light-emitting module 500 to emit light.

[0056] This embodiment suppresses leakage current in the storage module by setting a leakage current suppression module between the control terminal of the driving module and the common terminal of the compensation module and the first initialization module. Compared with the prior art, where the storage module can leak current through two paths, the compensation module and the first initialization module, the storage module in this embodiment only leaks current through the leakage current suppression module, i.e., there is only one leakage path. This reduces the number of leakage paths and the magnitude of the leakage current, which helps maintain the stability of the voltage at the control terminal of the driving module, improves the voltage holding rate of the control terminal of the driving module, and alleviates the flickering phenomenon of the light-emitting module when emitting light caused by changes in the current of the driving module.

[0057] Figure 3This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 3 Optionally, at least one of the nodes of the internal devices of the first initialization module 400, the nodes of the internal devices of the leakage current suppression module 700, the nodes connected to the first initialization module 400, the nodes connected to the control terminal G of the drive module 100, and the nodes connected to the compensation module 300 is connected to a voltage stabilizing capacitor.

[0058] For example, in this embodiment, the pixel circuit includes two voltage-stabilizing capacitors: a first voltage-stabilizing capacitor C1 and a second voltage-stabilizing capacitor C2. The control terminal of the leakage current suppression module 700 is connected to the leakage current control signal line EMB. One end of the first voltage-stabilizing capacitor C1 is connected to the control terminal G of the driving module 100, and the other end of the first voltage-stabilizing capacitor C2 is connected to the leakage current control signal line EMB. One end of the second voltage-stabilizing capacitor C2 is connected to node N1 of the internal device of the leakage current suppression module 700, and the other end of the second voltage-stabilizing capacitor C2 is connected to the initialization signal line Vref. The leakage current suppression module 700 may include a transistor, which may be a dual-gate transistor, so node N1 of the internal device of the leakage current suppression module 700 may be a dual-gate node of the dual-gate transistor.

[0059] The first voltage regulator capacitor C1 can stabilize the voltage of the control terminal G of the drive module 100, making the voltage of the control terminal G less susceptible to the influence of other signal jumps. The second voltage regulator capacitor C2 can stabilize the voltage at node N1 of the internal device of the leakage current suppression module 700, making the voltage at node N1 of the internal device of the leakage current suppression module 700 less susceptible to the influence of other signal jumps. When the leakage current suppression module 700 is turned on, the voltage at the control terminal G of the drive module 100 is equal to the voltage at node N1 of the internal device of the leakage current suppression module 700. After the leakage current suppression module 700 is turned off, the first voltage stabilizing capacitor C1 and the second voltage stabilizing capacitor C2 maintain the voltage at the control terminal G equal to the voltage at node N1 of the internal device of the leakage current suppression module 700. The smaller the voltage difference between the control terminal G of the drive module 100 and node N1 of the internal device of the leakage current suppression module 700, the smaller the leakage current of the leakage current suppression module 700. Therefore, by setting the first voltage stabilizing capacitor C1 and the second voltage stabilizing capacitor C2, the voltage stability of the control terminal of the drive module 100 can be maintained, the voltage holding rate of the control terminal G of the drive module 100 can be improved, the flickering phenomenon when the light-emitting module 500 emits light can be improved, and the display quality can be improved.

[0060] Continue to refer to Figure 3 Optionally, the storage module 200 includes a storage capacitor Cst, and the capacitance value of the voltage regulator capacitor is smaller than the capacitance value of the storage capacitor Cst.

[0061] The Zener capacitor differs from the storage capacitor Cst. The storage capacitor Cst needs to store the voltage at the control terminal of the drive module 100, therefore its capacitance value is relatively large. The Zener capacitor, however, is used to stabilize the voltage at the node it is connected to, thereby reducing leakage current. Therefore, the Zener capacitor's capacitance value can be smaller, even smaller than that of the storage capacitor Cst. The smaller capacitance value of the Zener capacitor allows for a smaller area of ​​its two plates, simplifying its layout in the circuit.

[0062] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 4 Optionally, the leakage current suppression module 700 includes a first transistor T1 and a second transistor T2;

[0063] The first terminal of the first transistor T1 is connected to the control terminal G of the drive module 100, and the second terminal of the first transistor T1 is connected to the second terminal of the first initialization module 400.

[0064] The first terminal of the second transistor T2 is connected to the second terminal of the first transistor T1, and the second terminal of the second transistor T2 is connected to the second terminal of the compensation module 300.

[0065] The gate of the first transistor T1 and the gate of the second transistor T2 are connected to the leakage control signal line EMB.

[0066] For example, both the first transistor T1 and the second transistor T2 are P-type transistors. When the leakage control signal line EMB is high, the first transistor T1 and the second transistor T2 are turned off; when the leakage control signal line EMB is low, the first transistor T1 and the second transistor T2 are turned on. In the first stage of pixel circuit operation, the leakage control signal line EMB is low, the first transistor T1 and the second transistor T2 are turned on, and the initialization voltage on the initialization signal line Vref is written to the control terminal G of the driving module 100 through the turned-on first initialization module 400 and the first transistor T1, thereby initializing the driving module 100. In the second stage, the data voltage on the data signal line Vdata is written to the control terminal of the driving module 100 through the turned-on data writing module 800, the driving module 100, the compensation module 300, the second transistor T2, and the first transistor T1, thereby writing the data voltage and threshold compensation.

[0067] In this embodiment, the control terminal G of the driving module 100 in the pixel circuit has only one leakage path, the first transistor T1, compared to... Figure 1The pixel circuit has two leakage paths, the second switch M2 and the fifth switch M5. In this embodiment, the pixel circuit reduces the number of leakage paths, thereby reducing the magnitude of leakage current. This reduces the voltage variation of the control terminal G of the driving module 100, making the voltage of the control terminal G of the driving module 100 more stable. This reduces the brightness decay of the light-emitting module 500 within one frame, thereby improving the flickering phenomenon of the light-emitting module 500 and improving the display quality.

[0068] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 5 Optionally, the light emission control module 600 includes a first light emission control module 610 and a second light emission control module 620;

[0069] The first light-emitting control module 610 is connected between the first power line Vdd and the second end of the driver module 100. The second light-emitting control module 620 is connected between the first end of the driver module 100 and the first end of the light-emitting module 500. The second end of the light-emitting module 500 is connected to the second power line Vss. The control terminals of the first light-emitting control module 610 and the second light-emitting control module 620 are connected to the light-emitting control signal line EM.

[0070] In the first and second stages of the pixel circuit, the first light-emitting control module 610 and the second light-emitting control module 620 are turned off under the control of the light-emitting control signal line EM. In the third stage, the first light-emitting control module 610 and the second light-emitting control module 620 are turned on under the control of the light-emitting control signal line EM. The first power supply voltage provided by the first power supply line Vdd is written to the second terminal of the driving module 100 through the first light-emitting control module 610. The driving module 100 drives the light-emitting module 500 to emit light according to the voltage of its control terminal G and the voltage of its second terminal.

[0071] Figure 6 A timing diagram of a leakage current control signal line and a light emission control signal line provided in an embodiment of the present invention. Figure 6 The timing diagram shown can be applied to Figure 5 The pixel circuit shown. (Reference) Figure 5 and Figure 6 Optionally, within a frame, the time interval of the pulse of the signal on the leakage control signal line EMB is within the time interval of the pulse of the signal on the light emission control signal line EM.

[0072] For example, the leakage current suppression module 700 is turned on when the signal on the leakage current control signal line EMB is low and turned off when it is high. The light emission control module 600 is turned on when the signal on the light emission control signal line EM is low and turned off when it is high. In the first stage t1 and the second stage t2, when the signal on the light emission control signal line EM is high, the light emission control module 600 is turned off, and when the signal on the leakage current control signal line EMB is low, the leakage current suppression module 700 is turned on. This allows the initialization voltage to be written to the control terminal G of the drive module 100 through the leakage current suppression module 700 in the first stage t1, and the data voltage to be written to the control terminal G of the drive module 100 through the leakage current suppression module 700 in the second stage t2. The conduction time interval of the leakage current suppression module 700 is located within the off-time interval of the light-emitting control module 600. This ensures that during the first stage t1 and the second stage t2 of the leakage current suppression module 700's conduction, the light-emitting control module 600 is in an off state. This prevents the light-emitting control module 600 from conducting during the first stage t1 and the second stage t2, which would cause the light-emitting module 500 to conduct. If this were to happen, and the control terminal G of the driver module 100 had not yet completed initialization or data writing and threshold compensation, the light-emitting module 500 would be lit up, affecting the display quality. Therefore, the pulse time interval of the signal on the leakage current control signal line EMB is located within the pulse time interval of the signal on the light-emitting control signal line EM. This ensures that the light-emitting module 500 is lit only after the driver module has completed initialization, data writing, and threshold compensation, thus improving the display quality.

[0073] Continue to refer to Figure 5 and Figure 6 Optionally, the signal on the leakage control signal line EMB and the signal on the light control signal line EM are opposite signals.

[0074] For example, both the leakage current suppression module 700 and the light emission control module 600 are P-type transistors. In the first stage t1, the signal on the leakage current control signal line EMB is low, and the signal on the light emission control signal line EM is high. The leakage current suppression module 700 is turned on, and the light emission control module 600 is turned off. The initialization voltage on the initialization signal line Vref is written to the control terminal G of the driver module 100 through the leakage current suppression module 700. In the second stage t2, the signal on the leakage current control signal line EMB is low, and the signal on the light emission control signal line EM is high. The leakage current suppression module 700 is turned on, and the light emission control module 600 is turned off. The data voltage on the data signal line Vdata is written to the control terminal G of the driver module 100 through the leakage current suppression module 700. In the third stage t3, the signal on the leakage control signal line EMB is high, and the signal on the light emission control signal line EM is low. The leakage suppression module 700 is turned off, and the light emission control module 600 is turned on. The first power supply voltage on the first power supply line Vdd is transmitted to the second terminal of the driver module 100 through the first light emission control module 610. The driver module 100 drives the light emission module 500 to emit light according to the voltage at its control terminal G and the voltage at its second terminal. The light emission control signal line EM is usually connected to the light emission control driver circuit located in the left and right bezel areas of the display panel. The light emission control driver circuit can be composed of cascaded shift registers. The signal on the leakage control signal line EMB and the signal on the light emission control signal line EM are inverted signals. It is only necessary to set an inverter at the output terminal of the light emission control driver circuit. The signal output by the light emission control driver circuit is inverted by the inverter and then output to the leakage control signal line EMB. There is no need to design a complex scanning circuit composed of shift registers for the leakage control signal line EMB. This can reduce the circuit components in the bezel area of ​​the display panel and make it easier to achieve a narrow bezel design for the display panel.

[0075] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 7 Optionally, the pixel circuit also includes a data writing module 800 and a second initialization module 900; the data writing module includes a third transistor T3, the driving module 100 includes a fourth transistor T4; the compensation module 300 includes a fifth transistor T5, the first initialization module 400 includes a sixth transistor T6; the second initialization module 900 includes a seventh transistor T7; the first light emission control module 610 includes an eighth transistor T8, and the second light emission control module 620 includes a ninth transistor T9;

[0076] The first terminal of the third transistor T3 is connected to the data signal line Vdata, the second terminal of the third transistor T3 is connected to the second terminal of the drive module 100, and the gate of the third transistor T3 is connected to the second scan line S2.

[0077] The first terminal of the fourth transistor T4 serves as the second terminal of the driving module 100, the second terminal of the fourth transistor T4 serves as the first terminal of the driving module 100, and the gate of the fourth transistor T4 serves as the control terminal G of the driving module 100.

[0078] The first terminal of the fifth transistor T5 serves as the first terminal of the compensation module 300, the second terminal of the fifth transistor T5 serves as the second terminal of the compensation module 300, and the gate of the fifth transistor T5 is connected to the second scan line S2.

[0079] The first terminal of the sixth transistor T6 serves as the first terminal of the first initialization module 400, the second terminal of the sixth transistor T6 serves as the second terminal of the first initialization module 400, and the gate of the sixth transistor T6 is connected to the first scan line S1.

[0080] The first terminal of the seventh transistor T7 is connected to the initialization signal line Vref, the second terminal of the seventh transistor T7 is connected to the first terminal of the light-emitting module 500, and the gate of the seventh transistor T7 is connected to the third scan line S3.

[0081] The first terminal of the eighth transistor T8 is connected to the first power supply line Vdata, the second terminal of the eighth transistor T8 is connected to the first terminal of the fourth transistor T4, and the gate of the eighth transistor T8 is connected to the light emission control signal line EM.

[0082] The first terminal of the ninth transistor T9 is connected to the second terminal of the fourth transistor T4, the second terminal of the ninth transistor T9 is connected to the first terminal of the light-emitting module 500, and the gate of the ninth transistor T9 is connected to the light-emitting control signal line EM.

[0083] The first transistor T1 and the sixth transistor T6 are dual-gate transistors.

[0084] Specifically, the first transistor T1 includes a first dual-gate transistor T11 and a second dual-gate transistor T12, and the sixth transistor T6 includes a third dual-gate transistor T61 and a fourth dual-gate transistor T62. The first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, eighth transistor T8, and ninth transistor T9 can be either P-type or N-type transistors; this embodiment does not impose a specific limitation. The example described uses P-type transistors as an illustration.

[0085] Figure 8 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention. Figure 8 The timing diagram shown can be applied to Figure 7 The pixel circuit will be explained using the example of the third scan line S3 and the second scan line S2 having the same signal. (Reference) Figure 7 and Figure 8The first stage t1 includes the second sub-stage t02 and the third sub-stage t03, the second stage t2 includes the fourth sub-stage t04, and the third stage t3 includes the sixth sub-stage t06.

[0086] In the first sub-stage t01, the signal on the light emission control signal line EM rises to a high level, and the eighth transistor T8 and the ninth transistor T9 are turned off. In the second sub-stage t02, the signal on the leakage current control signal line EMB drops to a low level, and the first transistor T1 and the second transistor T2 are turned on. In the third sub-stage t03, the signal on the first scan line S1 is low, and the sixth transistor T6 is turned on. In the third sub-stage t03, the initialization voltage provided by the initialization signal line Vref is transmitted to the gate of the fourth transistor T4 through the sixth transistor T6 and the first transistor T1, thereby resetting the gate of the fourth transistor T4. After the reset is complete, the signal on the first scan line S1 rises to a high level, and the sixth transistor T6 is turned off. In the first stage t1, the signals on the light emission control signal line EM and the second scan line S2 are high, and the third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are in a turned-off state.

[0087] In the fourth sub-stage t04, the signal on the second scan line S2 is at a low level, the third transistor T3 and the fifth transistor T5 are turned on, the signal on the leakage control signal line EMB is at a low level, the first transistor T1 and the second transistor T2 are turned on, and the data voltage on the data signal line Vdata is written to the gate of the fourth transistor T4 through the third transistor T3, the fourth transistor T4, the fifth transistor T5, the second transistor T2 and the first transistor T1, realizing the writing of the data voltage to the gate of the fourth transistor T4 and the compensation of the threshold voltage of the fourth transistor T4. In the fourth sub-stage t04, the signal on the third scan line S3 is the same as the signal on the second scan line S2, which is at a low level, the seventh transistor T7 is turned on, and the initialization voltage provided by the initialization signal line Vref is transmitted to the first terminal of the light-emitting module 500 through the seventh transistor T7 to reset the first terminal of the light-emitting module 500, thereby avoiding the influence of residual charge on the first terminal of the light-emitting module 500 on the display effect.

[0088] In the fifth sub-stage t05, the signal on the leakage control signal line EMB rises to a high level, and the first transistor T1 and the second transistor T2 are turned off. In the sixth sub-stage t06, the signals on the first scan line S1 and the second scan line S2 are at a high level, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off, the signal on the light emission control signal line EM is at a low level, the eighth transistor T8 and the ninth transistor T9 are turned on, and the first power supply voltage on the first power supply line Vdd is transmitted to the first electrode of the fourth transistor T4 through the eighth transistor T8. The fourth transistor T4 drives the light emission module 500 to emit light according to the voltage of its gate and the voltage of its first electrode.

[0089] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 9 Optionally, the pixel circuit also includes a first capacitor C11, a second capacitor C12, a third capacitor C13, a fourth capacitor C14, and a fifth capacitor C15.

[0090] The first terminal of the first capacitor C11 is connected to the gate of the fourth transistor T4, and the second terminal of the first capacitor C11 is connected to the leakage control signal line EMB. The first terminal of the second capacitor C12 is connected to the second terminal of the sixth transistor T6, and the second terminal of the second capacitor C12 is connected to the initialization signal line Vref. The first terminal of the third capacitor C13 is connected to the second terminal N3 of the second transistor T2, and the second terminal of the third capacitor C13 is connected to the initialization signal line Vref. The first terminal of the fourth capacitor C14 is connected to the dual-gate node N2 of the sixth transistor T6, and the second terminal of the fourth capacitor C14 is connected to the initialization signal line Vref. The first terminal of the fifth capacitor C15 is connected to the initialization signal line Vref, and the second terminal of the fifth capacitor C15 is connected to the dual-gate node N1 of the first transistor T1.

[0091] During the light-emitting stage, by adjusting the values ​​of the third capacitor C13 and the fourth capacitor C14, the voltage of the second terminal N3 of the second transistor T2 is made greater than the voltage of the first terminal of the second transistor T2, and the voltage of the first terminal of the second transistor T2 is made greater than the voltage of the dual-gate node N2 of the sixth transistor T6. This causes the second terminal N3 of the second transistor T2 to charge the first terminal of the second transistor T2, and the first terminal of the second transistor T2 to leak current into the dual-gate node N2 of the sixth transistor T6. This achieves a complementary charging and leakage process for the first terminal of the second transistor T2, balancing the potential of the first terminal of the second transistor T2, reducing the leakage current of the first terminal of the second transistor T2, improving the voltage holding rate of the control terminal G of the driving module 100 in the pixel circuit, improving the flickering phenomenon of the light-emitting module 500 under low-frequency driving, and improving the display quality.

[0092] The first capacitor C11, the second capacitor C12, and the fifth capacitor C15 can stabilize the voltage at the gate of the fourth transistor T4, the dual-gate node N1 of the first transistor T1, and the second terminal N3 of the second transistor T2. Since the voltages at the gate of the fourth transistor T4, the dual-gate node N1 of the first transistor T1, and the second terminal N3 of the second transistor T2 are equal when the first transistor T1 and the second transistor T2 are turned on, during the light-emitting stage, after the first transistor T1 and the second transistor T2 are turned off, the first capacitor C11, the second capacitor C12, and the fifth capacitor C15 can maintain the voltages at the gate of the fourth transistor T4, the dual-gate node N1 of the first transistor T1, and the second terminal N3 of the second transistor T2 equal. This reduces the leakage current of the first transistor T1, decreases the magnitude of the leakage current of the first transistor T1, maintains the stability of the voltage at the gate of the fourth transistor T4, improves the voltage retention rate of the control terminal G of the driving module 100 in the pixel circuit, improves the flickering phenomenon of the light-emitting module 500 under low-frequency driving, and improves the display quality.

[0093] Figure 10 A simulated signal waveform diagram provided in an embodiment of the present invention. Figure 10 for Figure 9 The waveform diagram corresponding to the operation of the pixel circuit shown is from... Figure 10 It can be seen that in the sixth sub-stage t06, the voltage of the control terminal G (gate of the fourth transistor T4) of the driving module 100 and the voltage of the second terminal N3 of the second transistor T2 both remain stable. This indicates that the first capacitor C11, the second capacitor C12, the third capacitor C13, the fourth capacitor C14 and the fifth capacitor C15 can maintain the voltage stability at the gate of the fourth transistor T4, improve the voltage holding rate of the control terminal G of the driving module 100 in the pixel circuit, improve the flickering phenomenon of the light-emitting module under low-frequency driving, and improve the display quality.

[0094] The present invention also provides a display panel, which includes the pixel circuit of any of the above.

[0095] This invention also provides a display device. Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, with reference to... Figure 11 The display device 01 includes the aforementioned display panel 02. The display device 01 can be... Figure 11 The mobile phone shown can also be a computer, television, smart wearable display device, etc., and the embodiments of the present invention do not make any special limitations on this.

[0096] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, include: The module includes a driver module, a storage module, a compensation module, a first initialization module, a light-emitting module, a light-emitting control module, and a leakage current suppression module. The storage module is connected to the control terminal of the drive module and is used to store the voltage of the control terminal of the drive module; The light-emitting control module, the driving module, and the light-emitting module are connected between the first power line and the second power line. The light-emitting control module is used to control the light-emitting module to emit light according to the driving signal output by the driving module based on the signal on the light-emitting control signal line. The first terminal of the first initialization module is connected to the initialization signal line, and the second terminal of the first initialization module is connected to the control terminal of the drive module through the leakage current suppression module. The first initialization module is used to write the initialization voltage provided by the initialization signal line to the control terminal of the drive module according to the signal on the first scan line. The first end of the compensation module is connected to the first end of the drive module, and the second end of the compensation module is connected to the control end of the drive module through the leakage current suppression module. The compensation module is used to perform threshold compensation on the drive module according to the signal on the second scan line. The leakage current suppression module is used to suppress leakage current in the storage module; The leakage current suppression module includes a first transistor and a second transistor; The first terminal of the first transistor is connected to the control terminal of the driving module, and the second terminal of the first transistor is connected to the second terminal of the first initialization module. The first terminal of the second transistor is connected to the second terminal of the first transistor, and the second terminal of the second transistor is connected to the second terminal of the compensation module; The gates of the first transistor and the second transistor are connected to a leakage control signal line; The first initialization module includes a sixth transistor, the first terminal of the sixth transistor serves as the first terminal of the first initialization module, the second terminal of the sixth transistor serves as the second terminal of the first initialization module, and the gate of the sixth transistor is connected to the first scan line. The first transistor and the sixth transistor are dual-gate transistors. When the signal of the leakage control signal line is high, the first transistor and the second transistor are turned off; when the signal of the leakage control signal line is low, the first transistor and the second transistor are turned on. The pixel circuit also includes a first capacitor, with a first end of the first capacitor connected to the control terminal of the driving module and a second end of the first capacitor connected to the leakage control signal line. The pixel circuit also includes a third capacitor, a fourth capacitor, and a fifth capacitor. The first end of the third capacitor is connected to the second terminal of the second transistor, and the second end of the third capacitor is connected to the initialization signal line. The first end of the fourth capacitor is connected to the dual-gate node of the sixth transistor, and the second end of the fourth capacitor is connected to the initialization signal line. During the light-emitting stage, by adjusting the size of the third capacitor and the fourth capacitor, the voltage of the second electrode of the second transistor is made greater than the voltage of the first electrode of the second transistor, and the voltage of the first electrode of the second transistor is made greater than the voltage of the dual-gate node of the sixth transistor, thereby charging the second electrode of the second transistor to the first electrode of the second transistor, and leaking current from the first electrode of the second transistor to the dual-gate node of the sixth transistor. The first end of the fifth capacitor is connected to the initialization signal line, and the second end of the fifth capacitor is connected to the dual-gate node of the first transistor. The light emission control module is turned on when the signal on the light emission control signal line is low and turned off when the signal is high. The signal on the leakage control signal line is the opposite of the signal on the light emission control signal line; The pixel circuit also includes a data writing module, which includes a third transistor. The first terminal of the third transistor is connected to a data signal line, the second terminal of the third transistor is connected to the second terminal of the driving module, and the gate of the third transistor is connected to a second scan line. The time it takes for the signal on the leakage control signal line to rise from a low level to a high level lags behind the time it takes for the signal on the second scan line to jump from an effective potential to an invalid potential. The effective potential is the potential that controls the data writing module to be turned on, and the invalid potential is the potential that controls the data writing module to be turned off.

2. The pixel circuit according to claim 1, characterized in that, The node connected to the first initialization module is equipped with a voltage stabilizing capacitor.

3. The pixel circuit according to claim 2, characterized in that, The storage module includes a storage capacitor, and the capacitance value of the voltage regulator capacitor is smaller than the capacitance value of the storage capacitor.

4. The pixel circuit according to claim 1, characterized in that, The light-emitting control module includes a first light-emitting control module and a second light-emitting control module; The first light-emitting control module is connected between the first power line and the second end of the driving module, the second light-emitting control module is connected between the first end of the driving module and the first end of the light-emitting module, the second end of the light-emitting module is connected to the second power line, and the control terminals of the first light-emitting control module and the second light-emitting module are connected to the light-emitting control signal line.

5. The pixel circuit according to claim 4, characterized in that, Within a frame, the time interval of the pulses on the leakage control signal line is within the time interval of the pulses on the light emission control signal line.

6. The pixel circuit according to claim 4, characterized in that, It also includes a second initialization module; the driving module includes a fourth transistor; the compensation module includes a fifth transistor; the second initialization module includes a seventh transistor; the first light-emitting control module includes an eighth transistor; and the second light-emitting control module includes a ninth transistor. The first terminal of the fourth transistor serves as the second terminal of the driving module, the second terminal of the fourth transistor serves as the first terminal of the driving module, and the gate of the fourth transistor serves as the control terminal of the driving module. The first terminal of the fifth transistor serves as the first terminal of the compensation module, the second terminal of the fifth transistor serves as the second terminal of the compensation module, and the gate of the fifth transistor is connected to the second scan line; The first terminal of the seventh transistor is connected to the initialization signal line, the second terminal of the seventh transistor is connected to the first terminal of the light-emitting module, and the gate of the seventh transistor is connected to the third scan line; The first terminal of the eighth transistor is connected to the first power supply line, the second terminal of the eighth transistor is connected to the first terminal of the fourth transistor, and the gate of the eighth transistor is connected to the light emission control signal line. The first terminal of the ninth transistor is connected to the second terminal of the fourth transistor, the second terminal of the ninth transistor is connected to the first terminal of the light-emitting module, and the gate of the ninth transistor is connected to the light-emitting control signal line.

7. The pixel circuit according to claim 6, characterized in that, Including the second capacitor; The first terminal of the second capacitor is connected to the second terminal of the sixth transistor, and the second terminal of the second capacitor is connected to the initialization signal line.

8. A display panel, characterized in that, Includes the pixel circuit described in any one of claims 1-7.

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