Method and system for implementing stacked chip high dynamic range image sensor

Abstract

The present application relates to a method and system for implementing a stacked chip high dynamic range image sensor. The method of implementing a stacked chip HDR algorithm in an image sensor begins by capturing a first frame having a first exposure time and a second frame having a second exposure time that is longer or shorter than the first exposure time using a pixel array. The pixel array is disposed in a first semiconductor die and is divided into pixel subarrays. Each pixel subarray is arranged into a pixel group, and each pixel group is arranged into a pixel cell array. A readout circuit disposed in a second semiconductor die acquires image data for the first frame and the second frame. Each pixel subarray is coupled to a corresponding readout circuit via a corresponding one of a plurality of conductors. The ADC circuit converts the image data from the first frame and the second frame into a first ADC output and a second ADC output. Functional logic located on the second semiconductor die sums the first ADC output and the second ADC output to produce a final ADC output. The present invention also describes other embodiments.

Description

[0001] This application is a divisional application of the Chinese invention patent application entitled “Method and System for Implementing Stacked Chip High Dynamic Range Image Sensor,” application number 201610344265.2, and filing date May 23, 2016. Technical Field

[0002] Examples of the present invention generally relate to image sensors. More particularly, examples of the present invention relate to methods and systems for implementing a stacked-die high dynamic range image sensor. Background Art

[0003] High-speed image sensors are widely used in many applications across diverse fields, including automotive, machine vision, and professional videography. The technology used to manufacture image sensors, and in particular complementary metal oxide semiconductor (CMOS) image sensors, continues to advance at a rapid pace. For example, the demand for higher frame rates and lower power consumption has driven the further miniaturization and integration of these image sensors.

[0004] One way to increase the frame rate of a CMOS image sensor is to increase the number of readout circuits operating in parallel. In conventional image sensors, a column of pixels in a pixel array can share a single readout circuit. In other conventional examples, a column of pixel cells in a pixel array can share multiple readout circuits. These solutions offer higher frame rates but require more silicon area, which does not contribute to the miniaturization of silicon image sensors.

[0005] In addition, many applications require high dynamic range (HDR) to capture images from 10 -1 Lux (for night vision) to 10 5 The high dynamic range (HDR) corresponds to a dynamic range of at least 100 dB (dB) for scene illumination in lux (for bright sunlight or direct headlight conditions). Current charge-coupled device (CCD) and CMOS sensors cannot achieve this range due to full-well limitations and noise floor limitations (which are typically around 60-70 dB). High dynamic range sensor designs are needed to extend the application of CMOS image sensors into the high dynamic range domain. Summary of the Invention

[0006] In one aspect, the present invention provides a method for implementing a stacked-die high dynamic range (HDR) algorithm in an image sensor, comprising: capturing, by a pixel array, a first frame having a first exposure time and a second frame having a second exposure time, wherein the first exposure time is longer or shorter than the second exposure time, wherein the pixel array is disposed in a first semiconductor die, wherein the pixel array is divided into a plurality of pixel subarrays, wherein each of the plurality of pixel subarrays is arranged into a plurality of pixel groups, and wherein each of the plurality of pixel groups is arranged into a pixel cell of a pxq array; acquiring, by a plurality of readout circuits, image data of the first frame and image data of the second frame, wherein the plurality of readout circuits are included in a readout circuit disposed in a second semiconductor die, wherein each of the plurality of pixel subarrays is coupled to a corresponding one of the plurality of readout circuits by a corresponding one of a plurality of conductors; converting, by a plurality of ADC circuits included in the readout circuit, the image data of the first frame from analog to digital to obtain a first ADC output and converting the image data of the second frame from analog to digital to obtain a second ADC output, respectively; and summing, by a function logic, the first ADC output and the second ADC output to generate a final ADC output, wherein the function logic is disposed in the second semiconductor die.

[0007] In another aspect, the present invention provides a stacked chip high dynamic range (HDR) imaging system comprising: a pixel array disposed in a first semiconductor die, wherein the pixel array is divided into a plurality of pixel sub-arrays, wherein each of the plurality of pixel sub-arrays is arranged into a plurality of pixel groups, and wherein each of the plurality of pixel groups is arranged into a pixel unit of a pxq array, wherein the pixel array captures a first frame having a first exposure time and a second frame having a second exposure time, wherein the first exposure time is longer or shorter than the second exposure time; and a plurality of readout circuits included in readout circuits disposed in a second semiconductor die, wherein the plurality of pixel sub-arrays are arranged into a plurality of pixel groups. Each of the columns is coupled to a corresponding one of the multiple readout circuits through a corresponding one of a plurality of conductors, wherein the multiple readout circuits acquire image data of the first frame and image data of the second frame, wherein the multiple readout circuits respectively include an analog-to-digital (ADC) circuit that converts the image data of the first frame from analog to digital to obtain a first ADC output and converts the image data of the second frame from analog to digital to obtain a second ADC output; and functional logic coupled to the readout circuit to sum the first ADC output and the second ADC output to produce a final ADC output, wherein the functional logic is disposed in the second semiconductor die.

[0008] On the other hand, the present invention provides a method for implementing a stacked-chip high dynamic range (HDR) algorithm in an image sensor, comprising: capturing a first frame with a first exposure time by a pixel array, wherein the pixel array is disposed in a first semiconductor die, wherein the pixel array is divided into a plurality of pixel sub-arrays, wherein each of the plurality of pixel sub-arrays is arranged into a plurality of pixel groups, and wherein each of the plurality of pixel groups is arranged into a pixel unit of a pxq array; converting image data of the first frame from analog to digital to obtain a first ADC output by a plurality of ADC circuits included in a readout circuit, wherein the plurality of readout circuits are included in a readout circuit disposed in a second semiconductor die, wherein the plurality of pixel sub-arrays in the plurality of pixel sub-arrays are each arranged into a plurality of pixel groups, and wherein the plurality of pixel groups in the plurality of pixel groups are each arranged into a pixel unit of a pxq array; each coupled to a corresponding one of the plurality of readout circuits by a corresponding one of a plurality of conductors; storing the first ADC output; capturing a second frame having a second exposure time by the pixel array, wherein the first exposure time is longer or shorter than the second exposure time; converting image data of the second frame from analog to digital by the ADC circuit to obtain a second ADC output; reading out the second ADC output and summing the second ADC output with the stored first ADC output by function logic to produce a final ADC output, wherein the function logic is disposed in the second semiconductor die; storing the final ADC output in a frame buffer included in the function logic; and performing HDR combining and linearization by an external host. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the figures of the accompanying drawings, embodiments of the present invention are illustrated by way of example and not by way of limitation, wherein like reference numerals indicate similar elements throughout the various views unless otherwise specified. It should be noted that references to "an" or "one" embodiment of the present invention in this disclosure are not necessarily references to the same embodiment, and are intended to mean at least one embodiment. In the drawings:

[0010] Figure 1 A block diagram is provided to illustrate an example imaging system including an image sensor having a pixel array with multiple pixels arranged in pixel subarrays with a pixel architecture for high dynamic range (HDR) in a stacked CMOS image sensor scheme in accordance with one embodiment of the present invention.

[0011] Figure 2 is a schematic diagram of a portion of an image sensor including an example pixel sub-array included in a pixel array in accordance with the teachings of the present invention.

[0012] Figure 3 To illustrate an embodiment of the present invention Figure 1 A block diagram of the details of the readout circuit.

[0013] Figure 4A flowchart illustrating an example process for reading out a pixel array divided into pixel sub-arrays according to one embodiment of the present invention.

[0014] Figure 5(a) and 5(b) Graph illustrating light levels output with respect to the least significant bit (LSB) for a longer exposure (Tlong) and a shorter exposure (Tshort) according to one embodiment of the present invention.

[0015] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present invention. Furthermore, to facilitate a less obstructed understanding of these various embodiments of the present invention, common but well-known elements that are useful or necessary in commercially feasible embodiments are generally not depicted. DETAILED DESCRIPTION

[0016] In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it should be understood that embodiments of the present invention may be practiced without these specific details. In other cases, well-known circuits, structures, and technologies are not shown to avoid obscuring understanding of this description.

[0017] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The particular features, structures, or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality.

[0018] As will be disclosed in various examples, an efficient method for reading out a pixel array with high dynamic range (HDR) utilizes pixel subarrays arranged in a stacked CMOS chip solution in which the pixel cells are included in a first semiconductor die and in which the readout circuitry is included in a second semiconductor die. For example, in one example, the first semiconductor die may be a pixel die, and the second semiconductor die may be an application-specific integrated circuit (ASIC) die. In one example, the pixel subarray may be composed of clusters of nxm pixel groups. In one example, according to the teachings of the present invention, the amplifier output nodes of the pixel cells within the nxm pixel groups are coupled together so that each of the nxm pixel groups shares a single readout circuit included in the readout circuitry. In one example, according to the teachings of the present invention, the pixel subarrays are read out in parallel at high speed and / or with low power. In one example, the HDR of a stacked chip image sensor having a shared pixel architecture in which clusters of pixel cells share readout circuitry is increased.

[0019] Figure 1 A block diagram illustrating an example imaging system including an image sensor having a pixel array with a plurality of pixels arranged in pixel subarrays using a pixel architecture for high dynamic range (HDR) in a stacked CMOS image sensor solution is provided in accordance with one embodiment of the present invention. Figure 1 As illustrated in FIG, an imaging system 100 includes an image sensor having a pixel array 105 divided into a plurality of pixel sub-arrays including a pixel architecture for HDR in a stacked image sensor solution, in accordance with the teachings of the present invention. In the illustrated example, imaging system 100 is implemented with a stacked CMOS chip including a pixel die 170 stacked together with and coupled to an ASIC die 180. For example, in one example, pixel die 170 includes pixel array 105, and ASIC die 180 includes control circuitry 120, readout circuitry 130, and function logic 140. In the depicted example, control circuitry 120 is coupled to control the operation of pixel array 105, which is coupled to be read out by readout circuitry 130 via bit lines 160.

[0020] Specifically, in Figure 1 In the example depicted in FIG, pixel array 105 is a two-dimensional (2D) array that is divided into a plurality of pixel sub-arrays 110, as shown. In one example, each pixel sub-array 110 includes a plurality of pixel groups, each of which includes a plurality of pixel cells ( Figure 1In an example, each of the plurality of pixel groups in the pixel subarray is coupled to utilize the same bit line of bit line 160 and share the same readout circuit in readout circuit 130, more details of which will be described below in conjunction with Figure 2 Provide a description.

[0021] Control circuitry 120 is coupled to pixel array 105 to control the operating characteristics of pixel array 105. In one example, control circuitry 120 is coupled to generate a global shutter signal for controlling image acquisition for each pixel cell. In this example, the global shutter signal simultaneously enables specific pixel cells within all pixel subarrays 110 of pixel array 105 to simultaneously transfer image charge from their respective photodetectors during a single acquisition window. In one embodiment, control circuitry 120 controls the pixel array to cause pixel array 105 to capture a first frame having a first exposure time and a second frame having a second exposure time. The first exposure time ("Tlong") may be longer than the second exposure time ("Tshort"). In other embodiments, the first exposure time ("Tshort") may be shorter than the second exposure time ("Tlong"). In one embodiment, automatic exposure control logic is included in function logic 140 and determines the ratio of the first exposure time to the second exposure time. The automatic exposure control logic thus calculates appropriate exposure values ​​(e.g., first and second exposure times), which are transmitted to the control circuit 120 for implementation during capture and readout of the pixel array 105. In this embodiment, a gain factor is determined by the ratio of the first exposure time to the second exposure time. The gain factor can be determined by the control circuit 120 or the function logic 140.

[0022] In one example, after each of the pixel cells in pixel subarray 110 has acquired or captured its image data or image charge, the image data is read out by readout circuitry 130 through bit lines of bit lines 160. In one embodiment, logic circuitry (not shown) may control readout circuitry 130 and output the image data to function logic 140. Function logic 140 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or otherwise).

[0023] Figure 2 In accordance with the teachings of the present invention, a pixel sub-array 210 (which may be included in a pixel array (such as, for example) Figure 1 Schematic diagram of an example of a portion of an image sensor including one of a plurality of pixel subarrays in an example pixel array 105). Figure 2In the example depicted in FIG, pixel subarray 210 includes a plurality of pixel groups 220, 221, 222, and 223 arranged in n=2 columns and m=2 rows. Figure 2 Each of the four pixel groups 220, 221, 222, and 223 of the pixel subarray 210 in the example depicted in includes four pixel cells 230, 231, 232, and 233 arranged in p=2 columns and q=2 rows, and pixel support circuitry 240 shared by all four pixel cells 230, 231, 232, and 233 of each pixel group 220, 221, 222, and 223.

[0024] The pixel unit is Figure 1 The minimum repeating unit of the pixel array 105, and Figure 2 Each of the pixel cells 230, 231, 232, and 233 shown in the example illustrated in FIG includes a photodetector 251 and a transfer transistor 252, which are coupled to be controlled by a transfer signal TG. Transfer transistors arranged in the same row in pixel array 105 and in the same position within the corresponding pixel group can be controlled by the same transfer signal. For example, the transfer transistor 252 of the pixel cell 230 arranged in the upper left corner of the pixel group 220 is controlled by the transfer signal TG1(i-1), and the corresponding pixel cell in the pixel group 221 arranged in the same row as the pixel cell 230 in the pixel group 220 also includes a transfer transistor controlled by the transfer signal TG1(i-1), as shown.

[0025] Each of the four transfer transistors 252 in the pixel cells 230, 231, 232, and 233 of a particular pixel group, such as pixel group 220, shares a single floating diffusion node 241. Each of the pixel support circuits 240 shown in the illustrated example is coupled to and shared by the four transfer transistors 252 in the pixel cells 230, 231, 232, and 233 of each particular pixel group and includes a reset transistor 242 and an amplifier transistor 243 (which, in the illustrated example, is a source-follower (SF) coupled transistor 243), a row select transistor 244, and a capacitor 245 (which is coupled to a capacitor line 270). Floating diffusion node 241 is coupled to be reset to a floating diffusion reset voltage by reset transistor 242 via a power supply RFD. Reset transistor 242 is coupled to be controlled in response to a reset signal RST. In the example, pixel groups arranged in the same row are controlled by the same reset signal. For example, pixel groups 220 and 221 are controlled by reset signal RST(i-1), while pixel groups 222 and 223 are controlled by reset signal RST(i).

[0026] Floating diffusion node 241 is also coupled to control a terminal of an amplifier transistor that is connected to the Figure 2 , is a source follower transistor 243 having its gate terminal coupled to the floating diffusion node 241 and its drain terminal coupled to the power supply VDD. In the depicted example, the row select transistor 244 is controlled by a row select signal. In the example, pixel groups arranged in the same row are controlled by the same row select signal RS. For example, pixel groups 220 and 221 are controlled by the row select signal RS(i-1), while pixel groups 222 and 223 are controlled by the row select signal RS(i). In one example, the row select transistor 224 is coupled between the bit line 260 and the drain terminal of the source follower transistor 243. The source terminal of the source follower transistor 243 is coupled to the bit line 260. The pixel cells in the same pixel subarray are coupled to the same bit line.

[0027] Capacitor 245 is coupled between floating diffusion region 241 and capacitor line 270. In the depicted example, capacitor line 270, coupled to pixel groups 220 and 222, is coupled to receive signal cap_line(j). Capacitor 245 can increase the capacitance of floating diffusion node 241 in response to cap_line(j) to increase the dynamic range of the pixel cell. In the illustrated example, capacitor 245 for each pixel group 220, 221, 222, and 223 can be used to disable other pixel groups when a particular pixel group is being read. For example, pixel groups 220 and 222 can be disabled during readout of pixel groups 221 and 223 by applying a low voltage to capacitor line 270 in response to cap_line(j). Similarly, pixel groups 221 and 223 can be disabled during readout of pixel groups 220 and 222 by applying a low voltage via cap_line(j+1).

[0028] In other examples, it will be appreciated that capacitor 245 and capacitor line 270 may be omitted, and pixel groups containing pixel cells that are not being read out may be disabled by applying a low voltage to RFD. In other examples, pixel groups containing pixel cells that are not being read out may be disabled by coupling a pull-down transistor between floating diffusion region 241 and a low voltage (e.g., ground) and enabling the pull-down transistor to provide the low voltage to floating diffusion region 241.

[0029] As summarized above, it should be noted that Figure 2, pixel sub-array 210 includes a plurality of pixel groups arranged in an n x m array, where n = 2 and m = 2. Additionally, it should be noted that each pixel group includes a plurality of pixel cells arranged in a pxq array, where p = 2 and q = 2, and where the pixel cells in each pixel group all share the same pixel support circuitry 240. It should of course be understood that the illustrated example utilizes n = 2, m = 2, p = 2, and q = 2 for purposes of explanation, and that in other examples, other values ​​may be used for n, m, p, and q, where n > 1, m > 1, p > 1, and q > 1, and where n, m, p, and q are integers.

[0030] As illustrated in the depicted example, all pixel cells of pixel subarray 210 are formed on pixel die 270 and share the same bit line 260. In one example, bit line 260 can couple all pixel cells of pixel subarray 210 to a single readout circuit 285, which can be included as one of a plurality of readout circuits included in readout circuit 283 formed on ASIC die 280 stacked with and coupled to pixel die 270. In one example, each individual readout circuit 285 of the plurality of readout circuits included in readout circuit 283 is coupled to an individual one of the plurality of pixel subarrays via a single bit line 260. In one example, interconnect layer 290 is disposed between pixel die 270 and ASIC die 280. In one example, interconnect layer 290 can include a plurality of conductors. In an example, each of the plurality of conductors can be utilized to couple readout circuit 283 to circuitry included in pixel die 270.

[0031] For example, in Figure 2 , bit line 260 is implemented using one of a plurality of conductors included in interconnect layer 290. In other words, in one example, each individual one of a plurality of pixel subarrays (e.g., pixel subarray 210) in pixel die 270 can be coupled to a corresponding individual one of a plurality of readout circuits (e.g., readout circuit 285) in readout circuit 283 included in ASIC die 280 through a corresponding individual one of a plurality of conductors (e.g., bit line 260) included in interconnect layer 290. Thus, in one example, each individual one of the plurality of pixel subarrays can be read out in parallel by a corresponding individual one of the plurality of readout circuits through a corresponding individual one of the plurality of conductors (or a single bit line) in accordance with the teachings of the present invention.

[0032] In one example, the interconnect layer 290 may include through-vias, such as micro through-silicon vias (μTSVs) or through-silicon vias (TSVs). In other examples, one pixel sub-array 210 may be coupled to one or more readout circuits 285 formed on the ASIC die 280. In other examples, two or more pixel sub-arrays 210 may share one readout circuit 285 formed on the ASIC die 280. In one example, each of the plurality of readout circuits 285 may include an analog-to-digital converter (ADC) circuit, an adder, and a memory (such as static random access memory (SRAM) or dynamic random access memory (DRAM)) formed on the ASIC die 280. In other examples, each of the plurality of readout circuits 285 may include an ADC circuit and an adder formed on the ASIC die 280, wherein the memory (such as SRAM and DRAM) is formed on a memory die, which may be coupled to the ASIC die 280 through the interconnect layer.

[0033] refer to Figure 3 , which is a diagram illustrating an embodiment of the present invention Figure 1 A block diagram showing details of one of the multiple readout circuits in the readout circuit 130. Figure 3 As shown in FIG. 1 , readout circuitry 130 may include scanning circuitry 310 and ADC circuitry 320. Scanning circuitry 310 may also include amplification circuitry, selection circuitry (e.g., a multiplexer), and the like to read out image data one row at a time along readout bit line 160, or may use various other techniques to read out image data, such as serial readout or fully parallel readout of all pixels simultaneously. In one embodiment, readout circuitry 130 reads out image data from pixel array 105, including reading out image data from two frames having set exposure times. The first frame may have an exposure time ("Tlong") that is longer than the exposure time ("Tshort") of the second frame. In other embodiments, the first frame may have an exposure time ("Tshort") that is shorter than the exposure time ("Tlong") of the second frame. Scanning circuitry 130 acquires image data for the first frame and image data for the second frame. In one embodiment, the image data for the first frame may be stored in function logic 140. Storing the image data for the first frame may be performed before a second frame having a shorter or longer exposure time is captured by the pixel array. The ADC circuit 320 may convert each of the image data from the scanning circuit 310 from analog to digital. For example, the ADC circuit 320 included in the readout circuit may convert the image data of the first frame from analog to digital to obtain a first ADC output and convert the image data of the second frame from analog to digital to obtain a second ADC output. Return to Reference Figure 1, function logic 140 may sum the first ADC output with the second ADC output to produce a final ADC output. An external host may then perform HDR combining and linearization. HDR combining and linearization are performed on a per-pixel, per-pixel cluster, or per-subarray basis. Accordingly, the exposure ratio may be varied on a per-pixel, per-pixel cluster, or per-subarray basis. For example, each cluster (or subarray) may dynamically determine (e.g., using a previous frame) the ratio of a longer exposure time (Tlong) to a shorter exposure time (Tshort).

[0034] In one embodiment, pixel array 105 may capture a first frame with a long exposure time. Readout circuitry 130 or function logic 140 may store the output of ADC circuitry 320. Pixel array 105 may then capture a second frame with a shorter exposure time. The ADC output for the second frame is read out and summed with the ADC output for the first frame. In this embodiment, ADC circuitry 320 is 9 bits in size. The summed ADC outputs for the first and second frames are stored in a frame buffer. In one embodiment, the summed result is 10-bit data and the frame buffer is 10 bits in size. An external host (off-chip) may then perform HDR combining and linearization of the summed result.

[0035] Furthermore, the following embodiments of the present invention may be described as processes, which are typically described as flowcharts (flow diagrams), structure diagrams, or block diagrams. Although a flowchart may describe operations as sequential processes, many operations may be performed in parallel or simultaneously. In addition, the order of operations may be rearranged. A process terminates when its operations are completed. A process may correspond to a method, a procedure, or the like.

[0036] Figure 4 Flowchart showing an example process for reading out a pixel array divided into pixel sub-arrays according to one embodiment of the present invention. In the depicted example, it should be understood that the process can be applied to, for example, Figure 1 and / or Figure 2 For example, as described above, each pixel subarray includes a plurality of pixel groups, each of the plurality of pixel groups includes a plurality of pixel cells, as described above with respect to Figure 1 and / or Figure 2Detailed description is provided herein. Method 400 begins at block 410 by capturing a first frame having a first exposure time using a pixel array. In one embodiment, the pixel array is disposed in a first semiconductor die. At block 402, a plurality of readout circuits acquire image data for the first frame. The readout circuits are included in a readout circuit disposed in a second semiconductor die. Each of the plurality of pixel subarrays is coupled to a corresponding one of the plurality of readout circuits via a corresponding one of a plurality of conductors. At block 403, a plurality of ADC circuits included in the readout circuits each convert the image data for the first frame from analog to digital to obtain a first ADC output. At block 404, functional logic stores the first ADC output. The functional logic may be disposed in the second semiconductor die. In one embodiment, a frame buffer included in the functional logic stores the first ADC output. At block 405, the pixel array captures a second frame having a second exposure time. The first exposure time may be longer than the second exposure time. In other embodiments, the first exposure time may be shorter than the second exposure time. At block 406, the readout circuit acquires image data for the second frame. At block 407, the ADC circuit converts the image data of the second frame from analog to digital to obtain a second ADC output. At block 408, the second ADC output is read out and the function logic sums the first ADC output with the second ADC output to produce a final ADC output. At block 409, the final ADC output is stored in a frame buffer included in the function logic. At block 410, the external host performs HDR combining and linearization.

[0037] In another embodiment, rather than the functional logic storing the first ADC output at block 404, the ADC circuit includes a frame buffer that stores the first ADC output. In this embodiment, the ADC circuit also includes a logic gate for summing the first ADC output with the second ADC output at block 408 to generate a final ADC output that is stored in the frame buffer of the ADC circuit at block 409. In another embodiment, the final ADC output may also be stored in a frame buffer included in the functional logic at block 409.

[0038] The processes explained above are described in terms of computer software and hardware. The described techniques may constitute machine-executable instructions embodied in a machine (e.g., computer) readable storage medium, which, when executed by a machine, will cause the machine to perform the described operations. Alternatively, the processes may be embodied in hardware, such as an application-specific integrated circuit ("ASIC") or the like.

[0039] Figure 5(a) and 5(b)Graph illustrating light levels with respect to the least significant bit (LSB) output corresponding to a frame with a longer exposure time (Tlong) and a frame with a shorter exposure time (Tshort) according to one embodiment of the present invention. Specifically, Figure 5(a) and 5(b) Possible 9-bit ADC outputs (e.g., first and second ADC outputs) corresponding to a first frame with a longer exposure time (Tlong) and a second frame with a shorter exposure time (Tshort) are shown, along with a 10-bit final ADC output that is the sum of the first and second ADC outputs. In other embodiments, the first frame may have a shorter exposure time ("Tshort") and the second frame may have a longer exposure time ("Tlong"). FIG5(b) further illustrates the results of HDR combining and linearization that can be performed off-chip by an external host.

[0040] By means of an imaging system including an image sensor having a pixel array with multiple pixels arranged in pixel subarrays using a pixel architecture for high dynamic range (HDR) in a stacked CMOS image sensor solution according to one embodiment of the present invention, the dynamic range can be increased without increasing the output data rate. Typically, unless HDR combining is performed on-chip, two or more frame captures must be output, which increases complexity and cost. Furthermore, the imaging system and readout method described herein increase the dynamic range of the image sensor without increasing the resolution of the ADC circuit 320. Finally, the imaging system and readout method according to embodiments of the present invention provide adaptive exposure time and dynamic range across the pixel array, and in particular, provide cluster-level control of the pixel array rather than control at the frame level.

[0041] The above description of the illustrated examples of the present invention (including what is described in the Abstract) is not intended to be exhaustive or limited to the precise forms disclosed. Although specific embodiments of the present invention and examples of the present invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention.

[0042] These modifications may be made to examples of the present invention in light of the above detailed description. The terms used in the appended claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and claims. Rather, the scope of the invention is to be determined entirely by the appended claims, which are to be construed in accordance with established rules of claim interpretation. The specification and drawings are accordingly to be regarded as illustrative rather than restrictive.

Claims

1. A method for implementing a stacked chip high dynamic range (HDR) algorithm in an image sensor, comprising: capturing a first frame having a first exposure time and a second frame having a second exposure time by a pixel array included in the stacked chip, wherein the first exposure time is longer or shorter than the second exposure time, wherein the pixel array is disposed in a first semiconductor die, wherein the pixel array is divided into a plurality of pixel sub-arrays, wherein each of the plurality of pixel sub-arrays is arranged into a plurality of pixel groups, and wherein each of the plurality of pixel groups is arranged as a pixel cell of a pxq array, wherein p and q are positive integers, wherein capturing the first frame and the second frame comprises using the first exposure time and the second exposure time, respectively, for the same pixel in the pixel array, wherein the plurality of pixel groups aligned in each single group column are coupled to each of a plurality of capacitor lines, and wherein each of the plurality of capacitor lines is coupled to receive each of capacitor line signals, and respective ones of the capacitor line signals are configured to apply a low voltage to the respective ones of the plurality of capacitor lines; The image data of the first frame and the image data of the second frame are acquired by a plurality of readout circuits included in the stacked chip. wherein the plurality of readout circuits are included in readout circuitry disposed in a second semiconductor die, wherein each of the plurality of pixel subarrays is coupled to a corresponding one of the plurality of readout circuits by a corresponding one of a plurality of conductors such that the plurality of pixel groups in each of the plurality of pixel subarrays share a single one of the plurality of readout circuits; converting the image data of the first frame from analog to digital to obtain a first ADC output and converting the image data of the second frame from analog to digital to obtain a second ADC output by a plurality of ADC circuits included in the readout circuit; as well as The first ADC output and the second ADC output are summed by function logic included in the stacked chip to produce a final ADC output, wherein the function logic is disposed in the second semiconductor die. 2 . The method of claim 1 , further comprising storing, by the function logic, the first ADC output.

3. The method of claim 2, further comprising performing HDR combining and linearization by an external host. 4 . The method of claim 3 , wherein the HDR combining and linearization is performed per pixel, per pixel cluster, or per sub-array. 5 . The method of claim 1 , further comprising determining, by automatic exposure control logic, a ratio of the first exposure time to the second exposure time. The method of claim 5 , wherein a gain factor is determined by the ratio of the first exposure time to the second exposure time.

7. The method of claim 1, wherein each of the plurality of pixel sub-arrays is arranged into a plurality of nxm pixel groups. The method according to claim 7 , wherein n, m, p and q are integers greater than 1.

9. The method of claim 3, wherein each of the plurality of pixel groups includes pixel support circuitry coupled to and shared by pixel cells of the pxq array included in the each of the plurality of pixel groups.

10. A stacked chip high dynamic range (HDR) imaging system comprising: a pixel array disposed in a first semiconductor die, wherein the pixel array is divided into a plurality of pixel sub-arrays, wherein each of the plurality of pixel sub-arrays is arranged into a plurality of pixel groups, and wherein each of the plurality of pixel groups is arranged into a pixel cell of a pxq array, wherein p and q are positive integers, and wherein the plurality of pixel groups aligned in each single group column are coupled to each of a plurality of capacitor lines, wherein each of the plurality of capacitor lines is coupled to receive each of capacitor line signals, and respective ones of the capacitor line signals are configured to apply a low voltage to respective ones of the plurality of capacitor lines, wherein the pixel array captures a first frame having a first exposure time and a second frame having a second exposure time, wherein the first exposure time is longer or shorter than the second exposure time; a plurality of readout circuits included in readout circuitry disposed in a second semiconductor die, wherein each of the plurality of pixel subarrays is coupled to a corresponding one of the plurality of readout circuits by a corresponding one of a plurality of conductors such that the plurality of pixel groups in each of the plurality of pixel subarrays share a single one of the plurality of readout circuits, wherein the plurality of readout circuits acquire the image data of the first frame and the image data of the second frame, wherein the plurality of readout circuits respectively include an analog / digital ADC circuit, the ADC circuit converting the image data of the first frame from analog to digital to obtain a first ADC output and converting the image data of the second frame from analog to digital to obtain a second ADC output; as well as Function logic coupled to the readout circuit to sum the first ADC output and the second ADC output to produce a final ADC output, wherein the function logic is disposed in the second semiconductor die.

11. The imaging system of claim 10, wherein the function logic stores the final ADC output in a frame buffer.

12. The imaging system of claim 10, wherein HDR combining and linearization are performed by an external host.

13. The imaging system of claim 12, wherein the HDR combining and linearization is performed per pixel, per pixel cluster, or per sub-array.

14. The imaging system of claim 10, further comprising: A control circuit disposed in the second semiconductor die is coupled to the pixel array to control operation of the pixel array, wherein the control circuit is disposed in the second semiconductor die.

15. The imaging system of claim 14, wherein the control circuit comprises automatic exposure control logic to determine a ratio of the first exposure time to the second exposure time.

16. The imaging system of claim 15, wherein a gain factor is determined by the ratio of the first exposure time to the second exposure time. 17 . The imaging system of claim 10 , further comprising an interconnect layer stacked between the first semiconductor die and the second semiconductor die, wherein the plurality of conductors are included in the interconnect layer.

18. The imaging system of claim 10, wherein each of the plurality of pixel sub-arrays is arranged into a plurality of nxm pixel groups.

19. The imaging system of claim 18, wherein n, m, p, and q are integers greater than 1.

20. The imaging system of claim 19, wherein each of the plurality of pixel groups includes pixel support circuitry coupled to and shared by pixel cells of the pxq array included in the each of the plurality of pixel groups.

21. The imaging system of claim 20, wherein the pixel support circuitry comprises: a floating diffusion node coupled to each of the pixel cells of the pxq array, wherein each of the pixel cells of the pxq array includes a photodetector coupled to the pixel support circuitry through a transfer transistor; a capacitor coupled between the floating diffusion node and the capacitor line; an amplifier transistor coupled to the floating diffusion node; a row select transistor coupled between a bit line coupled to the readout circuit and the amplifier transistor; as well as A reset transistor is coupled between the floating diffusion node and a reset voltage.

22. A method for implementing a stacked chip high dynamic range (HDR) algorithm in an image sensor, comprising: setting each of the plurality of capacitor lines with each of a plurality of voltages to determine each capacitance of the plurality of floating diffusions, capturing a first frame having a first exposure time by a pixel array included in a stacked chip, wherein the pixel array is disposed in a first semiconductor die, wherein the pixel array is divided into a plurality of pixel subarrays, wherein each of the plurality of pixel subarrays is arranged into a plurality of pixel groups, and wherein each of the plurality of pixel groups is arranged into a pixel cell of a px q array, wherein p and q are positive integers, wherein the plurality of pixel groups aligned in each single group column are coupled to each of a plurality of capacitor lines, and wherein each of the plurality of capacitor lines is coupled to receive each of capacitor line signals, and respective ones of the capacitor line signals are configured to apply a low voltage to the respective ones of the plurality of capacitor lines; converting the image data of the first frame from analog to digital by a plurality of ADC circuits included in readout circuitry included in the stacked chip to obtain first ADC outputs, wherein the plurality of readout circuits are included in readout circuitry disposed in a second semiconductor die, wherein each of the plurality of pixel subarrays is coupled to a corresponding one of the plurality of readout circuits by a corresponding one of a plurality of conductors such that the plurality of pixel groups in each of the plurality of pixel subarrays share a single readout circuit in the plurality of readout circuits; storing the first ADC output; capturing, by the pixel array, a second frame having a second exposure time, wherein the first exposure time is longer or shorter than the second exposure time, wherein capturing the first frame and the second frame comprises using the first exposure time and the second exposure time, respectively, for the same pixels in the pixel array; converting the image data of the second frame from analog to digital by the ADC circuit to obtain a second ADC output; reading out the second ADC output and summing the second ADC output with the stored first ADC output by function logic included in the stacked chip to produce a final ADC output, wherein the function logic is disposed in the second semiconductor die; storing the final ADC output in a frame buffer included in the function logic; as well as HDR combining and linearization are performed by an external host.

Images