Trigger receiving circuit for linear voltage regulator

Abstract

This invention is entitled "Trigger Receiver Circuit for Linear Regulators." The invention discloses a trigger receiver circuit for linear regulators such as low-dropout regulators (LDOs). This trigger receiver circuit is activated only when needed to receive current from the output in response to transient load changes. The trigger receiver circuit includes a large receiving transistor that, when activated, draws current from the LDO's output to quickly restore the output voltage to the regulated value, thereby improving the load transient response to load changes. The improved load transient response prevents the LDO's output transistor from completely deactivating to restore regulation. Therefore, the LDO's response to subsequent load transients is improved.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 799,205, filed on February 24, 2020. Technical Field

[0003] This disclosure relates to analog microelectronic circuits, and more specifically, to linear regulators having a receiving circuit that can be triggered to adapt to specific load transient conditions. Background Technology

[0004] A low dropout (LDO) regulator (i.e., LDO) is a linear regulator that is configured to control the output transistor (M... O The conduction level of ) is used to convert the unregulated input voltage (V) IN ) is converted into a regulated output voltage (V) OUT This creates a voltage drop between the input and output of the LDO, which responds to changes in the input voltage, thus keeping the output voltage constant (e.g., V relative to a reference voltage). REF ).

[0005] LDOs can respond to changing loads based on load transient response (LOTR). For example, if a changing load causes the output current (ILDO) to change... OUT If the output voltage (V) suddenly increases or decreases, the output voltage will... OUT The LDO circuit can deviate from its setpoint level for a period of time while responding. The LOTR describes the amplitude and response period of the deviation. Generally, a lower amplitude deviation is more desirable than a higher amplitude deviation, and a shorter period is more desirable than a longer period. The embodiments of this disclosure have emerged in this context. Summary of the Invention

[0006] In at least one aspect, this disclosure generally describes a method. The method includes regulating the output voltage using a low-dropout regulator (i.e., an LDO). The method also includes detecting a specific type of load transient (e.g., load increase) when the output voltage of the LDO meets a criterion (e.g., output voltage ≥ threshold voltage). The method includes receiving current from the output of the LDO using a triggered receiving circuit including a receiving transistor when the specific type of load transient is detected. Receiving includes activating the receiving transistor to receive current from the output of the LDO when the output voltage of the LDO meets the criterion, and gradually deactivating the receiving transistor when the output voltage does not meet the criterion.

[0007] In another aspect, this disclosure generally describes a low-dropout regulator (LDO). The LDO includes an output transistor configured to increase or decrease the current supplied (i.e., conducted) to the output of the LDO according to a corresponding decrease or increase in the output voltage of the LDO. The LDO also includes a trigger receiver circuit that is activated to receive current from the output of the LDO when the increase in the output voltage exceeds a threshold, and is gradually deactivated when the output voltage no longer exceeds the threshold.

[0008] In another aspect, this disclosure generally describes a trigger-receive circuit for a low-dropout regulator (LDO). The trigger-receive circuit includes a receive trigger coupled to the output voltage of the LDO. The receive trigger is configured to generate a trigger signal when the output voltage of the LDO meets a criterion, the trigger signal being maintained at the trigger voltage during the on-time period. The trigger-receive circuit also includes a receive control that receives the trigger signal and generates a receive control signal in response. The receive control signal is maintained at the on-time voltage during the on-time period and then gradually decreases according to a soft-turn-off curve during the off-time period. The trigger-receive circuit also includes a receive transistor that is activated by the on-time voltage (i.e., turned on, conducting) to receive current from the output of the LDO during the on-time period and then gradually deactivated according to a soft-turn-off curve during the off-time period.

[0009] In a possible implementation, the activation of the receiver transistor in the trigger receiver circuit reduces the load transient response of the LDO.

[0010] The foregoing illustrative invention, as well as other exemplary objectives and / or advantages and implementation methods of this disclosure, are further explained in the following detailed description and accompanying drawings. Attached Figure Description

[0011] Figure 1 This is a block diagram of a low-dropout regulator (i.e., LDO) including a trigger receiving circuit according to one possible embodiment of the present disclosure.

[0012] Figure 2 Includes time-based graphs showing the LDO's response to load transients when the trigger receiver circuit is not used, according to a possible implementation of this disclosure.

[0013] Figure 3 It is the reception control signal (V) according to a possible embodiment of this disclosure. S (Time-based graph)

[0014] Figure 4 Includes time-based graphs showing the LDO's response to load transients when using a triggered receiver circuit according to a possible implementation of this disclosure.

[0015] Figure 5 This is a schematic diagram of possible implementations of an LDO, including a block diagram of possible implementations of a trigger receiver circuit.

[0016] Figure 6 yes Figure 5 A detailed schematic diagram of the LDO shows a possible circuit implementation for triggering the receiver circuit.

[0017] Figure 7 This is a flowchart of a method for regulating the voltage to a changing load.

[0018] The components in the accompanying drawings are not necessarily drawn to scale relative to each other. Similar reference numerals may be used in several drawings to indicate corresponding parts. Detailed Implementation

[0019] Linear voltage regulators (i.e., linear regulators) can supply large output currents to a load, but their ability to sink the same amount of current may be insufficient. Therefore, a step-down of the output current from a high value to a low value can lead to unacceptable load transient response. This disclosure describes circuits and methods for responding to changes in load current, wherein additional sinks are added to improve the load transient response of the linear regulator. While the techniques disclosed in this invention are applicable to most linear regulators, implementations for low-dropout (LDO) regulators will be considered in detail.

[0020] This disclosure describes an LDO regulator including a sink circuit configured to respond to the type of load transient (LOT). The sink circuit includes a sink transistor coupled to the output of the LDO, which is configured to provide a high-capacity conductive path (e.g., from the output to ground) to quickly receive (i.e., leak) current from a load (e.g., a capacitive load) to help reduce the elevated output voltage (V). OUT The receiving transistor receives the sink-control signal (V). S The control is to turn on (i.e., reduce resistance) for a period of time to receive current from the load, and then turn off (i.e., increase resistance) according to a slow release (i.e., soft turn-off) curve after the receiving period. The soft turn-off curve reduces (or eliminates) the output voltage (V) caused by the on / off switching of the receiving transistor. OUTThe load transient response in [the context of] . For example, the soft-turn-off curve reduces the conductivity of the receiving transistor during the turn-off period according to the turn-off slope (rate), so that the load transient response generated by soft turn-off is less than a predetermined value. In other words, the turn-off period and turn-off rate can correspond to a load transient response less than a predetermined value.

[0021] The disclosed LDO regulator, including a trigger receiver circuit, advantageously reduces (e.g., compared to an LDO regulator without a receiver circuit) the period during which the elevated output voltage returns to the regulated value. This reduced period prevents the LDO from stabilizing at its control limits (i.e., the rails), which can help improve the LDO's response to subsequent load transients (i.e., back-to-back load transients). Furthermore, the conditional triggering (i.e., activation) of the trigger receiver circuit prevents the receiver circuit from affecting the LDO's operation under other load conditions, and thus can advantageously be achieved with limited (or no) influence on other parts of the LDO circuitry.

[0022] Load transient (LOT) is a (rapid) change in the load coupled to the output of the LDO, which causes the LDO's output current (IL) to change. OUT The corresponding (rapid) change. For example, a switchable load, such that when the switch decouples the load from the LDO, the LDO's output current changes from a non-zero current (e.g., I0). OUT >100 mA) rapidly changes to zero current (e.g., I OUT =0 mA). Load transients can be classified according to their behavior.

[0023] The first type of load resistance (LOT) is caused by a decrease in load resistance. The decreased load resistance (R) L This can lead to an output voltage (V) OUT The voltage level decreases accordingly from the regulated voltage level. In response, the LDO can be configured to increase the current from the output to the load (i.e., the supply current) in order to restore (i.e., increase) the output voltage back to the regulated voltage level.

[0024] The second type of LOT is caused by an increase in load resistance. An increased load resistance can lead to a decrease in output voltage (V). OUT The regulated voltage level increases accordingly. In response, the LDO can be configured to reduce the current from the output to the load, thereby reducing the output voltage back to the regulated voltage level. A summary of the above examples of load transients is shown in Table 1.

[0025] Table 1: Summary of Exemplary Load Transients (LOTs)

[0026] LOT: Category 1 LOT: Category II <![CDATA[R L ]]> ↓ Reduce ↑ Increase <![CDATA[I OUT ]]> ↑ Increase ↓ Reduce <![CDATA[V OUT ]]> ↓ Reduce ↑ Increase LDO response Supply current Received current

[0027] When the load is purely resistive, the increased output voltage simply decreases as the output current supplied to the load decreases. However, when the load includes reactive components (e.g., capacitor C) O In some cases, simply reducing the output current supplied to the load may not be sufficient to reduce the output voltage. For example, to reduce the output voltage on a capacitive load (such as an image sensor), the output of an LDO must be configured to receive current from the capacitive load in order to dissipate its voltage.

[0028] The faster an LDO can draw current from a capacitive load, the faster its output voltage can drop back to the regulated voltage level. If the LDO is limited in its ability to draw current from the load, the output voltage (V) will decrease. OUT The output voltage (V) can decrease slowly over a period of time. In other words, the output voltage (V) OUT The output voltage can remain above the regulated level during this cycle. The feedback response generated by the sustained high output voltage can cause the LDO to stabilize (i.e., the rail) at its control limits. In this case, the output transistor (M) O ) completely disconnected, and the output voltage (V OUT The output transistor (M) is no longer under control. O When the circuit is reconnected to restore control of the output voltage, subsequent load transients (i.e., load changes) can result in a very poor LOT response.

[0029] Figure 1 This is a block diagram of an LDO regulator including a trigger receiving circuit according to one possible embodiment of the present disclosure. The LDO 100 is configured to receive an unregulated input voltage (V) relative to ground voltage (GND) (at input 150 of the LDO). IN ), and transmits the regulated output voltage (V) relative to ground voltage (at the LDO output 155). OUT The output voltage is regulated by a regulating control circuit (i.e., regulating control 110). Regulating control 110 is configured to receive the output voltage (V). OUT This serves as feedback from the output of the LDO. The regulation control 110 is also configured to receive a reference voltage (V) from circuitry included in the LDO (but not shown). REF The reference voltage provides a voltage that can be compared with the output voltage (V). OUT The stable voltage level is compared with that of the control. The adjustment control 110 is configured to adjust the output voltage (V) to a stable voltage level. OUT ) and reference voltage (V REF The comparison is performed, and based on this comparison, a generator is generated for the output transistor 130 (M). O ) control signal (V G ).

[0030] The output transistor 130 (and other transistors of the LDO) can be implemented using a variety of technologies, including (but not limited to) bipolar junction transistors (BJTs) and field-effect transistors (FETs). Figure 1 The output transistor 130 shown is implemented as a (P-type) metal-oxide-semiconductor transistor (MOSFET). The control (e.g., gate) terminal of the output transistor 130 is configured to receive a control signal (e.g., gate voltage) from the regulation control 110. The control signal (V... G The voltage level generates a corresponding voltage drop (e.g., V) between the source and drain terminals of the output transistor 130. DS ).

[0031] like Figure 1 As shown, the input voltage (V) IN The LDO is coupled to the source terminal of the output transistor 130, and the output terminal of the LDO is coupled to the drain terminal of the output transistor 130. Therefore, the output voltage (V) OUT ) is the input voltage (V) IN ) and the voltage drop across the output transistor (i.e., V) DS The difference between ) and ). By controlling this voltage drop (V DS ), adjustable output voltage (V) OUT For example, if the input voltage (V) IN If the output voltage (V) increases, then the output voltage (V) will increase. OUT The output voltage (V) will increase. Adjusting control 110 will increase the output voltage (V). OUT ) and reference voltage (V REF This is compared to generate an increased voltage drop (V) across the output transistor. DS ) control signal (V G ), making the output voltage (V OUT The voltage is reduced back to the regulated voltage (i.e., relative to the reference voltage).

[0032] Output transistor 130 may be a power MOSFET designed (e.g., its dimensions are set to) conduct a relatively large current (e.g., >100 mA) from the input to the output of the LDO. Output transistor 130 is capable of conducting leakage current at levels that could cause output voltage variations (e.g., under no-load conditions), especially at elevated temperatures. To prevent this, the leakage current of output transistor 130 can sink to ground and not affect the output voltage. Therefore, the LDO may include a leakage transistor 140 configured to conduct current from output transistor 130 (M... O Leakage current is discharged (i.e., received (sink)) to prevent unwanted output voltage increases under low (e.g., zero) load conditions.

[0033] The leakage transistor 140 can be implemented as an (N-type) MOSFET with a smaller size relative to the output transistor 130. The leakage transistor 140 can be large enough to receive the level of leakage current from the output transistor 130, but small enough to keep the LDO's quiescent current low. The amount of leakage current that the leakage transistor 140 can receive can depend on the size of the output transistor (e.g., a larger output transistor can have a larger leakage current) and can depend on temperature (e.g., higher temperatures can cause a larger leakage current). In one possible implementation, the leakage current is small compared to the output current (e.g., <10 µA compared to >100 mA). Therefore, the output transistor 130 is able to supply more current than the current that the leakage transistor 140 can receive. Therefore, the LDO may include a trigger receiver circuit 120 to supplement (i.e., enhance) the receiving capability of the leakage transistor 140 for specific load (i.e., output voltage) conditions.

[0034] Load 190 may be coupled to the output of the LDO. Load 190 may include a resistive component 192 and a reactive component (e.g., a capacitor 194). Load transient (LOT) may include changes (e.g., abrupt changes) in the resistive and / or capacitive components of the load. As previously described, abrupt changes can cause a load transient response (LOTR) in the LDO. Without triggering the receiver circuit 120, the LDO may have a poor load transient response to loads requiring the reception of large currents.

[0035] Figure 2 This includes a time-based graph showing the LDO load transient response (LOTR) of an LDO without a triggered receiver circuit. The graph includes the output current (IL) for load variations as described in Table 1. OUT ) Curve 201 and output voltage (V) OUT ) Curve graph 202.

[0036] The first load change at point 210 causes the output voltage (V) to be affected. OUT The first load transient response 211 (LOTR) is reduced. In response, the regulation control 110 configures the output transistor 130 to supply current to the load 190 in order to reduce the output voltage (V) OUT The regulation recovers (i.e., increases) to the adjustment value of 215. Because the output transistor can supply a large current, the regulation recovers quickly (i.e., recovers before subsequent load transients).

[0037] The second load change at time 220 causes the output voltage (V) to be affected. OUT The second load transient 221 increases. In response, the LDO 100 is configured to receive current from the load in order to increase the output voltage (V) OUTThe output voltage is restored (i.e., reduced) to the regulation value 215 (i.e., the regulated voltage). However, without triggering the receiver circuit 120, the LDO relies on the leakage transistor to receive current from the load. Because the leakage transistor is small, the current is slowly leaked (i.e., received (sink)), and the second load transient response decreases at a very low rate. In this case, the output voltage remains (i.e., persists) above the regulation value 215 with an amplitude 230 higher than the regulation value 215. As the output voltage persists above the regulation value 215, the regulation control can disconnect the output transistor 130, causing it to no longer conduct (i.e., reducing any voltage between the input and output). In other words, in this case, the LDO's output can become unregulated.

[0038] The third load change at time 235 causes the output voltage (V) to be affected. OUT The reduced third load transient response 236 occurs before the LDO recovers from the second load change. Therefore, the third load transient response 236 can have an amplitude 240 much larger than the first load transient response 211. This increase in amplitude can be at least partly attributed to the (large) output transistor 130 being turned off due to the second load change and having to be turned back on to begin regulation.

[0039] The change in current caused by load variation can have amplitudes of several orders of magnitude. For example, I OUT The output current shown in graph 201 can vary from approximately 1 microamp (μA) to approximately 250 milliamp (mA) to accommodate load variations.

[0040] return Figure 1 The LDO 100 includes a trigger receiver circuit 120 to assist in receiving current from the load in response to load transients (see Table 1). The trigger receiver circuit 120 includes a receiver trigger circuit (i.e., a sink trigger 160) configured to generate a trigger signal to activate a receiver control circuit (i.e., a sink control 170) when a load change (i.e., a load transient) meets (e.g., conforms to) a receiver criterion. For example, the sink trigger 160 may be configured to output a current (V) from the load. OUT The signal is compared with a threshold, and if the output voltage exceeds the threshold level, the receive trigger can be activated (i.e., trigger) the receive control 170. The receive control 170 is configured to generate a receive control signal (V) once activated. SThe receiver transistor 180 is controlled to conduct current (i.e., the received current) from the LDO output to ground. The receiver transistor 180 can be a FET (e.g., an N-type power MOSFET) with dimensions capable of conducting a larger amount of current than the leakage transistor 140. In a possible implementation, the receiver transistor 180 is capable of rapidly (i.e., compared to no receiver transistor) discharging the output capacitor (i.e., C). O Excess (i.e., above the regulation) voltage (i.e., excess charge) on the transistor. In another possible implementation, the receiving transistor 180 is smaller than the output transistor 130. It may be advantageous to keep the size of the receiving transistor as small as possible to save die area.

[0041] Figure 3 It is the reception control signal (V) according to a possible embodiment of this disclosure. S A time-based graph of the received control signal (V) at time 310, when (or after) the trigger signal is received from the receive trigger 160. S The voltage rises to a forward voltage of 315 (e.g., V). IN The on-state voltage is sufficient to turn on the receiver transistor 180 (i.e., turn it on). The on-state voltage 315 can maintain the on-state for a period 320. The on-state 320 can be the time required to reduce the output voltage below a threshold. For example, a trigger signal provided by the receiver trigger 160 can reduce the receive control signal (V) to below a threshold. S Maintain the on-state voltage at 315 until the output voltage (V) is reached. OUT The voltage drops below the reference voltage (V). REF Add offset voltage (V) OS ).

[0042] After the turn-on period 320, the receiver transistor 180 can be deactivated (i.e., turned off, switched off, switched on) according to the soft turn-off curve 325 within the turn-off period 330. The soft turn-off curve 325 may include a linear or non-linear decrease in the level of the receiver control signal according to the turn-off slope 333. For example, the receiver control signal may be derived from the turn-on voltage (e.g., V). IN The voltage gradually decreases to ground voltage (e.g., zero volts). During the off-period 330, the receiving transistor 180 gradually switches from an on (i.e., conducting) condition to an off (i.e., non-conducting) condition (i.e., undergoing gradual deactivation). The off-period 330 can be set and / or adjusted based on the expected transient response of the LDO 100 to the on / off switching of the receiving transistor 180. For example, the off-period 330 can be adjusted to make the output voltage (V... OUT The load transient in the circuit is minimized. A longer off-time corresponds to a smaller load transient compared to a shorter off-time. The trigger receiver circuit is active only during the active period 335.

[0043] Figure 4This includes time-based graphs showing the LDO's response to load transients when using a triggered receiver circuit. These graphs include the output current (IL). OUT Curve 401, Trigger Signal Curve 402, Receive Control Signal (V) S ) Curve 403 and output voltage (V OUT )Graph 404, and shows as in Table 1 and Figure 2 The three load changes mentioned above.

[0044] The first load change at point 410 causes the output voltage (V) to be affected. OUT The first load transient response 411 (LOTR) is reduced. In response, the regulation control 110 configures the output transistor 130 to supply current to the load 190 in order to reduce the output voltage (V) OUT The value was restored (i.e., increased) to the adjustment value of 215.

[0045] For the first load transient response 411 of the first load change, with or without (see...) Figure 2 The case of trigger receiver circuit 120 (211) is the same, because the output voltage corresponding to the first load transient does not meet the conditions (i.e., the standard) for activating (i.e., triggering) trigger receiver circuit 120. The condition aspect of trigger receiver circuit 120 can advantageously promote low quiescent current of LDO, because a portion of trigger receiver circuit 120 is inactive until needed.

[0046] The second load change at the second time 420 causes a second load transient response 421, which includes the output voltage (V OUT The receive trigger 160 generates a trigger signal 422 when the output voltage change is sufficient to meet a criterion (e.g., equal to or above a threshold voltage). For example, the trigger signal can be changed to a trigger voltage that is held until the output voltage no longer meets the criterion (e.g., below a threshold voltage). The trigger signal can configure the receive control 170 to generate a receive control signal (V). S The receive control signal may correspond to the trigger signal. For example, the receive control signal may be changed to a level held according to the trigger signal. When at the holding level, the receive control signal may configure the receive transistor 180 to conduct current in order to reduce the output voltage. A second load transient without a trigger receive circuit (see...) Figure 2 221 in the middle) and the second load transient with a trigger receiving circuit (see 221) Figure 2 The period of the second load transient is compared with that of the trigger receiving circuit 120 (421) to show the period of the second load transient.

[0047] After the output voltage decreases, a control signal (V) is received. SThe output voltage gradually decreases, making the load transient response 423 in the output voltage caused by the switching (i.e., deactivation) of the receiving transistor very small (e.g., below a predetermined value). This is because the output voltage (V... OUT The voltage quickly returns to the regulated voltage 415, so the regulating control 110 is not forced to reach its control limits, and the output transistor remains on (i.e., turned on) to regulate the output voltage. In other words, the trigger receiver circuit 120 prevents loss of regulation in response to certain load transients. Therefore, the load transient response to subsequent load changes (i.e., back-to-back load transients) can be reduced because the output transistor 130 does not have to recover from a fully off state. In other words, using the trigger receiver circuit to receive current from the LDO output can improve (e.g., reduce) the back-to-back load transient response to below a predetermined value. The back-to-back load transient response can be defined as a first load transient response and a second load transient response separated by periods less than a predetermined value.

[0048] The third load change at time 430 causes the output voltage (V) to be affected. OUT The amplitude 440 of the third load transient response 436 with trigger receiving circuitry is smaller than the amplitude of the third load transient response without trigger receiving circuitry (see [reference]). Figure 2 (240) because by the time the third load change occurs, the output regulation has recovered from the second load change.

[0049] The second load transient response 421 at a second time 420 and the third load transient response 436 at a third time 430 can be referred to as back-to-back load transients because they are separated by relatively short periods (e.g., compared to the period required for recovery regulation). The method disclosed in this invention can advantageously improve back-to-back load transient responses.

[0050] The amplitude of the load transient response can correspond to the amplitude 437 of the output current change associated with the load transient. In the back-to-back load transient responses (including the second load transient response 421 and the third load transient response 436), the receiving transistor is partially turned on at a third time 430 as it slowly deactivates (i.e., turns off). In this example, the partial activation of the receiving transistor 180 results in an improved LOTR 436 because the current supplied by the output transistor (Mo) does not start from zero (see...). Figure 2 Instead of 236), it starts from the current provided by the receiving transistor 180, which is partially activated.

[0051] Figure 5 This is a schematic diagram of a possible implementation of an LDO regulator, including a block diagram of a possible implementation of the trigger receiver circuit. The LDO 100 includes an output transistor (M... OThe output transistor is coupled to the load 190° at the output (OUT) of the LDO. L C O Output transistor (M) O It is controlled by a regulating control circuit, which includes functions for adjusting the voltage based on a reference voltage (V). REF ) and output voltage (V OUT The difference between the two is used to adjust the output transistor (M). O The circuit is at its operating point (i.e., on). The difference is measured using a pair of differential transistors (M0, M1). The LDO 100 includes a leakage transistor (M12) which is large enough to quickly receive current equivalent to leakage current (e.g., microamps), but too small to quickly receive current equivalent to load variations (e.g., milliamps). Therefore, the LDO includes a triggered receiver circuit 120 to provide additional receiving capability under certain load conditions.

[0052] The trigger receiver circuit 120 includes a receiver transistor 180 (M17) that is large enough to quickly receive current equivalent to load changes. The conduction of the receiver transistor 180 is controlled by a receiver control 170 (i.e., a timer with slow release), which is triggered by a receiver trigger 160. The receiver trigger includes a comparator 510 configured to convert the output voltage (V...)... OUT ) and reference voltage (V REF Add offset voltage 520 (V) OS The comparison is performed such that the output voltage satisfies (e.g., satisfies) its ratio to the reference voltage (V). REF At least the offset voltage (V) OS The standard time generates the trigger signal.

[0053] Figure 6 yes Figure 5 A detailed schematic diagram of an LDO regulator is provided, further illustrating a possible circuit implementation of the trigger receiver circuit. The trigger receiver circuit may share transistors M0 and M1 of the regulation control circuit as a comparator (see [link to diagram]). Figure 5 (510). Offset voltage (see 510). Figure 5 The 520 can be provided by an offset comparator comprising a pair of transistors (M19, M20) with mismatched dimensions (e.g., channel widths). For example, M19 may be larger than transistor M20, as described by the size ratio. The size ratio may correspond to the comparator's offset voltage (V). OS Furthermore, in a possible implementation, the dimensions may be designed to provide an offset voltage in the range of approximately 10-20 millivolts (mV).

[0054] When the output voltage is higher than the reference voltage by an offset voltage (i.e., V), OUT ≥VREF +V OS When the transistor M23 is activated (i.e., turned on), it pulls the control terminal (e.g., the gate terminal) of the transistor M23 to ground. In other words, M23 receives a trigger signal created by the receive trigger 160, which includes transistors M0, M1, M19, M20, and M21.

[0055] The trigger signal pulls down the gate of transistor M23, activating (i.e., turning on) transistor M23, and the activation of transistor M23 charges capacitor C2 to V. IN When charging, the voltage (V) across capacitor C2 (which is coupled to the control terminal (e.g., the gate terminal) of the receiving transistor) is... IN The receiver transistor 180M25 is fully activated (i.e., the receiver transistor is turned on). As long as transistors M23 and M21 remain on, receiver transistor 180 remains on.

[0056] When the output voltage drops below the reference voltage plus the offset voltage (i.e., V) OUT <V REF +V OS When the capacitor is switched on, transistors M21 and M23 are deactivated (i.e., switched off). However, the receiving transistor remains switched on due to the charge on capacitor C2, and gradually switches off (i.e., slowly releases) as capacitor C2 is discharged by transistor M24. In other words, the receiving control 170 may include devices M23, M24, and C2.

[0057] The LDO described and illustrated is one possible implementation and variations are possible. Other LDO designs or topologies may advantageously utilize the triggered receiver circuitry with slowly deactivated receiver transistors disclosed in this invention to improve load transient response (e.g., back-to-back load transient response). Furthermore, for clarity and / or brevity, some circuitry (i.e., stages) of the LDO has been omitted. For example, the LDO may include other circuitry / stages, such as a reference stage (e.g., to generate VLDO). REF ) and bias level (e.g., to generate V) BIAS ).

[0058] Figure 7 A flowchart of a method for regulating the output voltage is shown. Method 700 includes regulating the output voltage of 710 using an LDO. The method also includes detecting a specific type of load transient (LOT) 720 (see Table 1, LOT: Second Type). The method includes receiving a current 730 from the output of the LDO using a triggered receiving circuit when the specific type of LOT is detected. Receiving the current from the output includes determining the output voltage (V). OUT740 checks whether the output voltage meets (e.g., satisfies) criterion 740. If the criterion is met, the receiving transistor 750 is activated. The transistor remains activated to receive current from the output until the output voltage no longer meets (e.g., satisfies) the criterion. When the output voltage no longer meets the criterion, the receiving transistor is gradually deactivated according to the soft-turn-off curve 760.

[0059] Typical embodiments have been disclosed in the specification and / or accompanying drawings. This disclosure is not limited to such exemplary embodiments. For example, a low-dropout regulator is a type of linear regulator, but the disclosed principles can also be used with other types of linear regulator circuits. The use of the term "and / or" includes any and all combinations of one or more of the associated listed entries. The accompanying drawings are schematic representations and therefore not necessarily drawn to scale. Unless otherwise stated, specific terms have been used in a general and descriptive sense and are not intended for limiting purposes.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar to or equivalent to those described herein may be used in practice or testing of this disclosure. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include multiple referents unless the context clearly specifies otherwise. The term “comprising” and its variations are used synonymously with the term “including” and its variations as used herein and are open-ended, non-limiting terms. The terms “optional” or “optionally” as used herein mean that a feature, event, or condition subsequently described may or may not occur, and the description includes instances where the feature, event, or condition occurs and instances where it does not occur. Scope may be expressed herein as from “about” a particular value and / or to “about” another particular value. When such a scope is expressed, an aspect includes from one particular value and / or to another particular value. Similarly, when a value is expressed as an approximate value using the antecedent “about,” it should be understood that the particular value forms another aspect. It should also be understood that each endpoint of a range is significant relative to another endpoint and independent of the other endpoint.

[0061] Some implementations may be implemented using various semiconductor processing and / or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with a semiconductor substrate, including, but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0062] While certain features of the described embodiments have been illustrated herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations falling within the scope of the embodiments. It should be understood that these modifications and variations are presented by way of example only and not limitation, and various changes in form and detail are possible. Any parts of the apparatus and / or methods described herein can be combined in any way, except for mutually exclusive combinations. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A method comprising: The output voltage is regulated using a low dropout voltage regulator (LDO). When the output voltage of the LDO meets the standard, a specific type of load transient is detected. as well as Upon detection of the specific type of load transient, a triggered receiving circuit including a receiving transistor receives current from the output of the LDO, wherein the receiving includes: When the output voltage of the LDO meets the standard, a receive control signal at the turn-on voltage is applied to the receive transistor to activate the receive transistor to receive current from the output terminal of the LDO; as well as When the output voltage does not meet the standard, the receive control signal applied to the receive transistor is gradually changed during the off period in order to deactivate the receive transistor.

2. The method of claim 1, wherein the particular type of load transient is a load increase, the criterion includes the output voltage of the LDO being higher than a threshold, and the threshold is a reference voltage plus an offset voltage.

3. The method according to claim 1, wherein the receiving control signal is: The LDO maintains its on-voltage state when the output voltage meets the specified criteria; and When the output voltage does not meet the standard, the voltage is reduced from the turn-on voltage to zero volts according to the soft-turn-off curve.

4. The method of claim 1, wherein activating the receive transistor to receive current from the output terminal of the LDO reduces the output voltage of the LDO, and wherein the size of the receive transistor is smaller than the size of the output transistor of the LDO.

5. A low dropout voltage regulator (LDO), comprising: An output transistor configured to increase or decrease the current supplied to the output terminal of the LDO in response to a decrease or increase in the output voltage of the LDO; and A trigger receiving circuit includes a receiving control configured to generate a receiving control signal that remains at an on-state voltage when the increase in the output voltage exceeds a threshold to activate a receiving transistor to receive current from the output of the LDO, and the receiving control is configured to gradually change the receiving control signal during a off-state period to deactivate the receiving transistor when the output voltage no longer exceeds the threshold.

6. The low dropout regulator (LDO) according to claim 5, wherein: The decrease or increase in the output voltage is caused by the decrease or increase in the load coupled to the output terminal of the LDO; The trigger receiving circuit includes a receiving trigger, which is configured to generate a trigger signal that remains at the trigger voltage for the on-time when the output voltage exceeds the threshold. The threshold is the reference voltage plus the offset voltage; and The receive trigger includes a pair of transistors that are mismatched in size at a ratio corresponding to the offset voltage.

7. The low dropout voltage regulator (LDO) according to claim 6, wherein: The receiving control is coupled between the receiving trigger and the gate of the receiving transistor, and the receiving control is configured to generate the receiving control signal based on the trigger signal, the receiving control signal controlling the receiving transistor; and The receive control signal is at an on-state voltage during the on-state period to activate the receive transistor, and after the on-state period, the receive control signal decreases during the off-state period according to a soft-turn-off curve to deactivate the receive transistor.

8. The low dropout regulator (LDO) of claim 7, wherein the soft-turn-off curve for deactivating the receiving transistor produces a load transient response below a predetermined value.

9. The low dropout regulator (LDO) of claim 7, wherein the receiving control includes a capacitor that is charged during the on-time and discharged during the off-time, the capacitor being coupled to the gate of the receiving transistor such that the soft-turn-off curve corresponds to the voltage of the capacitor when it is discharging.

10. The low dropout regulator (LDO) of claim 7, wherein the output transistor is of a first size and the receiving transistor is of a second size, the first size being larger than the second size.

11. The low dropout regulator (LDO) of claim 7, wherein the output transistor is not turned off when the trigger receiving circuit is activated.

12. A trigger receiving circuit for a linear regulator, comprising: A receive trigger, coupled to the output voltage of the linear regulator, is configured to generate a trigger signal that remains at the trigger voltage during the on-time when the output voltage of the linear regulator is above a threshold. A receiving control receives the trigger signal and generates a receiving control signal in response, wherein the receiving control signal is maintained at an on-voltage during the on-period and then gradually decreases during the off-period when the output voltage drops below the threshold; and A receiving transistor is activated by the turn-on voltage during the turn-on period to receive current from the output of the linear regulator, and is then gradually deactivated during the turn-off period.

13. The trigger receiving circuit for a linear regulator according to claim 12, wherein gradually deactivating the receiving transistor during the off period reduces the load transient response of the linear regulator caused by the on-to-off switching of the receiving transistor.

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