A wide input range fast transient response linear regulator without off-chip capacitor

Abstract

The application relates to a wide-input-range fast transient response linear voltage stabilizer without off-chip capacitance, which is designed to be a cycle folding common-source common-gate operational amplifier circuit, a rail-to-rail high-swing super source follower circuit, a dynamic peak detection circuit, a dynamic peak elimination circuit, and a power stage circuit containing an NMOS tube Mp and a resistor, so as to build the fast transient response linear voltage stabilizer, improve the transient characteristics of the low-dropout linear voltage stabilizer without off-chip capacitance, and realize stable work under low input voltage, have multifunctionality, and meet the needs of the continuous improvement of single-chip integration and the continuous development of digital-analog hybrid technology.

Description

Technical Field

[0001] This invention relates to a fast transient response linear regulator with a wide input range and no external capacitor, belonging to the field of linear regulator technology. Background Technology

[0002] Low-dropout linear regulators (LDOs) play a crucial role in integrated power management and are the power supply modules in System-on-Chip (SoC). With advancements in SoC technology, different modules have varying power supply voltage requirements to achieve optimal performance while minimizing power consumption.

[0003] To meet the diverse voltage requirements of on-chip systems, multiple low-dropout linear regulators (LDOs) are needed, especially for modules designed for low power consumption and operating at extremely low supply voltages. Each LDO requires individual design to ensure optimal efficiency. Using traditional LDOs with uF-level capacitors would increase the number of chip interfaces. Therefore, traditional LDOs are no longer suitable, and using capacitorless LDOs to power various modules of the on-chip system is a more appropriate solution. With increasing integration and the development of mixed-signal technology, the digital section, as the control part of the chip, has become an indispensable component in almost all chips. However, in on-chip systems, digital modules frequently switch, and the lack of external capacitors can lead to significant overshoot and undershoot voltages, as well as long recovery times. This can cause erroneous level switching within the digital module, which is particularly critical under low-voltage supply conditions. Therefore, improving the transient characteristics of capacitorless LDOs is crucial. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a fast transient response linear regulator with a wide input range and no external capacitor, which can suppress overshoot and undershoot when the load current jumps, and reduce the recovery time when the load current jumps, so as to meet the transient response requirements of a low dropout linear regulator with no external capacitor for on-chip system power supply, while having a wide output range.

[0005] To solve the above-mentioned technical problems, this invention adopts the following technical solution: This invention designs a fast transient response linear regulator with a wide input range and no external capacitor, used to achieve linear voltage regulation for the signal to be regulated. It includes an NMOS transistor Mp, resistors R1 and R2, and a cyclic folded cascode operational amplifier circuit. The power supply terminal, ground terminal, and bias voltage terminal of the cyclic folded cascode operational amplifier circuit are respectively connected to the power supply V. batThe circuit consists of: ground (GND) and bias voltage; the drain of the NMOS transistor Mp forms the input terminal of the linear regulator, used to receive the signal to be regulated; the output terminal of the cyclic folded common-source common-gate operational amplifier circuit is connected to the gate of the NMOS transistor Mp; the source of the NMOS transistor Mp is connected to ground in series with resistors R1 and R2, and the connection between the source of the NMOS transistor Mp and resistor R1 forms the output terminal of the regulator, and the connection between resistors R1 and R2 is connected to the feedback terminal of the cyclic folded common-source common-gate operational amplifier circuit.

[0006] As a preferred embodiment of the present invention, it further includes a rail-to-rail high-swing super source follower circuit, wherein the power supply terminal, ground terminal, and bias voltage terminal of the rail-to-rail high-swing super source follower circuit are respectively connected to power supply V. bat Grounding (GND) and bias voltage; the output terminal of the cyclic folded common-source common-gate operational amplifier circuit is connected to the input terminal of the rail-to-rail high-swing super source follower circuit, and the output terminal of the rail-to-rail high-swing super source follower circuit is connected to the gate of the NMOS transistor Mp.

[0007] As a preferred embodiment of the present invention: the rail-to-rail high-swing super source follower circuit includes PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, and MP8, NMOS transistors MN1, MN2, MN3, and MN4, and a bipolar NPN transistor Q1. The sources of PMOS transistors MP1, MP2, MP3, MP5, MP7, and MP8 all constitute the power supply terminals of the rail-to-rail high-swing super source follower circuit. The gate of PMOS transistor MP1 is connected to the gate of PMOS transistor MP2, and this connection terminal constitutes the bias voltage terminal of the rail-to-rail high-swing super source follower circuit, and is externally connected to a bias voltage V. P1 The gates of PMOS transistors MP3 and MP5 respectively form the bias voltage terminals of the rail-to-rail high-swing super source follower circuit, and are externally connected to a bias voltage V. P1 The drain of PMOS transistor MP1 is connected to the drain of NMOS transistor MN1. The gate of NMOS transistor MN1 forms the bias voltage terminal of the rail-to-rail high-swing super source follower circuit, and is externally biased by voltage V. N2The source of NMOS transistor MN1, the drain of PMOS transistor MP4, the drain of NMOS transistor MN2, the drain of PMOS transistor MP6, and the base of bipolar NPN transistor Q1 are connected together; the gate of PMOS transistor MP4 is connected to the gate of PMOS transistor MP6, and this connection constitutes the input terminal of the rail-to-rail high-swing super source follower circuit; the drain of PMOS transistor MP2, the source of NMOS transistor MN3, and the collector of bipolar NPN transistor Q1 are connected together, and this connection constitutes the output terminal of the rail-to-rail high-swing super source follower circuit; the PMOS transistor MP3... The drain of PMOS transistor MP4 is connected to the source of PMOS transistor MP5; the drains of PMOS transistors MP5, MP6, and MP7, and the gate of NMOS transistor MN3 are connected together, with the drain of PMOS transistor MP7 connected to the drain of NMOS transistor MN3; the gates of PMOS transistors MP7 and MP8, the drain of PMOS transistor MP8, and the drain of NMOS transistor MN4 are connected together; the gates of NMOS transistors MN2 and MN4 both form the bias voltage terminals of the rail-to-rail high-swing super source follower circuit, and are externally biased by a voltage V. N1 The source of NMOS transistor MN2, the source of NMOS transistor MN4, and the emitter of bipolar NPN transistor Q1 all constitute the ground terminal of the rail-to-rail high-swing super source follower circuit.

[0008] As a preferred embodiment of the present invention, it further includes a dynamic peak detection circuit and a dynamic peak elimination circuit, wherein the power supply terminal, ground terminal, and bias voltage terminal of the dynamic peak detection circuit and the dynamic peak elimination circuit are respectively connected to a power supply V. bat Grounding (GND) and bias voltage are connected; the connection between the source of NMOS transistor Mp and resistor R1 is connected to the feedback input of the dynamic peak detection circuit; the first and second outputs of the dynamic peak detection circuit are connected to the first and second inputs of the dynamic peak elimination circuit, respectively; the output of the dynamic peak elimination circuit is connected to the output of the rail-to-rail high swing super source circuit, and this connection point is connected to the gate of NMOS transistor Mp.

[0009] As a preferred embodiment of the present invention: the dynamic peak detection circuit includes PMOS transistor MP9, PMOS transistor MP10, NMOS transistor MN5, NMOS transistor MN6, and resistor R. H1 Resistance R H2 Capacitor C H1 Capacitor C H2 In this circuit, the sources of PMOS transistors MP9 and MP10 both constitute the power supply terminals of the dynamic peak detection circuit; resistor R H1 One end of the circuit forms the bias voltage terminal of the dynamic peak detection circuit, and is connected to an external bias voltage V. P1The gate of PMOS transistor MP9, the gate of PMOS transistor MP10, and resistor R. H1 The other end, capacitor C H1 One end of the four are connected together; capacitor C H1 The other end is connected to capacitor C H2 One end of the circuit is connected to the other end, and this connection point constitutes the feedback input terminal of the dynamic peak detection circuit; the drain of PMOS transistor MP9 is connected to the drain of NMOS transistor MN5, and this connection point constitutes the first output terminal of the dynamic peak detection circuit; the drain of PMOS transistor MP10 is connected to the drain of NMOS transistor MN6, and this connection point constitutes the second output terminal of the dynamic peak detection circuit; the gate of NMOS transistor MN5, the gate of NMOS transistor MN6, and resistor R... H2 One end of the capacitor C H2 The other end is connected to the four components; resistor R H2 The other end forms the bias voltage terminal of the dynamic peak detection circuit, and is connected to an external bias voltage V. N1 The source of NMOS transistor MN5 and the source of NMOS transistor MN6 form the ground terminal of the dynamic peak detection circuit.

[0010] As a preferred embodiment of the present invention: the dynamic peak cancellation circuit includes PMOS transistors MP11, MP12, MP13, MP14, MP15, MP16, and NMOS transistors MN7, MN8, MN9, MN10, MN11, and MN12. The sources of PMOS transistors MP16, MP14, MP13, and MP11 all constitute the power supply terminals of the dynamic peak cancellation circuit. The gate of PMOS transistor MP13 constitutes the bias voltage terminal of the dynamic peak cancellation circuit and is externally connected to a bias voltage V. P1The gates of PMOS transistors MP16, MP11, and MP12 are connected, and this connection constitutes the first input terminal of the dynamic peak cancellation circuit; the drain of PMOS transistor MP14 is connected to the source of PMOS transistor MP15; the gates of PMOS transistors MP14, MP15, and MP15, the drain of NMOS transistor MN11, and MP12 are connected; the drain of PMOS transistor MP11 is connected to the source of PMOS transistor MP12; the drain of PMOS transistor MP13, N... The drain of MOSFET MN9, the gate of NMOS transistor MN9, the gate of NMOS transistor MN10, and the gate of NMOS transistor MN7 are connected together; the source of NMOS transistor MN9 is connected to the drain of NMOS transistor MN10; the drain of NMOS transistor MN7, the gate of NMOS transistor MN8, and the gate of NMOS transistor MN12 are connected together, and this connection terminal constitutes the second input terminal of the dynamic peak cancellation circuit; the source of NMOS transistor MN7 is connected to the source of NMOS transistor MN8; the gate of NMOS transistor MN11 constitutes the bias voltage terminal of the dynamic peak cancellation circuit and is externally connected to a bias voltage V. N1 The drain of PMOS transistor MP16 is connected to the drain of NMOS transistor MN12, and this connection terminal forms the output terminal of the dynamic peak cancellation circuit. The sources of NMOS transistors MN12, MN11, MN10, and MN8 all form the ground terminal of the dynamic peak cancellation circuit.

[0011] As a preferred embodiment of the present invention: the cyclic folded cascode operational amplifier circuit includes PMOS transistors MP17, MP18, MP19, MP20, MP21, MP22, MP23, MP24, MP25, and NMOS transistors MN13, MN14, MN15, MN16, MN17, MN18, MN19, and MN20; wherein, the gate of PMOS transistor MP17 constitutes the bias voltage terminal of the cyclic folded cascode operational amplifier circuit and is externally connected to a bias voltage V. P1The sources of PMOS transistors MP17, MP24, and MP25 constitute the power supply terminals of the cyclically folded cascode operational amplifier circuit. The drains of PMOS transistors MP17, MP18, MP19, MP21, and MP20 are connected together. The gates of PMOS transistors MP18 and MP19 are connected, and this connection terminal constitutes the feedback terminal of the cyclically folded cascode operational amplifier circuit. The gates of PMOS transistors MP21 and MP20 are connected, and this connection terminal is externally connected to a reference voltage V. REF The drains of PMOS transistor MP18, NMOS transistor MN13, and NMOS transistor MN17 are connected together; the drains of PMOS transistor MP19, NMOS transistor MN20, NMOS transistor MN15, and NMOS transistor MN16 are connected together; the drains of PMOS transistor MP21, NMOS transistor MN19, NMOS transistor MN14, and NMOS transistor MN13 are connected together; the gate of NMOS transistor MN19 is connected to the gate of NMOS transistor MN20, and this connection terminal constitutes the bias voltage terminal of the cyclic folded cascode operational amplifier circuit, and is externally connected to a bias voltage V. N2 The source of NMOS transistor MN19, the source of NMOS transistor MN20, the gate of NMOS transistor MN14, and the gate of NMOS transistor MN15 are connected together; the drain of PMOS transistor MP20, the drain of NMOS transistor MN16, and the source of NMOS transistor MN18 are connected together; the gate of NMOS transistor MN17 is connected to the gate of NMOS transistor MN18, and this connection terminal constitutes the bias voltage terminal of the cyclic folded cascode operational amplifier circuit, and is externally connected to the bias voltage V. N2 The drain of PMOS transistor MP24 is connected to the source of PMOS transistor MP22; the drain of PMOS transistor MP25 is connected to the source of PMOS transistor MP23; the gates of PMOS transistor MP24, MP25, MP22, and NMOS transistor MN17 are connected together; the gate of PMOS transistor MP22 is connected to the gate of PMOS transistor MP23; the drain of PMOS transistor MP23 is connected to the drain of NMOS transistor MN18, and this connection terminal constitutes the output terminal of the cyclic folded cascode operational amplifier circuit; the sources of NMOS transistors MN13, MN14, MN15, and MN16 constitute the ground terminal of the cyclic folded cascode operational amplifier circuit.

[0012] The fast transient response linear regulator with wide input range and no external capacitor described in this invention has the following technical advantages compared with the prior art:

[0013] (1) The present invention designs a fast transient response linear regulator with a wide input range and no external capacitor. It designs a cyclic folded common source common gate operational amplifier circuit, a rail-to-rail high swing super source follower circuit, a dynamic peak detection circuit, and a dynamic peak elimination circuit. Combined with a power stage circuit including an NMOS transistor Mp and a resistor, the fast transient response linear regulator under the design is constructed, which improves the transient characteristics of the low dropout linear regulator without external capacitor. Compared with the traditional low dropout linear regulator, the design of the present invention can suppress overshoot and undershoot when the load current jumps, and also reduce the recovery time when the load current jumps. While meeting the transient response of the on-chip system, it has a large load current range and a wide input range, and achieves stable operation under low input voltage. It has multiple functions and meets the needs of the continuous improvement of single-chip integration and the continuous development of mixed digital-analog technology. Attached Figure Description

[0014] Figure 1 This is a circuit diagram of the fast transient response linear regulator with wide input range and no external capacitor designed in this invention;

[0015] Figure 2 This is a small-signal diagram of the fast transient response linear regulator designed in this invention;

[0016] Figure 3 These are the loop Bode plot simulation results of the fast transient response linear regulator designed in this invention;

[0017] Figure 4 This is the transient response simulation waveform of the fast transient response linear regulator designed in this invention when the load changes;

[0018] Figure 5 The simulation results show the output voltage of the fast transient response linear regulator designed in this invention as a function of load current.

[0019] Figure 6 This is the simulation result of the output voltage of the fast transient response linear regulator designed in this invention changing with the input voltage. Detailed Implementation

[0020] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0021] This invention presents a wide-input-range, capacitor-free, fast transient response linear regulator designed for linear voltage regulation of signals to be regulated. In practical applications, such as... Figure 1As shown, the specific design includes an NMOS transistor Mp, resistors R1 and R2, a cyclic folded cascode operational amplifier circuit, a rail-to-rail high-swing super source follower circuit, a dynamic peak detection circuit, and a dynamic peak elimination circuit. The power supply, ground, and bias voltage terminals of each circuit are connected to the power supply V. bat Ground (GND) and bias voltage.

[0022] In specific structural design, such as Figure 1 As shown, the drain of NMOS transistor Mp forms the input terminal of the linear regulator, used to receive the signal to be regulated. The source of NMOS transistor Mp is connected to ground in series with resistors R1 and R2. The connection between the source of NMOS transistor Mp and resistor R1 forms the output terminal of the regulator. The connection between the source of NMOS transistor Mp and resistor R1 is connected to the feedback input terminal of the dynamic peak detection circuit. The connection between resistors R1 and R2 is connected to the feedback terminal of the cyclic folded cascode operational amplifier circuit. The first and second output terminals of the dynamic peak detection circuit are connected to the first and second input terminals of the dynamic peak elimination circuit, respectively. The output terminal of the cyclic folded cascode operational amplifier circuit is connected to the input terminal of the rail-to-rail high-swing super source follower circuit. The output terminal of the rail-to-rail high-swing super source follower circuit and the output terminal of the dynamic peak elimination circuit are connected and converged, and this converged terminal is connected to the gate of NMOS transistor Mp.

[0023] Regarding the structure of the fast transient response linear regulator described above, further detailed structural design will be carried out, including, for example... Figure 1 As shown, the specific design of the cyclic folded cascode operational amplifier circuit includes PMOS transistors MP17, MP18, MP19, MP20, MP21, MP22, MP23, MP24, MP25, and NMOS transistors MN13, MN14, MN15, MN16, MN17, MN18, MN19, and MN20. The gate of PMOS transistor MP17 forms the bias voltage terminal of the cyclic folded cascode operational amplifier circuit and is externally connected to a bias voltage V. P1The sources of PMOS transistors MP17, MP24, and MP25 constitute the power supply terminals of the cyclically folded cascode operational amplifier circuit. The drains of PMOS transistors MP17, MP18, MP19, MP21, and MP20 are connected together. The gates of PMOS transistors MP18 and MP19 are connected, and this connection terminal constitutes the feedback terminal of the cyclically folded cascode operational amplifier circuit. The gates of PMOS transistors MP21 and MP20 are connected, and this connection terminal is externally connected to a reference voltage V. REF The drains of PMOS transistor MP18, NMOS transistor MN13, and NMOS transistor MN17 are connected together; the drains of PMOS transistor MP19, NMOS transistor MN20, NMOS transistor MN15, and NMOS transistor MN16 are connected together; the drains of PMOS transistor MP21, NMOS transistor MN19, NMOS transistor MN14, and NMOS transistor MN13 are connected together; the gate of NMOS transistor MN19 is connected to the gate of NMOS transistor MN20, and this connection terminal constitutes the bias voltage terminal of the cyclic folded cascode operational amplifier circuit, and is externally connected to a bias voltage V. N2 The source of NMOS transistor MN19, the source of NMOS transistor MN20, the gate of NMOS transistor MN14, and the gate of NMOS transistor MN15 are connected together; the drain of PMOS transistor MP20, the drain of NMOS transistor MN16, and the source of NMOS transistor MN18 are connected together; the gate of NMOS transistor MN17 is connected to the gate of NMOS transistor MN18, and this connection terminal constitutes the bias voltage terminal of the cyclic folded cascode operational amplifier circuit, and is externally connected to the bias voltage V. N2 The drain of PMOS transistor MP24 is connected to the source of PMOS transistor MP22; the drain of PMOS transistor MP25 is connected to the source of PMOS transistor MP23; the gates of PMOS transistor MP24, MP25, MP22, and NMOS transistor MN17 are connected together; the gate of PMOS transistor MP22 is connected to the gate of PMOS transistor MP23; the drain of PMOS transistor MP23 is connected to the drain of NMOS transistor MN18, and this connection terminal constitutes the output terminal of the cyclic folded cascode operational amplifier circuit; the sources of NMOS transistors MN13, MN14, MN15, and MN16 constitute the ground terminal of the cyclic folded cascode operational amplifier circuit.

[0024] Rail-to-rail high swing super source follow circuit such as Figure 1As shown, the specific design includes PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, and MP8, NMOS transistors MN1, MN2, MN3, and MN4, and a bipolar NPN transistor Q1. The sources of PMOS transistors MP1, MP2, MP3, MP5, MP7, and MP8 all constitute the power supply terminals of the rail-to-rail high-swing super source follower circuit. The gate of PMOS transistor MP1 is connected to the gate of PMOS transistor MP2, and this connection terminal constitutes the bias voltage terminal of the rail-to-rail high-swing super source follower circuit, which is externally connected to a bias voltage V. P1 The gates of PMOS transistors MP3 and MP5 respectively form the bias voltage terminals of the rail-to-rail high-swing super source follower circuit, and are externally connected to a bias voltage V. P1 The drain of PMOS transistor MP1 is connected to the drain of NMOS transistor MN1. The gate of NMOS transistor MN1 forms the bias voltage terminal of the rail-to-rail high-swing super source follower circuit, and is externally biased by voltage V. N2 The source of NMOS transistor MN1, the drain of PMOS transistor MP4, the drain of NMOS transistor MN2, the drain of PMOS transistor MP6, and the base of bipolar NPN transistor Q1 are connected together; the gate of PMOS transistor MP4 is connected to the gate of PMOS transistor MP6, and this connection constitutes the input terminal of the rail-to-rail high-swing super source follower circuit; the drain of PMOS transistor MP2, the source of NMOS transistor MN3, and the collector of bipolar NPN transistor Q1 are connected together, and this connection constitutes the output terminal of the rail-to-rail high-swing super source follower circuit; the PMOS transistor MP3... The drain of PMOS transistor MP4 is connected to the source of PMOS transistor MP5; the drains of PMOS transistors MP5, MP6, and MP7, and the gate of NMOS transistor MN3 are connected together, with the drain of PMOS transistor MP7 connected to the drain of NMOS transistor MN3; the gates of PMOS transistors MP7 and MP8, the drain of PMOS transistor MP8, and the drain of NMOS transistor MN4 are connected together; the gates of NMOS transistors MN2 and MN4 both form the bias voltage terminals of the rail-to-rail high-swing super source follower circuit, and are externally biased by a voltage V. N1 The source of NMOS transistor MN2, the source of NMOS transistor MN4, and the emitter of bipolar NPN transistor Q1 all constitute the ground terminal of the rail-to-rail high-swing super source follower circuit.

[0025] Dynamic peak detection circuit such as Figure 1As shown, the specific design includes PMOS transistor MP9, PMOS transistor MP10, NMOS transistor MN5, NMOS transistor MN6, and resistor R. H1 Resistance R H2 Capacitor C H1 Capacitor C H2 In this circuit, the sources of PMOS transistors MP9 and MP10 both constitute the power supply terminals of the dynamic peak detection circuit; resistor R H1 One end of the circuit forms the bias voltage terminal of the dynamic peak detection circuit, and is connected to an external bias voltage V. P1 The gate of PMOS transistor MP9, the gate of PMOS transistor MP10, and resistor R. H1 The other end, capacitor C H1 One end of the four are connected together; capacitor C H1 The other end is connected to capacitor C H2 One end of the circuit is connected to the other end, and this connection point constitutes the feedback input terminal of the dynamic peak detection circuit; the drain of PMOS transistor MP9 is connected to the drain of NMOS transistor MN5, and this connection point constitutes the first output terminal of the dynamic peak detection circuit; the drain of PMOS transistor MP10 is connected to the drain of NMOS transistor MN6, and this connection point constitutes the second output terminal of the dynamic peak detection circuit; the gate of NMOS transistor MN5, the gate of NMOS transistor MN6, and resistor R... H2 One end of the capacitor C H2 The other end is connected to the four components; resistor R H2 The other end forms the bias voltage terminal of the dynamic peak detection circuit, and is connected to an external bias voltage V. N1 The source of NMOS transistor MN5 and the source of NMOS transistor MN6 form the ground terminal of the dynamic peak detection circuit.

[0026] Dynamic peak elimination circuit, such as Figure 1 As shown, the specific design includes PMOS transistors MP11, MP12, MP13, MP14, MP15, MP16, and NMOS transistors MN7, MN8, MN9, MN10, MN11, and MN12. The sources of PMOS transistors MP16, MP14, MP13, and MP11 all constitute the power supply terminals of the dynamic peak cancellation circuit. The gate of PMOS transistor MP13 constitutes the bias voltage terminal of the dynamic peak cancellation circuit and is externally connected to a bias voltage V. P1The gates of PMOS transistors MP16, MP11, and MP12 are connected, and this connection constitutes the first input terminal of the dynamic peak cancellation circuit; the drain of PMOS transistor MP14 is connected to the source of PMOS transistor MP15; the gates of PMOS transistors MP14, MP15, and MP15, the drain of NMOS transistor MN11, and MP12 are connected; the drain of PMOS transistor MP11 is connected to the source of PMOS transistor MP12; the drain of PMOS transistor MP13, N... The drain of MOSFET MN9, the gate of NMOS transistor MN9, the gate of NMOS transistor MN10, and the gate of NMOS transistor MN7 are connected together; the source of NMOS transistor MN9 is connected to the drain of NMOS transistor MN10; the drain of NMOS transistor MN7, the gate of NMOS transistor MN8, and the gate of NMOS transistor MN12 are connected together, and this connection terminal constitutes the second input terminal of the dynamic peak cancellation circuit; the source of NMOS transistor MN7 is connected to the source of NMOS transistor MN8; the gate of NMOS transistor MN11 constitutes the bias voltage terminal of the dynamic peak cancellation circuit and is externally connected to a bias voltage V. N1 The drain of PMOS transistor MP16 is connected to the drain of NMOS transistor MN12, and this connection terminal forms the output terminal of the dynamic peak cancellation circuit. The sources of NMOS transistors MN12, MN11, MN10, and MN8 all form the ground terminal of the dynamic peak cancellation circuit.

[0027] Further analysis of the optimal technical solution designed based on this invention reveals that the first stage consists of a cyclically folded cascode operational amplifier circuit with common-mode feedback, exhibiting high slew rate, high gain, and a high gain-bandwidth product. The input transistor is divided into two parts, each carrying a constant and equal current, with the mirror current ratio as follows: Figure 1 As shown, their cross-connection ensures that the small-signal currents applied to the sources of NMOS transistors MN17 and MN18 are in the same direction. Compared with the traditional cyclic folded cascode op-amp, using two NMOS transistors MN19 and MN20 as common-mode feedback resistors instead of active loads increases the gain of the first-stage error amplifier, improves the overall DC gain at steady state, and improves the accuracy of the output voltage.

[0028] The second stage is a rail-to-rail high-swing super source follower circuit. Compared to a traditional super source follower, an NMOS transistor MN3 is inserted at the output of the buffer. Its gate-source voltage follows the changes in the output load current of the low-dropout linear regulator (LDO). When the load current is large, the NMOS transistor MN3 acts as a level shifter. This maximizes the driving capability of the buffer for the power transistor. A simple circuit structure consisting of PMOS transistors MP1, MP2, MP3, NMOS transistor MN1, and MP4 can pull the buffer output close to the power rail under light load conditions, and can keep the current Ia flowing through NMOS transistor MN2 very small without affecting its function. When the input voltage remains constant, the increase in output voltage causes an increase in the drain current of PMOS transistor MP6, thereby increasing the total current flowing into the output node. Through this feedback mechanism, the buffer impedance is reduced by a factor of (1+β). The buffer current bias will follow the output load current over a large range and increase the slew rate during transient current jumps. The buffer in this invention has a wider range of output voltage and output current, and is easier to maintain stability due to the reduced output impedance.

[0029] like Figure 1 The dynamic peak detection circuit and dynamic peak elimination circuit shown can reduce the change in output voltage when the load current jumps. The dynamic peak detection circuit detects the change in output voltage and couples it to the gate of PMOS transistor MP16 and NMOS transistor MN12, which activates the push-pull structure formed by PMOS transistor MP16 and NMOS transistor MN12. This generates a differential current, which quickly turns on the self-biased low-voltage common-source common-gate current mirror composed of NMOS transistors MN7, NMOS transistor MN8, PMOS transistor MP13, NMOS transistor MN9, and NMOS transistor MN10. This forms a current amplifier with high swing and high current gain, which charges and discharges the gate capacitor of the power transistor, rapidly changing the operating voltage of the regulator and improving the transient response characteristics.

[0030] like Figure 2 The diagram shown is a small-signal circuit diagram corresponding to the low-dropout linear regulator designed in this invention. The corresponding loop transfer function can be obtained based on the small-signal model.

[0031] The equivalent gain of the first-stage cyclic folded cascode operational amplifier circuit is shown in Equation (1):

[0032] G m1 =[1+g m3a,4a (r o11,12 ||r 01b,2b ||r o3b,4b )]g m1a,b (1)

[0033] The signals from the main feedback loop and the fast dynamic feedback loop are added at the gate of the power transistor in the form of current. The transfer functions of the main feedback loop, the fast dynamic feedback loop, and the overall loop are expressed by the following formulas:

[0034]

[0035]

[0036]

[0037] Among them, G m1 It is the equivalent gain of the cyclically folded cascode operational amplifier circuit; R o This is the equivalent output impedance of the fast transient response linear regulator with wide input range and no external capacitors designed in this invention, i.e., the equivalent output impedance of the VOUT port; C L This invention relates to the parasitic capacitance of the output of a fast transient response linear regulator with a wide input range and no external capacitors, specifically the load capacitance at the VOUT port; G m2 This is the equivalent gain of the dynamic peak detection circuit and the dynamic peak elimination circuit. ω P1 It is the pole located at the output of the first-stage cyclically folded cascode operational amplifier circuit, ω P2 It is the pole located at the output of the low-dropout linear regulator, ω P3 It is the pole located at the gate of the NMOS transistor Mp. The dynamic peak detection circuit and dynamic peak cancellation circuit can be regarded as a bandpass filter, forming a fast feedback loop for rapid response to load transients. To achieve fast response, resistor R... H1 With capacitor C H1 The product remains small, and the resistance R H2 With capacitor C H2 The product of these two factors remains small, causing this pole to be located at a high frequency. Therefore, the impact of the fast dynamic feedback loop on the overall loop stability can be ignored. The entire loop can be approximated as a system with three poles, where the rail-to-rail high-swing super source follower circuit pushes the gate pole of the NMOS transistor Mp to a high frequency.

[0038] like Figure 3 The simulation results of the low-dropout linear regulator loop shown are as follows: with an input voltage of 1.1V and an output voltage of 0.9V, the minimum DC gain of the loop is 72dB under different load current conditions, ensuring accurate output voltage. The feedback loop remains stable under different load currents. Furthermore, the Bode plot and small-signal analysis results are in good agreement, with the dominant pole located at the output of the error amplifier having a major impact on loop stability.

[0039] like Figure 4The transient response waveforms of the low-dropout linear regulator of the present invention are shown. Figure (a) shows the transient response when the load current jumps from 1mA to 200mA with an input voltage of 1.1V and an output voltage of 0.9V, and the load current jump time is 100ns. Simulation results show that the maximum undershoot voltage is 187mV, the maximum overshoot is 198mV, and the slowest recovery time is 0.6us. Figure (b) shows the transient response when the load current jumps from 1mA to 70mA with an input voltage of 1.8V and an output voltage of 1.6V, and the load current jump time is 100ns. Simulation results show that the maximum undershoot voltage is 193mV, the maximum overshoot is 199mV, and the slowest recovery time is 1.3us. Simulation results show that the transient characteristics of the low-dropout linear regulator of the present invention are improved, and it can meet the requirements of being used as a power supply module for an on-chip system without external capacitors.

[0040] like Figure 5 The diagram illustrates the output voltage variation of the low-dropout linear regulator of this invention with load current when the input voltage is 1.1V. The output voltage variation is less than 0.00005V as the load current changes from 1mA to 200mA. Based on simulation results, the load regulation of the low-dropout linear regulator designed in this invention is 0.1976uV / mA.

[0041] like Figure 6 The diagram illustrates how the output voltage of the low-dropout linear regulator of this invention changes with the input voltage. The input voltage changes from 1.1V to 1.9V, and the output voltage change is less than 0.00001V. According to simulation results, the linear regulation of the low-dropout linear regulator designed in this invention is only 0.0124mV / V.

[0042] The above-described technical solution presents a fast transient response linear regulator with a wide input range and no external capacitors. It incorporates a cyclic folded common-source cascode operational amplifier circuit, a rail-to-rail high-swing super source follower circuit, a dynamic peak detection circuit, and a dynamic peak elimination circuit. Combined with a power stage circuit including an NMOS transistor Mp and resistors, this design constructs a fast transient response linear regulator, improving the transient characteristics of a low-dropout linear regulator without external capacitors. Compared to traditional low-dropout linear regulators, this design can suppress overshoot and undershoot during load current transitions and reduce recovery time. While meeting the transient response requirements of on-chip systems, it offers a large load current range and a wide input range, achieving stable operation under low input voltages. This multi-functional design meets the demands of increasing monolithic integration and the continuous development of mixed-signal technology.

[0043] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A fast transient response linear regulator with a wide input range and no external capacitor, used to achieve linear voltage regulation for the signal to be regulated, characterized in that: This includes an NMOS transistor Mp, resistors R1 and R2, a cyclic folded cascode operational amplifier circuit, a rail-to-rail high-swing super source follower circuit, a dynamic peak detection circuit, and a dynamic peak elimination circuit. The power supply, ground, and bias voltage terminals of each circuit are connected to the power supply V. bat Ground (GND) and bias voltage; In this circuit, the drain of NMOS transistor Mp forms the input terminal of the linear regulator, used to receive the signal to be regulated; the source of NMOS transistor Mp is connected to ground via resistors R1 and R2 in series; the connection between the source of NMOS transistor Mp and resistor R1 forms the output terminal of the regulator; the connection between the source of NMOS transistor Mp and resistor R1 is connected to the feedback input terminal of the dynamic peak detection circuit; and the connection between resistors R1 and R2 is connected to the feedback terminal of the cyclic folded cascode operational amplifier circuit; the first and second output terminals of the dynamic peak detection circuit are connected to the first and second input terminals of the dynamic peak elimination circuit, respectively; the output terminal of the cyclic folded cascode operational amplifier circuit is connected to the input terminal of the rail-to-rail high-swing super source follower circuit; the output terminal of the rail-to-rail high-swing super source follower circuit is connected to the gate of NMOS transistor Mp; the output terminal of the dynamic peak elimination circuit and the output terminal of the rail-to-rail high-swing super source follower circuit converge, and this converged terminal is connected to the gate of NMOS transistor Mp. The rail-to-rail high-swing super source follower circuit includes PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, and MP8, NMOS transistors MN1, MN2, MN3, and MN4, and a bipolar NPN transistor Q1. The sources of PMOS transistors MP1, MP2, MP3, MP5, MP7, and MP8 constitute the power supply terminals of the rail-to-rail high-swing super source follower circuit. The gate of PMOS transistor MP1 is connected to the gate of PMOS transistor MP2, and this connection terminal constitutes the bias voltage terminal of the rail-to-rail high-swing super source follower circuit, which is externally connected to a bias voltage V. P1 The gates of PMOS transistors MP3 and MP5 respectively form the bias voltage terminals of the rail-to-rail high-swing super source follower circuit, and are externally connected to a bias voltage V. P1 The drain of PMOS transistor MP1 is connected to the drain of NMOS transistor MN1. The gate of NMOS transistor MN1 forms the bias voltage terminal of the rail-to-rail high-swing super source follower circuit, and is externally biased by voltage V. N2 The source of NMOS transistor MN1, the drain of PMOS transistor MP4, the drain of NMOS transistor MN2, the drain of PMOS transistor MP6, and the base of bipolar NPN transistor Q1 are connected together; the gate of PMOS transistor MP4 is connected to the gate of PMOS transistor MP6, and this connection constitutes the input terminal of the rail-to-rail high-swing super source follower circuit; the drain of PMOS transistor MP2, the source of NMOS transistor MN3, and the collector of bipolar NPN transistor Q1 are connected together, and this connection constitutes the output terminal of the rail-to-rail high-swing super source follower circuit; the PMOS transistor MP3... The drain of PMOS transistor MP4 is connected to the source of PMOS transistor MP5; the drains of PMOS transistors MP5, MP6, and MP7, and the gate of NMOS transistor MN3 are connected together, with the drain of PMOS transistor MP7 connected to the drain of NMOS transistor MN3; the gates of PMOS transistors MP7 and MP8, the drain of PMOS transistor MP8, and the drain of NMOS transistor MN4 are connected together; the gates of NMOS transistors MN2 and MN4 both form the bias voltage terminals of the rail-to-rail high-swing super source follower circuit, and are externally biased by a voltage V. N1 The source of NMOS transistor MN2, the source of NMOS transistor MN4, and the emitter of bipolar NPN transistor Q1 all constitute the ground terminal of the rail-to-rail high-swing super source follower circuit.

2. The wide input range, capacitor-free, fast transient response linear regulator according to claim 1, characterized in that: The dynamic peak detection circuit includes PMOS transistor MP9, PMOS transistor MP10, NMOS transistor MN5, NMOS transistor MN6, and resistor R. H1 Resistance R H2 Capacitor C H1 Capacitor C H2 In this circuit, the sources of PMOS transistors MP9 and MP10 both constitute the power supply terminals of the dynamic peak detection circuit; resistor R H1 One end of the circuit forms the bias voltage terminal of the dynamic peak detection circuit, and is connected to an external bias voltage V. P1 The gate of PMOS transistor MP9, the gate of PMOS transistor MP10, and resistor R. H1 The other end, capacitor C H1 One end of the four are connected together; capacitor C H1 The other end is connected to capacitor C H2 One end of the circuit is connected to the other end, and this connection point constitutes the feedback input terminal of the dynamic peak detection circuit; the drain of PMOS transistor MP9 is connected to the drain of NMOS transistor MN5, and this connection point constitutes the first output terminal of the dynamic peak detection circuit; the drain of PMOS transistor MP10 is connected to the drain of NMOS transistor MN6, and this connection point constitutes the second output terminal of the dynamic peak detection circuit; the gate of NMOS transistor MN5, the gate of NMOS transistor MN6, and resistor R... H2 One end of the capacitor C H2 The other end is connected to the four components; resistor R H2 The other end forms the bias voltage terminal of the dynamic peak detection circuit, and is connected to an external bias voltage V. N1 The source of NMOS transistor MN5 and the source of NMOS transistor MN6 form the ground terminal of the dynamic peak detection circuit.

3. The wide input range, capacitor-free, fast transient response linear regulator according to claim 1, characterized in that: The dynamic peak cancellation circuit includes PMOS transistors MP11, MP12, MP13, MP14, MP15, and MP16, and NMOS transistors MN7, MN8, MN9, MN10, MN11, and MN12. The sources of PMOS transistors MP16, MP14, MP13, and MP11 all constitute the power supply terminals of the dynamic peak cancellation circuit. The gate of PMOS transistor MP13 constitutes the bias voltage terminal of the dynamic peak cancellation circuit and is externally connected to a bias voltage V. P1 The gates of PMOS transistors MP16, MP11, and MP12 are connected, and this connection constitutes the first input terminal of the dynamic peak cancellation circuit; the drain of PMOS transistor MP14 is connected to the source of PMOS transistor MP15; the gates of PMOS transistors MP14, MP15, and MP15, the drain of NMOS transistor MN11, and MP12 are connected; the drain of PMOS transistor MP11 is connected to the source of PMOS transistor MP12; the drain of PMOS transistor MP13, N... The drain of MOSFET MN9, the gate of NMOS transistor MN9, the gate of NMOS transistor MN10, and the gate of NMOS transistor MN7 are connected together; the source of NMOS transistor MN9 is connected to the drain of NMOS transistor MN10; the drain of NMOS transistor MN7, the gate of NMOS transistor MN8, and the gate of NMOS transistor MN12 are connected together, and this connection terminal constitutes the second input terminal of the dynamic peak cancellation circuit; the source of NMOS transistor MN7 is connected to the drain of NMOS transistor MN8; the gate of NMOS transistor MN11 constitutes the bias voltage terminal of the dynamic peak cancellation circuit and is externally connected to a bias voltage V. N1 The drain of PMOS transistor MP16 is connected to the drain of NMOS transistor MN12, and this connection terminal forms the output terminal of the dynamic peak cancellation circuit. The sources of NMOS transistors MN12, MN11, MN10, and MN8 all form the ground terminal of the dynamic peak cancellation circuit.

4. The fast transient response linear regulator with wide input range and no external capacitor as described in claim 1, characterized in that: The cyclic folded cascode operational amplifier circuit includes PMOS transistors MP17, MP18, MP19, MP20, MP21, MP22, MP23, MP24, MP25, and NMOS transistors MN13, MN14, MN15, MN16, MN17, MN18, MN19, and MN20. The gate of PMOS transistor MP17 forms the bias voltage terminal of the cyclic folded cascode operational amplifier circuit and is externally connected to a bias voltage V. P1 The sources of PMOS transistors MP17, MP24, and MP25 constitute the power supply terminals of the cyclically folded cascode operational amplifier circuit. The drains of PMOS transistors MP17, MP18, MP19, MP21, and MP20 are connected together. The gates of PMOS transistors MP18 and MP19 are connected, and this connection terminal constitutes the feedback terminal of the cyclically folded cascode operational amplifier circuit. The gates of PMOS transistors MP21 and MP20 are connected, and this connection terminal is externally connected to a reference voltage V. REF The drains of PMOS transistor MP18, NMOS transistor MN13, and NMOS transistor MN17 are connected together; the drains of PMOS transistor MP19, NMOS transistor MN20, NMOS transistor MN15, and NMOS transistor MN16 are connected together; the drains of PMOS transistor MP21, NMOS transistor MN19, NMOS transistor MN14, and NMOS transistor MN13 are connected together; the gate of NMOS transistor MN19 is connected to the gate of NMOS transistor MN20, and this connection terminal constitutes the bias voltage terminal of the cyclic folded cascode operational amplifier circuit, and is externally connected to a bias voltage V. N2 The source of NMOS transistor MN19, the source of NMOS transistor MN20, the gate of NMOS transistor MN14, and the gate of NMOS transistor MN15 are connected together; the drain of PMOS transistor MP20, the drain of NMOS transistor MN16, and the source of NMOS transistor MN18 are connected together; the gate of NMOS transistor MN17 is connected to the gate of NMOS transistor MN18, and this connection terminal constitutes the bias voltage terminal of the cyclic folded cascode operational amplifier circuit, and is externally connected to the bias voltage V. N2 The drain of PMOS transistor MP24 is connected to the source of PMOS transistor MP22; the drain of PMOS transistor MP25 is connected to the source of PMOS transistor MP23; the gates of PMOS transistor MP24, MP25, MP22, and NMOS transistor MN17 are connected together; the gate of PMOS transistor MP22 is connected to the gate of PMOS transistor MP23; the drain of PMOS transistor MP23 is connected to the drain of NMOS transistor MN18, and this connection terminal constitutes the output terminal of the cyclic folded cascode operational amplifier circuit; the sources of NMOS transistors MN13, MN14, MN15, and MN16 constitute the ground terminal of the cyclic folded cascode operational amplifier circuit.

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