Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate comprises: a display area and a non-display area surrounding the display area, the display area comprises: a plurality of scanning lines extending along a first direction and a plurality of sub-pixels arranged in an array, the display area comprises: a first display area and a second display area, the first display area is located at the periphery of the second display area, the second display area comprises: a light-transmitting display area and a transitional display area, the transitional display area is located at the side of the light-transmitting display area; the light-transmitting display area comprises: m rows and n columns of sub-pixels, the transitional display area comprises: m rows and n columns of sub-pixels, the i-th row of sub-pixels in the light-transmitting display area and the i-th row of sub-pixels in the transitional display area are located in the same row; each sub-pixel located in the transitional display area comprises: a pixel circuit and a light-emitting element, the pixel circuits of the i-th row and i+1-th row of sub-pixels located in the transitional display area are connected to the same scanning line.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] At present, the concept of full-screen mobile phones has received widespread attention in the mobile phone market and is also the development direction of future mobile phones. In this full-screen mobile phone, the camera can be hidden so that the front visible area is almost entirely the screen, so that users can get a better display effect. Summary of the invention

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate, comprising: a display area and a non-display area surrounding the display area, wherein the display area comprises: a plurality of scan lines extending along a first direction and a plurality of sub-pixels arranged in an array, wherein the display area comprises: a first display area and a second display area, wherein the first display area is located at the periphery of the second display area, and the second display area comprises: a light-transmitting display area and a transitional display area, wherein the transitional display area is located at a side of the light-transmitting display area;

[0006] The light-transmitting display area includes: m rows and n columns of sub-pixels, each sub-pixel in the light-transmitting display area includes: a light-emitting element, the light-emitting element of each sub-pixel in the i-th row of the light-transmitting display area is electrically connected to the light-emitting element of the sub-pixel in the i+1-th row of the light-transmitting display area and of the same color, where i is an odd number less than or equal to m;

[0007] The transitional display area comprises: m rows and n columns of sub-pixels, the i-th row of the light-transmitting display area and the i-th row of the transitional display area are located in the same row; each sub-pixel located in the transitional display area comprises: a pixel circuit and a light-emitting element, the light-emitting element of each sub-pixel located in the i-th row of the transitional display area is electrically connected to the light-emitting element of the sub-pixel of the same color located in the i+1-th row of the transitional display area; the pixel circuit and the light-emitting element of the sub-pixel located in the i-th row of the transitional display area are electrically connected, the pixel circuit of the sub-pixel located in the i+1-th row and the j-th column of the transitional display area is electrically connected to the light-emitting element of the sub-pixel located in the i+1-th row and the j-th column of the light-transmitting display area, and j is a positive integer less than or equal to n;

[0008] The pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are connected to the same scan line.

[0009] In some possible implementations, the pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are connected to the first scan line or the second scan line;

[0010] Among them, the first scan line is a scan line that is located in the same row as the i-th row of sub-pixels located in the transition display area and is connected to the sub-pixels located in the first display area; the second scan line is a scan line that is located in the same row as the i+1-th row of sub-pixels located in the transition display area and is connected to the sub-pixels located in the first display area.

[0011] In some possible implementations, the first display area includes: a plurality of sub-pixels, each sub-pixel located in the first display area includes: a pixel circuit and a light-emitting element; at least three sub-pixels located in the same row constitute a pixel unit; the light-emitting element includes: an anode, an organic light-emitting layer and a cathode;

[0012] The anode of the light-emitting element of each sub-pixel in the pixel unit of the i-th row and the k-th column in the light-transmitting display area is electrically connected to the anode of the light-emitting element of a sub-pixel of the same color in the pixel unit of the i+1-th row and the k-th column in the light-transmitting display area, k is a positive integer less than or equal to K, K=n / 3 or n / 4;

[0013] The anode of the light-emitting element of each sub-pixel in the pixel unit of the i-th row and the j-th column in the transition display area is electrically connected to the anode of the light-emitting element of a sub-pixel of the same color in the pixel unit of the i+1-th row and the j-th column in the transition display area;

[0014] The pixel circuit of the sub-pixel in the i+1th row and jth column in the transitional display area is electrically connected to the anode of the light-emitting element of the sub-pixel in the i+1th row and jth column in the light-transmitting display area;

[0015] The pixel circuit of the sub-pixel located in the first display area is electrically connected to the anode of the light emitting element.

[0016] In some possible implementations, the display substrate further includes: a plurality of data lines extending along a second direction, a pixel circuit of a sub-pixel in the i-th row and j-th column located in the transition display area is electrically connected to a first data line, a pixel circuit of a sub-pixel in the i+1-th row and j-th column located in the transition display area is electrically connected to a second data line, and the first direction and the second direction intersect;

[0017] Among them, the first data line is a data line that is located in the same column as the sub-pixel in the i-th row and j-th column located in the transition display area and is connected to the pixel circuit of the sub-pixel located in the first display area; the second data line is a data line that is located in the same column as the sub-pixel in the i+1-th row and j-th column located in the light-transmitting display area and is connected to the pixel circuit of the sub-pixel located in the first display area.

[0018] In some possible implementations, the method further includes: a data connection line, wherein the data connection line and the data line are arranged in a different layer;

[0019] The data connection line is electrically connected to the pixel circuit of the i+1th row and jth column sub-pixel located in the transition display area and the second data line connected to the pixel circuit of the i+1th row and jth column sub-pixel located in the transition display area.

[0020] In some possible implementations, the light-transmitting display area includes: a first side and a second side that are oppositely disposed, and a third side and a fourth side that are oppositely disposed; the transitional display area includes: a first transitional display area and a second transitional display area;

[0021] The first transition display area is located at a first side of the light-transmitting display area, the second transition display area is located at a second side of the light-transmitting display area, and the first transition display area and the second transition display area are arranged along a first direction.

[0022] In some possible implementations, the number of the second display area is at least one.

[0023] In some possible implementations, when the number of the second display area is one, the first display area includes: a first normal display area, a second normal display area, a third normal display area, and a fourth normal display area;

[0024] The kth row of the first normal display area is the same row as the kth row of the light-transmitting display area, and the kth row of the second normal display area is the same row as the kth row of the light-transmitting display area, where k is a positive integer greater than or equal to 1 and less than or equal to m;

[0025] The first normal display area is located on a side of the first transition display area away from the light-transmitting display area, and the second normal display area is located on a side of the second transition display area away from the light-transmitting display area; the third normal display area is located on a third side of the light-transmitting display area, and the fourth normal display area is located on a fourth side of the light-transmitting display area; the third normal display area and the fourth normal display area are arranged along the second direction.

[0026] In some possible implementations, when the pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are connected to the first scanning line, the first scanning line includes: a first scanning portion and a second scanning portion that are spaced apart; the second scanning line includes: a third scanning portion and a fourth scanning portion that are spaced apart and extend along the first direction;

[0027] The first scanning section is electrically connected to the pixel circuits of the i-th row and the i+1-th row of sub-pixels located in the first transition display area and the pixel circuit of the i-th row of sub-pixels located in the first normal display area;

[0028] The second scanning section is electrically connected to the pixel circuits of the i-th row and the i+1-th row of sub-pixels in the second transition display area and the pixel circuit of the i-th row of sub-pixels in the second normal display area respectively;

[0029] The third scanning unit is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area;

[0030] The fourth scanning unit is electrically connected to the pixel circuits of the (i+1)th row of sub-pixels located in the second normal display area.

[0031] In some possible implementations, the first scanning portion includes: a first connecting portion, a second connecting portion, and a third connecting portion, the first connecting portion and the third connecting portion extend along a first direction, and the second connecting portion extends along a second direction;

[0032] The first connection portion is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area, the pixel circuit of the i-th row of sub-pixels located in the first transition display area, and the second connection portion; the second connection portion is electrically connected to the third connection portion; and the third connection portion is electrically connected to the pixel circuit of the i+1-th row of sub-pixels located in the first transition display area;

[0033] The second scanning portion includes: a fourth connecting portion, a fifth connecting portion and a sixth connecting portion, the fourth connecting portion and the sixth connecting portion extend along the first direction, and the fifth connecting portion extends along the second direction;

[0034] The fourth connection portion is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second normal display area, the pixel circuit of the i-th row of sub-pixels located in the second transition display area, and the fifth connection portion respectively; the fifth connection portion is electrically connected to the sixth connection portion; and the sixth connection portion is electrically connected to the pixel circuit of the i+1-th row of sub-pixels located in the second transition display area.

[0035] In some possible implementations, the first scanning portion further includes: a seventh connecting portion extending along the second direction, the seventh connecting portion being electrically connected to the first connecting portion and the third connecting portion respectively;

[0036] The second scanning portion further includes an eighth connecting portion extending along the second direction, wherein the eighth connecting portion is electrically connected to the fourth connecting portion and the sixth connecting portion respectively.

[0037] In some possible implementations, the first scanning line further includes: a first scanning connection portion, and / or the second scanning line further includes: a second scanning portion;

[0038] The first scanning connection part is electrically connected to the first scanning part and the second scanning part respectively;

[0039] The second scanning connection part is electrically connected to the third scanning part and the fourth scanning part respectively.

[0040] In some possible implementations, when the pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are connected to the second scan line, the second scan line includes: a first scan portion and a second scan portion that are spaced apart; the first scan line includes: a third scan portion and a fourth scan portion that are spaced apart and extend along the first direction;

[0041] The first scanning section is electrically connected to the pixel circuits of the i-th row and the i+1-th row of sub-pixels located in the first transition display area and the pixel circuit of the i+1-th row of sub-pixels located in the first normal display area;

[0042] The second scanning section is electrically connected to the pixel circuits of the i-th row and the i+1-th row of sub-pixels in the second transition display area and the pixel circuit of the i+1-th row of sub-pixels in the second normal display area;

[0043] The third scanning unit is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area;

[0044] The fourth scanning unit is electrically connected to the pixel circuits of the i-th row of sub-pixels located in the second normal display area.

[0045] In some possible implementations, the first scanning portion includes: a first connection portion, a second connection portion, and a third connection portion, the first connection portion and the third connection portion extend along the first direction, and the second connection portion extends along the second direction; the first connection portion is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area, the pixel circuit of the i+1th row of sub-pixels located in the first transition display area, and the second connection portion; the second connection portion is electrically connected to the third connection portion; and the third connection portion is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first transition display area;

[0046] The second scanning part includes: a fourth connecting part, a fifth connecting part and a sixth connecting part, the fourth connecting part and the sixth connecting part extend along the first direction, and the fifth connecting part extends along the second direction; the fourth connecting part is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the second normal display area, the pixel circuit of the i+1th row of sub-pixels located in the second transition display area, and the fifth connecting part respectively; the fifth connecting part is electrically connected to the sixth connecting part; and the sixth connecting part is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second transition display area.

[0047] In some possible implementations, the first scanning portion further includes: a seventh connecting portion extending along the second direction, the seventh connecting portion being electrically connected to the first connecting portion and the third connecting portion respectively;

[0048] The second scanning portion further includes an eighth connecting portion extending along the second direction, and the eighth connecting portion is electrically connected to the fourth connecting portion and the sixth connecting portion respectively.

[0049] In some possible implementations, the second scan line further includes: a first scan connection portion, and / or the first scan line further includes: a second scan connection portion;

[0050] The first scanning connection part is electrically connected to the first scanning part and the second scanning part respectively;

[0051] The second scanning connection part is electrically connected to the third scanning part and the fourth scanning part respectively.

[0052] In some possible implementations, when the number of the second display areas is at least two, the first display area includes: a first normal display area, a second normal display area, a third normal display area, a fourth normal display area, and Q-1 fifth normal display areas; the kth row of the first normal display area is the same row as the kth row of the light-transmitting display area, the kth row of the second normal display area is the same row as the kth row of the light-transmitting display area, the kth row of the fifth normal display area is the same row as the kth row of the light-transmitting display area, k is a positive integer greater than or equal to 1 and less than or equal to m, and Q is the number of the second display areas;

[0053] The first normal display area is located on a side of the first transition display area away from the light-transmitting display area, and the second normal display area is located on a side of the second transition display area away from the light-transmitting display area; the third normal display area is located on a third side of the light-transmitting display area, and the fourth normal display area is located on a fourth side of the light-transmitting display area; the third normal display area and the fourth normal display area are arranged along the second direction; the i-th fifth normal display area is located between the i-th second display area and the i+1-th second display area.

[0054] In some possible implementations, when the pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are connected to the first scan line,

[0055] The first scan line is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area, the pixel circuit of the i-th row of sub-pixels located in the first transition display area and the second transition display area of ​​all the second display areas, the pixel circuit of the i+1-th row of sub-pixels located in the first transition display area and the second transition display area of ​​all the second display areas, the pixel circuit of the i-th row of sub-pixels in all the fifth normal display areas, and the pixel circuit of the i-th row of sub-pixels located in the second normal display area;

[0056] The second scan line is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area, the pixel circuit of the i+1th row of sub-pixels located in the second normal display area, and the pixel circuit of the i+1th row of sub-pixels located in all fifth normal display areas;

[0057] The first scanning line includes: a first scanning portion, Q-1 second scanning portions and a third scanning portion, and Q first scanning connecting portions;

[0058] The first scanning section is electrically connected to the pixel circuits of the i-th row of sub-pixels located in the first normal display area and the pixel circuits of the i-th row and the i+1-th row of sub-pixels located in the first transition display area of ​​the first second display area;

[0059] The t-th second scanning section is electrically connected to the pixel circuit of the i-th row of sub-pixels in the t-th fifth normal display area, the pixel circuit of the i-th row and i+1-th row of sub-pixels in the second transition display area of ​​the t-th second display area, and the pixel circuit of the i-th row and i+1-th row of sub-pixels in the first transition display area of ​​the t+1-th second display area, respectively, where t is a positive integer less than Q;

[0060] The third scanning section is electrically connected to the pixel circuits of the i-th row and the i+1-th row of sub-pixels in the second transition display area of ​​the Q-th second display area and the pixel circuit of the i-th row of sub-pixels in the second normal display area;

[0061] The first first scanning connection part is electrically connected to the first scanning part and the first second scanning part respectively, the t-th first scanning connection part is electrically connected to the t-1-th second scanning part and the t-th second scanning part respectively; the Q-th first scanning connection part is electrically connected to the Q-1-th second scanning part and the third scanning part respectively;

[0062] The second scanning line includes: a fourth scanning portion, Q-1 fifth scanning portions and a sixth scanning portion, and Q second scanning connecting portions;

[0063] The fourth scanning unit is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area;

[0064] The t-th fifth scanning unit is electrically connected to the pixel circuit of the i+1-th row of sub-pixels in the t-th fifth normal display area;

[0065] The sixth scanning unit is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the second first display area;

[0066] The first second scanning connection part is electrically connected to the first scanning part and the first second scanning part respectively, the tth second scanning connection part is electrically connected to the t-1th second scanning part and the tth second scanning part respectively; the Qth second scanning connection part is electrically connected to the Q-1th second scanning part and the third scanning part respectively.

[0067] In some possible implementations, when the pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are connected to the second scan line,

[0068] The first scanning line is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area, the pixel circuit of the i-th row of sub-pixels located in the second normal display area, and the pixel circuit of the i-th row of sub-pixels located in all fifth normal display areas respectively;

[0069] The second scan lines are respectively electrically connected to the pixel circuits of the i+1th row of sub-pixels located in the first normal display area, the pixel circuits of the i-th row and the i+1th row of sub-pixels located in the first transition display area and the second transition display area of ​​all the second display areas, the pixel circuits of the i+1th row of sub-pixels in all the fifth normal display areas, and the pixel circuits of the i+1th row of sub-pixels located in the second normal display area;

[0070] The second scanning line comprises: a first scanning portion, Q-1 second scanning portions and a third scanning portion, and Q first scanning connecting portions;

[0071] The first scanning section is electrically connected to the pixel circuits of the i+1th row of sub-pixels located in the first normal display area and the pixel circuits of the i-th row and the i+1th row of sub-pixels located in the first transition display area of ​​the first second display area;

[0072] The t-th second scanning section is electrically connected to the pixel circuits of the i+1-th row of sub-pixels in the t-th fifth normal display area, the pixel circuits of the i-th row and i+1-th row of sub-pixels in the second transition display area of ​​the t-th second display area, and the pixel circuits of the i-th row and i+1-th row of sub-pixels in the first transition display area of ​​the t+1-th second display area;

[0073] The third scanning section is electrically connected to the pixel circuits of the i-th row and i+1-th row of sub-pixels in the second transition display area of ​​the Q-th second display area and the pixel circuit of the i+1-th row of sub-pixels in the second normal display area;

[0074] The first first scanning connection part is electrically connected to the first scanning part and the first second scanning part respectively, the t-th second scanning connection part is electrically connected to the t-1-th second scanning part and the t-th second scanning part respectively; the Q-th second scanning connection part is electrically connected to the Q-1-th second scanning part and the third scanning part respectively;

[0075] The first scanning line includes: a fourth scanning portion, Q-1 fifth scanning portions, a sixth scanning portion and Q second scanning connecting portions;

[0076] The fourth scanning unit is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area;

[0077] The t-th fifth scanning unit is electrically connected to the pixel circuit of the i-th row of sub-pixels in the t-th fifth normal display area;

[0078] The sixth scanning unit is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second normal display area;

[0079] The first second scanning connection part is electrically connected to the first scanning part and the first second scanning part respectively, the tth second scanning connection part is electrically connected to the t-1th second scanning part and the tth second scanning part respectively; the Qth second scanning connection part is electrically connected to the Q-1th second scanning part and the third scanning part respectively.

[0080] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0081] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0083] Figure 1 It is a structural schematic diagram of a display substrate;

[0084] Figure 2 A schematic diagram of a planar structure of a display area of ​​a display substrate provided by an exemplary embodiment;

[0085] Figure 3 A schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure;

[0086] Figure 4 is a schematic diagram of an equivalent circuit of a pixel circuit;

[0087] Figure 5 is a working timing diagram of a pixel circuit;

[0088] Figure 6 A schematic diagram of a display substrate provided by an exemplary embodiment Figure 1 ;

[0089] Figure 7 A schematic structural diagram of a display substrate provided for another exemplary embodiment;

[0090] Figure 8 Schematic diagram of the division of the display area Figure 1 ;

[0091] Fig. 9 Schematic diagram of the division of the display area Figure 2 ;

[0092] Fig.10 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 1 ;

[0093] Fig.11 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 2 ;

[0094] Fig.12 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 3 ;

[0095] Fig.13 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 4 ;

[0096] Fig.14 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 5 ;

[0097] Fig.15 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 6 ;

[0098] Fig.16 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 7 ;

[0099] Fig.17 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 8 ;

[0100] Fig.18 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 1 ;

[0101] Fig.19 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 2 ;

[0102] Fig. 20 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 3 ;

[0103] Fig.21 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 4 ;

[0104] Fig. 22 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 5 ;

[0105] Fig.23 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 6 ;

[0106] Fig.24 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 7 ;

[0107] Fig.25 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 8 ;

[0108] Fig.26 A schematic diagram of multiple scan lines provided for yet another exemplary embodiment Figure 1 ;

[0109] Fig. 27 A schematic diagram of multiple scan lines provided for yet another exemplary embodiment Figure 2 ;

[0110] Fig.28 A schematic diagram of multiple scan lines provided for yet another exemplary embodiment Figure 3 ;

[0111] Fig.29 A schematic diagram of multiple scan lines provided for yet another exemplary embodiment Figure 4 ;

[0112] Fig.30 A timing diagram of some signals provided for an exemplary embodiment;

[0113] Fig.31 A timing diagram of some signals is provided for another exemplary embodiment. DETAILED DESCRIPTION

[0114] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings hereinafter. Note that the embodiments can be implemented in a number of different forms. A person of ordinary skill in the relevant technical field can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0115] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0116] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0117] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0118] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0119] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0120] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0121] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0122] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0123] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0124] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0125] Figure 1 Schematic diagram of the structure of a display substrate. Figure 1 As shown, the display substrate may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver and a pixel array, and the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emitting signal lines (E1 to Eo) and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, a clock signal suitable for the specification of the scan signal driver, a scan start signal, etc. to the scan signal driver, and a clock signal suitable for the specification of the light emitting signal driver, an emission stop signal, etc. to the light emitting signal driver. The data signal driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan signal driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan signal driver may sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may sequentially transmit a scan start signal provided in the form of an on-level pulse to a next-level circuit under the control of a clock signal to generate a scan signal, and m may be a natural number. The luminous signal driver may generate an emission signal to be provided to the luminous signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the luminous signal driver may sequentially provide an emission signal having an off-level pulse to the luminous signal lines E1 to Eo. For example, the luminous signal driver may be constructed in the form of a shift register, and may sequentially transmit a luminous stop signal provided in the form of an off-level pulse to a next-level circuit under the control of a clock signal to generate a luminous signal, and o may be a natural number. The pixel array may include a plurality of sub-pixels Pxij. Each subpixel Pxij may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emitting signal line, and i and j may be natural numbers. Subpixel Pxij may refer to a subpixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0126] The full-screen display product includes: a light-transmitting display area for setting an optical device and a transitional display area located on the side of the light-transmitting display area. The light-transmitting display area and the transitional display area in a full-screen display product are not displayed at the same time, which affects the display effect of the display product.

[0127] Figure 2 A schematic diagram of a planar structure of a display area of ​​a display substrate provided by an exemplary embodiment. Figure 3 Schematic diagram of the structure of the display substrate provided by the embodiment of the present disclosure. Figure 2 and Figure 3 As shown, the display substrate provided by the embodiment of the present disclosure includes: a display area R10 and a non-display area surrounding the display area, the display area includes: a plurality of scanning lines G extending along a first direction and a plurality of sub-pixels P arranged in an array, the display area includes: a first display area R10 and a second display area R20, the first display area R10 is located at the periphery of the second display area R20, the second display area R20 includes: a light-transmitting display area R21 and a transition display area R22, the transition display area R22 is located on the side of the light-transmitting display area R21.

[0128] like Figure 3 As shown, in an exemplary embodiment, the light-transmitting display area includes: m rows and n columns of sub-pixels P, and each sub-pixel located in the light-transmitting display area includes: a light-emitting element 11. The light-emitting element 11 of each sub-pixel located in the i-th row of the light-transmitting display area is electrically connected to the light-emitting element 11 of the sub-pixel of the same color located in the i+1-th row of the light-transmitting display area, where i is an odd number less than or equal to m. Each sub-pixel located in the light-transmitting display area does not include a pixel circuit.

[0129] like Figure 3 As shown, the transition display area includes: m rows and n columns of sub-pixels, the i-th row of sub-pixels in the light-transmitting display area and the i-th row of sub-pixels in the transition display area are located in the same row; each sub-pixel located in the transition display area includes: a pixel circuit 10 and a light-emitting element 11, and the light-emitting element of each sub-pixel in the i-th row of the transition display area is electrically connected to the light-emitting element of the sub-pixel of the same color located in the i+1-th row of the transition display area.

[0130] like Figure 3 As shown, the pixel circuit of the sub-pixel in the i-th row and the light-emitting element in the transition display area are electrically connected, and the pixel circuit of the sub-pixel in the i+1-th row and the j-th column in the transition display area is electrically connected to the light-emitting element of the sub-pixel in the i+1-th row and the j-th column in the light-transmitting display area, where j is a positive integer less than or equal to n.

[0131] like Figure 3 As shown, the pixel circuits of the sub-pixels in the i-th row and the i+1-th row located in the transition display area are connected to the same scan line.

[0132] In an exemplary embodiment, the first display area and the second display area have the same resolution. The resolution (Pixels Per Inch, PPI for short) refers to the number of pixels per unit area, which can be called pixel density. The higher the PPI value, the higher the density at which the display substrate can display the picture, and the richer the details of the picture.

[0133] In an exemplary embodiment, the position of the light-transmitting display area may correspond to the position of the optical device, and has the functions of displaying images and transmitting light, and the transmitted light is received by the optical device. The transitional display area has the functions of displaying images and providing signals to the light-transmitting display area.

[0134] In an exemplary embodiment, the values ​​of m and n can be determined according to the size of the optical device.

[0135] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the light-transmitting display area may be any one or more of the following: rectangular, polygonal, circular, and elliptical, and the optical device may be a fingerprint recognition device, a camera device, or an optical sensor such as 3D imaging, which is not limited in the present disclosure. For example, when the shape of the light-transmitting display area is circular, the diameter of the circle may be approximately 3 mm to 5 mm. For another example, when the shape of the light-transmitting display area is rectangular, the side length of the rectangle may be approximately 3 mm to 5 mm. Figures 2 to 5 The description is made by taking the shape of the light-transmitting display area as a rectangle as an example.

[0136] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the transition display area may be any one or more of the following: rectangular, polygonal, circular, and elliptical.

[0137] In an exemplary embodiment, the shape of the sub-pixel can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon and other polygons, and the arrangement can be X-shaped, cross-shaped or herringbone-shaped, etc., which is not limited in the present disclosure.

[0138] In an exemplary embodiment, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Figure 4 is a schematic diagram of an equivalent circuit of a pixel circuit. Figure 4 As shown, the pixel circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C and 7 signal lines (data signal line Data, first scan signal line S1, second scan signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS).

[0139] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0140] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so that the charge amount of the control electrode of the third transistor T3 is initialized.

[0141] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0142] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between its control electrode and the first electrode.

[0143] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data signal line Data to be input to the pixel circuit.

[0144] The control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be called light emitting transistors. When the on-level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.

[0145] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device to initialize or release the charge accumulated in the first electrode of the light emitting device.

[0146] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal. The first scanning signal line S1 is a scanning signal line in the pixel circuit of the current display row, and the second scanning signal line S2 is a scanning signal line in the pixel circuit of the previous display row, that is, for the nth display row, the first scanning signal line S1 is S(n), and the second scanning signal line S2 is S(n-1), and the second scanning signal line S2 of the current display row is the same as the first scanning signal line S1 in the pixel circuit of the previous display row, which can reduce the signal lines of the display substrate and realize a narrow frame of the display substrate.

[0147] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0148] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light emitting signal line E and the initial signal line INIT extend in the horizontal direction, and the second power line VSS, the first power line VDD and the data signal line Data extend in the vertical direction.

[0149] Figure 5 This is a working timing diagram of a pixel circuit. Figure 4 The operation process of the pixel circuit of the example is described in detail with reference to the exemplary embodiment of the present disclosure. Figure 4 The pixel circuit includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C and 7 signal lines (data signal line Data, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS), and all 7 transistors are P-type transistors.

[0150] In an exemplary embodiment, the operation process of the pixel circuit may include:

[0151] The first stage A1 is called the reset stage. The signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scanning signal line S2 is a low-level signal, which turns on the first transistor T1. The signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the OLED does not emit light.

[0152] The second stage A2 is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals, and the data signal line Data outputs a data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal of the first scanning signal line S1 is a low level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line Data is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage of the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light. The signal of the second scanning signal line S2 is a high-level signal, which turns off the first transistor T1. The signal of the light-emitting signal line E is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.

[0153] The third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light-emitting signal line E is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.

[0154] During the pixel circuit driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0155] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0156] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line VDD.

[0157] The display substrate provided by the embodiment of the present disclosure includes: a display area and a non-display area surrounding the display area, the display area includes: a plurality of scanning lines extending along a first direction and a plurality of sub-pixels arranged in an array, the display area includes: a first display area and a second display area, the first display area is located at the periphery of the second display area, the second display area includes: a light-transmitting display area and a transitional display area, the transitional display area is located at the side of the light-transmitting display area; the light-transmitting display area includes: m rows and n columns of sub-pixels, each sub-pixel located in the light-transmitting display area includes: a light-emitting element, the light-emitting element of each sub-pixel located in the i-th row of the light-transmitting display area is electrically connected to the light-emitting element of the sub-pixel of the same color located in the i+1-th row of the light-transmitting display area, i is an odd number less than or equal to m; the transitional display area includes: m rows and n columns of sub-pixels, each sub-pixel located in the light-transmitting display area includes: a light-emitting element, the light-emitting element of each sub-pixel located in the i-th row of the light-transmitting display area is electrically connected to the light-emitting element of the sub-pixel of the same color located in the i+1-th row of the light-transmitting display area, i is an odd number less than or equal to m; There are n columns of sub-pixels, the i-th row of sub-pixels in the light-transmitting display area and the i-th row of sub-pixels in the transition display area are located in the same row; each sub-pixel located in the transition display area comprises: a pixel circuit and a light-emitting element, the light-emitting element of each sub-pixel located in the i-th row of the transition display area is electrically connected to the light-emitting element of the sub-pixel of the same color located in the i+1-th row of the transition display area; the pixel circuit and the light-emitting element of the sub-pixel in the i-th row of the transition display area are electrically connected, the pixel circuit of the sub-pixel in the i+1-th row and the j-th column of the transition display area is electrically connected to the light-emitting element of the sub-pixel in the i+1-th row and the j-th column of the light-transmitting display area, j is a positive integer less than or equal to n; the pixel circuits of the sub-pixels in the i-th row and the i+1-th row of the transition display area are connected to the same scanning line. The present invention electrically connects the pixel circuit of the sub-pixel in the i+1th row and jth column in the transition display area with the light-emitting element of the sub-pixel in the i+1th row and jth column in the light-transmitting display area, and connects the pixel circuits of the sub-pixels in the i-row and i+1th row in the transition display area to the same scan line, thereby ensuring that the light-transmitting display area and the transition display area are displayed simultaneously, thereby improving the display effect of the display substrate.

[0158] In an exemplary embodiment, Figure 6 A schematic diagram of a display substrate provided by an exemplary embodiment Figure 1 , Figure 7 FIG. 1 is a schematic diagram of the structure of a display substrate provided by another exemplary embodiment. Figure 3 , Figure 6 and Figure 7 As shown, the pixel circuits of the i-th row and the i+1-th row of sub-pixels located in the transition display area are connected to the first scan line G1 or the second scan line G2. The first scan line G1 is a scan line that is located in the same row as the i-th row of sub-pixels located in the transition display area and connected to the sub-pixels located in the first display area; the second scan line G2 is a scan line that is located in the same row as the i+1-th row of sub-pixels located in the transition display area and connected to the sub-pixels located in the first display area. Figure 3 , Figure 6 and Figure 7 The description is made by taking the example that the pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are electrically connected to the first scanning line.

[0159] like Figure 3 , Figure 6 and Figure 7 As shown, in an exemplary embodiment, the first display area may include: a plurality of sub-pixels. Each sub-pixel located in the first display area may include: a pixel circuit and a light-emitting element.

[0160] like Figure 3 , Figure 6 and Figure 7 As shown, in an exemplary embodiment, at least three sub-pixels located in the same row constitute a pixel unit. The light emitting element 11 includes: an anode, an organic light emitting layer and a cathode.

[0161] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HoleInjection Layer, HIL), a hole transport layer (Hole Transport Layer, HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HoleBlock Layer, HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0162] In an exemplary embodiment, a pixel unit may include, or may include, a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which is not limited in the present disclosure. When a pixel unit includes three sub-pixels, the three sub-pixels may be arranged horizontally in parallel, vertically in parallel, or in a herringbone manner; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged horizontally in parallel, vertically in parallel, or in a square manner, which is not limited in the present disclosure. The present disclosure is described by taking each pixel unit as including four sub-pixels, and the four sub-pixels are red sub-pixels, green sub-pixels, blue sub-pixels, and green sub-pixels, or blue sub-pixels, green sub-pixels, red sub-pixels, and green sub-pixels as examples.

[0163] In an exemplary embodiment, the sub-pixels of the pixel units in the same row are arranged in the same manner. The sub-pixels of the pixel units in the same column may be arranged in the same manner or in different manners. This disclosure is described by taking the different pixel units in the same column as an example.

[0164] like Figure 3 , Figure 6 and Figure 7As shown, in an exemplary embodiment, the anode of the light-emitting element of each sub-pixel located in the pixel unit of the i-th row and the k-th column of the light-transmitting display area is electrically connected to the anode of the light-emitting element of a sub-pixel of the same color located in the pixel unit of the i+1-th row and the k-th column of the light-transmitting display area, respectively, where k is a positive integer less than or equal to K, and K=n / 3 or n / 4.

[0165] In an exemplary embodiment, the anode of the light-emitting element of the sub-pixel located in the pixel unit of the i-th row and the k-th column of the light-transmitting display area is electrically connected to the anode of the light-emitting element of the sub-pixel located in the pixel unit of the i+1-th row and the k-th column of the light-transmitting display area that is closest to the pixel and has the same color.

[0166] like Figure 3 , Figure 6 and Figure 7 As shown, in an exemplary embodiment, the anode of the light-emitting element of each sub-pixel in the pixel unit of the i-th row and the j-th column in the transition display area is electrically connected to the anode of the light-emitting element of a sub-pixel of the same color in the pixel unit of the i+1-th row and the j-th column in the transition display area.

[0167] In an exemplary embodiment, the anode of the light-emitting element of each sub-pixel located in the pixel unit of the i-th row and j-th column of the transition display area is electrically connected to the anode of the light-emitting element of the sub-pixel with the same color that is closest to the pixel unit of the i+1-th row and j-th column of the transition display area.

[0168] like Figure 3 , Figure 6 and Figure 7 As shown, in an exemplary embodiment, the pixel circuit of the sub-pixel located in the i+1th row and jth column of the transition display area is electrically connected to the anode of the light-emitting element of the sub-pixel located in the i+1th row and jth column of the light-transmitting display area.

[0169] In an exemplary embodiment, the pixel circuit of the sub-pixel located in the first display area is electrically connected to the anode of the light emitting element.

[0170] like Figure 3 , Figure 6 and Figure 7 As shown, in an exemplary embodiment, the display substrate may further include: a plurality of data lines D extending along the second direction, the pixel circuit of the sub-pixel in the i-th row and j-th column located in the transition display area is electrically connected to the first data line D1, and the pixel circuit of the sub-pixel in the i+1-th row and j-th column located in the transition display area is electrically connected to the second data line D2.

[0171] In an exemplary embodiment, the first direction and the second direction intersect. The first data line D1 is a data line located in the same column as the sub-pixel in the i-th row and j-th column located in the transition display area and connected to the pixel circuit of the sub-pixel in the first display area; the second data line D2 is a data line located in the same column as the sub-pixel in the i+1-th row and j-th column located in the light-transmitting display area and connected to the pixel circuit of the sub-pixel in the first display area.

[0172] like Figure 3 , Figure 6 and Figure 7 As shown, in an exemplary embodiment, the display substrate may further include: a data connection line DL, which is arranged in a different layer from the data line D. The data connection line is electrically connected to the second data line connected to the pixel circuit of the sub-pixel in the i+1th row and jth column located in the transition display area and the pixel circuit of the sub-pixel in the i+1th row and jth column located in the transition display area.

[0173] In an exemplary embodiment, the data link line DL may be located on a side of the data line D close to the substrate, or may be located on a side of the data line D far from the substrate.

[0174] like Figure 2 , Figure 3 , Figure 6 and Figure 7 As shown, in an exemplary embodiment, the light-transmitting display area R21 includes: a first side and a second side arranged oppositely and a third side and a fourth side arranged oppositely; the transition display area R22 includes: a first transition display area R221 and a second transition display area R222.

[0175] The first transition display area R221 is located at a first side of the light-transmitting display area R21 , the second transition display area R222 is located at a second side of the light-transmitting display area R21 , and the first transition display area R221 and the second transition display area R222 are arranged along a first direction.

[0176] In an exemplary embodiment, the number of the second display area is at least one. Figure 2 , Figure 3 , Figure 6 and Figure 7 The description is made assuming that the number of the second display area is one.

[0177] Figure 8 Schematic diagram of the division of the display area Figure 1 .like Figure 8As shown, in an exemplary embodiment, when the number of the second display area is one, the first display area R10 includes: a first normal display area R11, a second normal display area R12, a third normal display area R13 and a fourth normal display area R14. The k-th row of the first normal display area R11 is the same row as the k-th row of the light-transmitting display area R21, the k-th row of the second normal display area R12 is the same row as the k-th row of the light-transmitting display area R21, and k is a positive integer greater than or equal to 1 and less than or equal to m;

[0178] The first normal display area R11 is located on a side of the first transition display area R221 away from the light-transmitting display area R21, and the second normal display area R12 is located on a side of the second transition display area R222 away from the light-transmitting display area R21; the third normal display area R13 is located on the third side of the light-transmitting display area R21, and the fourth normal display area R14 is located on the fourth side of the light-transmitting display area R21; the third normal display area R13 and the fourth normal display area R14 are arranged along the second direction.

[0179] Fig. 9 Schematic diagram of the division of the display area Figure 2 .like Fig. 9 As shown, in an exemplary embodiment, when the number of the second display areas is at least two, the first display area includes: a first normal display area R11, a second normal display area R12, a third normal display area R13, a fourth normal display area R14 and Q-1 fifth normal display areas R15; the k-th row of the first normal display area R11 is the same row as the k-th row of the light-transmitting display area R21, the k-th row of the second normal display area R12 is the same row as the k-th row of the light-transmitting display area R21, the k-th row of the fifth normal display area R15 is the same row as the k-th row of the light-transmitting display area R21, k is a positive integer greater than or equal to 1 and less than or equal to m, and Q is the number of the second display areas;

[0180] The first normal display area R11 is located on a side of the first transition display area R221 away from the light-transmitting display area R21, and the second normal display area R12 is located on a side of the second transition display area R222 away from the light-transmitting display area R21; the third normal display area R13 is located on the third side of the light-transmitting display area R21, and the fourth normal display area R14 is located on the fourth side of the light-transmitting display area R21; the third normal display area R13 and the fourth normal display area R14 are arranged along the second direction; the i-th fifth normal display area R15 is located between the i-th second display area and the i+1-th second display area. Fig. 9 The explanation is given below by taking Q=2 as an example.

[0181] In an exemplary embodiment, Figure 3 , Figure 6 and Figure 7As shown, the first data line D1 can be located in the same column as the sub-pixel located in the i-th row and j-th column of the light-transmitting display area, and can be electrically connected to the pixel circuits of the sub-pixels located in the third normal display area and the fourth normal display area and the pixel circuit of the sub-pixel located in the i-th row and j-th column of the light-transmitting display area.

[0182] In an exemplary embodiment, Figure 3 , Figure 6 and Figure 7 As shown, the second data line D2 may include: a first sub-data line and a second sub-data line that are arranged at intervals and extend along the second direction, and the first sub-data line and the second sub-data line are arranged along the second direction. The first sub-data line is located in the same column as the sub-pixel in the i+1th row and jth column of the light-transmitting display area, and is electrically connected to the pixel circuit of the sub-pixel in the third normal display area. The second sub-data line is located in the same column as the sub-pixel in the i+1th row and jth column of the light-transmitting display area, and is electrically connected to the pixel circuit of the sub-pixel in the fourth normal display area.

[0183] Fig.10 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 1 , Fig.11 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 2 .like Fig.10 and Fig.11 As shown, when there is only one second display area and the pixel circuits of the i-th row and i+1-th row of sub-pixels in the transition display area are connected to the first scan line, the first scan line G1 includes: a first scan part G11 and a second scan part G12 arranged at intervals. The second scan line G2 includes: a third scan part G13 and a fourth scan part G14 arranged at intervals and extending along the first direction. Among them, the first scan part G11 is electrically connected to the pixel circuits of the i-th row of sub-pixels in the first transition display area R221, the pixel circuits of the i+1-th row of sub-pixels in the first transition display area R221, and the pixel circuits of the i-th row of sub-pixels in the first normal display area. The second scan part G12 is electrically connected to the pixel circuits of the i-th row and i+1-th row of sub-pixels in the second transition display area R222, and the pixel circuits of the i-th row of sub-pixels in the second normal display area. The third scan part G13 is electrically connected to the pixel circuits of the i+1-th row of sub-pixels in the first normal display area. The fourth scanning unit G14 is electrically connected to the pixel circuits of the sub-pixels in the (i+1)th row in the second normal display area.

[0184] In an exemplary embodiment, Fig.10 and Fig.11As shown, the first scanning part may include: a first connection part G111, a second connection part G112 and a third connection part G113. The first connection part G111 and the third connection part G113 extend along the first direction, and the second connection part G112 extends along the second direction. The first connection part G111 is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area, the pixel circuit of the i-th row of sub-pixels located in the first transition display area R221, and the second connection part G112 respectively; the second connection part G112 is electrically connected to the third connection part G113; and the third connection part G113 is electrically connected to the pixel circuit of the i+1-th row of sub-pixels located in the first transition display area R221. Fig.10 The first scanning part in is an open loop.

[0185] In an exemplary embodiment, Fig.10 and Fig.11 As shown, the second scanning part G12 includes: a fourth connection part G121, a fifth connection part G122 and a sixth connection part G123, the fourth connection part G121 and the sixth connection part G123 extend along the first direction, and the fifth connection part G122 extends along the second direction. The fourth connection part G121 is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second normal display area, the pixel circuit of the i-th row of sub-pixels located in the second transition display area R222, and the fifth connection part G122 respectively; the fifth connection part G122 is electrically connected to the sixth connection part G123, and the sixth connection part G123 is electrically connected to the pixel circuit of the i+1-th row of sub-pixels located in the second transition display area R222. Fig.10 The second scanning part in is an open loop.

[0186] In an exemplary embodiment, Fig.11 As shown, the first scanning part G11 may further include: a seventh connection part G114. The seventh connection part G114 extends along the second direction. The seventh connection part G114 is electrically connected to the first connection part G111 and the third connection part G113 respectively. Fig.11 The first scanning portion in the display area includes a closed loop, and the first scanning portion located in the transition display area is a closed loop.

[0187] In an exemplary embodiment, the first scanning section located in the transition display area is a closed loop, which can reduce the load of the first scanning line.

[0188] In an exemplary embodiment, Fig.11 As shown, the second scanning portion G12 may further include: an eighth connection portion G124. The eighth connection portion G124 extends along the second direction. The eighth connection portion G124 is electrically connected to the fourth connection portion G121 and the sixth connection portion G123. Fig.11 The second scanning portion in the display area includes a closed loop, and the second scanning portion located in the transition display area is a closed loop.

[0189] In an exemplary embodiment, the second scanning section located in the transition display area is a closed loop, which can reduce the load of the first scanning line.

[0190] Fig.12 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 3 , Fig.13 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 4 , Fig.14 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 5 , Fig.15 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 6 , Fig.16 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 7 , Fig.17 A schematic diagram of multiple scan lines provided for an exemplary embodiment Figure 8 .like Figures 12 to 17 As shown, the first scan line G1 may further include: a first scan connection portion GC1, and / or the second scan line G2 may further include: a second scan line G2.

[0191] The first scanning connection portion GC1 is electrically connected to the first scanning portion G11 and the second scanning portion G12 respectively; the second scanning connection portion GC2 is electrically connected to the third scanning portion G13 and the fourth scanning portion G14 respectively. Fig.12 The description is made by taking the first scanning part and the second scanning part as an open loop, and the first scanning line including the first scanning connection part GC1 as an example. Fig.13 The description is made by taking the first scanning part and the second scanning part as an open loop, and the second scanning line including the second scanning connection part GC2 as an example. Fig.14 The description is made by taking the first scanning part and the second scanning part as an open loop, and the first scanning line includes the first scanning connection part GC1 and the second scanning line includes the second scanning connection part GC2 as an example. Fig.15 The description is made by taking an example that the first scanning portion and the second scanning portion include a closed loop, and the first scanning line includes the first scanning connection portion GC1. Fig.16 The description is made by taking an example that the first scanning portion and the second scanning portion include a closed loop, and the second scanning line includes the second scanning connection portion GC2. Fig.17 The description is made by taking an example that the first scanning part and the second scanning part include a closed loop, and include a first scanning connection part GC1 and the second scanning line includes a second scanning connection part GC2.

[0192] Fig.18 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 1 , Fig.19 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 2 .like Fig.18 and Fig.19 As shown, when there is only one second display area and the pixel circuits of the i-th row and the i+1-th row of sub-pixels in the transition display area are connected to the second scan line, the second scan line G2 includes: a first scan portion G21 and a second scan portion G22 arranged at intervals. The first scan line G1 includes: a third scan portion G23 and a fourth scan portion G24 arranged at intervals and extending along the first direction.

[0193] In an exemplary embodiment, the first scanning unit G21 may be electrically connected to the pixel circuits of the i-th and i+1-th rows of sub-pixels in the first transition display area R221 and the pixel circuits of the i+1-th row of sub-pixels in the first normal display area.

[0194] In an exemplary embodiment, the second scanning unit G22 may be electrically connected to the pixel circuits of the i-th and i+1-th rows of sub-pixels in the second transition display area R222 and the pixel circuits of the i+1-th row of sub-pixels in the second normal display area, respectively.

[0195] In an exemplary embodiment, the third scanning unit G23 may be electrically connected to the pixel circuits of the i-th row of sub-pixels located in the first normal display area.

[0196] In an exemplary embodiment, the fourth scanning unit G24 may be electrically connected to the pixel circuits of the i-th row of sub-pixels located in the second normal display area.

[0197] In an exemplary embodiment, Fig.18 and Fig.19 As shown, the first scanning portion G21 may include: a first connection portion G211, a second connection portion G212 and a third connection portion G213. The first connection portion G211 and the third connection portion G213 extend along the first direction, and the second connection portion G212 extends along the second direction. In an exemplary embodiment, the first connection portion G211 may be electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area, the pixel circuit of the i+1th row of sub-pixels located in the first transition display area R221, and the second connection portion G212, respectively. The second connection portion G212 may be electrically connected to the third connection portion G213. The third connection portion G213 may be electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first transition display area R221. Fig.18 The first scanning part in is an open loop.

[0198] In an exemplary embodiment, Fig.18 and Fig.19As shown, the second scanning part G22 may include: a fourth connection part G221, a fifth connection part G222 and a sixth connection part G223. The fourth connection part G221 and the sixth connection part G223 extend along the first direction, and the fifth connection part G222 extends along the second direction. In an exemplary embodiment, the fourth connection part G221 is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the second normal display area, the pixel circuit of the i+1th row of sub-pixels located in the second transition display area R222, and the fifth connection part respectively; the fifth connection part G222 is electrically connected to the sixth connection part G223; and the sixth connection part G223 is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second transition display area R222. Fig.18 The second scanning part in is an open loop.

[0199] In an exemplary embodiment, Fig.19 As shown, the first scanning portion G21 may further include: a seventh connection portion G214 extending along the second direction, wherein the seventh connection portion G214 is electrically connected to the first connection portion G211 and the third connection portion G213 respectively. Fig.19 The first scanning portion in the display area includes a closed loop, and the first scanning portion located in the transition display area is a closed loop.

[0200] In an exemplary embodiment, the first scanning section located in the transition display area is a closed loop, which can reduce the load of the first scanning line.

[0201] In an exemplary embodiment, Fig.19 As shown, the second scanning portion G22 may further include: an eighth connection portion G224 extending along the second direction, wherein the eighth connection portion G224 is electrically connected to the fourth connection portion G221 and the sixth connection portion G223 respectively. Fig.19 The second scanning portion in the display area includes a closed loop, and the second scanning portion located in the transition display area is a closed loop.

[0202] In an exemplary embodiment, the second scanning section located in the transition display area is a closed loop, which can reduce the load of the first scanning line.

[0203] Fig. 20 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 3 , Fig.21 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 4 , Fig. 22 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 5 , Fig.23 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 6 , Fig.24 A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 7 , Fig.25A schematic diagram of multiple scan lines provided for another exemplary embodiment Figure 8 .like Figure 20 to Figure 25 As shown, the first scan line G1 may further include: a first scan connection portion GC1, and / or the second scan line G2 may further include: a second scan line G2.

[0204] In an exemplary embodiment, the first scanning connection portion GC1 is electrically connected to the first scanning portion G11 and the second scanning portion G12 respectively; and the second scanning connection portion GC2 is electrically connected to the third scanning portion G13 and the fourth scanning portion G14 respectively. Fig. 20 The description is made by taking the first scanning part and the second scanning part as an open loop, and the first scanning line including the first scanning connection part GC1 as an example. Fig.21 The description is made by taking the first scanning part and the second scanning part as an open loop, and the second scanning line including the second scanning connection part GC2 as an example. Fig. 22 The description is made by taking the first scanning part and the second scanning part as an open loop, and the first scanning line includes the first scanning connection part GC1 and the second scanning line includes the second scanning connection part GC2 as an example. Fig.23 The description is made by taking an example that the first scanning portion and the second scanning portion include a closed loop, and the first scanning line includes the first scanning connection portion GC1. Fig.24 The description is made by taking an example that the first scanning portion and the second scanning portion include a closed loop, and the second scanning line includes the second scanning connection portion GC2. Fig.25 The description is made by taking an example that the first scanning portion and the second scanning portion include a closed loop, the first scanning line includes the first scanning connection portion GC1, and the second scanning line includes the second scanning connection portion GC2.

[0205] In an exemplary embodiment, the driving mode of the scan line may be determined according to the load of the scan line and the space of the display substrate.

[0206] In an exemplary embodiment, Fig.10 , Fig.11 , Fig.18 , Fig.19 As shown in FIG. , the first scan line G1 adopts double-sided driving, the second scan line can adopt double-sided driving, and the scan lines G other than the first scan line and the second scan line can adopt double-sided driving or single-sided driving.

[0207] In an exemplary embodiment, Fig.12 , Fig.15 , Fig.21 and Fig.24 As shown, the first scan line G1 can be driven unilaterally or bilaterally, the second scan line can be driven bilaterally, and the scan lines G other than the first scan line and the second scan line can be driven bilaterally or unilaterally.

[0208] In an exemplary embodiment, Fig.13 , Fig.16 , Fig. 20 and Fig.23 As shown, the first scan line G1 can be driven on both sides, the second scan line can be driven on one side or both sides, and the scan lines G other than the first scan line and the second scan line can be driven on both sides or on one side.

[0209] In an exemplary embodiment, Fig.14 , Fig.17 , Fig. 22 and Fig.25 As shown, all scan lines can be driven by double-side driving or single-side driving.

[0210] In an exemplary embodiment, the scan line adopts double-sided driving to reduce the load of the scan line. The scan line adopts a single-sided area to achieve a narrow frame of the display substrate.

[0211] Fig.26 A schematic diagram of multiple scan lines provided for yet another exemplary embodiment Figure 1 , Fig. 27 A schematic diagram of multiple scan lines provided for yet another exemplary embodiment Figure 2 .like Fig.26 and Fig. 27 As shown, when there are at least two second display areas, and the pixel circuits of the i-th row and i+1-th row of sub-pixels in the transitional display area are connected to the first scan line G1, the first scan line G1 can be electrically connected to the pixel circuits of the i-th row of sub-pixels in the first normal display area, the pixel circuits of the i-th row of sub-pixels in the first transitional display area R221 and the second transitional display area R222 of all second display areas, the pixel circuits of the i+1-th row of sub-pixels in the first transitional display area and the second transitional display area R221 of all second display areas, the pixel circuits of the i-th row of sub-pixels in all fifth normal display areas, and the pixel circuits of the i-th row of sub-pixels in the second normal display area. The second scan line can be electrically connected to the pixel circuits of the i+1-th row of sub-pixels in the first normal display area, the pixel circuits of the i+1-th row of sub-pixels in the second normal display area, and the pixel circuits of the i+1-th row of sub-pixels in all fifth normal display areas.

[0212] In an exemplary embodiment, Fig.26 and Fig. 27As shown, the first scanning line may include: a first scanning unit G31, Q-1 second scanning units G32, a third scanning unit G33 and Q first scanning connection units G34. Among them, the first scanning unit G31 can be electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area, and the pixel circuit of the i-th row and i+1-th row of sub-pixels located in the first transition display area R221 of the first second display area. The t-th second scanning unit G32 is electrically connected to the pixel circuit of the i-th row of sub-pixels in the t-th fifth normal display area, the pixel circuit of the i-th row and i+1-th row of sub-pixels in the second transition display area of ​​the t-th second display area, and the pixel circuit of the i-th row and i+1-th row of sub-pixels in the first transition display area of ​​the t+1-th second display area, t is a positive integer less than Q. The third scanning unit G33 is electrically connected to the pixel circuit of the i-th row and i+1-th row of sub-pixels located in the second transition display area R222 of the Q-th second display area, and the pixel circuit of the i-th row of sub-pixels in the second normal display area. The first first scanning connection part G34 can be electrically connected to the first scanning part G31 and the first second scanning part G32, respectively; the tth first scanning connection part G34 can be electrically connected to the t-1th second scanning part G32 and the tth second scanning part G32, respectively; the Qth first scanning connection part G34 can be electrically connected to the Q-1th second scanning part G32 and the third scanning part G33, respectively. Fig.26 and Fig. 27 The explanation is given below by taking Q=2 as an example.

[0213] In an exemplary embodiment, the first scanning section, the second scanning section and the third scanning section may be open loops or include closed loops. When the first scanning section includes a closed loop, the first scanning section located in the transition display area is a closed loop. When the second scanning section includes a closed loop, the second scanning section located in the transition display area is a closed loop. When the third scanning section includes a closed loop, the third scanning section located in the transition display area is a closed loop. Fig.26 The description is made by taking the first scanning unit, the second scanning unit and the third scanning unit as an open loop as an example. Fig. 27 The description is made by taking the example that the first scanning unit, the second scanning unit and the third scanning unit include a closed loop.

[0214] In an exemplary embodiment, the first scanning section, the second scanning section and the third scanning section located in the transition display area are closed loops to reduce the load of the first scanning line.

[0215] In an exemplary embodiment, Fig.26 and Fig. 27As shown, the second scan line may include: a fourth scan section G41, Q-1 fifth scan sections G42 and a sixth scan section G43, and Q second scan connection sections G44. Among them, the fourth scan section G41 may be electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area. The tth fifth scan section G42 may be electrically connected to the pixel circuit of the i+1th row of sub-pixels in the tth fifth normal display area. The sixth scan section G43 may be electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the second first display area. The first second scan connection section G44 may be electrically connected to the first scan section G41 and the first second scan section G42, respectively; the tth second scan connection section G44 may be electrically connected to the t-1th second scan section G42 and the tth second scan section G42, respectively; the Qth second scan connection section G44 may be electrically connected to the Q-1th second scan section G42 and the third scan section G43, respectively.

[0216] Fig.28 A schematic diagram of multiple scan lines provided for yet another exemplary embodiment Figure 3 , Fig.29 A schematic diagram of multiple scan lines provided for yet another exemplary embodiment Figure 4 .like Fig.28 and Fig.29 As shown, when there are at least two second display areas, and the pixel circuits of the i-th row and i+1-th row of sub-pixels located in the transition display area are connected to the second scan line G2, the first scan line G1 can be electrically connected to the pixel circuits of the i-th row of sub-pixels located in the first normal display area, the pixel circuits of the i-th row of sub-pixels located in the second normal display area, and the pixel circuits of the i-th row of sub-pixels located in all fifth normal display areas. The second scan line G2 can be electrically connected to the pixel circuits of the i+1-th row of sub-pixels located in the first normal display area, the pixel circuits of the i-th row and i+1-th row of sub-pixels located in the first transition display area R21 and the second transition display area R222 of all second display areas, the pixel circuits of the i+1-th row of sub-pixels in all fifth normal display areas, and the pixel circuits of the i+1-th row of sub-pixels located in the second normal display area.

[0217] In an exemplary embodiment, Fig.28 and Fig.29As shown, the second scan line may include: a first scan section G31, Q-1 second scan sections G32, a third scan section G33, and Q first scan connection sections G34. Among them, the first scan section G31 may be electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area and the pixel circuit of the i-th row and i+1th row of sub-pixels located in the first transition display area of ​​the first second display area. The t-th second scan section G32 may be electrically connected to the pixel circuit of the i+1th row of sub-pixels in the t-th fifth normal display area, the pixel circuit of the i-th row and i+1th row of sub-pixels in the second transition display area of ​​the t-th second display area, and the pixel circuit of the i-th row and i+1th row of sub-pixels in the first transition display area of ​​the t+1-th second display area. The third scan section G33 is electrically connected to the pixel circuit of the i-th row and i+1th row of sub-pixels located in the second transition display area of ​​the Q-th second display area and the pixel circuit of the i+1th row of sub-pixels in the second normal display area. The first first scanning connection part G34 is electrically connected to the first scanning part G31 and the first second scanning part G32, respectively; the tth second scanning connection part G34 can be electrically connected to the t-1th second scanning part G32 and the tth second scanning part G32, respectively; the Qth second scanning connection part G34 can be electrically connected to the Q-1th second scanning part G32 and the third scanning part G33, respectively. Fig.28 and Fig.29 The explanation is given below by taking Q=2 as an example.

[0218] In an exemplary embodiment, the first scanning section, the second scanning section, and the third scanning section may be open loops, or may include closed loops. When the first scanning section includes a closed loop, the first scanning section located in the transition display area is a closed loop. When the second scanning section includes a closed loop, the second scanning section located in the transition display area is a closed loop. When the third scanning section includes a closed loop, the third scanning section located in the transition display area is a closed loop. When the first scanning section, the second scanning section, and the third scanning section include a closed loop, the load of the first scanning line can be reduced. Fig.28 The description is made by taking the first scanning unit, the second scanning unit and the third scanning unit as an open loop as an example. Fig.29 The description is made by taking the example that the first scanning unit, the second scanning unit and the third scanning unit include a closed loop.

[0219] In an exemplary embodiment, the first scanning section, the second scanning section and the third scanning section located in the transition display area are closed loops to reduce the load of the second scanning line.

[0220] In an exemplary embodiment, Fig.28 and Fig.29As shown, the first scan line may include: a fourth scan section G41, Q-1 fifth scan sections G42, a sixth scan section G43 and Q second scan connection sections G44. Among them, the fourth scan section G41 may be electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area. The t-th fifth scan section G42 may be electrically connected to the pixel circuit of the i-th row of sub-pixels in the t-th fifth normal display area. The sixth scan section G43 may be electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second normal display area. The first second scan connection section G44 is electrically connected to the first scan section G41 and the first second scan section G42, respectively; the t-th second scan connection section G44 is electrically connected to the t-1-th second scan section G42 and the t-th second scan section G42, respectively; the Q-th second scan connection section G44 is electrically connected to the Q-1-th second scan section G42 and the third scan section G43, respectively.

[0221] In an exemplary embodiment, when the number of the second display areas is at least two, the scan lines in the display substrate can be driven by a single side or a double side. When the scan lines are driven by a double side, the display effect of the display substrate can be improved.

[0222] Figures 10 to 29 The description is made by taking the example that the light-transmitting display area includes four rows and four columns of pixel units, wherein each pixel unit includes at least three sub-pixels of different colors. The present disclosure is not limited thereto.

[0223] like Figures 10 to 29 As shown, the orthographic projection of the first scan line on the substrate and the orthographic projection of the second scan line on the substrate may or may not have an overlapping area, which is determined according to the structure of the first scan line and the second scan line, and the present disclosure does not make any limitation.

[0224] In an exemplary embodiment, when there is no overlapping area between the orthographic projection of the first scan line on the substrate and the orthographic projection of the second scan line on the substrate, the first scan line and the second scan line are arranged in the same layer.

[0225] In an exemplary embodiment, when the orthographic projection of the first scan line and the second scan line on the substrate overlaps with the orthographic projection of the second scan line on the substrate, the first scan line may include: a first non-overlapping portion and a first overlapping portion, the first non-overlapping portion and the second scan line are arranged in the same layer, and the first overlapping portion may be arranged on a side of the second scan line close to the substrate, or may be arranged on a side of the second scan line away from the substrate. The first non-overlapping portion is a portion of the first scan line that does not overlap with the second scan line, and the first overlapping portion is a portion of the first scan line that overlaps with the second scan line.

[0226] In an exemplary embodiment, when the orthographic projection of the first scan line and the second scan line on the substrate overlaps with the orthographic projection of the second scan line on the substrate, the second scan line may include: a second non-overlapping portion and a second overlapping portion, the second non-overlapping portion being arranged in the same layer as the first scan line, and the second overlapping portion being arranged on a side of the first scan line close to the substrate, or being arranged on a side of the first scan line far from the substrate. The second non-overlapping portion is a portion of the second scan line that does not overlap with the first scan line, and the second overlapping portion is a portion of the second scan line that overlaps with the first scan line.

[0227] Fig.30 A timing diagram of some signals provided for an exemplary embodiment, Fig.31 A timing diagram of some signals is provided for another exemplary embodiment. Fig.30 The following description is made by taking the example that the pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are electrically connected to the first scanning line. Fig.31 The description is made by taking the example that the pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are electrically connected to the second scanning line. Fig.30 and Fig.31 GR1 is the scanning signal connected to the pixel circuit connected to the sub-pixels in the i-th row and the i+1-th row in the transparent display area, GR2 is the scanning signal connected to the pixel circuit connected to the sub-pixels in the i-th row and the i+1-th row in the transition display area, GR_1 is the scanning signal of the scanning line connected to the pixel circuit of the sub-pixel in the same row as the i-th row in the transition display area and located in the first display area, GR_2 is the scanning signal of the scanning line connected to the pixel circuit of the sub-pixel in the same row as the i+1-th row in the transition display area and located in the first display area. D is the data signal of the data line. Fig.30 As shown in FIG. 1 , when the pixel circuits of the sub-pixels in the i-th row and the i+1-th row of the transition display area are electrically connected to the first scan line, GR1 and GR2 are the same as GR_1. Fig.31 As shown, when the pixel circuits of the sub-pixels in the i-th row and the i+1-th row of the transition display area are electrically connected to the first scan line, GR1 and GR2 are the same as GR_1.

[0228] The embodiment of the present disclosure further provides a display device, which may include: a display substrate.

[0229] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0230] In an exemplary embodiment, the display device may further include: a functional component located in the light-transmitting display area and located on the non-light-emitting side of the display device. External ambient light may be incident on the functional component through the light-transmitting display area.

[0231] In an exemplary embodiment, the functional components may include at least one of a camera module (e.g., a front camera module), a 3D structured light module (e.g., a 3D structured light sensor), a time-of-flight 3D imaging module (e.g., a time-of-flight sensor), an infrared sensing module (e.g., an infrared sensing sensor), etc.

[0232] In an exemplary embodiment, the front camera module is usually enabled when the user takes a selfie or makes a video call, and the display area of ​​the display device displays the image obtained by the selfie for the user to watch. The front camera module includes, for example, a lens, an image sensor, an image processing chip, etc. The optical image of the scene generated by the lens is projected onto the surface of the image sensor (the image sensor includes CCD and CMOS) and converted into an electrical signal, which is converted into a digital image signal through the analog-to-digital conversion of the image processing chip, and then sent to the processor for processing, and the image of the scene is output on the display screen.

[0233] In an exemplary embodiment, a 3D structured light sensor and a time of flight (ToF) sensor may be used for face recognition to unlock a display device, etc.

[0234] For example, the functional component may include only a camera module to realize the function of selfie or video call; for example, the functional component may also include a 3D structured light module or a time-of-flight 3D imaging module to realize face recognition unlocking, etc. The present disclosure includes but is not limited to this.

[0235] The display device provided by the embodiment of the present disclosure can display images in the light-transmitting display area to maintain the display integrity of the entire display device.

[0236] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0237] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0238] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate, characterized in that: include: A display area and a non-display area surrounding the display area, the display area comprising: a plurality of scan lines extending along a first direction and a plurality of sub-pixels arranged in an array, the display area comprising: a first display area and a second display area, the first display area being located at the periphery of the second display area, the second display area comprising: a light-transmitting display area and a transitional display area, the transitional display area being located at a side of the light-transmitting display area; The light-transmitting display area includes: m rows and n columns of sub-pixels, each sub-pixel in the light-transmitting display area includes: a light-emitting element, the light-emitting element of each sub-pixel in the i-th row of the light-transmitting display area is electrically connected to the light-emitting element of the sub-pixel in the i+1-th row of the light-transmitting display area and of the same color, where i is an odd number less than or equal to m; The transitional display area comprises: m rows and n columns of sub-pixels, the i-th row of the light-transmitting display area and the i-th row of the transitional display area are located in the same row; each sub-pixel located in the transitional display area comprises: a pixel circuit and a light-emitting element, the light-emitting element of each sub-pixel located in the i-th row of the transitional display area is electrically connected to the light-emitting element of the sub-pixel of the same color located in the i+1-th row of the transitional display area; the pixel circuit and the light-emitting element of the sub-pixel located in the i-th row of the transitional display area are electrically connected, the pixel circuit of the sub-pixel located in the i+1-th row and the j-th column of the transitional display area is electrically connected to the light-emitting element of the sub-pixel located in the i+1-th row and the j-th column of the light-transmitting display area, and j is a positive integer less than or equal to n; The pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are connected to the same scan line.

2. The display substrate according to claim 1, characterized in that: The pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are connected to the first scan line or the second scan line; Among them, the first scan line is a scan line that is located in the same row as the i-th row of sub-pixels located in the transition display area and is connected to the sub-pixels located in the first display area; the second scan line is a scan line that is located in the same row as the i+1-th row of sub-pixels located in the transition display area and is connected to the sub-pixels located in the first display area.

3. The display substrate according to claim 1 or 2, characterized in that: The first display area includes: a plurality of sub-pixels, each sub-pixel in the first display area includes: a pixel circuit and a light-emitting element; at least three sub-pixels in the same row constitute a pixel unit; the light-emitting element includes: an anode, an organic light-emitting layer and a cathode; The anode of the light-emitting element of each sub-pixel in the pixel unit of the i-th row and the k-th column in the light-transmitting display area is electrically connected to the anode of the light-emitting element of a sub-pixel of the same color in the pixel unit of the i+1-th row and the k-th column in the light-transmitting display area, k is a positive integer less than or equal to K, K=n / 3 or n / 4; The anode of the light-emitting element of each sub-pixel in the pixel unit of the i-th row and the j-th column in the transition display area is electrically connected to the anode of the light-emitting element of a sub-pixel of the same color in the pixel unit of the i+1-th row and the j-th column in the transition display area; The pixel circuit of the sub-pixel in the i+1th row and jth column in the transitional display area is electrically connected to the anode of the light-emitting element of the sub-pixel in the i+1th row and jth column in the light-transmitting display area; The pixel circuit of the sub-pixel located in the first display area is electrically connected to the anode of the light emitting element.

4. The display substrate according to claim 3, characterized in that: The display substrate further comprises: a plurality of data lines extending along a second direction, the pixel circuit of the sub-pixel in the i-th row and j-th column located in the transition display area is electrically connected to the first data line, the pixel circuit of the sub-pixel in the i+1-th row and j-th column located in the transition display area is electrically connected to the second data line, and the first direction and the second direction intersect; Among them, the first data line is a data line that is located in the same column as the sub-pixel in the i-th row and j-th column located in the transition display area and is connected to the pixel circuit of the sub-pixel located in the first display area; the second data line is a data line that is located in the same column as the sub-pixel in the i+1-th row and j-th column located in the light-transmitting display area and is connected to the pixel circuit of the sub-pixel located in the first display area.

5. The display substrate according to claim 4, characterized in that: Also includes: A data connection line, wherein the data connection line and the data line are arranged in a different layer; The data connection line is electrically connected to the pixel circuit of the i+1th row and jth column sub-pixel located in the transition display area and the second data line connected to the pixel circuit of the i+1th row and jth column sub-pixel located in the transition display area.

6. The display substrate according to claim 2, characterized in that: The light-transmitting display area includes: a first side and a second side arranged opposite to each other, and a third side and a fourth side arranged opposite to each other; the transitional display area includes: a first transitional display area and a second transitional display area; The first transition display area is located at a first side of the light-transmitting display area, the second transition display area is located at a second side of the light-transmitting display area, and the first transition display area and the second transition display area are arranged along a first direction.

7. The display substrate according to claim 6, characterized in that: The number of the second display area is at least one.

8. The display substrate according to claim 7, characterized in that: When the number of the second display area is one, the first display area includes: a first normal display area, a second normal display area, a third normal display area and a fourth normal display area; The kth row of the first normal display area is the same row as the kth row of the light-transmitting display area, and the kth row of the second normal display area is the same row as the kth row of the light-transmitting display area, where k is a positive integer greater than or equal to 1 and less than or equal to m; The first normal display area is located on a side of the first transition display area away from the light-transmitting display area, and the second normal display area is located on a side of the second transition display area away from the light-transmitting display area; the third normal display area is located on a third side of the light-transmitting display area, and the fourth normal display area is located on a fourth side of the light-transmitting display area; the third normal display area and the fourth normal display area are arranged along the second direction.

9. The display substrate according to claim 8, characterized in that: When the pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are connected to the first scanning line, the first scanning line includes: a first scanning portion and a second scanning portion arranged at intervals; the second scanning line includes: a third scanning portion and a fourth scanning portion arranged at intervals and extending along the first direction; The first scanning section is electrically connected to the pixel circuits of the i-th row and the i+1-th row of sub-pixels located in the first transition display area and the pixel circuit of the i-th row of sub-pixels located in the first normal display area; The second scanning section is electrically connected to the pixel circuits of the i-th row and the i+1-th row of sub-pixels located in the second transition display area and the pixel circuit of the i-th row of sub-pixels located in the second normal display area; The third scanning unit is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area; The fourth scanning unit is electrically connected to the pixel circuits of the sub-pixels in the (i+1)th row located in the second normal display area.

10. The display substrate according to claim 9, characterized in that: The first scanning portion includes: a first connecting portion, a second connecting portion and a third connecting portion, the first connecting portion and the third connecting portion extend along a first direction, and the second connecting portion extends along a second direction; The first connection portion is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area, the pixel circuit of the i-th row of sub-pixels located in the first transition display area, and the second connection portion; the second connection portion is electrically connected to the third connection portion; and the third connection portion is electrically connected to the pixel circuit of the i+1-th row of sub-pixels located in the first transition display area; The second scanning portion includes: a fourth connecting portion, a fifth connecting portion and a sixth connecting portion, the fourth connecting portion and the sixth connecting portion extend along the first direction, and the fifth connecting portion extends along the second direction; The fourth connection portion is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second normal display area, the pixel circuit of the i-th row of sub-pixels located in the second transition display area, and the fifth connection portion respectively; the fifth connection portion is electrically connected to the sixth connection portion; and the sixth connection portion is electrically connected to the pixel circuit of the i+1-th row of sub-pixels located in the second transition display area.

11. The display substrate according to claim 10, characterized in that: The first scanning portion further includes: a seventh connecting portion extending along the second direction, and the second scanning portion further includes: an eighth connecting portion extending along the second direction; The seventh connection portion is electrically connected to the first connection portion and the third connection portion respectively; The eighth connection portion is electrically connected to the fourth connection portion and the sixth connection portion respectively.

12. The display substrate according to claim 10 or 11, characterized in that: The first scanning line further includes: a first scanning connection portion, and / or the second scanning line further includes: a second scanning connection portion; The first scanning connection part is electrically connected to the first scanning part and the second scanning part respectively; The second scanning connection part is electrically connected to the third scanning part and the fourth scanning part respectively.

13. The display substrate according to claim 8, characterized in that: When the pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are connected to the second scanning line, the second scanning line includes: a first scanning portion and a second scanning portion arranged at intervals; the first scanning line includes: a third scanning portion and a fourth scanning portion arranged at intervals and extending along the first direction; The first scanning section is electrically connected to the pixel circuits of the i-th row and the i+1-th row of sub-pixels located in the first transition display area and the pixel circuit of the i+1-th row of sub-pixels located in the first normal display area; The second scanning section is electrically connected to the pixel circuits of the i-th row and the i+1-th row of sub-pixels in the second transition display area and the pixel circuit of the i+1-th row of sub-pixels in the second normal display area; The third scanning unit is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area; The fourth scanning unit is electrically connected to the pixel circuits of the i-th row of sub-pixels located in the second normal display area.

14. The display substrate according to claim 13, characterized in that: The first scanning portion comprises: a first connection portion, a second connection portion and a third connection portion, the first connection portion and the third connection portion extend along a first direction, and the second connection portion extends along a second direction; the first connection portion is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area, the pixel circuit of the i+1th row of sub-pixels located in the first transition display area, and the second connection portion respectively; the second connection portion is electrically connected to the third connection portion; and the third connection portion is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first transition display area; The second scanning part includes: a fourth connecting part, a fifth connecting part and a sixth connecting part, the fourth connecting part and the sixth connecting part extend along the first direction, and the fifth connecting part extends along the second direction; the fourth connecting part is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the second normal display area, the pixel circuit of the i+1th row of sub-pixels located in the second transition display area, and the fifth connecting part respectively; the fifth connecting part is electrically connected to the sixth connecting part; and the sixth connecting part is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second transition display area.

15. The display substrate according to claim 14, characterized in that: The first scanning portion further includes: a seventh connecting portion extending along the second direction, the seventh connecting portion being electrically connected to the first connecting portion and the third connecting portion respectively; The second scanning portion further includes an eighth connecting portion extending along the second direction, and the eighth connecting portion is electrically connected to the fourth connecting portion and the sixth connecting portion respectively.

16. The display substrate according to claim 14 or 15, characterized in that: The second scanning line further includes: a first scanning connection portion, and / or the first scanning line further includes: a second scanning connection portion; The first scanning connection part is electrically connected to the first scanning part and the second scanning part respectively; The second scanning connection part is electrically connected to the third scanning part and the fourth scanning part respectively.

17. The display substrate according to claim 7, characterized in that: When the number of the second display areas is at least two, the first display area includes: a first normal display area, a second normal display area, a third normal display area, a fourth normal display area and Q-1 fifth normal display areas; the kth row of the first normal display area is the same row as the kth row of the light-transmitting display area, the kth row of the second normal display area is the same row as the kth row of the light-transmitting display area, the kth row of the fifth normal display area is the same row as the kth row of the light-transmitting display area, k is a positive integer greater than or equal to 1 and less than or equal to m, and Q is the number of the second display areas; The first normal display area is located on a side of the first transition display area away from the light-transmitting display area, and the second normal display area is located on a side of the second transition display area away from the light-transmitting display area; the third normal display area is located on a third side of the light-transmitting display area, and the fourth normal display area is located on a fourth side of the light-transmitting display area; the third normal display area and the fourth normal display area are arranged along the second direction; the i-th fifth normal display area is located between the i-th second display area and the i+1-th second display area.

18. The display substrate according to claim 17, characterized in that: When the pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are connected to the first scan line, The first scan line is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area, the pixel circuit of the i-th row of sub-pixels located in the first transition display area and the second transition display area of ​​all the second display areas, the pixel circuit of the i+1-th row of sub-pixels located in the first transition display area and the second transition display area of ​​all the second display areas, the pixel circuit of the i-th row of sub-pixels in all the fifth normal display areas, and the pixel circuit of the i-th row of sub-pixels located in the second normal display area; The second scan line is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area, the pixel circuit of the i+1th row of sub-pixels located in the second normal display area, and the pixel circuit of the i+1th row of sub-pixels located in all fifth normal display areas; The first scanning line includes: a first scanning portion, Q-1 second scanning portions and a third scanning portion, and Q first scanning connecting portions; The first scanning section is electrically connected to the pixel circuits of the i-th row of sub-pixels located in the first normal display area and the pixel circuits of the i-th row and the i+1-th row of sub-pixels located in the first transition display area of ​​the first second display area; The t-th second scanning section is electrically connected to the pixel circuit of the i-th row of sub-pixels in the t-th fifth normal display area, the pixel circuit of the i-th row and i+1-th row of sub-pixels in the second transition display area of ​​the t-th second display area, and the pixel circuit of the i-th row and i+1-th row of sub-pixels in the first transition display area of ​​the t+1-th second display area, respectively, where t is a positive integer less than Q; The third scanning section is electrically connected to the pixel circuits of the i-th row and the i+1-th row of sub-pixels in the second transition display area of ​​the Q-th second display area and the pixel circuit of the i-th row of sub-pixels in the second normal display area; The first first scanning connection part is electrically connected to the first scanning part and the first second scanning part respectively, the t-th first scanning connection part is electrically connected to the t-1-th second scanning part and the t-th second scanning part respectively; the Q-th first scanning connection part is electrically connected to the Q-1-th second scanning part and the third scanning part respectively; The second scanning line includes: a fourth scanning portion, Q-1 fifth scanning portions and a sixth scanning portion, and Q second scanning connecting portions; The fourth scanning unit is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area; The t-th fifth scanning unit is electrically connected to the pixel circuit of the i+1-th row of sub-pixels in the t-th fifth normal display area; The sixth scanning unit is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the second first display area; The first second scanning connection part is electrically connected to the first scanning part and the first second scanning part respectively, the tth second scanning connection part is electrically connected to the t-1th second scanning part and the tth second scanning part respectively; the Qth second scanning connection part is electrically connected to the Q-1th second scanning part and the third scanning part respectively.

19. The display substrate according to claim 17, characterized in that: When the pixel circuits of the sub-pixels in the i-th row and the i+1-th row in the transition display area are connected to the second scan line, The first scanning line is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area, the pixel circuit of the i-th row of sub-pixels located in the second normal display area, and the pixel circuit of the i-th row of sub-pixels located in all fifth normal display areas respectively; The second scan lines are respectively electrically connected to the pixel circuits of the i+1th row of sub-pixels located in the first normal display area, the pixel circuits of the i-th row and the i+1th row of sub-pixels located in the first transition display area and the second transition display area of ​​all the second display areas, the pixel circuits of the i+1th row of sub-pixels in all the fifth normal display areas, and the pixel circuits of the i+1th row of sub-pixels located in the second normal display area; The second scanning line comprises: a first scanning portion, Q-1 second scanning portions and a third scanning portion, and Q first scanning connecting portions; The first scanning section is electrically connected to the pixel circuits of the i+1th row of sub-pixels located in the first normal display area and the pixel circuits of the i-th row and the i+1th row of sub-pixels located in the first transition display area of ​​the first second display area; The t-th second scanning section is electrically connected to the pixel circuits of the i+1-th row of sub-pixels in the t-th fifth normal display area, the pixel circuits of the i-th row and i+1-th row of sub-pixels in the second transition display area of ​​the t-th second display area, and the pixel circuits of the i-th row and i+1-th row of sub-pixels in the first transition display area of ​​the t+1-th second display area; The third scanning section is electrically connected to the pixel circuits of the i-th row and i+1-th row of sub-pixels in the second transition display area of ​​the Q-th second display area and the pixel circuit of the i+1-th row of sub-pixels in the second normal display area; The first first scanning connection part is electrically connected to the first scanning part and the first second scanning part respectively, the t-th second scanning connection part is electrically connected to the t-1-th second scanning part and the t-th second scanning part respectively; the Q-th second scanning connection part is electrically connected to the Q-1-th second scanning part and the third scanning part respectively; The first scanning line includes: a fourth scanning portion, Q-1 fifth scanning portions, a sixth scanning portion and Q second scanning connecting portions; The fourth scanning unit is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area; The t-th fifth scanning unit is electrically connected to the pixel circuit of the i-th row of sub-pixels in the t-th fifth normal display area; The sixth scanning unit is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second normal display area; The first second scanning connection part is electrically connected to the first scanning part and the first second scanning part respectively, the tth second scanning connection part is electrically connected to the t-1th second scanning part and the tth second scanning part respectively; the Qth second scanning connection part is electrically connected to the Q-1th second scanning part and the third scanning part respectively.

20. A display device, characterized in that: include: A display substrate as claimed in any one of claims 1 to 19.

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